Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	838	1			T16	4		T29	8		T72	8
all_values[1]	838	1			T16	4		T29	8		T72	8
all_values[2]	838	1			T16	4		T29	8		T72	8
all_values[3]	838	1			T16	4		T29	8		T72	8
all_values[4]	838	1			T16	4		T29	8		T72	8
all_values[5]	838	1			T16	4		T29	8		T72	8
all_values[6]	838	1			T16	4		T29	8		T72	8
all_values[7]	838	1			T16	4		T29	8		T72	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3551

1

T16

15

T29

43

T72

31

auto[1]

3153

1

T16

17

T29

21

T72

33

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2489

1

T16

17

T29

24

T72

26

auto[1]

4215

1

T16

15

T29

40

T72

38

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4006

1

T16

23

T29

37

T72

38

auto[1]

2698

1

T16

9

T29

27

T72

26

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	4	44	91.67	4
Automatically Generated Cross Bins	48	4	44	91.67	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	254	1			T16	1		T29	5		T72	1
all_values[0]	auto[0]	auto[1]	auto[1]	244	1			T16	1		T29	1		T72	2
all_values[0]	auto[1]	auto[0]	auto[1]	193	1			T16	2		T29	1		T72	4
all_values[0]	auto[1]	auto[1]	auto[1]	147	1			T29	1		T72	1		T73	2
all_values[1]	auto[0]	auto[0]	auto[0]	270	1			T16	1		T29	4		T72	2
all_values[1]	auto[0]	auto[1]	auto[0]	227	1			T16	2		T29	2		T72	1
all_values[1]	auto[1]	auto[0]	auto[1]	193	1			T72	4		T73	3		T111	2
all_values[1]	auto[1]	auto[1]	auto[1]	148	1			T16	1		T29	2		T72	1
all_values[2]	auto[0]	auto[0]	auto[0]	176	1			T16	1		T29	2		T73	1
all_values[2]	auto[0]	auto[0]	auto[1]	78	1			T72	1		T73	2		T111	1
all_values[2]	auto[0]	auto[1]	auto[0]	139	1			T72	2		T112	6		T108	1
all_values[2]	auto[0]	auto[1]	auto[1]	92	1			T16	2		T29	2		T72	1
all_values[2]	auto[1]	auto[0]	auto[1]	188	1			T29	3		T72	1		T73	1
all_values[2]	auto[1]	auto[1]	auto[1]	165	1			T16	1		T29	1		T72	3
all_values[3]	auto[0]	auto[0]	auto[0]	157	1			T16	1		T29	2		T72	1
all_values[3]	auto[0]	auto[0]	auto[1]	89	1			T29	1		T73	1		T112	3
all_values[3]	auto[0]	auto[1]	auto[0]	137	1			T16	2		T29	1		T72	2
all_values[3]	auto[0]	auto[1]	auto[1]	101	1			T72	3		T112	3		T108	2
all_values[3]	auto[1]	auto[0]	auto[1]	185	1			T29	2		T73	3		T112	5
all_values[3]	auto[1]	auto[1]	auto[1]	169	1			T16	1		T29	2		T72	2
all_values[4]	auto[0]	auto[0]	auto[0]	180	1			T16	3		T29	3		T72	4
all_values[4]	auto[0]	auto[0]	auto[1]	80	1			T29	1		T72	1		T112	2
all_values[4]	auto[0]	auto[1]	auto[0]	155	1			T16	1		T29	2		T72	2
all_values[4]	auto[0]	auto[1]	auto[1]	85	1			T111	1		T112	3		T108	1
all_values[4]	auto[1]	auto[0]	auto[1]	200	1			T29	1		T72	1		T73	1
all_values[4]	auto[1]	auto[1]	auto[1]	138	1			T29	1		T73	1		T111	1
all_values[5]	auto[0]	auto[0]	auto[0]	187	1			T16	1		T72	1		T73	2
all_values[5]	auto[0]	auto[0]	auto[1]	89	1			T29	2		T72	1		T73	1
all_values[5]	auto[0]	auto[1]	auto[0]	167	1			T16	2		T73	1		T112	5
all_values[5]	auto[0]	auto[1]	auto[1]	83	1			T72	1		T111	2		T112	2
all_values[5]	auto[1]	auto[0]	auto[1]	175	1			T16	1		T29	6		T72	3
all_values[5]	auto[1]	auto[1]	auto[1]	137	1			T72	2		T111	1		T112	3
all_values[6]	auto[0]	auto[0]	auto[0]	182	1			T29	4		T72	2		T73	1
all_values[6]	auto[0]	auto[0]	auto[1]	85	1			T16	1		T73	1		T111	1
all_values[6]	auto[0]	auto[1]	auto[0]	159	1			T72	3		T73	1		T112	5
all_values[6]	auto[0]	auto[1]	auto[1]	77	1			T16	1		T72	1		T111	1
all_values[6]	auto[1]	auto[0]	auto[1]	177	1			T16	2		T29	2		T73	1
all_values[6]	auto[1]	auto[1]	auto[1]	158	1			T29	2		T72	2		T73	3
all_values[7]	auto[0]	auto[0]	auto[0]	193	1			T16	1		T29	3		T72	2
all_values[7]	auto[0]	auto[0]	auto[1]	66	1			T73	1		T111	2		T112	2
all_values[7]	auto[0]	auto[1]	auto[0]	160	1			T16	2		T29	1		T72	4
all_values[7]	auto[0]	auto[1]	auto[1]	94	1			T29	1		T73	1		T112	1
all_values[7]	auto[1]	auto[0]	auto[1]	154	1			T29	1		T72	2		T73	2
all_values[7]	auto[1]	auto[1]	auto[1]	171	1			T16	1		T29	2		T73	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal