Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.27 99.27 97.95 100.00 98.80 100.00 99.61


Total test records in report: 1317
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T1256 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.56536731 Apr 18 12:46:39 PM PDT 24 Apr 18 12:46:41 PM PDT 24 43009224 ps
T1257 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.4236789329 Apr 18 12:46:35 PM PDT 24 Apr 18 12:46:37 PM PDT 24 64222778 ps
T1258 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.4063155305 Apr 18 12:46:31 PM PDT 24 Apr 18 12:46:33 PM PDT 24 36890086 ps
T1259 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2158646392 Apr 18 12:46:29 PM PDT 24 Apr 18 12:46:31 PM PDT 24 141503143 ps
T1260 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.654749874 Apr 18 12:47:00 PM PDT 24 Apr 18 12:47:01 PM PDT 24 30102017 ps
T1261 /workspace/coverage/cover_reg_top/10.uart_csr_rw.859857356 Apr 18 12:46:37 PM PDT 24 Apr 18 12:46:39 PM PDT 24 40889476 ps
T85 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.787264638 Apr 18 12:46:44 PM PDT 24 Apr 18 12:46:47 PM PDT 24 83038446 ps
T110 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.4267202542 Apr 18 12:46:42 PM PDT 24 Apr 18 12:46:44 PM PDT 24 179977822 ps
T1262 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1308523510 Apr 18 12:46:34 PM PDT 24 Apr 18 12:46:36 PM PDT 24 48483679 ps
T49 /workspace/coverage/cover_reg_top/14.uart_csr_rw.3367917248 Apr 18 12:46:43 PM PDT 24 Apr 18 12:46:45 PM PDT 24 12411728 ps
T1263 /workspace/coverage/cover_reg_top/21.uart_intr_test.2622371261 Apr 18 12:46:49 PM PDT 24 Apr 18 12:46:51 PM PDT 24 17665304 ps
T1264 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.324386815 Apr 18 12:46:50 PM PDT 24 Apr 18 12:46:53 PM PDT 24 22615143 ps
T1265 /workspace/coverage/cover_reg_top/32.uart_intr_test.1084639538 Apr 18 12:46:48 PM PDT 24 Apr 18 12:46:51 PM PDT 24 17849613 ps
T1266 /workspace/coverage/cover_reg_top/49.uart_intr_test.263903680 Apr 18 12:46:55 PM PDT 24 Apr 18 12:46:57 PM PDT 24 15633220 ps
T1267 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3196955480 Apr 18 12:46:48 PM PDT 24 Apr 18 12:46:50 PM PDT 24 32214918 ps
T1268 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3635427555 Apr 18 12:46:37 PM PDT 24 Apr 18 12:46:39 PM PDT 24 175582457 ps
T1269 /workspace/coverage/cover_reg_top/27.uart_intr_test.855256445 Apr 18 12:46:55 PM PDT 24 Apr 18 12:46:57 PM PDT 24 89133686 ps
T1270 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3435997356 Apr 18 12:46:43 PM PDT 24 Apr 18 12:46:45 PM PDT 24 57371080 ps
T1271 /workspace/coverage/cover_reg_top/5.uart_csr_rw.2884889358 Apr 18 12:46:39 PM PDT 24 Apr 18 12:46:41 PM PDT 24 63268995 ps
T1272 /workspace/coverage/cover_reg_top/12.uart_intr_test.3646960448 Apr 18 12:46:52 PM PDT 24 Apr 18 12:46:53 PM PDT 24 35179509 ps
T81 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.3766244419 Apr 18 12:46:33 PM PDT 24 Apr 18 12:46:35 PM PDT 24 397787391 ps
T1273 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.229672799 Apr 18 12:46:30 PM PDT 24 Apr 18 12:46:32 PM PDT 24 23440257 ps
T1274 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3406870827 Apr 18 12:46:42 PM PDT 24 Apr 18 12:46:43 PM PDT 24 165900496 ps
T1275 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1521757248 Apr 18 12:46:50 PM PDT 24 Apr 18 12:46:53 PM PDT 24 715925634 ps
T1276 /workspace/coverage/cover_reg_top/5.uart_intr_test.818461580 Apr 18 12:46:48 PM PDT 24 Apr 18 12:46:50 PM PDT 24 18269035 ps
T1277 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.3414861358 Apr 18 12:46:57 PM PDT 24 Apr 18 12:46:59 PM PDT 24 168172937 ps
T1278 /workspace/coverage/cover_reg_top/36.uart_intr_test.2186035537 Apr 18 12:46:57 PM PDT 24 Apr 18 12:46:59 PM PDT 24 17576340 ps
T1279 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1864753841 Apr 18 12:47:01 PM PDT 24 Apr 18 12:47:03 PM PDT 24 16018122 ps
T1280 /workspace/coverage/cover_reg_top/6.uart_csr_rw.3834839915 Apr 18 12:46:36 PM PDT 24 Apr 18 12:46:37 PM PDT 24 36211954 ps
T1281 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3891268622 Apr 18 12:46:42 PM PDT 24 Apr 18 12:46:44 PM PDT 24 28092565 ps
T1282 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3009593293 Apr 18 12:46:28 PM PDT 24 Apr 18 12:46:30 PM PDT 24 202589972 ps
T1283 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.745310582 Apr 18 12:47:03 PM PDT 24 Apr 18 12:47:05 PM PDT 24 58153178 ps
T1284 /workspace/coverage/cover_reg_top/44.uart_intr_test.505747669 Apr 18 12:46:57 PM PDT 24 Apr 18 12:46:59 PM PDT 24 101769257 ps
T1285 /workspace/coverage/cover_reg_top/33.uart_intr_test.499994034 Apr 18 12:46:49 PM PDT 24 Apr 18 12:46:52 PM PDT 24 151621286 ps
T1286 /workspace/coverage/cover_reg_top/42.uart_intr_test.2872372237 Apr 18 12:46:55 PM PDT 24 Apr 18 12:46:56 PM PDT 24 26874149 ps
T1287 /workspace/coverage/cover_reg_top/13.uart_intr_test.678860475 Apr 18 12:46:49 PM PDT 24 Apr 18 12:46:52 PM PDT 24 35226053 ps
T1288 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.791992345 Apr 18 12:46:24 PM PDT 24 Apr 18 12:46:26 PM PDT 24 23828305 ps
T1289 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2805720722 Apr 18 12:46:40 PM PDT 24 Apr 18 12:46:41 PM PDT 24 57979511 ps
T1290 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2476069065 Apr 18 12:46:48 PM PDT 24 Apr 18 12:46:51 PM PDT 24 29968796 ps
T79 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3247191309 Apr 18 12:46:26 PM PDT 24 Apr 18 12:46:29 PM PDT 24 178776995 ps
T1291 /workspace/coverage/cover_reg_top/0.uart_tl_errors.3995197408 Apr 18 12:46:28 PM PDT 24 Apr 18 12:46:30 PM PDT 24 301934475 ps
T1292 /workspace/coverage/cover_reg_top/7.uart_tl_errors.4105297562 Apr 18 12:46:39 PM PDT 24 Apr 18 12:46:42 PM PDT 24 426533646 ps
T1293 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.998689279 Apr 18 12:46:46 PM PDT 24 Apr 18 12:46:48 PM PDT 24 28762794 ps
T1294 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.3850866666 Apr 18 12:46:41 PM PDT 24 Apr 18 12:46:44 PM PDT 24 98032585 ps
T1295 /workspace/coverage/cover_reg_top/4.uart_tl_errors.1406418522 Apr 18 12:46:31 PM PDT 24 Apr 18 12:46:34 PM PDT 24 45131749 ps
T1296 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.515741919 Apr 18 12:46:29 PM PDT 24 Apr 18 12:46:32 PM PDT 24 965881120 ps
T1297 /workspace/coverage/cover_reg_top/47.uart_intr_test.1853114984 Apr 18 12:46:55 PM PDT 24 Apr 18 12:46:57 PM PDT 24 41008100 ps
T1298 /workspace/coverage/cover_reg_top/10.uart_tl_errors.4102927377 Apr 18 12:46:35 PM PDT 24 Apr 18 12:46:38 PM PDT 24 258694365 ps
T1299 /workspace/coverage/cover_reg_top/16.uart_intr_test.3342738339 Apr 18 12:46:48 PM PDT 24 Apr 18 12:46:49 PM PDT 24 52711740 ps
T1300 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.3866636206 Apr 18 12:46:25 PM PDT 24 Apr 18 12:46:28 PM PDT 24 171512362 ps
T1301 /workspace/coverage/cover_reg_top/14.uart_tl_errors.288215525 Apr 18 12:46:47 PM PDT 24 Apr 18 12:46:50 PM PDT 24 382415582 ps
T1302 /workspace/coverage/cover_reg_top/0.uart_intr_test.4014898418 Apr 18 12:46:29 PM PDT 24 Apr 18 12:46:30 PM PDT 24 12808716 ps
T1303 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1488791536 Apr 18 12:46:26 PM PDT 24 Apr 18 12:46:28 PM PDT 24 79439017 ps
T1304 /workspace/coverage/cover_reg_top/28.uart_intr_test.3431030662 Apr 18 12:46:49 PM PDT 24 Apr 18 12:46:52 PM PDT 24 11477547 ps
T1305 /workspace/coverage/cover_reg_top/29.uart_intr_test.327805545 Apr 18 12:46:49 PM PDT 24 Apr 18 12:46:51 PM PDT 24 14314437 ps
T1306 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.4015677015 Apr 18 12:46:38 PM PDT 24 Apr 18 12:46:40 PM PDT 24 101123873 ps
T1307 /workspace/coverage/cover_reg_top/20.uart_intr_test.350484056 Apr 18 12:46:48 PM PDT 24 Apr 18 12:46:49 PM PDT 24 54128088 ps
T1308 /workspace/coverage/cover_reg_top/16.uart_csr_rw.2445092775 Apr 18 12:46:42 PM PDT 24 Apr 18 12:46:44 PM PDT 24 27560948 ps
T1309 /workspace/coverage/cover_reg_top/11.uart_csr_rw.1403112749 Apr 18 12:46:42 PM PDT 24 Apr 18 12:46:44 PM PDT 24 28091996 ps
T1310 /workspace/coverage/cover_reg_top/9.uart_intr_test.501168734 Apr 18 12:46:43 PM PDT 24 Apr 18 12:46:45 PM PDT 24 50511528 ps
T1311 /workspace/coverage/cover_reg_top/40.uart_intr_test.2001556739 Apr 18 12:46:54 PM PDT 24 Apr 18 12:46:56 PM PDT 24 15283761 ps
T1312 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1392791894 Apr 18 12:46:32 PM PDT 24 Apr 18 12:46:34 PM PDT 24 78807165 ps
T1313 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1718057602 Apr 18 12:46:41 PM PDT 24 Apr 18 12:46:42 PM PDT 24 25247026 ps
T1314 /workspace/coverage/cover_reg_top/43.uart_intr_test.1010227748 Apr 18 12:46:54 PM PDT 24 Apr 18 12:47:00 PM PDT 24 18466679 ps
T1315 /workspace/coverage/cover_reg_top/1.uart_csr_rw.4252075344 Apr 18 12:46:24 PM PDT 24 Apr 18 12:46:26 PM PDT 24 12353973 ps
T1316 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3020877724 Apr 18 12:46:49 PM PDT 24 Apr 18 12:46:53 PM PDT 24 288500307 ps
T1317 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.502373940 Apr 18 12:46:47 PM PDT 24 Apr 18 12:46:49 PM PDT 24 33825326 ps

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.2770035295
Short name T5
Test name
Test status
Simulation time 230652855294 ps
CPU time 283.44 seconds
Started Apr 18 01:53:56 PM PDT 24
Finished Apr 18 01:58:40 PM PDT 24
Peak memory 217468 kb
Host smart-ebadd682-453c-44c4-a370-95bbbcb30f36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770035295 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.2770035295
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_stress_all.1490364763
Short name T249
Test name
Test status
Simulation time 287967104597 ps
CPU time 2858.65 seconds
Started Apr 18 01:52:43 PM PDT 24
Finished Apr 18 02:40:23 PM PDT 24
Peak memory 201104 kb
Host smart-93c0eab6-687c-4ba7-8630-81c972639bcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490364763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.1490364763
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.1759608353
Short name T111
Test name
Test status
Simulation time 1531685828149 ps
CPU time 1243.06 seconds
Started Apr 18 01:51:31 PM PDT 24
Finished Apr 18 02:12:15 PM PDT 24
Peak memory 227684 kb
Host smart-e79bdefe-61e0-4e5d-bb69-dcf1dfc1129b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759608353 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.1759608353
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.3934052347
Short name T11
Test name
Test status
Simulation time 220847448005 ps
CPU time 799.95 seconds
Started Apr 18 01:53:55 PM PDT 24
Finished Apr 18 02:07:16 PM PDT 24
Peak memory 217272 kb
Host smart-79422000-882d-449e-b28d-3162e258b092
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934052347 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.3934052347
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_stress_all.1153165894
Short name T122
Test name
Test status
Simulation time 373504143728 ps
CPU time 1273.99 seconds
Started Apr 18 01:51:25 PM PDT 24
Finished Apr 18 02:12:40 PM PDT 24
Peak memory 200792 kb
Host smart-55ab52ae-11c7-455a-8dd8-e960c6eab21c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153165894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.1153165894
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.1640753937
Short name T120
Test name
Test status
Simulation time 344876032904 ps
CPU time 418.34 seconds
Started Apr 18 01:53:51 PM PDT 24
Finished Apr 18 02:00:50 PM PDT 24
Peak memory 217352 kb
Host smart-e3e14dd6-d0be-48e4-9e37-c9274733451f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640753937 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.1640753937
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.480660042
Short name T72
Test name
Test status
Simulation time 319301441707 ps
CPU time 1127.09 seconds
Started Apr 18 01:53:42 PM PDT 24
Finished Apr 18 02:12:29 PM PDT 24
Peak memory 227092 kb
Host smart-0ba9c5a3-168b-40ad-b80b-4a782e0b00bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480660042 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.480660042
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_sec_cm.1576173877
Short name T23
Test name
Test status
Simulation time 36615812 ps
CPU time 0.8 seconds
Started Apr 18 01:51:21 PM PDT 24
Finished Apr 18 01:51:23 PM PDT 24
Peak memory 218632 kb
Host smart-a384ffea-b12e-40cd-af3e-c46eae504dcd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576173877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.1576173877
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/18.uart_intr.3216560354
Short name T12
Test name
Test status
Simulation time 37731736970 ps
CPU time 59.88 seconds
Started Apr 18 01:51:57 PM PDT 24
Finished Apr 18 01:52:57 PM PDT 24
Peak memory 200860 kb
Host smart-7969f7c1-1679-45a0-87dc-7e01974ef2f6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216560354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.3216560354
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/39.uart_stress_all.2093555614
Short name T1
Test name
Test status
Simulation time 367665171425 ps
CPU time 168.03 seconds
Started Apr 18 01:53:03 PM PDT 24
Finished Apr 18 01:55:52 PM PDT 24
Peak memory 216680 kb
Host smart-ad4011c4-55e7-4b10-b178-fa2ec4111663
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093555614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.2093555614
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.3218900132
Short name T118
Test name
Test status
Simulation time 231069840255 ps
CPU time 184.28 seconds
Started Apr 18 01:52:16 PM PDT 24
Finished Apr 18 01:55:20 PM PDT 24
Peak memory 200896 kb
Host smart-3e03a86f-9456-45f0-95d2-fb07ef11bf8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218900132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.3218900132
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.4269157675
Short name T40
Test name
Test status
Simulation time 48567517137 ps
CPU time 365.28 seconds
Started Apr 18 01:51:59 PM PDT 24
Finished Apr 18 01:58:05 PM PDT 24
Peak memory 216520 kb
Host smart-6f542514-198a-45cb-bc45-c1b69b896045
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269157675 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.4269157675
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_fifo_full.1504702978
Short name T121
Test name
Test status
Simulation time 142113453212 ps
CPU time 88.93 seconds
Started Apr 18 01:52:44 PM PDT 24
Finished Apr 18 01:54:13 PM PDT 24
Peak memory 200844 kb
Host smart-74e30533-28c4-4155-9b9b-c56f40d337af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504702978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.1504702978
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_full.2867673137
Short name T116
Test name
Test status
Simulation time 208865502713 ps
CPU time 228.48 seconds
Started Apr 18 01:52:22 PM PDT 24
Finished Apr 18 01:56:11 PM PDT 24
Peak memory 200892 kb
Host smart-f85e4830-5523-47d2-9ce0-4c8f9d80f152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867673137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2867673137
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.4127844141
Short name T82
Test name
Test status
Simulation time 90440881 ps
CPU time 0.92 seconds
Started Apr 18 12:46:44 PM PDT 24
Finished Apr 18 12:46:46 PM PDT 24
Peak memory 198628 kb
Host smart-7cc65bed-b91e-428f-88d3-fb2d36126452
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127844141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.4127844141
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.2925408417
Short name T22
Test name
Test status
Simulation time 41465064 ps
CPU time 0.56 seconds
Started Apr 18 01:51:09 PM PDT 24
Finished Apr 18 01:51:10 PM PDT 24
Peak memory 195632 kb
Host smart-80db479a-60b2-48c7-b1e3-ed971b8a3d86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925408417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2925408417
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.3368619432
Short name T113
Test name
Test status
Simulation time 31796594865 ps
CPU time 61.71 seconds
Started Apr 18 01:53:59 PM PDT 24
Finished Apr 18 01:55:01 PM PDT 24
Peak memory 200844 kb
Host smart-be73415f-2e8a-4472-8999-246cbdc92f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368619432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3368619432
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.2410656206
Short name T47
Test name
Test status
Simulation time 13182504 ps
CPU time 0.6 seconds
Started Apr 18 12:46:36 PM PDT 24
Finished Apr 18 12:46:38 PM PDT 24
Peak memory 195428 kb
Host smart-cbe952cc-e7b2-42b5-95ee-5c77f43d9fa6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410656206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.2410656206
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.2294273687
Short name T29
Test name
Test status
Simulation time 151144464630 ps
CPU time 1031.49 seconds
Started Apr 18 01:51:24 PM PDT 24
Finished Apr 18 02:08:37 PM PDT 24
Peak memory 217340 kb
Host smart-6ec0ff8c-1e63-47d8-9e12-14dba61e0824
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294273687 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.2294273687
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.2043657491
Short name T99
Test name
Test status
Simulation time 1115199332731 ps
CPU time 517.56 seconds
Started Apr 18 01:52:20 PM PDT 24
Finished Apr 18 02:00:59 PM PDT 24
Peak memory 217384 kb
Host smart-04bdf857-13b2-49fd-9a16-243215c84825
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043657491 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.2043657491
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.2280278762
Short name T32
Test name
Test status
Simulation time 69561091097 ps
CPU time 28.9 seconds
Started Apr 18 01:54:32 PM PDT 24
Finished Apr 18 01:55:01 PM PDT 24
Peak memory 200776 kb
Host smart-e3c64fe2-592f-4a4b-a535-4fc956e6889f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280278762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.2280278762
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_stress_all.3532702836
Short name T181
Test name
Test status
Simulation time 931567576537 ps
CPU time 964.41 seconds
Started Apr 18 01:51:33 PM PDT 24
Finished Apr 18 02:07:38 PM PDT 24
Peak memory 200892 kb
Host smart-39c5302e-e4a6-4f52-81b1-eebffecca04d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532702836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.3532702836
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.2952170267
Short name T142
Test name
Test status
Simulation time 83959455147 ps
CPU time 180.43 seconds
Started Apr 18 01:54:10 PM PDT 24
Finished Apr 18 01:57:11 PM PDT 24
Peak memory 200884 kb
Host smart-9889d737-baef-47e4-95f3-a3c11f63f1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952170267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.2952170267
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_stress_all.3287480486
Short name T19
Test name
Test status
Simulation time 385247905023 ps
CPU time 346.83 seconds
Started Apr 18 01:53:19 PM PDT 24
Finished Apr 18 01:59:06 PM PDT 24
Peak memory 216588 kb
Host smart-ba59ab8e-41e7-45e3-a71a-3f5f0a2f6331
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287480486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.3287480486
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.2555539555
Short name T112
Test name
Test status
Simulation time 388527047232 ps
CPU time 596.04 seconds
Started Apr 18 01:52:06 PM PDT 24
Finished Apr 18 02:02:03 PM PDT 24
Peak memory 217356 kb
Host smart-87926cbf-c610-48dd-828f-ebc05e8af0d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555539555 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.2555539555
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.792453162
Short name T138
Test name
Test status
Simulation time 34446445736 ps
CPU time 31.3 seconds
Started Apr 18 01:54:46 PM PDT 24
Finished Apr 18 01:55:18 PM PDT 24
Peak memory 200852 kb
Host smart-4e082f79-7202-420a-adc8-adfb37627645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792453162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.792453162
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.4007379224
Short name T14
Test name
Test status
Simulation time 244650459409 ps
CPU time 96.13 seconds
Started Apr 18 01:53:11 PM PDT 24
Finished Apr 18 01:54:48 PM PDT 24
Peak memory 200828 kb
Host smart-c5cac100-244c-4959-9c52-097d293accbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007379224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.4007379224
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.2625963189
Short name T145
Test name
Test status
Simulation time 152571379727 ps
CPU time 165.35 seconds
Started Apr 18 01:54:29 PM PDT 24
Finished Apr 18 01:57:15 PM PDT 24
Peak memory 200824 kb
Host smart-323d03a5-9001-45c7-8d11-e0ea7b38cba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625963189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.2625963189
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.3766244419
Short name T81
Test name
Test status
Simulation time 397787391 ps
CPU time 1.31 seconds
Started Apr 18 12:46:33 PM PDT 24
Finished Apr 18 12:46:35 PM PDT 24
Peak memory 199380 kb
Host smart-d84415d9-41d6-4a63-bd9d-f88a636a6d80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766244419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.3766244419
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/default/44.uart_perf.492406247
Short name T262
Test name
Test status
Simulation time 13856932961 ps
CPU time 352.81 seconds
Started Apr 18 01:53:20 PM PDT 24
Finished Apr 18 01:59:13 PM PDT 24
Peak memory 200124 kb
Host smart-02ca94d0-9c0f-4a0b-b9d7-32821cd50e11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=492406247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.492406247
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3247191309
Short name T79
Test name
Test status
Simulation time 178776995 ps
CPU time 1.34 seconds
Started Apr 18 12:46:26 PM PDT 24
Finished Apr 18 12:46:29 PM PDT 24
Peak memory 199472 kb
Host smart-ff6f1cdd-6fe1-4630-af72-c0c66d03ed77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247191309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.3247191309
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.2355674583
Short name T166
Test name
Test status
Simulation time 383256533684 ps
CPU time 681.96 seconds
Started Apr 18 01:52:49 PM PDT 24
Finished Apr 18 02:04:12 PM PDT 24
Peak memory 215572 kb
Host smart-e2b9dd0f-c1f6-4461-bcf5-5419c017093f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355674583 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.2355674583
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_stress_all.3135878198
Short name T148
Test name
Test status
Simulation time 484814932988 ps
CPU time 383.64 seconds
Started Apr 18 01:52:54 PM PDT 24
Finished Apr 18 01:59:19 PM PDT 24
Peak memory 200836 kb
Host smart-fdfb59af-c063-4fcc-971b-26df87479663
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135878198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.3135878198
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.4255327383
Short name T54
Test name
Test status
Simulation time 298314295654 ps
CPU time 133.67 seconds
Started Apr 18 01:53:53 PM PDT 24
Finished Apr 18 01:56:07 PM PDT 24
Peak memory 200820 kb
Host smart-16c7414d-d925-4f04-a71e-4738aa2375e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255327383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.4255327383
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.634538158
Short name T3
Test name
Test status
Simulation time 151343896585 ps
CPU time 65.83 seconds
Started Apr 18 01:54:11 PM PDT 24
Finished Apr 18 01:55:18 PM PDT 24
Peak memory 200828 kb
Host smart-db0b730c-33bb-45e9-92c3-ec431390bd4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634538158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.634538158
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.1535772434
Short name T161
Test name
Test status
Simulation time 131049914631 ps
CPU time 156.62 seconds
Started Apr 18 01:54:20 PM PDT 24
Finished Apr 18 01:56:57 PM PDT 24
Peak memory 200812 kb
Host smart-5bb36f8e-a38e-4180-9ccd-6c19616ce9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535772434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.1535772434
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.2775340416
Short name T149
Test name
Test status
Simulation time 56279450200 ps
CPU time 31.17 seconds
Started Apr 18 01:54:32 PM PDT 24
Finished Apr 18 01:55:03 PM PDT 24
Peak memory 200836 kb
Host smart-82cc194a-a1f5-49ec-b15f-e72c8ec2b042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775340416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.2775340416
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.968993189
Short name T140
Test name
Test status
Simulation time 110206160181 ps
CPU time 94.26 seconds
Started Apr 18 01:52:45 PM PDT 24
Finished Apr 18 01:54:21 PM PDT 24
Peak memory 200704 kb
Host smart-5b7afaff-ae7e-4756-92c1-c4a41ae6c4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968993189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.968993189
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.3128367116
Short name T195
Test name
Test status
Simulation time 36402826008 ps
CPU time 25.13 seconds
Started Apr 18 01:54:10 PM PDT 24
Finished Apr 18 01:54:36 PM PDT 24
Peak memory 200828 kb
Host smart-00855945-8920-40b7-8099-db267734e9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128367116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.3128367116
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_fifo_full.1801493148
Short name T401
Test name
Test status
Simulation time 84403108034 ps
CPU time 103.06 seconds
Started Apr 18 01:52:13 PM PDT 24
Finished Apr 18 01:53:57 PM PDT 24
Peak memory 200912 kb
Host smart-605457ac-8470-43c9-927b-c0c74fffa078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801493148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.1801493148
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.3876989191
Short name T176
Test name
Test status
Simulation time 132310041471 ps
CPU time 189.28 seconds
Started Apr 18 01:54:47 PM PDT 24
Finished Apr 18 01:57:57 PM PDT 24
Peak memory 200792 kb
Host smart-bdbe1bc7-2119-4ca2-878f-a0701ed996e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876989191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.3876989191
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.1034652708
Short name T811
Test name
Test status
Simulation time 24466312636 ps
CPU time 34.46 seconds
Started Apr 18 01:54:59 PM PDT 24
Finished Apr 18 01:55:34 PM PDT 24
Peak memory 200872 kb
Host smart-96a8332f-2396-4357-bb5e-892fbd79314e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034652708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.1034652708
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.2583674914
Short name T103
Test name
Test status
Simulation time 256642330822 ps
CPU time 836.07 seconds
Started Apr 18 01:52:52 PM PDT 24
Finished Apr 18 02:06:48 PM PDT 24
Peak memory 216992 kb
Host smart-09a8a8cc-4844-4d11-90fb-0db3a992c969
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583674914 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.2583674914
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_stress_all.800311036
Short name T210
Test name
Test status
Simulation time 231843687697 ps
CPU time 382.38 seconds
Started Apr 18 01:53:25 PM PDT 24
Finished Apr 18 01:59:48 PM PDT 24
Peak memory 200924 kb
Host smart-60c91946-8f68-4a02-9401-c73dab18aa16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800311036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.800311036
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.3303245224
Short name T217
Test name
Test status
Simulation time 34505176900 ps
CPU time 55.6 seconds
Started Apr 18 01:53:57 PM PDT 24
Finished Apr 18 01:54:53 PM PDT 24
Peak memory 200820 kb
Host smart-05836fd2-bda8-4380-81f4-550fd8e34ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303245224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.3303245224
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.1950891811
Short name T759
Test name
Test status
Simulation time 224318157189 ps
CPU time 804.82 seconds
Started Apr 18 01:52:15 PM PDT 24
Finished Apr 18 02:05:40 PM PDT 24
Peak memory 225808 kb
Host smart-c3ab736d-5721-451c-b31a-8f94d7185c61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950891811 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.1950891811
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.1737838097
Short name T231
Test name
Test status
Simulation time 217733682438 ps
CPU time 42.22 seconds
Started Apr 18 01:54:23 PM PDT 24
Finished Apr 18 01:55:06 PM PDT 24
Peak memory 200828 kb
Host smart-b3a42f28-fb1e-4289-9514-eb1792dc1a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737838097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.1737838097
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.3304413208
Short name T920
Test name
Test status
Simulation time 142324162568 ps
CPU time 110.65 seconds
Started Apr 18 01:54:35 PM PDT 24
Finished Apr 18 01:56:26 PM PDT 24
Peak memory 200856 kb
Host smart-b26dcffd-ea94-4f9f-b5a5-123f80ffaf2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304413208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.3304413208
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.1164325842
Short name T141
Test name
Test status
Simulation time 75182837658 ps
CPU time 37.15 seconds
Started Apr 18 01:54:46 PM PDT 24
Finished Apr 18 01:55:24 PM PDT 24
Peak memory 200824 kb
Host smart-5a1986ed-813f-4650-ad15-f09ce55351ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164325842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.1164325842
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.1942405167
Short name T242
Test name
Test status
Simulation time 33414838861 ps
CPU time 93.06 seconds
Started Apr 18 01:54:48 PM PDT 24
Finished Apr 18 01:56:21 PM PDT 24
Peak memory 200920 kb
Host smart-5e0be467-cb35-4fa5-b2cd-24eb181da90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942405167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.1942405167
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.1425141920
Short name T198
Test name
Test status
Simulation time 101511646925 ps
CPU time 304.92 seconds
Started Apr 18 01:53:57 PM PDT 24
Finished Apr 18 01:59:03 PM PDT 24
Peak memory 200852 kb
Host smart-006159fa-b418-4e08-b973-917c4916ceb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425141920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.1425141920
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.3669592393
Short name T882
Test name
Test status
Simulation time 182384369728 ps
CPU time 25.01 seconds
Started Apr 18 01:52:11 PM PDT 24
Finished Apr 18 01:52:37 PM PDT 24
Peak memory 200796 kb
Host smart-3ddd751a-c751-4801-938d-c8a87f6c1319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669592393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.3669592393
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.1631917056
Short name T208
Test name
Test status
Simulation time 85796138679 ps
CPU time 71.09 seconds
Started Apr 18 01:54:13 PM PDT 24
Finished Apr 18 01:55:24 PM PDT 24
Peak memory 200900 kb
Host smart-e7480c2e-4202-45c7-8f83-8899cba0084f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631917056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.1631917056
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.2851187360
Short name T230
Test name
Test status
Simulation time 125763280736 ps
CPU time 33.6 seconds
Started Apr 18 01:54:12 PM PDT 24
Finished Apr 18 01:54:46 PM PDT 24
Peak memory 200904 kb
Host smart-6addf18a-110f-4dc1-a97e-f86a1f0427f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851187360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.2851187360
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.3342221339
Short name T134
Test name
Test status
Simulation time 48720080415 ps
CPU time 24.82 seconds
Started Apr 18 01:54:11 PM PDT 24
Finished Apr 18 01:54:37 PM PDT 24
Peak memory 200844 kb
Host smart-1da78e23-d7a2-4138-8d6c-75e2f8a4da42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342221339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.3342221339
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.2612684354
Short name T187
Test name
Test status
Simulation time 102618489330 ps
CPU time 25.11 seconds
Started Apr 18 01:54:11 PM PDT 24
Finished Apr 18 01:54:37 PM PDT 24
Peak memory 200788 kb
Host smart-e329a9d4-6434-43e4-b008-58d5b305df7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612684354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.2612684354
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.828494530
Short name T202
Test name
Test status
Simulation time 102820475702 ps
CPU time 69.02 seconds
Started Apr 18 01:54:11 PM PDT 24
Finished Apr 18 01:55:20 PM PDT 24
Peak memory 200880 kb
Host smart-845138d4-3146-45fb-b5ea-22b7d91159e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828494530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.828494530
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.4239286729
Short name T211
Test name
Test status
Simulation time 118812732603 ps
CPU time 17.92 seconds
Started Apr 18 01:54:13 PM PDT 24
Finished Apr 18 01:54:31 PM PDT 24
Peak memory 200856 kb
Host smart-74df0a7c-6a92-457c-b957-44276cd018ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239286729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.4239286729
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.1377804806
Short name T221
Test name
Test status
Simulation time 39427844813 ps
CPU time 32.03 seconds
Started Apr 18 01:54:17 PM PDT 24
Finished Apr 18 01:54:50 PM PDT 24
Peak memory 200872 kb
Host smart-dd560935-b10d-4524-8a5b-4021236362ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377804806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.1377804806
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.3937348699
Short name T226
Test name
Test status
Simulation time 13389999049 ps
CPU time 42.18 seconds
Started Apr 18 01:54:31 PM PDT 24
Finished Apr 18 01:55:14 PM PDT 24
Peak memory 200824 kb
Host smart-8ae8042a-cd4b-46b7-be59-a30b09a203fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937348699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.3937348699
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_stress_all.4061683103
Short name T159
Test name
Test status
Simulation time 372494822433 ps
CPU time 197.14 seconds
Started Apr 18 01:51:25 PM PDT 24
Finished Apr 18 01:54:43 PM PDT 24
Peak memory 200864 kb
Host smart-3d848825-4f7d-4310-979d-0818a0295a07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061683103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.4061683103
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.392953118
Short name T225
Test name
Test status
Simulation time 43701579016 ps
CPU time 21.75 seconds
Started Apr 18 01:54:26 PM PDT 24
Finished Apr 18 01:54:48 PM PDT 24
Peak memory 200816 kb
Host smart-a3e0debe-1420-47af-87c8-ce29e248933f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392953118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.392953118
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.2974820417
Short name T243
Test name
Test status
Simulation time 52190928723 ps
CPU time 37.4 seconds
Started Apr 18 01:54:35 PM PDT 24
Finished Apr 18 01:55:13 PM PDT 24
Peak memory 200776 kb
Host smart-3f54c123-e2f9-4407-9947-cffa2047d0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974820417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.2974820417
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.3457183774
Short name T237
Test name
Test status
Simulation time 155306003918 ps
CPU time 239.18 seconds
Started Apr 18 01:54:31 PM PDT 24
Finished Apr 18 01:58:31 PM PDT 24
Peak memory 200856 kb
Host smart-f53a8e75-453e-455e-ab04-879aee039e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457183774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.3457183774
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.1605087279
Short name T214
Test name
Test status
Simulation time 81763732724 ps
CPU time 76.33 seconds
Started Apr 18 01:54:31 PM PDT 24
Finished Apr 18 01:55:48 PM PDT 24
Peak memory 200856 kb
Host smart-95d69ed2-6542-4912-8ed6-f46e4352eafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605087279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1605087279
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.305262311
Short name T191
Test name
Test status
Simulation time 112860787971 ps
CPU time 32.02 seconds
Started Apr 18 01:54:41 PM PDT 24
Finished Apr 18 01:55:13 PM PDT 24
Peak memory 200872 kb
Host smart-15682159-a6c0-4ec8-88dd-02eb56d53bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305262311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.305262311
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.2432924943
Short name T240
Test name
Test status
Simulation time 17108790781 ps
CPU time 32.01 seconds
Started Apr 18 01:54:47 PM PDT 24
Finished Apr 18 01:55:19 PM PDT 24
Peak memory 200868 kb
Host smart-4b80db25-daf9-4b78-a2b2-0a9d357926b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432924943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.2432924943
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.3928817132
Short name T235
Test name
Test status
Simulation time 172348597933 ps
CPU time 125.76 seconds
Started Apr 18 01:54:50 PM PDT 24
Finished Apr 18 01:56:57 PM PDT 24
Peak memory 200836 kb
Host smart-335ca562-d6ab-4b2f-b63d-99d980c95404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928817132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.3928817132
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.703171581
Short name T247
Test name
Test status
Simulation time 41205613882 ps
CPU time 14.68 seconds
Started Apr 18 01:54:54 PM PDT 24
Finished Apr 18 01:55:09 PM PDT 24
Peak memory 200596 kb
Host smart-de1044d4-c710-4d34-85c6-b23995e1c9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703171581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.703171581
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.3231923639
Short name T244
Test name
Test status
Simulation time 29637693623 ps
CPU time 64.02 seconds
Started Apr 18 01:53:51 PM PDT 24
Finished Apr 18 01:54:55 PM PDT 24
Peak memory 200764 kb
Host smart-185248c9-ac53-4de4-82ee-283f354910a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231923639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.3231923639
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1488791536
Short name T1303
Test name
Test status
Simulation time 79439017 ps
CPU time 0.66 seconds
Started Apr 18 12:46:26 PM PDT 24
Finished Apr 18 12:46:28 PM PDT 24
Peak memory 195476 kb
Host smart-ca64d11e-2abb-4bed-8966-09e885a5cf09
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488791536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.1488791536
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.3866636206
Short name T1300
Test name
Test status
Simulation time 171512362 ps
CPU time 2.53 seconds
Started Apr 18 12:46:25 PM PDT 24
Finished Apr 18 12:46:28 PM PDT 24
Peak memory 197776 kb
Host smart-c7bd08eb-22b6-4c5f-adfb-a6e85402b423
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866636206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.3866636206
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3602910074
Short name T1178
Test name
Test status
Simulation time 51492508 ps
CPU time 0.58 seconds
Started Apr 18 12:46:31 PM PDT 24
Finished Apr 18 12:46:32 PM PDT 24
Peak memory 195420 kb
Host smart-b557d14c-fe13-46da-b3ac-a52ee2c38417
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602910074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.3602910074
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1080479937
Short name T1203
Test name
Test status
Simulation time 28689910 ps
CPU time 1.1 seconds
Started Apr 18 12:46:26 PM PDT 24
Finished Apr 18 12:46:28 PM PDT 24
Peak memory 200168 kb
Host smart-fbe674ac-2ec4-46d5-a6f7-55a30712a0cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080479937 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.1080479937
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.3829849519
Short name T1207
Test name
Test status
Simulation time 41845909 ps
CPU time 0.57 seconds
Started Apr 18 12:46:25 PM PDT 24
Finished Apr 18 12:46:26 PM PDT 24
Peak memory 195392 kb
Host smart-36961fdf-c758-443a-8a54-87f0e3441f1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829849519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.3829849519
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.4014898418
Short name T1302
Test name
Test status
Simulation time 12808716 ps
CPU time 0.58 seconds
Started Apr 18 12:46:29 PM PDT 24
Finished Apr 18 12:46:30 PM PDT 24
Peak memory 194444 kb
Host smart-00ad11fd-847a-4a39-8e16-3b9a173dbd20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014898418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.4014898418
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.501511454
Short name T1202
Test name
Test status
Simulation time 21308079 ps
CPU time 0.66 seconds
Started Apr 18 12:46:26 PM PDT 24
Finished Apr 18 12:46:28 PM PDT 24
Peak memory 195748 kb
Host smart-a485c4f8-b073-4ddc-9b55-28c2d8c134d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501511454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_
outstanding.501511454
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.3995197408
Short name T1291
Test name
Test status
Simulation time 301934475 ps
CPU time 1.89 seconds
Started Apr 18 12:46:28 PM PDT 24
Finished Apr 18 12:46:30 PM PDT 24
Peak memory 200132 kb
Host smart-b06e373e-83a5-4398-aedf-10fe92ed063f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995197408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.3995197408
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2383977055
Short name T83
Test name
Test status
Simulation time 78274766 ps
CPU time 0.92 seconds
Started Apr 18 12:46:31 PM PDT 24
Finished Apr 18 12:46:34 PM PDT 24
Peak memory 198528 kb
Host smart-afb16f28-7a3c-429f-b1de-f76b177bb42c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383977055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2383977055
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3128477961
Short name T1186
Test name
Test status
Simulation time 21387934 ps
CPU time 0.71 seconds
Started Apr 18 12:46:27 PM PDT 24
Finished Apr 18 12:46:28 PM PDT 24
Peak memory 195348 kb
Host smart-ac0aed7b-cba9-4aa7-bdee-5a7040cceb3c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128477961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.3128477961
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2470315510
Short name T1185
Test name
Test status
Simulation time 35579871 ps
CPU time 1.34 seconds
Started Apr 18 12:46:30 PM PDT 24
Finished Apr 18 12:46:33 PM PDT 24
Peak memory 197668 kb
Host smart-e19decb4-2900-4d27-9240-e5c3ece9c3d1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470315510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.2470315510
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3936204994
Short name T1231
Test name
Test status
Simulation time 27276255 ps
CPU time 0.6 seconds
Started Apr 18 12:46:28 PM PDT 24
Finished Apr 18 12:46:29 PM PDT 24
Peak memory 195312 kb
Host smart-c09be537-6129-4cf3-9a3a-be212669ec59
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936204994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.3936204994
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3009593293
Short name T1282
Test name
Test status
Simulation time 202589972 ps
CPU time 0.75 seconds
Started Apr 18 12:46:28 PM PDT 24
Finished Apr 18 12:46:30 PM PDT 24
Peak memory 199872 kb
Host smart-dc22efc0-5631-4751-a495-e1e84bcbd63f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009593293 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.3009593293
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.4252075344
Short name T1315
Test name
Test status
Simulation time 12353973 ps
CPU time 0.56 seconds
Started Apr 18 12:46:24 PM PDT 24
Finished Apr 18 12:46:26 PM PDT 24
Peak memory 195460 kb
Host smart-5baeff85-302c-43de-8261-77517d5d0a87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252075344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.4252075344
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.371715390
Short name T1188
Test name
Test status
Simulation time 53201647 ps
CPU time 0.54 seconds
Started Apr 18 12:46:28 PM PDT 24
Finished Apr 18 12:46:30 PM PDT 24
Peak memory 194468 kb
Host smart-e6a0e4d0-c31a-4239-9c80-00bcf1b88496
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371715390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.371715390
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2415424112
Short name T67
Test name
Test status
Simulation time 17591393 ps
CPU time 0.77 seconds
Started Apr 18 12:46:30 PM PDT 24
Finished Apr 18 12:46:32 PM PDT 24
Peak memory 197236 kb
Host smart-267c48ed-16e5-41b1-9859-fe4a232ee26e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415424112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.2415424112
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.1108066915
Short name T1245
Test name
Test status
Simulation time 473270964 ps
CPU time 1.9 seconds
Started Apr 18 12:46:30 PM PDT 24
Finished Apr 18 12:46:34 PM PDT 24
Peak memory 200016 kb
Host smart-f326a295-ee03-4154-87da-76b28f64b270
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108066915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.1108066915
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2527924136
Short name T1230
Test name
Test status
Simulation time 44232417 ps
CPU time 1.1 seconds
Started Apr 18 12:46:36 PM PDT 24
Finished Apr 18 12:46:38 PM PDT 24
Peak memory 200108 kb
Host smart-85943da3-a881-452c-a717-a72c733107e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527924136 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.2527924136
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.859857356
Short name T1261
Test name
Test status
Simulation time 40889476 ps
CPU time 0.61 seconds
Started Apr 18 12:46:37 PM PDT 24
Finished Apr 18 12:46:39 PM PDT 24
Peak memory 195500 kb
Host smart-ef5918ef-4ec3-4f8a-a6a2-0c8108f8ba29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859857356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.859857356
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.3728123700
Short name T1189
Test name
Test status
Simulation time 12802369 ps
CPU time 0.58 seconds
Started Apr 18 12:46:44 PM PDT 24
Finished Apr 18 12:46:46 PM PDT 24
Peak memory 194340 kb
Host smart-8bc0b698-bd6e-4695-bf3f-9afbe54b04a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728123700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.3728123700
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2956869388
Short name T1243
Test name
Test status
Simulation time 26826762 ps
CPU time 0.7 seconds
Started Apr 18 12:46:48 PM PDT 24
Finished Apr 18 12:46:51 PM PDT 24
Peak memory 196428 kb
Host smart-b568e360-e567-46c6-842f-02157744208c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956869388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.2956869388
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.4102927377
Short name T1298
Test name
Test status
Simulation time 258694365 ps
CPU time 2.18 seconds
Started Apr 18 12:46:35 PM PDT 24
Finished Apr 18 12:46:38 PM PDT 24
Peak memory 199956 kb
Host smart-512470e6-1f03-4da4-8e7e-2ff582b4db25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102927377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.4102927377
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1855816616
Short name T1211
Test name
Test status
Simulation time 512815550 ps
CPU time 1.61 seconds
Started Apr 18 12:46:35 PM PDT 24
Finished Apr 18 12:46:38 PM PDT 24
Peak memory 199224 kb
Host smart-16051b07-0762-4731-aadc-f432ae0cc979
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855816616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.1855816616
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.527630886
Short name T1209
Test name
Test status
Simulation time 19919664 ps
CPU time 1.03 seconds
Started Apr 18 12:46:52 PM PDT 24
Finished Apr 18 12:46:54 PM PDT 24
Peak memory 199864 kb
Host smart-d3f9ea0b-1fda-4660-b498-6edd253faed9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527630886 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.527630886
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.1403112749
Short name T1309
Test name
Test status
Simulation time 28091996 ps
CPU time 0.55 seconds
Started Apr 18 12:46:42 PM PDT 24
Finished Apr 18 12:46:44 PM PDT 24
Peak memory 195452 kb
Host smart-c09934b6-ecd0-4774-a907-e693d1867bb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403112749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.1403112749
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.2279982310
Short name T1179
Test name
Test status
Simulation time 36590980 ps
CPU time 0.56 seconds
Started Apr 18 12:46:43 PM PDT 24
Finished Apr 18 12:46:45 PM PDT 24
Peak memory 194436 kb
Host smart-491f2f98-0547-48bd-aadd-d7fdadde8781
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279982310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.2279982310
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3435997356
Short name T1270
Test name
Test status
Simulation time 57371080 ps
CPU time 0.69 seconds
Started Apr 18 12:46:43 PM PDT 24
Finished Apr 18 12:46:45 PM PDT 24
Peak memory 196908 kb
Host smart-fa5f98dc-5ba2-4d11-b313-86681a89e32b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435997356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.3435997356
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.1035215374
Short name T1213
Test name
Test status
Simulation time 142527132 ps
CPU time 1.89 seconds
Started Apr 18 12:46:37 PM PDT 24
Finished Apr 18 12:46:40 PM PDT 24
Peak memory 200144 kb
Host smart-edef83db-dcd3-445a-bbb4-adc9cb9fefed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035215374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.1035215374
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.4267202542
Short name T110
Test name
Test status
Simulation time 179977822 ps
CPU time 1.24 seconds
Started Apr 18 12:46:42 PM PDT 24
Finished Apr 18 12:46:44 PM PDT 24
Peak memory 199316 kb
Host smart-a4b1cc69-ab69-4814-9892-5ed093c66755
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267202542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.4267202542
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.400501785
Short name T1247
Test name
Test status
Simulation time 101664064 ps
CPU time 1.27 seconds
Started Apr 18 12:46:43 PM PDT 24
Finished Apr 18 12:46:46 PM PDT 24
Peak memory 199972 kb
Host smart-626b927d-f538-43be-bb31-0707991209fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400501785 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.400501785
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.1206581098
Short name T1199
Test name
Test status
Simulation time 35053154 ps
CPU time 0.61 seconds
Started Apr 18 12:46:43 PM PDT 24
Finished Apr 18 12:46:45 PM PDT 24
Peak memory 195560 kb
Host smart-bb19ec9b-e4d6-48de-a9b3-00c364a800dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206581098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.1206581098
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.3646960448
Short name T1272
Test name
Test status
Simulation time 35179509 ps
CPU time 0.59 seconds
Started Apr 18 12:46:52 PM PDT 24
Finished Apr 18 12:46:53 PM PDT 24
Peak memory 194436 kb
Host smart-bfab4504-a0c1-4e27-91b2-b5339576ee91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646960448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.3646960448
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3817213853
Short name T66
Test name
Test status
Simulation time 32282394 ps
CPU time 0.8 seconds
Started Apr 18 12:46:45 PM PDT 24
Finished Apr 18 12:46:47 PM PDT 24
Peak memory 196344 kb
Host smart-a6bb246b-6ed5-41a1-be02-11cd3943d3d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817213853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.3817213853
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.62170848
Short name T1228
Test name
Test status
Simulation time 795571371 ps
CPU time 1.17 seconds
Started Apr 18 12:46:42 PM PDT 24
Finished Apr 18 12:46:44 PM PDT 24
Peak memory 200156 kb
Host smart-396f7749-75f3-43b6-b6c4-9814af74263e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62170848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.62170848
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3406870827
Short name T1274
Test name
Test status
Simulation time 165900496 ps
CPU time 0.89 seconds
Started Apr 18 12:46:42 PM PDT 24
Finished Apr 18 12:46:43 PM PDT 24
Peak memory 198708 kb
Host smart-9638c660-ba15-4892-a67d-3799388d2f14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406870827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3406870827
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.654749874
Short name T1260
Test name
Test status
Simulation time 30102017 ps
CPU time 0.62 seconds
Started Apr 18 12:47:00 PM PDT 24
Finished Apr 18 12:47:01 PM PDT 24
Peak memory 197200 kb
Host smart-15ed8951-76f6-4cb6-aed4-10a853361a63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654749874 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.654749874
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.4145732584
Short name T65
Test name
Test status
Simulation time 11819681 ps
CPU time 0.62 seconds
Started Apr 18 12:46:45 PM PDT 24
Finished Apr 18 12:46:47 PM PDT 24
Peak memory 195440 kb
Host smart-cddc9aed-f3f3-4833-a91c-e73f1a36c24e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145732584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.4145732584
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.678860475
Short name T1287
Test name
Test status
Simulation time 35226053 ps
CPU time 0.55 seconds
Started Apr 18 12:46:49 PM PDT 24
Finished Apr 18 12:46:52 PM PDT 24
Peak memory 194392 kb
Host smart-671fd19c-fe75-4492-a618-f05350a5b35b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678860475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.678860475
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1718057602
Short name T1313
Test name
Test status
Simulation time 25247026 ps
CPU time 0.66 seconds
Started Apr 18 12:46:41 PM PDT 24
Finished Apr 18 12:46:42 PM PDT 24
Peak memory 195780 kb
Host smart-4392b088-5109-4b56-8a5a-1b82050b1f26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718057602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.1718057602
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.2600653606
Short name T1242
Test name
Test status
Simulation time 147112630 ps
CPU time 2.15 seconds
Started Apr 18 12:46:44 PM PDT 24
Finished Apr 18 12:46:47 PM PDT 24
Peak memory 200064 kb
Host smart-e39761fa-bc70-42a4-9240-8b939a13ca54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600653606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.2600653606
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.607640383
Short name T84
Test name
Test status
Simulation time 423196367 ps
CPU time 1.33 seconds
Started Apr 18 12:46:43 PM PDT 24
Finished Apr 18 12:46:45 PM PDT 24
Peak memory 199396 kb
Host smart-6f7fead2-8ace-4de8-a4cf-1662ea50403b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607640383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.607640383
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3138610538
Short name T1234
Test name
Test status
Simulation time 28667283 ps
CPU time 0.9 seconds
Started Apr 18 12:46:45 PM PDT 24
Finished Apr 18 12:46:47 PM PDT 24
Peak memory 199800 kb
Host smart-fd90294b-298c-4cf3-9ffa-26c061f24432
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138610538 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.3138610538
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.3367917248
Short name T49
Test name
Test status
Simulation time 12411728 ps
CPU time 0.58 seconds
Started Apr 18 12:46:43 PM PDT 24
Finished Apr 18 12:46:45 PM PDT 24
Peak memory 195392 kb
Host smart-f07364c6-b330-447d-ac8d-aa2da0acbd58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367917248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.3367917248
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.3806257919
Short name T1208
Test name
Test status
Simulation time 31575999 ps
CPU time 0.56 seconds
Started Apr 18 12:46:49 PM PDT 24
Finished Apr 18 12:46:52 PM PDT 24
Peak memory 194360 kb
Host smart-062a28ab-9b35-4a4e-8785-af39d1370fc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806257919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.3806257919
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3194257839
Short name T1232
Test name
Test status
Simulation time 113174036 ps
CPU time 0.73 seconds
Started Apr 18 12:46:43 PM PDT 24
Finished Apr 18 12:46:46 PM PDT 24
Peak memory 197220 kb
Host smart-ff45dd6d-c268-451e-8028-2853e234c09a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194257839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.3194257839
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.288215525
Short name T1301
Test name
Test status
Simulation time 382415582 ps
CPU time 2.16 seconds
Started Apr 18 12:46:47 PM PDT 24
Finished Apr 18 12:46:50 PM PDT 24
Peak memory 199984 kb
Host smart-928abefe-d06b-4cc7-81f5-5f8cc8469c8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288215525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.288215525
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3076347269
Short name T78
Test name
Test status
Simulation time 105948411 ps
CPU time 1.34 seconds
Started Apr 18 12:46:47 PM PDT 24
Finished Apr 18 12:46:49 PM PDT 24
Peak memory 199476 kb
Host smart-7772dfba-584a-4653-8922-d0359bee52ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076347269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3076347269
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.998689279
Short name T1293
Test name
Test status
Simulation time 28762794 ps
CPU time 1.13 seconds
Started Apr 18 12:46:46 PM PDT 24
Finished Apr 18 12:46:48 PM PDT 24
Peak memory 199996 kb
Host smart-799fb518-5c7a-448e-a19e-359ae4abf341
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998689279 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.998689279
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.770004744
Short name T68
Test name
Test status
Simulation time 34089100 ps
CPU time 0.59 seconds
Started Apr 18 12:46:51 PM PDT 24
Finished Apr 18 12:46:53 PM PDT 24
Peak memory 195456 kb
Host smart-f368d893-6d9d-4c80-b019-bd5207420491
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770004744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.770004744
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.3577451573
Short name T1195
Test name
Test status
Simulation time 23780803 ps
CPU time 0.55 seconds
Started Apr 18 12:46:48 PM PDT 24
Finished Apr 18 12:46:49 PM PDT 24
Peak memory 194220 kb
Host smart-169bef9e-a51d-401c-b240-6b121248c72c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577451573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.3577451573
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3287489157
Short name T1215
Test name
Test status
Simulation time 53365821 ps
CPU time 0.77 seconds
Started Apr 18 12:46:45 PM PDT 24
Finished Apr 18 12:46:47 PM PDT 24
Peak memory 197708 kb
Host smart-a0ef4f0f-d304-4c60-bc10-511755a1f6f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287489157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.3287489157
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.2656134980
Short name T1192
Test name
Test status
Simulation time 90223164 ps
CPU time 1.48 seconds
Started Apr 18 12:46:51 PM PDT 24
Finished Apr 18 12:46:54 PM PDT 24
Peak memory 200120 kb
Host smart-d91a53a9-9506-46ae-83f2-177715feb5f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656134980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.2656134980
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.3850866666
Short name T1294
Test name
Test status
Simulation time 98032585 ps
CPU time 1.35 seconds
Started Apr 18 12:46:41 PM PDT 24
Finished Apr 18 12:46:44 PM PDT 24
Peak memory 199384 kb
Host smart-cb2f2b36-5b32-4794-931b-f98b2e3e6a18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850866666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.3850866666
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3891268622
Short name T1281
Test name
Test status
Simulation time 28092565 ps
CPU time 0.73 seconds
Started Apr 18 12:46:42 PM PDT 24
Finished Apr 18 12:46:44 PM PDT 24
Peak memory 199068 kb
Host smart-bcfe0090-150a-4f6c-b677-932526fa0a0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891268622 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.3891268622
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.2445092775
Short name T1308
Test name
Test status
Simulation time 27560948 ps
CPU time 0.6 seconds
Started Apr 18 12:46:42 PM PDT 24
Finished Apr 18 12:46:44 PM PDT 24
Peak memory 195436 kb
Host smart-f29fe3fa-9015-4ba4-9b74-836a50a6de4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445092775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.2445092775
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.3342738339
Short name T1299
Test name
Test status
Simulation time 52711740 ps
CPU time 0.57 seconds
Started Apr 18 12:46:48 PM PDT 24
Finished Apr 18 12:46:49 PM PDT 24
Peak memory 194252 kb
Host smart-c617e9ef-d519-45a5-b1bb-3948b6f375d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342738339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.3342738339
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2805720722
Short name T1289
Test name
Test status
Simulation time 57979511 ps
CPU time 0.72 seconds
Started Apr 18 12:46:40 PM PDT 24
Finished Apr 18 12:46:41 PM PDT 24
Peak memory 196080 kb
Host smart-07353d88-5da1-4afa-8260-be9c215c436d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805720722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.2805720722
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.1843483973
Short name T1235
Test name
Test status
Simulation time 338961601 ps
CPU time 1.9 seconds
Started Apr 18 12:46:48 PM PDT 24
Finished Apr 18 12:46:50 PM PDT 24
Peak memory 200008 kb
Host smart-0a890480-b246-4d54-ac82-2ee092cce31c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843483973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.1843483973
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3020877724
Short name T1316
Test name
Test status
Simulation time 288500307 ps
CPU time 1.3 seconds
Started Apr 18 12:46:49 PM PDT 24
Finished Apr 18 12:46:53 PM PDT 24
Peak memory 199376 kb
Host smart-bf2c8d3e-e805-4a28-bad4-b81b4edadce0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020877724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3020877724
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.745310582
Short name T1283
Test name
Test status
Simulation time 58153178 ps
CPU time 0.66 seconds
Started Apr 18 12:47:03 PM PDT 24
Finished Apr 18 12:47:05 PM PDT 24
Peak memory 197336 kb
Host smart-6edd53f1-49e5-431b-9081-54650ebc938e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745310582 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.745310582
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.2413769400
Short name T1198
Test name
Test status
Simulation time 25800269 ps
CPU time 0.62 seconds
Started Apr 18 12:46:44 PM PDT 24
Finished Apr 18 12:46:46 PM PDT 24
Peak memory 195600 kb
Host smart-33f69689-6747-46c8-847f-8690cf2208ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413769400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.2413769400
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.676428960
Short name T1241
Test name
Test status
Simulation time 18426778 ps
CPU time 0.63 seconds
Started Apr 18 12:47:01 PM PDT 24
Finished Apr 18 12:47:03 PM PDT 24
Peak memory 194380 kb
Host smart-05b39e5c-c044-4140-9688-9e1a0099d4f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676428960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.676428960
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.451129680
Short name T69
Test name
Test status
Simulation time 14612509 ps
CPU time 0.68 seconds
Started Apr 18 12:46:50 PM PDT 24
Finished Apr 18 12:46:53 PM PDT 24
Peak memory 195804 kb
Host smart-086befe9-3265-4729-a934-ee96fcf250bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451129680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr
_outstanding.451129680
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.1643319443
Short name T1248
Test name
Test status
Simulation time 221226462 ps
CPU time 1.98 seconds
Started Apr 18 12:46:41 PM PDT 24
Finished Apr 18 12:46:43 PM PDT 24
Peak memory 200004 kb
Host smart-4f32b608-d7be-4700-8775-77d86929c4cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643319443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.1643319443
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.331475689
Short name T77
Test name
Test status
Simulation time 630542105 ps
CPU time 0.92 seconds
Started Apr 18 12:46:42 PM PDT 24
Finished Apr 18 12:46:44 PM PDT 24
Peak memory 198888 kb
Host smart-272a82c4-fcf5-428b-8040-2541bdc2cd56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331475689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.331475689
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.324386815
Short name T1264
Test name
Test status
Simulation time 22615143 ps
CPU time 0.81 seconds
Started Apr 18 12:46:50 PM PDT 24
Finished Apr 18 12:46:53 PM PDT 24
Peak memory 199720 kb
Host smart-cf6ea9cc-f23f-4821-a71f-8f1445da9784
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324386815 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.324386815
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.3853398750
Short name T70
Test name
Test status
Simulation time 25107186 ps
CPU time 0.59 seconds
Started Apr 18 12:46:49 PM PDT 24
Finished Apr 18 12:46:52 PM PDT 24
Peak memory 195340 kb
Host smart-051f29c7-165d-4b77-b0b6-3d20b6d55f0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853398750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3853398750
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.346139771
Short name T1212
Test name
Test status
Simulation time 34383290 ps
CPU time 0.58 seconds
Started Apr 18 12:46:50 PM PDT 24
Finished Apr 18 12:46:53 PM PDT 24
Peak memory 194376 kb
Host smart-cbdb2f69-812e-4b69-9b51-55eaef2ccfe3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346139771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.346139771
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3196955480
Short name T1267
Test name
Test status
Simulation time 32214918 ps
CPU time 0.62 seconds
Started Apr 18 12:46:48 PM PDT 24
Finished Apr 18 12:46:50 PM PDT 24
Peak memory 195896 kb
Host smart-f57ed368-9bbe-4ed1-b484-30fec536131b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196955480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.3196955480
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.3372378321
Short name T1187
Test name
Test status
Simulation time 66862552 ps
CPU time 0.94 seconds
Started Apr 18 12:46:56 PM PDT 24
Finished Apr 18 12:46:59 PM PDT 24
Peak memory 199668 kb
Host smart-045cab05-e08f-4882-9ee0-5910ee7a9406
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372378321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.3372378321
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1521757248
Short name T1275
Test name
Test status
Simulation time 715925634 ps
CPU time 1.37 seconds
Started Apr 18 12:46:50 PM PDT 24
Finished Apr 18 12:46:53 PM PDT 24
Peak memory 199244 kb
Host smart-b670f979-6425-45c6-acc3-e4ba774d4c1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521757248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1521757248
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3916693996
Short name T1251
Test name
Test status
Simulation time 19402265 ps
CPU time 0.81 seconds
Started Apr 18 12:46:49 PM PDT 24
Finished Apr 18 12:46:52 PM PDT 24
Peak memory 199848 kb
Host smart-ee92bfbf-e4aa-4378-87e3-73195db22f31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916693996 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.3916693996
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.3486085378
Short name T1244
Test name
Test status
Simulation time 21956675 ps
CPU time 0.6 seconds
Started Apr 18 12:46:50 PM PDT 24
Finished Apr 18 12:46:52 PM PDT 24
Peak memory 195528 kb
Host smart-ce79e3c2-97f5-4d4b-a948-7c6b630b3931
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486085378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.3486085378
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.1080754156
Short name T1233
Test name
Test status
Simulation time 44819686 ps
CPU time 0.59 seconds
Started Apr 18 12:46:49 PM PDT 24
Finished Apr 18 12:46:51 PM PDT 24
Peak memory 194336 kb
Host smart-aa3677ae-422c-4697-a3ac-7ee9207ae4f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080754156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.1080754156
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.3414861358
Short name T1277
Test name
Test status
Simulation time 168172937 ps
CPU time 0.69 seconds
Started Apr 18 12:46:57 PM PDT 24
Finished Apr 18 12:46:59 PM PDT 24
Peak memory 195436 kb
Host smart-5971345f-f219-4fbb-aace-27df164ce6c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414861358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.3414861358
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.1167148854
Short name T1236
Test name
Test status
Simulation time 119707623 ps
CPU time 1.91 seconds
Started Apr 18 12:46:50 PM PDT 24
Finished Apr 18 12:46:54 PM PDT 24
Peak memory 200068 kb
Host smart-55207150-e072-42f3-9ed0-312fba733def
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167148854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.1167148854
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3327008621
Short name T80
Test name
Test status
Simulation time 137929557 ps
CPU time 1.38 seconds
Started Apr 18 12:46:51 PM PDT 24
Finished Apr 18 12:46:54 PM PDT 24
Peak memory 199516 kb
Host smart-3a7badac-2ea4-422e-ab0b-68b5a2bb6d3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327008621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.3327008621
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3968109567
Short name T46
Test name
Test status
Simulation time 28509648 ps
CPU time 0.78 seconds
Started Apr 18 12:46:26 PM PDT 24
Finished Apr 18 12:46:28 PM PDT 24
Peak memory 196352 kb
Host smart-352f1550-8b44-4bb4-a2a6-789063f7db23
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968109567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3968109567
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3615003424
Short name T1222
Test name
Test status
Simulation time 212159518 ps
CPU time 2.29 seconds
Started Apr 18 12:46:25 PM PDT 24
Finished Apr 18 12:46:29 PM PDT 24
Peak memory 197968 kb
Host smart-e1dcb3ff-ec4e-46c4-a1de-c5cb20cf14eb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615003424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.3615003424
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.791992345
Short name T1288
Test name
Test status
Simulation time 23828305 ps
CPU time 0.55 seconds
Started Apr 18 12:46:24 PM PDT 24
Finished Apr 18 12:46:26 PM PDT 24
Peak memory 195388 kb
Host smart-28b2d6a1-0cbb-4417-9b6b-8429cf502cec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791992345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.791992345
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1308523510
Short name T1262
Test name
Test status
Simulation time 48483679 ps
CPU time 0.63 seconds
Started Apr 18 12:46:34 PM PDT 24
Finished Apr 18 12:46:36 PM PDT 24
Peak memory 197284 kb
Host smart-7e83eee7-2c61-4da3-b351-545294abecd4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308523510 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.1308523510
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.1518177763
Short name T48
Test name
Test status
Simulation time 50517753 ps
CPU time 0.6 seconds
Started Apr 18 12:46:26 PM PDT 24
Finished Apr 18 12:46:28 PM PDT 24
Peak memory 195520 kb
Host smart-a6dc5fa0-873f-48a6-abfb-199b86b74920
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518177763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.1518177763
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.2645428612
Short name T1216
Test name
Test status
Simulation time 35177983 ps
CPU time 0.65 seconds
Started Apr 18 12:46:28 PM PDT 24
Finished Apr 18 12:46:29 PM PDT 24
Peak memory 194300 kb
Host smart-fc083a99-25ce-40ad-a5f4-abe841126402
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645428612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.2645428612
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3863892231
Short name T63
Test name
Test status
Simulation time 64183062 ps
CPU time 0.65 seconds
Started Apr 18 12:46:31 PM PDT 24
Finished Apr 18 12:46:33 PM PDT 24
Peak memory 195496 kb
Host smart-246c417e-7408-4c0f-b5a5-c5946f66a063
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863892231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.3863892231
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.1453139106
Short name T1206
Test name
Test status
Simulation time 456709033 ps
CPU time 2.55 seconds
Started Apr 18 12:46:24 PM PDT 24
Finished Apr 18 12:46:28 PM PDT 24
Peak memory 200052 kb
Host smart-bd206c55-b3a3-41b0-a2ee-f7477b4ce26a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453139106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.1453139106
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3760915400
Short name T1204
Test name
Test status
Simulation time 89405853 ps
CPU time 0.95 seconds
Started Apr 18 12:46:26 PM PDT 24
Finished Apr 18 12:46:28 PM PDT 24
Peak memory 199052 kb
Host smart-206fee36-d8c1-476a-8c9a-db74b81b3fa1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760915400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.3760915400
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.350484056
Short name T1307
Test name
Test status
Simulation time 54128088 ps
CPU time 0.53 seconds
Started Apr 18 12:46:48 PM PDT 24
Finished Apr 18 12:46:49 PM PDT 24
Peak memory 194452 kb
Host smart-152684d9-718d-49cf-9f88-26b42d08a530
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350484056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.350484056
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.2622371261
Short name T1263
Test name
Test status
Simulation time 17665304 ps
CPU time 0.57 seconds
Started Apr 18 12:46:49 PM PDT 24
Finished Apr 18 12:46:51 PM PDT 24
Peak memory 194436 kb
Host smart-3ab3fec4-0b5e-4979-ae16-090c5282bff4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622371261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.2622371261
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.2758180435
Short name T1180
Test name
Test status
Simulation time 50519941 ps
CPU time 0.58 seconds
Started Apr 18 12:46:51 PM PDT 24
Finished Apr 18 12:46:53 PM PDT 24
Peak memory 194364 kb
Host smart-b553eaa0-5f23-4dd6-9fff-96772dbd8c0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758180435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.2758180435
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.995606110
Short name T1196
Test name
Test status
Simulation time 17515502 ps
CPU time 0.58 seconds
Started Apr 18 12:46:48 PM PDT 24
Finished Apr 18 12:46:50 PM PDT 24
Peak memory 194392 kb
Host smart-ca45599e-8fdb-431e-8bdb-b8dbdb23421e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995606110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.995606110
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.2153003054
Short name T1254
Test name
Test status
Simulation time 19128832 ps
CPU time 0.59 seconds
Started Apr 18 12:46:49 PM PDT 24
Finished Apr 18 12:46:51 PM PDT 24
Peak memory 194308 kb
Host smart-46f6ca1e-54eb-4140-95db-8626bd10a3c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153003054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.2153003054
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.767377875
Short name T1246
Test name
Test status
Simulation time 14624757 ps
CPU time 0.59 seconds
Started Apr 18 12:46:56 PM PDT 24
Finished Apr 18 12:46:58 PM PDT 24
Peak memory 194212 kb
Host smart-45220869-2ebe-478b-9225-267b2ce03eb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767377875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.767377875
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.17167263
Short name T1197
Test name
Test status
Simulation time 111435288 ps
CPU time 0.56 seconds
Started Apr 18 12:46:49 PM PDT 24
Finished Apr 18 12:46:51 PM PDT 24
Peak memory 194340 kb
Host smart-ff8dbccd-fe12-40ec-9294-2491daeeff37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17167263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.17167263
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.855256445
Short name T1269
Test name
Test status
Simulation time 89133686 ps
CPU time 0.58 seconds
Started Apr 18 12:46:55 PM PDT 24
Finished Apr 18 12:46:57 PM PDT 24
Peak memory 194212 kb
Host smart-1f4494ef-b70f-4532-83dd-5835d568af12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855256445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.855256445
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.3431030662
Short name T1304
Test name
Test status
Simulation time 11477547 ps
CPU time 0.59 seconds
Started Apr 18 12:46:49 PM PDT 24
Finished Apr 18 12:46:52 PM PDT 24
Peak memory 194248 kb
Host smart-a3ede21e-7211-4e58-bd08-8d00010184a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431030662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.3431030662
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.327805545
Short name T1305
Test name
Test status
Simulation time 14314437 ps
CPU time 0.59 seconds
Started Apr 18 12:46:49 PM PDT 24
Finished Apr 18 12:46:51 PM PDT 24
Peak memory 194348 kb
Host smart-7fab158a-ac72-485b-9ff1-55df78e8ad29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327805545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.327805545
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3273149979
Short name T1182
Test name
Test status
Simulation time 66540200 ps
CPU time 0.72 seconds
Started Apr 18 12:46:29 PM PDT 24
Finished Apr 18 12:46:31 PM PDT 24
Peak memory 196316 kb
Host smart-5d417e53-7105-4a40-9bd0-d02c579d9dfe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273149979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.3273149979
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3697531689
Short name T1214
Test name
Test status
Simulation time 691569305 ps
CPU time 2.34 seconds
Started Apr 18 12:46:30 PM PDT 24
Finished Apr 18 12:46:34 PM PDT 24
Peak memory 198088 kb
Host smart-d53575ba-972e-41a1-a529-e12c71d970d5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697531689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.3697531689
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.4063155305
Short name T1258
Test name
Test status
Simulation time 36890086 ps
CPU time 0.58 seconds
Started Apr 18 12:46:31 PM PDT 24
Finished Apr 18 12:46:33 PM PDT 24
Peak memory 195464 kb
Host smart-0192f5de-667a-4dff-a3b2-4229c3163467
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063155305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.4063155305
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.749322274
Short name T1184
Test name
Test status
Simulation time 240175480 ps
CPU time 0.9 seconds
Started Apr 18 12:46:34 PM PDT 24
Finished Apr 18 12:46:35 PM PDT 24
Peak memory 199804 kb
Host smart-018f3b07-f722-42d9-ae0d-e177bfc50177
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749322274 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.749322274
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.4273666563
Short name T1224
Test name
Test status
Simulation time 29064516 ps
CPU time 0.59 seconds
Started Apr 18 12:46:31 PM PDT 24
Finished Apr 18 12:46:33 PM PDT 24
Peak memory 195460 kb
Host smart-b116e81b-1c2d-47c9-ba0f-76db7999d9b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273666563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.4273666563
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.1036341297
Short name T1177
Test name
Test status
Simulation time 12632784 ps
CPU time 0.61 seconds
Started Apr 18 12:46:31 PM PDT 24
Finished Apr 18 12:46:33 PM PDT 24
Peak memory 194260 kb
Host smart-8680fe2f-4530-4bb4-8d97-3f979bf0259d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036341297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.1036341297
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2158646392
Short name T1259
Test name
Test status
Simulation time 141503143 ps
CPU time 0.65 seconds
Started Apr 18 12:46:29 PM PDT 24
Finished Apr 18 12:46:31 PM PDT 24
Peak memory 195544 kb
Host smart-b1ba946b-c250-4448-a24a-f53e42ea4c09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158646392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.2158646392
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.2663915556
Short name T1220
Test name
Test status
Simulation time 139084297 ps
CPU time 2.41 seconds
Started Apr 18 12:46:31 PM PDT 24
Finished Apr 18 12:46:35 PM PDT 24
Peak memory 200080 kb
Host smart-967d85b1-9616-4c06-accc-77198aebe3ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663915556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2663915556
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.2644179275
Short name T76
Test name
Test status
Simulation time 100071126 ps
CPU time 1.28 seconds
Started Apr 18 12:46:30 PM PDT 24
Finished Apr 18 12:46:33 PM PDT 24
Peak memory 199404 kb
Host smart-04413d2f-cb49-4583-bca2-c19531c87488
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644179275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.2644179275
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.17127824
Short name T1217
Test name
Test status
Simulation time 13556380 ps
CPU time 0.58 seconds
Started Apr 18 12:46:49 PM PDT 24
Finished Apr 18 12:46:52 PM PDT 24
Peak memory 194380 kb
Host smart-4ee8e8bb-a7a4-4dee-8f4b-f08b3e962f89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17127824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.17127824
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.3628490162
Short name T1229
Test name
Test status
Simulation time 38282825 ps
CPU time 0.63 seconds
Started Apr 18 12:46:49 PM PDT 24
Finished Apr 18 12:46:51 PM PDT 24
Peak memory 194420 kb
Host smart-303e09d0-1047-456e-ab98-85d26ff5b54d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628490162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.3628490162
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.1084639538
Short name T1265
Test name
Test status
Simulation time 17849613 ps
CPU time 0.56 seconds
Started Apr 18 12:46:48 PM PDT 24
Finished Apr 18 12:46:51 PM PDT 24
Peak memory 194448 kb
Host smart-34cf67e1-4d24-4735-9a37-a630110683e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084639538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.1084639538
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.499994034
Short name T1285
Test name
Test status
Simulation time 151621286 ps
CPU time 0.55 seconds
Started Apr 18 12:46:49 PM PDT 24
Finished Apr 18 12:46:52 PM PDT 24
Peak memory 194256 kb
Host smart-4053affb-a0f3-4be6-8ac3-3287c1598d40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499994034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.499994034
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.2640578410
Short name T1249
Test name
Test status
Simulation time 14669054 ps
CPU time 0.57 seconds
Started Apr 18 12:46:49 PM PDT 24
Finished Apr 18 12:46:52 PM PDT 24
Peak memory 194404 kb
Host smart-13824ad9-7a46-42fe-a1c0-8f9cab860c72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640578410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.2640578410
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.2858503376
Short name T1190
Test name
Test status
Simulation time 14739144 ps
CPU time 0.61 seconds
Started Apr 18 12:46:55 PM PDT 24
Finished Apr 18 12:46:57 PM PDT 24
Peak memory 194452 kb
Host smart-2607bfb6-aa5d-4159-9767-055989eef704
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858503376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.2858503376
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.2186035537
Short name T1278
Test name
Test status
Simulation time 17576340 ps
CPU time 0.64 seconds
Started Apr 18 12:46:57 PM PDT 24
Finished Apr 18 12:46:59 PM PDT 24
Peak memory 194360 kb
Host smart-270dc39a-df03-4034-be6b-61fbd2cc3b66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186035537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2186035537
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.3605099883
Short name T1221
Test name
Test status
Simulation time 13713510 ps
CPU time 0.56 seconds
Started Apr 18 12:47:17 PM PDT 24
Finished Apr 18 12:47:19 PM PDT 24
Peak memory 194372 kb
Host smart-ce190518-99af-42e1-ac5d-367aeffce436
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605099883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.3605099883
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.2959977272
Short name T1226
Test name
Test status
Simulation time 21695543 ps
CPU time 0.55 seconds
Started Apr 18 12:46:53 PM PDT 24
Finished Apr 18 12:46:55 PM PDT 24
Peak memory 194448 kb
Host smart-00a802d6-83de-4a0a-83ff-3e8e90119ca4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959977272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.2959977272
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.2953564105
Short name T1210
Test name
Test status
Simulation time 43674924 ps
CPU time 0.6 seconds
Started Apr 18 12:47:06 PM PDT 24
Finished Apr 18 12:47:08 PM PDT 24
Peak memory 194384 kb
Host smart-c69254ce-7060-42d8-8d26-f76808ddf5ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953564105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.2953564105
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.229672799
Short name T1273
Test name
Test status
Simulation time 23440257 ps
CPU time 0.69 seconds
Started Apr 18 12:46:30 PM PDT 24
Finished Apr 18 12:46:32 PM PDT 24
Peak memory 195424 kb
Host smart-8e322a39-fb2d-4015-86b3-60278ee4dd35
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229672799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.229672799
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.515741919
Short name T1296
Test name
Test status
Simulation time 965881120 ps
CPU time 2.3 seconds
Started Apr 18 12:46:29 PM PDT 24
Finished Apr 18 12:46:32 PM PDT 24
Peak memory 197232 kb
Host smart-259c7720-91f0-417b-924e-35b0949df17c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515741919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.515741919
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1190410382
Short name T1252
Test name
Test status
Simulation time 46268997 ps
CPU time 0.65 seconds
Started Apr 18 12:46:31 PM PDT 24
Finished Apr 18 12:46:33 PM PDT 24
Peak memory 195432 kb
Host smart-817f3d7c-31fb-4c2e-919f-b52b2e344885
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190410382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.1190410382
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2532651426
Short name T1219
Test name
Test status
Simulation time 68949108 ps
CPU time 1.06 seconds
Started Apr 18 12:46:29 PM PDT 24
Finished Apr 18 12:46:31 PM PDT 24
Peak memory 199844 kb
Host smart-523a4b03-d82c-4dc1-84b0-d93360de1637
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532651426 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.2532651426
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.1352482762
Short name T71
Test name
Test status
Simulation time 50901425 ps
CPU time 0.57 seconds
Started Apr 18 12:46:32 PM PDT 24
Finished Apr 18 12:46:34 PM PDT 24
Peak memory 195448 kb
Host smart-85af9b40-1318-4cac-9170-dffa7d99a56c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352482762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.1352482762
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.239168856
Short name T1201
Test name
Test status
Simulation time 31559615 ps
CPU time 0.54 seconds
Started Apr 18 12:46:48 PM PDT 24
Finished Apr 18 12:46:50 PM PDT 24
Peak memory 194448 kb
Host smart-34d4c38a-d41e-41a5-9efb-96a59563dda0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239168856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.239168856
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.3837191405
Short name T1225
Test name
Test status
Simulation time 20705953 ps
CPU time 0.64 seconds
Started Apr 18 12:46:30 PM PDT 24
Finished Apr 18 12:46:32 PM PDT 24
Peak memory 196452 kb
Host smart-c6c36bdb-bca5-4c02-9141-e89fa68ef4a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837191405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.3837191405
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.1406418522
Short name T1295
Test name
Test status
Simulation time 45131749 ps
CPU time 1.19 seconds
Started Apr 18 12:46:31 PM PDT 24
Finished Apr 18 12:46:34 PM PDT 24
Peak memory 200056 kb
Host smart-89d03332-9858-472f-bc9a-a0a37bb7768d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406418522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.1406418522
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1392791894
Short name T1312
Test name
Test status
Simulation time 78807165 ps
CPU time 1.24 seconds
Started Apr 18 12:46:32 PM PDT 24
Finished Apr 18 12:46:34 PM PDT 24
Peak memory 199176 kb
Host smart-508046da-840f-4991-9ead-2f0522bb96cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392791894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.1392791894
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.2001556739
Short name T1311
Test name
Test status
Simulation time 15283761 ps
CPU time 0.58 seconds
Started Apr 18 12:46:54 PM PDT 24
Finished Apr 18 12:46:56 PM PDT 24
Peak memory 194584 kb
Host smart-b2f93b43-27c7-4e74-b773-4cc20bc4d807
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001556739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.2001556739
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.2347237689
Short name T1194
Test name
Test status
Simulation time 28828367 ps
CPU time 0.6 seconds
Started Apr 18 12:46:56 PM PDT 24
Finished Apr 18 12:46:58 PM PDT 24
Peak memory 194348 kb
Host smart-d75292ed-a140-4dde-9fa0-85580eea92e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347237689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.2347237689
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.2872372237
Short name T1286
Test name
Test status
Simulation time 26874149 ps
CPU time 0.56 seconds
Started Apr 18 12:46:55 PM PDT 24
Finished Apr 18 12:46:56 PM PDT 24
Peak memory 194344 kb
Host smart-fd40be93-eadb-45da-a0f7-3b90f0a927a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872372237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.2872372237
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.1010227748
Short name T1314
Test name
Test status
Simulation time 18466679 ps
CPU time 0.57 seconds
Started Apr 18 12:46:54 PM PDT 24
Finished Apr 18 12:47:00 PM PDT 24
Peak memory 194404 kb
Host smart-ad177ab4-54ad-4bcb-b18f-7ec636b97039
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010227748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.1010227748
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.505747669
Short name T1284
Test name
Test status
Simulation time 101769257 ps
CPU time 0.64 seconds
Started Apr 18 12:46:57 PM PDT 24
Finished Apr 18 12:46:59 PM PDT 24
Peak memory 194380 kb
Host smart-7598bced-e517-4e05-8f9f-f7a1718bbcd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505747669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.505747669
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.1585737303
Short name T1200
Test name
Test status
Simulation time 32175673 ps
CPU time 0.58 seconds
Started Apr 18 12:47:01 PM PDT 24
Finished Apr 18 12:47:02 PM PDT 24
Peak memory 194368 kb
Host smart-7e567f4f-3794-43dc-b75b-cb50dc8f2a00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585737303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.1585737303
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.2519146360
Short name T1240
Test name
Test status
Simulation time 30855632 ps
CPU time 0.57 seconds
Started Apr 18 12:46:56 PM PDT 24
Finished Apr 18 12:46:58 PM PDT 24
Peak memory 194244 kb
Host smart-74773110-6146-414d-bc7a-5817c46b2671
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519146360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2519146360
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.1853114984
Short name T1297
Test name
Test status
Simulation time 41008100 ps
CPU time 0.57 seconds
Started Apr 18 12:46:55 PM PDT 24
Finished Apr 18 12:46:57 PM PDT 24
Peak memory 194304 kb
Host smart-5266ceda-ebfb-4bb5-82bd-5a31f3c33767
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853114984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.1853114984
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.2381169199
Short name T1183
Test name
Test status
Simulation time 84299441 ps
CPU time 0.57 seconds
Started Apr 18 12:46:56 PM PDT 24
Finished Apr 18 12:46:58 PM PDT 24
Peak memory 194372 kb
Host smart-a6ca50d0-dfd4-4e1f-a450-bcb5af89acf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381169199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2381169199
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.263903680
Short name T1266
Test name
Test status
Simulation time 15633220 ps
CPU time 0.56 seconds
Started Apr 18 12:46:55 PM PDT 24
Finished Apr 18 12:46:57 PM PDT 24
Peak memory 194280 kb
Host smart-767fc387-33c3-4dfe-827d-7966c2519330
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263903680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.263903680
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1931409274
Short name T1205
Test name
Test status
Simulation time 80040132 ps
CPU time 0.79 seconds
Started Apr 18 12:46:36 PM PDT 24
Finished Apr 18 12:46:38 PM PDT 24
Peak memory 199824 kb
Host smart-19d86f22-3485-4e75-b450-dd4fffd61872
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931409274 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.1931409274
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.2884889358
Short name T1271
Test name
Test status
Simulation time 63268995 ps
CPU time 0.64 seconds
Started Apr 18 12:46:39 PM PDT 24
Finished Apr 18 12:46:41 PM PDT 24
Peak memory 195660 kb
Host smart-9bbaf3a6-0b20-4f27-83b1-388feb89c985
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884889358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.2884889358
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.818461580
Short name T1276
Test name
Test status
Simulation time 18269035 ps
CPU time 0.55 seconds
Started Apr 18 12:46:48 PM PDT 24
Finished Apr 18 12:46:50 PM PDT 24
Peak memory 194332 kb
Host smart-b6a4ccb9-a417-4d4e-8c50-9e9e52571c5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818461580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.818461580
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2476069065
Short name T1290
Test name
Test status
Simulation time 29968796 ps
CPU time 0.78 seconds
Started Apr 18 12:46:48 PM PDT 24
Finished Apr 18 12:46:51 PM PDT 24
Peak memory 196696 kb
Host smart-73beb651-63c2-4651-9ea7-e46994aeb9b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476069065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.2476069065
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.3550879045
Short name T1191
Test name
Test status
Simulation time 93369277 ps
CPU time 1.11 seconds
Started Apr 18 12:46:31 PM PDT 24
Finished Apr 18 12:46:33 PM PDT 24
Peak memory 200120 kb
Host smart-61074b15-61ad-45cc-9164-5428780ef228
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550879045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.3550879045
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.502373940
Short name T1317
Test name
Test status
Simulation time 33825326 ps
CPU time 0.77 seconds
Started Apr 18 12:46:47 PM PDT 24
Finished Apr 18 12:46:49 PM PDT 24
Peak memory 199784 kb
Host smart-00486d11-dac9-46b6-86da-67eb63176f0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502373940 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.502373940
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.3834839915
Short name T1280
Test name
Test status
Simulation time 36211954 ps
CPU time 0.6 seconds
Started Apr 18 12:46:36 PM PDT 24
Finished Apr 18 12:46:37 PM PDT 24
Peak memory 195376 kb
Host smart-e3c4fcaa-fd06-481b-8bd2-d61eee274975
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834839915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.3834839915
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.1517294123
Short name T1218
Test name
Test status
Simulation time 39356303 ps
CPU time 0.56 seconds
Started Apr 18 12:46:38 PM PDT 24
Finished Apr 18 12:46:39 PM PDT 24
Peak memory 194296 kb
Host smart-d5f3b887-9d24-4c4d-b2df-45897f4b1352
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517294123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.1517294123
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.4236789329
Short name T1257
Test name
Test status
Simulation time 64222778 ps
CPU time 0.62 seconds
Started Apr 18 12:46:35 PM PDT 24
Finished Apr 18 12:46:37 PM PDT 24
Peak memory 194656 kb
Host smart-f537a8ac-bdd7-4db5-96de-a0efe657f875
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236789329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.4236789329
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.3762569667
Short name T1181
Test name
Test status
Simulation time 38817262 ps
CPU time 1.85 seconds
Started Apr 18 12:46:39 PM PDT 24
Finished Apr 18 12:46:41 PM PDT 24
Peak memory 200016 kb
Host smart-0b8cf9ee-e5b3-41a5-af00-f0c0953852fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762569667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.3762569667
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.787264638
Short name T85
Test name
Test status
Simulation time 83038446 ps
CPU time 1.34 seconds
Started Apr 18 12:46:44 PM PDT 24
Finished Apr 18 12:46:47 PM PDT 24
Peak memory 199332 kb
Host smart-ca1bff42-f290-44f0-97e4-0ee7310ea0e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787264638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.787264638
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.56536731
Short name T1256
Test name
Test status
Simulation time 43009224 ps
CPU time 0.88 seconds
Started Apr 18 12:46:39 PM PDT 24
Finished Apr 18 12:46:41 PM PDT 24
Peak memory 199716 kb
Host smart-6f9722af-eb58-47bf-bb7c-2ead44866de3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56536731 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.56536731
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.1659901924
Short name T1239
Test name
Test status
Simulation time 28700331 ps
CPU time 0.63 seconds
Started Apr 18 12:46:35 PM PDT 24
Finished Apr 18 12:46:36 PM PDT 24
Peak memory 195392 kb
Host smart-5755903e-6f18-4c9b-a2eb-6cec1e7a48ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659901924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.1659901924
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.3492838846
Short name T1250
Test name
Test status
Simulation time 23316315 ps
CPU time 0.57 seconds
Started Apr 18 12:46:38 PM PDT 24
Finished Apr 18 12:46:39 PM PDT 24
Peak memory 194328 kb
Host smart-8128c427-fce9-48b4-aeef-899b0d366633
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492838846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.3492838846
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.3009733435
Short name T1223
Test name
Test status
Simulation time 21898090 ps
CPU time 0.71 seconds
Started Apr 18 12:46:37 PM PDT 24
Finished Apr 18 12:46:38 PM PDT 24
Peak memory 195736 kb
Host smart-510390cc-8ac0-4e2d-9335-206e27e3b491
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009733435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.3009733435
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.4105297562
Short name T1292
Test name
Test status
Simulation time 426533646 ps
CPU time 2.15 seconds
Started Apr 18 12:46:39 PM PDT 24
Finished Apr 18 12:46:42 PM PDT 24
Peak memory 200152 kb
Host smart-db29193e-dc01-4a5c-a574-b92cfa0175b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105297562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.4105297562
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.2469242478
Short name T1255
Test name
Test status
Simulation time 90364090 ps
CPU time 1.22 seconds
Started Apr 18 12:46:36 PM PDT 24
Finished Apr 18 12:46:38 PM PDT 24
Peak memory 199448 kb
Host smart-49dba001-fb53-47a0-a4f8-8d84a4ca3e6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469242478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.2469242478
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.4015677015
Short name T1306
Test name
Test status
Simulation time 101123873 ps
CPU time 0.74 seconds
Started Apr 18 12:46:38 PM PDT 24
Finished Apr 18 12:46:40 PM PDT 24
Peak memory 198284 kb
Host smart-adf0a6a4-e472-43f8-a028-683672afe002
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015677015 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.4015677015
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.3181008354
Short name T1193
Test name
Test status
Simulation time 28502231 ps
CPU time 0.63 seconds
Started Apr 18 12:46:36 PM PDT 24
Finished Apr 18 12:46:38 PM PDT 24
Peak memory 194356 kb
Host smart-6236771a-e4c8-4d8b-ae67-cdbe4354a114
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181008354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.3181008354
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3085577359
Short name T1253
Test name
Test status
Simulation time 77106184 ps
CPU time 0.69 seconds
Started Apr 18 12:46:39 PM PDT 24
Finished Apr 18 12:46:40 PM PDT 24
Peak memory 196644 kb
Host smart-4f6775aa-c772-4d35-90fb-885c7c902d92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085577359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.3085577359
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.1019530800
Short name T1227
Test name
Test status
Simulation time 100050205 ps
CPU time 1.67 seconds
Started Apr 18 12:46:37 PM PDT 24
Finished Apr 18 12:46:40 PM PDT 24
Peak memory 200080 kb
Host smart-519a301b-fc4a-46fc-955e-1eb1f26fc517
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019530800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.1019530800
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1864753841
Short name T1279
Test name
Test status
Simulation time 16018122 ps
CPU time 0.69 seconds
Started Apr 18 12:47:01 PM PDT 24
Finished Apr 18 12:47:03 PM PDT 24
Peak memory 198508 kb
Host smart-cae1c783-fca0-4ad7-81da-c13efc1da785
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864753841 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.1864753841
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.1947076355
Short name T1237
Test name
Test status
Simulation time 19247993 ps
CPU time 0.56 seconds
Started Apr 18 12:46:36 PM PDT 24
Finished Apr 18 12:46:38 PM PDT 24
Peak memory 195356 kb
Host smart-b3fb8fb1-81f3-4e3f-9efe-49e93beab80e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947076355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.1947076355
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.501168734
Short name T1310
Test name
Test status
Simulation time 50511528 ps
CPU time 0.63 seconds
Started Apr 18 12:46:43 PM PDT 24
Finished Apr 18 12:46:45 PM PDT 24
Peak memory 194356 kb
Host smart-a5f8b8f4-60c5-4090-aadd-faabb739d902
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501168734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.501168734
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.688266757
Short name T64
Test name
Test status
Simulation time 19515885 ps
CPU time 0.62 seconds
Started Apr 18 12:46:36 PM PDT 24
Finished Apr 18 12:46:38 PM PDT 24
Peak memory 195516 kb
Host smart-505f60b9-a85a-40bf-9ac8-dbaa68cb579a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688266757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_
outstanding.688266757
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.272957983
Short name T1238
Test name
Test status
Simulation time 71554760 ps
CPU time 1.07 seconds
Started Apr 18 12:46:51 PM PDT 24
Finished Apr 18 12:46:54 PM PDT 24
Peak memory 199988 kb
Host smart-6bc787bc-7e56-4331-a42b-d028ac2c8dd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272957983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.272957983
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3635427555
Short name T1268
Test name
Test status
Simulation time 175582457 ps
CPU time 1 seconds
Started Apr 18 12:46:37 PM PDT 24
Finished Apr 18 12:46:39 PM PDT 24
Peak memory 199052 kb
Host smart-33bb3ac6-b6ce-4cb4-aac7-8e33374957de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635427555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.3635427555
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_fifo_full.273869674
Short name T714
Test name
Test status
Simulation time 66345172549 ps
CPU time 17.4 seconds
Started Apr 18 01:51:14 PM PDT 24
Finished Apr 18 01:51:32 PM PDT 24
Peak memory 200844 kb
Host smart-114b338d-c2c3-4824-8853-90bf0b77e762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273869674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.273869674
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.2383385411
Short name T677
Test name
Test status
Simulation time 15374912247 ps
CPU time 12.81 seconds
Started Apr 18 01:51:16 PM PDT 24
Finished Apr 18 01:51:29 PM PDT 24
Peak memory 199116 kb
Host smart-2f0ff00e-8e38-4af7-a826-7a7af3f93e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383385411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.2383385411
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.2969159149
Short name T892
Test name
Test status
Simulation time 41818176018 ps
CPU time 71.27 seconds
Started Apr 18 01:51:17 PM PDT 24
Finished Apr 18 01:52:29 PM PDT 24
Peak memory 200900 kb
Host smart-48590d07-b8a1-4cbd-91d8-378f12085ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969159149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.2969159149
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.816619892
Short name T608
Test name
Test status
Simulation time 41472709743 ps
CPU time 55.74 seconds
Started Apr 18 01:51:21 PM PDT 24
Finished Apr 18 01:52:17 PM PDT 24
Peak memory 200216 kb
Host smart-b5e78432-d97d-4102-863f-65cb8e3cc861
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816619892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.816619892
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.3894769573
Short name T342
Test name
Test status
Simulation time 112279098468 ps
CPU time 211.36 seconds
Started Apr 18 01:51:26 PM PDT 24
Finished Apr 18 01:54:59 PM PDT 24
Peak memory 200720 kb
Host smart-e4b40cfa-3d41-4699-b8a4-ea05bec8df57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3894769573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.3894769573
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.1275756867
Short name T430
Test name
Test status
Simulation time 4757655599 ps
CPU time 10.37 seconds
Started Apr 18 01:51:12 PM PDT 24
Finished Apr 18 01:51:23 PM PDT 24
Peak memory 200772 kb
Host smart-00734c85-3059-4b22-8aa9-cf3e1c266985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275756867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1275756867
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.3064258263
Short name T545
Test name
Test status
Simulation time 103274673571 ps
CPU time 172.69 seconds
Started Apr 18 01:51:26 PM PDT 24
Finished Apr 18 01:54:20 PM PDT 24
Peak memory 200528 kb
Host smart-d198ea4d-0b79-473b-9f22-61ea96c809b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064258263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.3064258263
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.2642421113
Short name T375
Test name
Test status
Simulation time 34323212828 ps
CPU time 741.43 seconds
Started Apr 18 01:51:28 PM PDT 24
Finished Apr 18 02:03:55 PM PDT 24
Peak memory 200812 kb
Host smart-ee267a9c-66a7-4dc2-b7f3-33f601393f02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2642421113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.2642421113
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.2977408340
Short name T1078
Test name
Test status
Simulation time 5752727751 ps
CPU time 42.39 seconds
Started Apr 18 01:51:18 PM PDT 24
Finished Apr 18 01:52:01 PM PDT 24
Peak memory 199532 kb
Host smart-90996c40-e1cc-4bee-bac5-946d69c8df99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2977408340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.2977408340
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.1382347101
Short name T364
Test name
Test status
Simulation time 15516138246 ps
CPU time 17.33 seconds
Started Apr 18 01:51:26 PM PDT 24
Finished Apr 18 01:51:45 PM PDT 24
Peak memory 200888 kb
Host smart-8f7321a2-6d2e-4b53-a1db-7b03b2419bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382347101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.1382347101
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.2039662265
Short name T613
Test name
Test status
Simulation time 34919456362 ps
CPU time 60.67 seconds
Started Apr 18 01:51:26 PM PDT 24
Finished Apr 18 01:52:28 PM PDT 24
Peak memory 196940 kb
Host smart-f9080a98-43d5-4faf-a501-eca3aa9b557e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039662265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.2039662265
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.1873323184
Short name T25
Test name
Test status
Simulation time 34195879 ps
CPU time 0.8 seconds
Started Apr 18 01:51:27 PM PDT 24
Finished Apr 18 01:51:28 PM PDT 24
Peak memory 218888 kb
Host smart-b5e98eef-2dbf-4f24-ac6d-6cfd16b96bf0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873323184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.1873323184
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.1448021179
Short name T547
Test name
Test status
Simulation time 254531091 ps
CPU time 1.31 seconds
Started Apr 18 01:51:10 PM PDT 24
Finished Apr 18 01:51:12 PM PDT 24
Peak memory 199388 kb
Host smart-902ec005-eff9-4076-9c16-7387e1db58e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448021179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.1448021179
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.640451965
Short name T895
Test name
Test status
Simulation time 444472384685 ps
CPU time 285.29 seconds
Started Apr 18 01:51:19 PM PDT 24
Finished Apr 18 01:56:05 PM PDT 24
Peak memory 200872 kb
Host smart-77cbf81d-4565-4e30-9a40-f23401b021e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640451965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.640451965
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.2848339400
Short name T1052
Test name
Test status
Simulation time 86733481329 ps
CPU time 212.69 seconds
Started Apr 18 01:51:19 PM PDT 24
Finished Apr 18 01:54:53 PM PDT 24
Peak memory 215996 kb
Host smart-8f088e70-dcaa-41c1-8921-418724fe3c33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848339400 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.2848339400
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.3993421099
Short name T590
Test name
Test status
Simulation time 386655649 ps
CPU time 1.97 seconds
Started Apr 18 01:51:25 PM PDT 24
Finished Apr 18 01:51:27 PM PDT 24
Peak memory 199388 kb
Host smart-95f11ad7-9a19-4446-9a23-fb2cd85855b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993421099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.3993421099
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.3939896655
Short name T746
Test name
Test status
Simulation time 52169080836 ps
CPU time 105.65 seconds
Started Apr 18 01:51:27 PM PDT 24
Finished Apr 18 01:53:14 PM PDT 24
Peak memory 200876 kb
Host smart-fd403092-48b4-4fcf-b7da-978f6c69dea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939896655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.3939896655
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.141530196
Short name T842
Test name
Test status
Simulation time 18984818 ps
CPU time 0.52 seconds
Started Apr 18 01:51:17 PM PDT 24
Finished Apr 18 01:51:18 PM PDT 24
Peak memory 195192 kb
Host smart-e4131480-cd17-4a82-a4fe-4ab0cbb7578a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141530196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.141530196
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.881512754
Short name T277
Test name
Test status
Simulation time 26363984895 ps
CPU time 12.01 seconds
Started Apr 18 01:51:26 PM PDT 24
Finished Apr 18 01:51:40 PM PDT 24
Peak memory 200772 kb
Host smart-0a8e78f3-edca-4935-9c9b-0d60b330a710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881512754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.881512754
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.2949503423
Short name T456
Test name
Test status
Simulation time 86923463406 ps
CPU time 142.11 seconds
Started Apr 18 01:51:17 PM PDT 24
Finished Apr 18 01:53:40 PM PDT 24
Peak memory 200800 kb
Host smart-d8358688-f4df-4546-bcf2-e458dee03f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949503423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.2949503423
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.1219806564
Short name T735
Test name
Test status
Simulation time 89167273727 ps
CPU time 26.49 seconds
Started Apr 18 01:51:11 PM PDT 24
Finished Apr 18 01:51:38 PM PDT 24
Peak memory 200832 kb
Host smart-86e3f313-1805-432b-8178-a4596c618208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219806564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.1219806564
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.3905654700
Short name T1055
Test name
Test status
Simulation time 46186128240 ps
CPU time 80.38 seconds
Started Apr 18 01:51:09 PM PDT 24
Finished Apr 18 01:52:30 PM PDT 24
Peak memory 199804 kb
Host smart-d9d1d251-7050-4b64-bc11-b46b32f7ebec
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905654700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.3905654700
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.3304653503
Short name T867
Test name
Test status
Simulation time 124064639289 ps
CPU time 533.5 seconds
Started Apr 18 01:51:19 PM PDT 24
Finished Apr 18 02:00:13 PM PDT 24
Peak memory 200912 kb
Host smart-aea99958-9a1b-4676-a034-4ab46d93e122
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3304653503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.3304653503
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.2862953320
Short name T983
Test name
Test status
Simulation time 6252799348 ps
CPU time 6.31 seconds
Started Apr 18 01:51:28 PM PDT 24
Finished Apr 18 01:51:35 PM PDT 24
Peak memory 200096 kb
Host smart-41775d2a-2dd3-43c5-9eb2-2c150767b028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862953320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.2862953320
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.1880957583
Short name T636
Test name
Test status
Simulation time 18798061562 ps
CPU time 32.49 seconds
Started Apr 18 01:51:24 PM PDT 24
Finished Apr 18 01:51:57 PM PDT 24
Peak memory 199564 kb
Host smart-d4c309e2-006b-4475-9df3-2ab762a1743e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880957583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.1880957583
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.3028766469
Short name T265
Test name
Test status
Simulation time 16778143736 ps
CPU time 1018.29 seconds
Started Apr 18 01:51:14 PM PDT 24
Finished Apr 18 02:08:13 PM PDT 24
Peak memory 200800 kb
Host smart-376dfece-c50f-43eb-9f5b-b6752e40555b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3028766469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.3028766469
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.373061619
Short name T384
Test name
Test status
Simulation time 4131348062 ps
CPU time 31.9 seconds
Started Apr 18 01:51:19 PM PDT 24
Finished Apr 18 01:51:51 PM PDT 24
Peak memory 198700 kb
Host smart-e5008cf6-3cdb-496a-9ba3-0e0c286c5316
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=373061619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.373061619
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.4057541901
Short name T284
Test name
Test status
Simulation time 231250231740 ps
CPU time 116.27 seconds
Started Apr 18 01:51:18 PM PDT 24
Finished Apr 18 01:53:15 PM PDT 24
Peak memory 200860 kb
Host smart-e456c76c-8eed-445b-83a0-54fa4ff3f810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057541901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.4057541901
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.2329377674
Short name T844
Test name
Test status
Simulation time 2011383486 ps
CPU time 3.9 seconds
Started Apr 18 01:51:28 PM PDT 24
Finished Apr 18 01:51:33 PM PDT 24
Peak memory 196328 kb
Host smart-5e2d4c60-9ebd-4b05-945c-88b3d8c814a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329377674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.2329377674
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_smoke.547549571
Short name T308
Test name
Test status
Simulation time 5915696481 ps
CPU time 8.99 seconds
Started Apr 18 01:51:13 PM PDT 24
Finished Apr 18 01:51:22 PM PDT 24
Peak memory 199984 kb
Host smart-10746227-09ef-4885-b82b-aa5e8d3a1162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547549571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.547549571
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.1461057926
Short name T1092
Test name
Test status
Simulation time 31411264311 ps
CPU time 70.97 seconds
Started Apr 18 01:51:27 PM PDT 24
Finished Apr 18 01:52:39 PM PDT 24
Peak memory 200980 kb
Host smart-f24645ce-eb6b-4f23-a1f8-a8ba41e63ec9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461057926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.1461057926
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.3950741747
Short name T711
Test name
Test status
Simulation time 12788556611 ps
CPU time 67.19 seconds
Started Apr 18 01:51:09 PM PDT 24
Finished Apr 18 01:52:16 PM PDT 24
Peak memory 200824 kb
Host smart-dc8189e7-d128-44c3-9d0c-920ec86759d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950741747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.3950741747
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.4136669118
Short name T521
Test name
Test status
Simulation time 166036098853 ps
CPU time 77.04 seconds
Started Apr 18 01:51:28 PM PDT 24
Finished Apr 18 01:52:46 PM PDT 24
Peak memory 200908 kb
Host smart-54e2e506-1d84-4ade-bc15-f1724b78cf3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136669118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.4136669118
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.2325761863
Short name T864
Test name
Test status
Simulation time 127349421 ps
CPU time 0.57 seconds
Started Apr 18 01:51:38 PM PDT 24
Finished Apr 18 01:51:39 PM PDT 24
Peak memory 196184 kb
Host smart-bbcc6b47-dd0e-4611-ab6c-503284a932e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325761863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.2325761863
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.3793257380
Short name T537
Test name
Test status
Simulation time 28763575481 ps
CPU time 44.2 seconds
Started Apr 18 01:51:42 PM PDT 24
Finished Apr 18 01:52:27 PM PDT 24
Peak memory 200904 kb
Host smart-1ba7fe92-b2ab-46f1-97b7-fbf0fb36233f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793257380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.3793257380
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.4030473107
Short name T257
Test name
Test status
Simulation time 125779258384 ps
CPU time 112.73 seconds
Started Apr 18 01:51:37 PM PDT 24
Finished Apr 18 01:53:30 PM PDT 24
Peak memory 200844 kb
Host smart-b6be57aa-1c60-4c4c-8726-44e8edece38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030473107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.4030473107
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.2560015767
Short name T123
Test name
Test status
Simulation time 12744156022 ps
CPU time 18.3 seconds
Started Apr 18 01:51:37 PM PDT 24
Finished Apr 18 01:51:56 PM PDT 24
Peak memory 200804 kb
Host smart-551f158c-33d2-4ba3-b4ac-61bb8aaeda67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560015767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.2560015767
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.762625826
Short name T275
Test name
Test status
Simulation time 123813122477 ps
CPU time 151.25 seconds
Started Apr 18 01:51:39 PM PDT 24
Finished Apr 18 01:54:11 PM PDT 24
Peak memory 200600 kb
Host smart-a651fa3a-1245-4528-91b3-848529c631da
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762625826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.762625826
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.2421705323
Short name T1024
Test name
Test status
Simulation time 85369067924 ps
CPU time 259.68 seconds
Started Apr 18 01:51:48 PM PDT 24
Finished Apr 18 01:56:08 PM PDT 24
Peak memory 200812 kb
Host smart-1d406e8b-456d-4579-a852-91e41ea08fdb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2421705323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.2421705323
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.1500001709
Short name T511
Test name
Test status
Simulation time 2688957191 ps
CPU time 3.07 seconds
Started Apr 18 01:51:45 PM PDT 24
Finished Apr 18 01:51:48 PM PDT 24
Peak memory 198796 kb
Host smart-7beaef86-d101-40e5-b2d1-e8f2df982743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500001709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.1500001709
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.3483493119
Short name T831
Test name
Test status
Simulation time 151947491646 ps
CPU time 30.79 seconds
Started Apr 18 01:51:36 PM PDT 24
Finished Apr 18 01:52:08 PM PDT 24
Peak memory 201020 kb
Host smart-5615153d-3a45-4811-9419-fc831e542a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483493119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.3483493119
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.3054362487
Short name T678
Test name
Test status
Simulation time 12601769041 ps
CPU time 242.56 seconds
Started Apr 18 01:51:44 PM PDT 24
Finished Apr 18 01:55:47 PM PDT 24
Peak memory 200576 kb
Host smart-7c86086a-85a4-4df1-9f76-e9d23f08a323
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3054362487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.3054362487
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.2985185001
Short name T823
Test name
Test status
Simulation time 2858054534 ps
CPU time 17.14 seconds
Started Apr 18 01:51:37 PM PDT 24
Finished Apr 18 01:51:55 PM PDT 24
Peak memory 199008 kb
Host smart-c3522829-bc1c-48fb-aaf3-3ee9f9c10ec9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2985185001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.2985185001
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.3094835970
Short name T563
Test name
Test status
Simulation time 24949137532 ps
CPU time 40.5 seconds
Started Apr 18 01:51:40 PM PDT 24
Finished Apr 18 01:52:21 PM PDT 24
Peak memory 200828 kb
Host smart-fdff3835-7b5f-4892-aaf9-449cae759acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094835970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.3094835970
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.824509291
Short name T840
Test name
Test status
Simulation time 3563359867 ps
CPU time 2.21 seconds
Started Apr 18 01:51:54 PM PDT 24
Finished Apr 18 01:51:57 PM PDT 24
Peak memory 196752 kb
Host smart-15bd8bc4-014c-4793-b717-033f8b5d9aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824509291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.824509291
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.78413367
Short name T791
Test name
Test status
Simulation time 11598655331 ps
CPU time 14.72 seconds
Started Apr 18 01:51:56 PM PDT 24
Finished Apr 18 01:52:12 PM PDT 24
Peak memory 200672 kb
Host smart-9e5e6899-a62e-4fce-a3c2-a2a768b51461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78413367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.78413367
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.1266025469
Short name T981
Test name
Test status
Simulation time 356957412857 ps
CPU time 167.31 seconds
Started Apr 18 01:51:37 PM PDT 24
Finished Apr 18 01:54:25 PM PDT 24
Peak memory 200832 kb
Host smart-dbfdc71f-1840-4b27-85ac-4fed2d85be88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266025469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.1266025469
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.1882796493
Short name T836
Test name
Test status
Simulation time 31237107944 ps
CPU time 272.23 seconds
Started Apr 18 01:51:35 PM PDT 24
Finished Apr 18 01:56:07 PM PDT 24
Peak memory 217448 kb
Host smart-b57a0a2c-3f9b-466c-a840-316a0192cdac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882796493 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.1882796493
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.4248789572
Short name T779
Test name
Test status
Simulation time 575443165 ps
CPU time 2.4 seconds
Started Apr 18 01:51:42 PM PDT 24
Finished Apr 18 01:51:45 PM PDT 24
Peak memory 199164 kb
Host smart-a8642aab-d814-4ab6-bf6b-f24de9ef0e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248789572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.4248789572
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.2572919758
Short name T397
Test name
Test status
Simulation time 107543585205 ps
CPU time 18.87 seconds
Started Apr 18 01:51:41 PM PDT 24
Finished Apr 18 01:52:01 PM PDT 24
Peak memory 200852 kb
Host smart-e3270a93-672f-4d1a-998d-1ad4c8e23ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572919758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.2572919758
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.507725739
Short name T543
Test name
Test status
Simulation time 30749228050 ps
CPU time 22.76 seconds
Started Apr 18 01:54:00 PM PDT 24
Finished Apr 18 01:54:23 PM PDT 24
Peak memory 200828 kb
Host smart-191119d4-0c84-4db1-b79c-ff96a6a060cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507725739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.507725739
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3326368455
Short name T216
Test name
Test status
Simulation time 170218697222 ps
CPU time 73.63 seconds
Started Apr 18 01:54:00 PM PDT 24
Finished Apr 18 01:55:14 PM PDT 24
Peak memory 200912 kb
Host smart-dca44458-f3f3-4c57-acd1-62c816cccd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326368455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3326368455
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.306441751
Short name T234
Test name
Test status
Simulation time 117473785772 ps
CPU time 18.6 seconds
Started Apr 18 01:54:01 PM PDT 24
Finished Apr 18 01:54:20 PM PDT 24
Peak memory 200784 kb
Host smart-4e60dbd8-7617-4d7c-9f3b-df6621513199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306441751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.306441751
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.2685305807
Short name T632
Test name
Test status
Simulation time 73398135451 ps
CPU time 87 seconds
Started Apr 18 01:54:01 PM PDT 24
Finished Apr 18 01:55:29 PM PDT 24
Peak memory 200916 kb
Host smart-426920bc-1913-4beb-9f27-186a742b4754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685305807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.2685305807
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.3742313515
Short name T736
Test name
Test status
Simulation time 155261211798 ps
CPU time 107.65 seconds
Started Apr 18 01:54:00 PM PDT 24
Finished Apr 18 01:55:48 PM PDT 24
Peak memory 200908 kb
Host smart-2dd922d7-ea68-44ed-861c-2cd92b87014b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742313515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.3742313515
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.3353658233
Short name T833
Test name
Test status
Simulation time 88390455144 ps
CPU time 133.63 seconds
Started Apr 18 01:53:59 PM PDT 24
Finished Apr 18 01:56:13 PM PDT 24
Peak memory 200840 kb
Host smart-6a812554-743b-475e-810c-aca2bbf20ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353658233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.3353658233
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.1891984006
Short name T232
Test name
Test status
Simulation time 99652804640 ps
CPU time 52.19 seconds
Started Apr 18 01:54:06 PM PDT 24
Finished Apr 18 01:54:59 PM PDT 24
Peak memory 200860 kb
Host smart-27363e59-94f4-4060-b770-732bf5f451a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891984006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1891984006
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.3963194725
Short name T888
Test name
Test status
Simulation time 17582759820 ps
CPU time 31.33 seconds
Started Apr 18 01:54:07 PM PDT 24
Finished Apr 18 01:54:39 PM PDT 24
Peak memory 200828 kb
Host smart-56d93049-f7a8-4aaa-a5b9-96fcf1cdf6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963194725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.3963194725
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.264286830
Short name T346
Test name
Test status
Simulation time 48463778 ps
CPU time 0.56 seconds
Started Apr 18 01:51:55 PM PDT 24
Finished Apr 18 01:51:56 PM PDT 24
Peak memory 196196 kb
Host smart-700f0426-c69f-4204-8ca0-b102d8e9f3cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264286830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.264286830
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.711536572
Short name T1039
Test name
Test status
Simulation time 256992668719 ps
CPU time 324.08 seconds
Started Apr 18 01:51:38 PM PDT 24
Finished Apr 18 01:57:03 PM PDT 24
Peak memory 200904 kb
Host smart-d8ef8ecc-8f86-4219-a677-2a4b51737eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711536572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.711536572
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.3294329792
Short name T165
Test name
Test status
Simulation time 19738190542 ps
CPU time 9.36 seconds
Started Apr 18 01:52:00 PM PDT 24
Finished Apr 18 01:52:10 PM PDT 24
Peak memory 200068 kb
Host smart-a9e0c9bb-71c4-49b7-902d-ef4495a5a444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294329792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.3294329792
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.1075251326
Short name T643
Test name
Test status
Simulation time 14334992039 ps
CPU time 7.65 seconds
Started Apr 18 01:51:51 PM PDT 24
Finished Apr 18 01:51:59 PM PDT 24
Peak memory 200876 kb
Host smart-9f4816bb-d561-4239-a434-7cbde767bf75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075251326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.1075251326
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.157978464
Short name T645
Test name
Test status
Simulation time 30321502527 ps
CPU time 48.86 seconds
Started Apr 18 01:51:38 PM PDT 24
Finished Apr 18 01:52:27 PM PDT 24
Peak memory 200656 kb
Host smart-77327e38-8ccf-404d-84a6-e56bf5762d3a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157978464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.157978464
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.218411821
Short name T340
Test name
Test status
Simulation time 58383115264 ps
CPU time 467.95 seconds
Started Apr 18 01:51:43 PM PDT 24
Finished Apr 18 01:59:31 PM PDT 24
Peak memory 200820 kb
Host smart-37f01b86-000a-4968-9f9b-5d471271a5b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=218411821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.218411821
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.1760909638
Short name T975
Test name
Test status
Simulation time 5544387109 ps
CPU time 4.81 seconds
Started Apr 18 01:51:41 PM PDT 24
Finished Apr 18 01:51:46 PM PDT 24
Peak memory 199668 kb
Host smart-34dd2833-8708-4c18-a9e3-a3a629b2b5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760909638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.1760909638
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.1730580149
Short name T1128
Test name
Test status
Simulation time 35938729826 ps
CPU time 57.88 seconds
Started Apr 18 01:51:38 PM PDT 24
Finished Apr 18 01:52:37 PM PDT 24
Peak memory 209284 kb
Host smart-1e27d410-4c3e-4bd0-bda1-d4c044f929e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730580149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.1730580149
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.2487810658
Short name T577
Test name
Test status
Simulation time 16346733221 ps
CPU time 845.49 seconds
Started Apr 18 01:51:56 PM PDT 24
Finished Apr 18 02:06:03 PM PDT 24
Peak memory 200856 kb
Host smart-5be32702-44c4-4c27-a120-c28c85055d0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2487810658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.2487810658
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.2006090691
Short name T652
Test name
Test status
Simulation time 3086826148 ps
CPU time 2.05 seconds
Started Apr 18 01:51:39 PM PDT 24
Finished Apr 18 01:51:42 PM PDT 24
Peak memory 199188 kb
Host smart-e781b7ee-4f16-4bc4-b4ed-b596d2db561d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2006090691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.2006090691
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.960394886
Short name T1070
Test name
Test status
Simulation time 33733670038 ps
CPU time 39.77 seconds
Started Apr 18 01:51:37 PM PDT 24
Finished Apr 18 01:52:17 PM PDT 24
Peak memory 200708 kb
Host smart-a7c3a274-f951-4ab0-b516-d8814f18a51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960394886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.960394886
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.223547206
Short name T339
Test name
Test status
Simulation time 1894030393 ps
CPU time 3.86 seconds
Started Apr 18 01:51:36 PM PDT 24
Finished Apr 18 01:51:41 PM PDT 24
Peak memory 196248 kb
Host smart-d5aa7aa1-41f1-4280-8fe2-9800c00f9f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223547206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.223547206
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.1903436276
Short name T789
Test name
Test status
Simulation time 5603696554 ps
CPU time 7.58 seconds
Started Apr 18 01:51:40 PM PDT 24
Finished Apr 18 01:51:48 PM PDT 24
Peak memory 200788 kb
Host smart-19d5bd24-7086-44a0-b05c-76dd0b724e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903436276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.1903436276
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.1703283067
Short name T1029
Test name
Test status
Simulation time 281963832791 ps
CPU time 888.49 seconds
Started Apr 18 01:51:55 PM PDT 24
Finished Apr 18 02:06:44 PM PDT 24
Peak memory 200800 kb
Host smart-7f50ce54-a3a8-4683-ac50-0e2a8fca5303
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703283067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.1703283067
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.1070732169
Short name T1133
Test name
Test status
Simulation time 66519255944 ps
CPU time 191.42 seconds
Started Apr 18 01:51:45 PM PDT 24
Finished Apr 18 01:54:56 PM PDT 24
Peak memory 216448 kb
Host smart-56ad1155-417d-4d93-b0db-952d9b8b63a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070732169 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.1070732169
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.3138510820
Short name T553
Test name
Test status
Simulation time 1152134843 ps
CPU time 1.67 seconds
Started Apr 18 01:51:53 PM PDT 24
Finished Apr 18 01:51:55 PM PDT 24
Peak memory 198552 kb
Host smart-f048e207-50e6-4a9f-9105-094f22b8fb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138510820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.3138510820
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.1322001654
Short name T610
Test name
Test status
Simulation time 49709646211 ps
CPU time 37.8 seconds
Started Apr 18 01:51:39 PM PDT 24
Finished Apr 18 01:52:17 PM PDT 24
Peak memory 200672 kb
Host smart-3702441d-5bab-4530-be84-1cc1e79cc54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322001654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.1322001654
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.4236681259
Short name T611
Test name
Test status
Simulation time 7053361036 ps
CPU time 17.15 seconds
Started Apr 18 01:54:07 PM PDT 24
Finished Apr 18 01:54:25 PM PDT 24
Peak memory 200836 kb
Host smart-b4a84dc5-9e6b-4e6c-9cf0-49d7bbdc867b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236681259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.4236681259
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.1893065558
Short name T576
Test name
Test status
Simulation time 33236289762 ps
CPU time 50.09 seconds
Started Apr 18 01:54:06 PM PDT 24
Finished Apr 18 01:54:57 PM PDT 24
Peak memory 200636 kb
Host smart-3a59de2c-4fd3-4d7a-afae-baf081398035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893065558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.1893065558
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.2822519635
Short name T624
Test name
Test status
Simulation time 73557366889 ps
CPU time 82.59 seconds
Started Apr 18 01:54:06 PM PDT 24
Finished Apr 18 01:55:29 PM PDT 24
Peak memory 200912 kb
Host smart-48d55fe7-98c9-4f00-977a-748e1d48b32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822519635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.2822519635
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.1766687593
Short name T725
Test name
Test status
Simulation time 185459365888 ps
CPU time 202.58 seconds
Started Apr 18 01:54:06 PM PDT 24
Finished Apr 18 01:57:29 PM PDT 24
Peak memory 200872 kb
Host smart-0d970d47-26bb-4d2f-b376-9a2d56402304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766687593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.1766687593
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.3489717267
Short name T424
Test name
Test status
Simulation time 53254086794 ps
CPU time 71.59 seconds
Started Apr 18 01:54:07 PM PDT 24
Finished Apr 18 01:55:19 PM PDT 24
Peak memory 200784 kb
Host smart-2e46b139-20a1-4a94-9f2b-0c797ccf005f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489717267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.3489717267
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.2548982372
Short name T236
Test name
Test status
Simulation time 116079316439 ps
CPU time 123.12 seconds
Started Apr 18 01:54:07 PM PDT 24
Finished Apr 18 01:56:11 PM PDT 24
Peak memory 200872 kb
Host smart-5749cc08-8246-4bcc-8ad2-0ce5835b6455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548982372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.2548982372
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.2677315202
Short name T637
Test name
Test status
Simulation time 7582987954 ps
CPU time 12.61 seconds
Started Apr 18 01:54:05 PM PDT 24
Finished Apr 18 01:54:18 PM PDT 24
Peak memory 199524 kb
Host smart-073d3a26-b714-4020-8460-c6ab7ecfa78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677315202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.2677315202
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.2960734781
Short name T910
Test name
Test status
Simulation time 174546010370 ps
CPU time 68.82 seconds
Started Apr 18 01:54:06 PM PDT 24
Finished Apr 18 01:55:15 PM PDT 24
Peak memory 200836 kb
Host smart-63edcd59-74e7-47f2-ab46-e8d5c2e0c1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960734781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.2960734781
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.3850483646
Short name T906
Test name
Test status
Simulation time 17486344147 ps
CPU time 30.17 seconds
Started Apr 18 01:54:09 PM PDT 24
Finished Apr 18 01:54:40 PM PDT 24
Peak memory 200852 kb
Host smart-065fdbe8-ee3f-4577-ae36-ac9f2555ea13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850483646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.3850483646
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.4197214353
Short name T428
Test name
Test status
Simulation time 24579771357 ps
CPU time 13.67 seconds
Started Apr 18 01:54:08 PM PDT 24
Finished Apr 18 01:54:22 PM PDT 24
Peak memory 199172 kb
Host smart-ba0d34d7-7e5d-4919-b4aa-cea3eb82a8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197214353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.4197214353
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.1901037095
Short name T767
Test name
Test status
Simulation time 16039951 ps
CPU time 0.57 seconds
Started Apr 18 01:51:58 PM PDT 24
Finished Apr 18 01:51:59 PM PDT 24
Peak memory 195204 kb
Host smart-4d34c129-54fd-4271-8131-45ae12fd396f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901037095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.1901037095
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.164653421
Short name T483
Test name
Test status
Simulation time 149608730379 ps
CPU time 54.69 seconds
Started Apr 18 01:51:56 PM PDT 24
Finished Apr 18 01:52:52 PM PDT 24
Peak memory 200924 kb
Host smart-7780fb44-2347-4ba1-8fbf-674a8aa27eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164653421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.164653421
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.3745691886
Short name T938
Test name
Test status
Simulation time 179516153830 ps
CPU time 106.31 seconds
Started Apr 18 01:51:42 PM PDT 24
Finished Apr 18 01:53:28 PM PDT 24
Peak memory 200888 kb
Host smart-2293257f-6c23-4e1d-8d37-92d996b96577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745691886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.3745691886
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.207474454
Short name T996
Test name
Test status
Simulation time 85369396901 ps
CPU time 44.89 seconds
Started Apr 18 01:51:50 PM PDT 24
Finished Apr 18 01:52:35 PM PDT 24
Peak memory 200856 kb
Host smart-08742745-ec75-481c-b39b-c044a0bb812b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207474454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.207474454
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.193380901
Short name T1018
Test name
Test status
Simulation time 43677859043 ps
CPU time 29.99 seconds
Started Apr 18 01:51:54 PM PDT 24
Finished Apr 18 01:52:25 PM PDT 24
Peak memory 200828 kb
Host smart-e868b718-cbf9-413f-a31d-4ccacf8e2ec7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193380901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.193380901
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.271776541
Short name T790
Test name
Test status
Simulation time 110615857239 ps
CPU time 725.99 seconds
Started Apr 18 01:51:56 PM PDT 24
Finished Apr 18 02:04:03 PM PDT 24
Peak memory 200828 kb
Host smart-95c37300-20b0-425f-9123-9fe6757c5668
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=271776541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.271776541
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.468999953
Short name T768
Test name
Test status
Simulation time 5193106067 ps
CPU time 8.93 seconds
Started Apr 18 01:51:44 PM PDT 24
Finished Apr 18 01:51:53 PM PDT 24
Peak memory 200216 kb
Host smart-7d072879-9b11-4a47-a105-d8271cf4d7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468999953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.468999953
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.4254346155
Short name T696
Test name
Test status
Simulation time 394678680311 ps
CPU time 66.9 seconds
Started Apr 18 01:51:44 PM PDT 24
Finished Apr 18 01:52:51 PM PDT 24
Peak memory 201028 kb
Host smart-5b2efb6b-378b-4372-95d1-6728da8bd083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254346155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.4254346155
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.4238629052
Short name T1031
Test name
Test status
Simulation time 6625928577 ps
CPU time 28.92 seconds
Started Apr 18 01:51:59 PM PDT 24
Finished Apr 18 01:52:28 PM PDT 24
Peak memory 201028 kb
Host smart-b818ce9b-97a6-4784-8e65-bff6bb42d7b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4238629052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.4238629052
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.270105684
Short name T358
Test name
Test status
Simulation time 6117065720 ps
CPU time 50.88 seconds
Started Apr 18 01:51:43 PM PDT 24
Finished Apr 18 01:52:34 PM PDT 24
Peak memory 198916 kb
Host smart-1a1a63de-790d-4100-ab24-c155633c0482
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=270105684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.270105684
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.1951546857
Short name T828
Test name
Test status
Simulation time 135204175932 ps
CPU time 357.45 seconds
Started Apr 18 01:51:43 PM PDT 24
Finished Apr 18 01:57:41 PM PDT 24
Peak memory 200864 kb
Host smart-3fcf66e1-1f2a-40e8-9fa2-9693fb36bc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951546857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.1951546857
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.4245700539
Short name T296
Test name
Test status
Simulation time 6567991726 ps
CPU time 1.71 seconds
Started Apr 18 01:51:56 PM PDT 24
Finished Apr 18 01:51:58 PM PDT 24
Peak memory 197208 kb
Host smart-e9099e5a-f5d9-4820-9ad5-7ee85fbc008b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245700539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.4245700539
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.3036469950
Short name T533
Test name
Test status
Simulation time 688359656 ps
CPU time 1.56 seconds
Started Apr 18 01:51:43 PM PDT 24
Finished Apr 18 01:51:45 PM PDT 24
Peak memory 199096 kb
Host smart-fe1eb131-0533-4752-8887-35b62109e1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036469950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.3036469950
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.1053799725
Short name T156
Test name
Test status
Simulation time 378222897163 ps
CPU time 310.5 seconds
Started Apr 18 01:51:44 PM PDT 24
Finished Apr 18 01:56:54 PM PDT 24
Peak memory 200836 kb
Host smart-d89257f9-b071-46d5-a98d-4e27231d4b19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053799725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.1053799725
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.874568363
Short name T1086
Test name
Test status
Simulation time 81998113779 ps
CPU time 907.04 seconds
Started Apr 18 01:51:43 PM PDT 24
Finished Apr 18 02:06:51 PM PDT 24
Peak memory 217560 kb
Host smart-8824c37b-3891-4d6f-bcf9-263f8b8d6c34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874568363 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.874568363
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.1179856875
Short name T932
Test name
Test status
Simulation time 433698912 ps
CPU time 1.51 seconds
Started Apr 18 01:51:42 PM PDT 24
Finished Apr 18 01:51:43 PM PDT 24
Peak memory 197912 kb
Host smart-0a085adc-c5d2-44d3-a8c5-f568fe97e5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179856875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.1179856875
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.2382351281
Short name T492
Test name
Test status
Simulation time 37771466010 ps
CPU time 36.77 seconds
Started Apr 18 01:51:56 PM PDT 24
Finished Apr 18 01:52:34 PM PDT 24
Peak memory 200884 kb
Host smart-db6c3726-1f8d-4b8c-a19a-e4788d60f646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382351281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.2382351281
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.2819389789
Short name T199
Test name
Test status
Simulation time 161873865116 ps
CPU time 81.48 seconds
Started Apr 18 01:54:08 PM PDT 24
Finished Apr 18 01:55:30 PM PDT 24
Peak memory 200896 kb
Host smart-cbb1a3d9-5085-484a-bbba-10109c7894dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819389789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.2819389789
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.4195262495
Short name T729
Test name
Test status
Simulation time 252333409006 ps
CPU time 22.19 seconds
Started Apr 18 01:54:07 PM PDT 24
Finished Apr 18 01:54:29 PM PDT 24
Peak memory 200904 kb
Host smart-c323b893-4c1d-4b96-862a-265fb58d4168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195262495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.4195262495
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.1325874011
Short name T924
Test name
Test status
Simulation time 12985973764 ps
CPU time 15.6 seconds
Started Apr 18 01:54:11 PM PDT 24
Finished Apr 18 01:54:27 PM PDT 24
Peak memory 200860 kb
Host smart-170d6465-b177-4c34-a7d0-15fa4c94ffc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325874011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.1325874011
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.805790993
Short name T681
Test name
Test status
Simulation time 133919836285 ps
CPU time 59.96 seconds
Started Apr 18 01:54:06 PM PDT 24
Finished Apr 18 01:55:06 PM PDT 24
Peak memory 200808 kb
Host smart-352892bf-b314-415e-8e6f-49357c68170d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805790993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.805790993
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.1341175049
Short name T900
Test name
Test status
Simulation time 53432811172 ps
CPU time 69.03 seconds
Started Apr 18 01:54:06 PM PDT 24
Finished Apr 18 01:55:16 PM PDT 24
Peak memory 200832 kb
Host smart-1ea2d57b-2558-4e2a-98cf-f2a70c131fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341175049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.1341175049
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.3384362950
Short name T754
Test name
Test status
Simulation time 15837390358 ps
CPU time 21.88 seconds
Started Apr 18 01:54:07 PM PDT 24
Finished Apr 18 01:54:29 PM PDT 24
Peak memory 200848 kb
Host smart-55648ec6-7e88-4d4c-95fd-b5a8b8024360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384362950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.3384362950
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.2581574487
Short name T885
Test name
Test status
Simulation time 24095758640 ps
CPU time 21.84 seconds
Started Apr 18 01:54:06 PM PDT 24
Finished Apr 18 01:54:29 PM PDT 24
Peak memory 200684 kb
Host smart-df421131-5f9d-48cf-964e-d6df0dcf5c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581574487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.2581574487
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.1598481411
Short name T200
Test name
Test status
Simulation time 126868922340 ps
CPU time 194.63 seconds
Started Apr 18 01:54:08 PM PDT 24
Finished Apr 18 01:57:23 PM PDT 24
Peak memory 200812 kb
Host smart-d94f0b76-34c2-432e-b198-38cb830482a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598481411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.1598481411
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.1383008384
Short name T418
Test name
Test status
Simulation time 25628801230 ps
CPU time 14.4 seconds
Started Apr 18 01:54:05 PM PDT 24
Finished Apr 18 01:54:20 PM PDT 24
Peak memory 200848 kb
Host smart-ffb9c410-9a31-4106-b47b-4653fad08641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383008384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.1383008384
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.221432019
Short name T1050
Test name
Test status
Simulation time 157885194284 ps
CPU time 282.68 seconds
Started Apr 18 01:54:05 PM PDT 24
Finished Apr 18 01:58:48 PM PDT 24
Peak memory 200704 kb
Host smart-75ade669-b71d-4fb1-9620-714dcce26dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221432019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.221432019
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.2287559168
Short name T378
Test name
Test status
Simulation time 152542346 ps
CPU time 0.55 seconds
Started Apr 18 01:52:20 PM PDT 24
Finished Apr 18 01:52:21 PM PDT 24
Peak memory 196412 kb
Host smart-40ea3185-ce10-40da-9c6e-1396e4e8a11d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287559168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.2287559168
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.876150572
Short name T404
Test name
Test status
Simulation time 45024270408 ps
CPU time 75.77 seconds
Started Apr 18 01:52:07 PM PDT 24
Finished Apr 18 01:53:24 PM PDT 24
Peak memory 200864 kb
Host smart-ae4eaee5-cfa4-4ed8-a33c-37b9fbbbf3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876150572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.876150572
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.4011099772
Short name T1146
Test name
Test status
Simulation time 15493830831 ps
CPU time 21.77 seconds
Started Apr 18 01:51:59 PM PDT 24
Finished Apr 18 01:52:21 PM PDT 24
Peak memory 201096 kb
Host smart-b01d345c-c19f-4cac-bf87-565e6fc42d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011099772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.4011099772
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.4012388532
Short name T530
Test name
Test status
Simulation time 127550270133 ps
CPU time 135.93 seconds
Started Apr 18 01:51:59 PM PDT 24
Finished Apr 18 01:54:16 PM PDT 24
Peak memory 200848 kb
Host smart-fa2c1d97-2bf6-412b-9f8e-d2696a797c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012388532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.4012388532
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.332273560
Short name T622
Test name
Test status
Simulation time 4043274793 ps
CPU time 1.96 seconds
Started Apr 18 01:51:58 PM PDT 24
Finished Apr 18 01:52:01 PM PDT 24
Peak memory 200868 kb
Host smart-e650a1f3-bac0-4da9-aa29-3226170e6926
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332273560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.332273560
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.2320262236
Short name T356
Test name
Test status
Simulation time 351433676031 ps
CPU time 176.96 seconds
Started Apr 18 01:52:11 PM PDT 24
Finished Apr 18 01:55:08 PM PDT 24
Peak memory 200836 kb
Host smart-84e67dd0-a7c0-4d8a-9442-483fb51b47e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2320262236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.2320262236
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.3440862315
Short name T441
Test name
Test status
Simulation time 10492455264 ps
CPU time 6.08 seconds
Started Apr 18 01:52:19 PM PDT 24
Finished Apr 18 01:52:26 PM PDT 24
Peak memory 200108 kb
Host smart-71d7e1a1-428a-4c76-9d21-cb082e03d47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440862315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.3440862315
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.1892222046
Short name T739
Test name
Test status
Simulation time 161299549103 ps
CPU time 163.68 seconds
Started Apr 18 01:51:48 PM PDT 24
Finished Apr 18 01:54:32 PM PDT 24
Peak memory 200340 kb
Host smart-65a8b7dc-b3a2-4683-a305-4c6313797c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892222046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.1892222046
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.3234125370
Short name T544
Test name
Test status
Simulation time 17930425287 ps
CPU time 936.01 seconds
Started Apr 18 01:51:57 PM PDT 24
Finished Apr 18 02:07:33 PM PDT 24
Peak memory 200892 kb
Host smart-32c033f7-beae-4c43-aa38-b2d34158a626
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3234125370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.3234125370
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.2557927534
Short name T475
Test name
Test status
Simulation time 6595456217 ps
CPU time 16.45 seconds
Started Apr 18 01:51:49 PM PDT 24
Finished Apr 18 01:52:06 PM PDT 24
Peak memory 200004 kb
Host smart-202eb167-0f8e-4d81-b894-ded8ad5500e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2557927534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.2557927534
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.3123613128
Short name T491
Test name
Test status
Simulation time 3177513252 ps
CPU time 1.82 seconds
Started Apr 18 01:51:48 PM PDT 24
Finished Apr 18 01:51:50 PM PDT 24
Peak memory 197172 kb
Host smart-bc77cfbd-fd0e-4366-93d4-2baa181ef948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123613128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.3123613128
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.2322956824
Short name T1087
Test name
Test status
Simulation time 11626113891 ps
CPU time 42.24 seconds
Started Apr 18 01:51:58 PM PDT 24
Finished Apr 18 01:52:41 PM PDT 24
Peak memory 200684 kb
Host smart-e14098d3-59ae-4bb1-b32a-8aaa397bef63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322956824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.2322956824
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.1487716646
Short name T1066
Test name
Test status
Simulation time 115517298701 ps
CPU time 60.22 seconds
Started Apr 18 01:52:00 PM PDT 24
Finished Apr 18 01:53:01 PM PDT 24
Peak memory 200696 kb
Host smart-9ef58949-070a-4eef-8e83-1c5b704c93f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487716646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.1487716646
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.1119536573
Short name T1120
Test name
Test status
Simulation time 154207452677 ps
CPU time 295.21 seconds
Started Apr 18 01:51:49 PM PDT 24
Finished Apr 18 01:56:44 PM PDT 24
Peak memory 217328 kb
Host smart-58f680a5-6116-487d-a367-86366f075f4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119536573 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.1119536573
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.52338921
Short name T494
Test name
Test status
Simulation time 1585068108 ps
CPU time 2.04 seconds
Started Apr 18 01:51:56 PM PDT 24
Finished Apr 18 01:51:59 PM PDT 24
Peak memory 200824 kb
Host smart-94872f89-fa37-4631-8560-d1ed7386aecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52338921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.52338921
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.837336914
Short name T1084
Test name
Test status
Simulation time 40109566646 ps
CPU time 60.64 seconds
Started Apr 18 01:51:53 PM PDT 24
Finished Apr 18 01:52:54 PM PDT 24
Peak memory 200760 kb
Host smart-7e29496c-d645-4198-940c-94243d7c5d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837336914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.837336914
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.2258983453
Short name T896
Test name
Test status
Simulation time 10160430380 ps
CPU time 16.11 seconds
Started Apr 18 01:54:10 PM PDT 24
Finished Apr 18 01:54:27 PM PDT 24
Peak memory 200876 kb
Host smart-5b36d4c0-e18c-46a7-9b2a-01480df3ad98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258983453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2258983453
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.233238837
Short name T1064
Test name
Test status
Simulation time 166807310166 ps
CPU time 60.49 seconds
Started Apr 18 01:54:14 PM PDT 24
Finished Apr 18 01:55:14 PM PDT 24
Peak memory 200888 kb
Host smart-ff5c4a38-1cb2-456b-809b-e0d5b93f1696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233238837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.233238837
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.1054365855
Short name T795
Test name
Test status
Simulation time 56614470527 ps
CPU time 142.82 seconds
Started Apr 18 01:54:11 PM PDT 24
Finished Apr 18 01:56:34 PM PDT 24
Peak memory 200824 kb
Host smart-285ff05c-f2c3-40f7-bf51-4be9e047c2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054365855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1054365855
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.2245892021
Short name T757
Test name
Test status
Simulation time 33480726161 ps
CPU time 54.65 seconds
Started Apr 18 01:54:11 PM PDT 24
Finished Apr 18 01:55:06 PM PDT 24
Peak memory 200940 kb
Host smart-3af466f0-c368-4a71-8803-efe96069d739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245892021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.2245892021
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.3768603489
Short name T1060
Test name
Test status
Simulation time 49782455301 ps
CPU time 43.62 seconds
Started Apr 18 01:54:12 PM PDT 24
Finished Apr 18 01:54:56 PM PDT 24
Peak memory 200864 kb
Host smart-8812d50c-bdf0-4427-a26e-2160ae02cd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768603489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.3768603489
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.1112150006
Short name T726
Test name
Test status
Simulation time 30204324997 ps
CPU time 30.79 seconds
Started Apr 18 01:54:11 PM PDT 24
Finished Apr 18 01:54:43 PM PDT 24
Peak memory 200876 kb
Host smart-48498a6b-6156-4d30-b428-b91e91828070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112150006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.1112150006
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.3097362423
Short name T343
Test name
Test status
Simulation time 16173732 ps
CPU time 0.56 seconds
Started Apr 18 01:52:00 PM PDT 24
Finished Apr 18 01:52:01 PM PDT 24
Peak memory 196224 kb
Host smart-24073c1f-ab3d-4811-b31a-bfc3cbbaac02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097362423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.3097362423
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.2058161862
Short name T370
Test name
Test status
Simulation time 175012915603 ps
CPU time 260.96 seconds
Started Apr 18 01:51:48 PM PDT 24
Finished Apr 18 01:56:10 PM PDT 24
Peak memory 200852 kb
Host smart-cb422342-de65-4ab5-b81c-4d865adaed76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058161862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.2058161862
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.4137303780
Short name T132
Test name
Test status
Simulation time 27785557620 ps
CPU time 48.38 seconds
Started Apr 18 01:52:02 PM PDT 24
Finished Apr 18 01:52:51 PM PDT 24
Peak memory 200656 kb
Host smart-6cd8f65e-5d0c-44d7-a350-e3c6e388929a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137303780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.4137303780
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.244996544
Short name T1132
Test name
Test status
Simulation time 293427189588 ps
CPU time 34.28 seconds
Started Apr 18 01:51:49 PM PDT 24
Finished Apr 18 01:52:24 PM PDT 24
Peak memory 198192 kb
Host smart-21de6dfb-135e-4a54-be65-454650d91af5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244996544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.244996544
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.2998484712
Short name T737
Test name
Test status
Simulation time 106421720876 ps
CPU time 669.71 seconds
Started Apr 18 01:52:02 PM PDT 24
Finished Apr 18 02:03:12 PM PDT 24
Peak memory 200928 kb
Host smart-458b02d9-50a0-45c7-ada3-661d4823f450
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2998484712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.2998484712
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.2969624006
Short name T801
Test name
Test status
Simulation time 11533127830 ps
CPU time 23.82 seconds
Started Apr 18 01:51:46 PM PDT 24
Finished Apr 18 01:52:10 PM PDT 24
Peak memory 200780 kb
Host smart-f7a989d7-613a-411a-bedd-4f18be8c61fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969624006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.2969624006
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.4193712425
Short name T473
Test name
Test status
Simulation time 16528819513 ps
CPU time 16.8 seconds
Started Apr 18 01:52:07 PM PDT 24
Finished Apr 18 01:52:24 PM PDT 24
Peak memory 199672 kb
Host smart-b4c3d43a-bf0b-4a84-b8cf-a550f4c667bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193712425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.4193712425
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.3680416518
Short name T1054
Test name
Test status
Simulation time 3608345549 ps
CPU time 225.98 seconds
Started Apr 18 01:51:49 PM PDT 24
Finished Apr 18 01:55:35 PM PDT 24
Peak memory 200856 kb
Host smart-d73eee5d-d253-42c7-a59a-5436221f0316
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3680416518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.3680416518
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.382308545
Short name T994
Test name
Test status
Simulation time 1504594024 ps
CPU time 1.88 seconds
Started Apr 18 01:52:00 PM PDT 24
Finished Apr 18 01:52:02 PM PDT 24
Peak memory 198708 kb
Host smart-345e6db4-71a1-440a-b1aa-dc97bda9b3ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=382308545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.382308545
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.3313302286
Short name T977
Test name
Test status
Simulation time 81580435073 ps
CPU time 14.43 seconds
Started Apr 18 01:51:50 PM PDT 24
Finished Apr 18 01:52:05 PM PDT 24
Peak memory 200812 kb
Host smart-d45515ee-e3d2-4cc6-9d29-f2686c94ef19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313302286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.3313302286
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.2656901800
Short name T305
Test name
Test status
Simulation time 1903892797 ps
CPU time 3.64 seconds
Started Apr 18 01:51:49 PM PDT 24
Finished Apr 18 01:51:54 PM PDT 24
Peak memory 196260 kb
Host smart-6ab5c52a-156b-482c-b5c1-395125bc0dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656901800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.2656901800
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.565121004
Short name T301
Test name
Test status
Simulation time 560473887 ps
CPU time 1.9 seconds
Started Apr 18 01:52:06 PM PDT 24
Finished Apr 18 01:52:09 PM PDT 24
Peak memory 199684 kb
Host smart-b39f3259-e8e7-4dc8-b7ad-6cf61d5ee946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565121004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.565121004
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.1230683696
Short name T357
Test name
Test status
Simulation time 57783460871 ps
CPU time 101.91 seconds
Started Apr 18 01:51:50 PM PDT 24
Finished Apr 18 01:53:32 PM PDT 24
Peak memory 200896 kb
Host smart-4bcff63c-c991-4ed1-baca-6a5428831a12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230683696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.1230683696
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.1464844820
Short name T100
Test name
Test status
Simulation time 18770791229 ps
CPU time 205.14 seconds
Started Apr 18 01:51:59 PM PDT 24
Finished Apr 18 01:55:25 PM PDT 24
Peak memory 217360 kb
Host smart-760c08e4-224d-4deb-83b4-45b3faa1c400
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464844820 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.1464844820
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.4274870763
Short name T349
Test name
Test status
Simulation time 2492963249 ps
CPU time 2.95 seconds
Started Apr 18 01:51:55 PM PDT 24
Finished Apr 18 01:51:59 PM PDT 24
Peak memory 199724 kb
Host smart-1e47dd69-d9dc-4bf7-9ccf-f4c9b8592e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274870763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.4274870763
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.4117342478
Short name T446
Test name
Test status
Simulation time 58092429532 ps
CPU time 66.27 seconds
Started Apr 18 01:51:47 PM PDT 24
Finished Apr 18 01:52:53 PM PDT 24
Peak memory 200880 kb
Host smart-9cd5ef12-2cf7-4813-8635-b5d00f8b5d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117342478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.4117342478
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.412204339
Short name T190
Test name
Test status
Simulation time 18560815467 ps
CPU time 32.31 seconds
Started Apr 18 01:54:12 PM PDT 24
Finished Apr 18 01:54:45 PM PDT 24
Peak memory 200892 kb
Host smart-d59fa076-4eef-48eb-bea9-283b2fd5c16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412204339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.412204339
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.2038210286
Short name T180
Test name
Test status
Simulation time 54894295672 ps
CPU time 90.06 seconds
Started Apr 18 01:54:11 PM PDT 24
Finished Apr 18 01:55:42 PM PDT 24
Peak memory 200900 kb
Host smart-9bacc01f-df14-4bd6-a67a-9e87618a5d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038210286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.2038210286
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.2736199622
Short name T532
Test name
Test status
Simulation time 95692299528 ps
CPU time 10.9 seconds
Started Apr 18 01:54:16 PM PDT 24
Finished Apr 18 01:54:28 PM PDT 24
Peak memory 200584 kb
Host smart-502d62d3-ae3d-4099-8f02-76c0827d9e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736199622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.2736199622
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.3337522997
Short name T860
Test name
Test status
Simulation time 159943464810 ps
CPU time 147.23 seconds
Started Apr 18 01:54:12 PM PDT 24
Finished Apr 18 01:56:40 PM PDT 24
Peak memory 200840 kb
Host smart-59c4a951-a658-4b41-b3b9-4fa45cfb7028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337522997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.3337522997
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.2363168694
Short name T206
Test name
Test status
Simulation time 89130088341 ps
CPU time 41 seconds
Started Apr 18 01:54:11 PM PDT 24
Finished Apr 18 01:54:52 PM PDT 24
Peak memory 200796 kb
Host smart-eb69c813-be3b-45b1-9ebf-54bd544fda99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363168694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.2363168694
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.184871271
Short name T782
Test name
Test status
Simulation time 29528328920 ps
CPU time 37.12 seconds
Started Apr 18 01:54:10 PM PDT 24
Finished Apr 18 01:54:47 PM PDT 24
Peak memory 200904 kb
Host smart-baf91b7d-2aee-4bc2-bd66-070a1fa46837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184871271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.184871271
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.3715034480
Short name T1049
Test name
Test status
Simulation time 51739072 ps
CPU time 0.54 seconds
Started Apr 18 01:51:54 PM PDT 24
Finished Apr 18 01:51:55 PM PDT 24
Peak memory 196224 kb
Host smart-ecba6702-37c8-47c1-9425-e99c20394f85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715034480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.3715034480
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.3650682862
Short name T107
Test name
Test status
Simulation time 93015685888 ps
CPU time 42.28 seconds
Started Apr 18 01:52:06 PM PDT 24
Finished Apr 18 01:52:49 PM PDT 24
Peak memory 200880 kb
Host smart-5e744dc3-184a-4a6c-b323-9c3d96024734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650682862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.3650682862
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.3053628395
Short name T966
Test name
Test status
Simulation time 124161581312 ps
CPU time 15.14 seconds
Started Apr 18 01:51:49 PM PDT 24
Finished Apr 18 01:52:05 PM PDT 24
Peak memory 200872 kb
Host smart-033aad31-7421-4523-82f3-b5e984a8e153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053628395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.3053628395
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.4211635396
Short name T539
Test name
Test status
Simulation time 76538208670 ps
CPU time 32.9 seconds
Started Apr 18 01:52:02 PM PDT 24
Finished Apr 18 01:52:35 PM PDT 24
Peak memory 200604 kb
Host smart-500430a9-b373-4923-8d54-d5b5386ca963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211635396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.4211635396
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.4021679434
Short name T353
Test name
Test status
Simulation time 27173047895 ps
CPU time 7.37 seconds
Started Apr 18 01:51:47 PM PDT 24
Finished Apr 18 01:51:55 PM PDT 24
Peak memory 197872 kb
Host smart-03097f88-85ab-4717-80f9-603039a3097a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021679434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.4021679434
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.396408009
Short name T514
Test name
Test status
Simulation time 64752437825 ps
CPU time 144.44 seconds
Started Apr 18 01:52:12 PM PDT 24
Finished Apr 18 01:54:37 PM PDT 24
Peak memory 200900 kb
Host smart-0283d79f-6ea1-43a6-8ada-7558c8d8e083
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=396408009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.396408009
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.2136904860
Short name T345
Test name
Test status
Simulation time 6886574356 ps
CPU time 4.41 seconds
Started Apr 18 01:51:59 PM PDT 24
Finished Apr 18 01:52:04 PM PDT 24
Peak memory 199832 kb
Host smart-21f56f73-4a56-4edf-bea1-8e96e81a8ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136904860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.2136904860
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.4008152236
Short name T758
Test name
Test status
Simulation time 14325493101 ps
CPU time 7.85 seconds
Started Apr 18 01:51:48 PM PDT 24
Finished Apr 18 01:51:56 PM PDT 24
Peak memory 199940 kb
Host smart-c42fecd6-8306-4e7d-93c7-505e5e5db1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008152236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.4008152236
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.1932284816
Short name T578
Test name
Test status
Simulation time 15400937406 ps
CPU time 222.47 seconds
Started Apr 18 01:52:10 PM PDT 24
Finished Apr 18 01:55:53 PM PDT 24
Peak memory 200916 kb
Host smart-32887026-835d-4d4a-b053-3673026e9c42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1932284816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1932284816
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.1575843221
Short name T927
Test name
Test status
Simulation time 5501301086 ps
CPU time 3.79 seconds
Started Apr 18 01:51:59 PM PDT 24
Finished Apr 18 01:52:04 PM PDT 24
Peak memory 199772 kb
Host smart-c1fb96a9-1a75-4f1b-9b77-c68ab9f2d36c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1575843221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.1575843221
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.410381128
Short name T1020
Test name
Test status
Simulation time 16451113971 ps
CPU time 24.94 seconds
Started Apr 18 01:52:20 PM PDT 24
Finished Apr 18 01:52:46 PM PDT 24
Peak memory 200632 kb
Host smart-f0fb3be6-8f21-4578-bcca-fedad931a218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410381128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.410381128
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.2698696615
Short name T512
Test name
Test status
Simulation time 3021980607 ps
CPU time 1.79 seconds
Started Apr 18 01:51:46 PM PDT 24
Finished Apr 18 01:51:48 PM PDT 24
Peak memory 196896 kb
Host smart-21eee385-24c0-4f64-8a4b-8cae896fcbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698696615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.2698696615
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.2979419048
Short name T1116
Test name
Test status
Simulation time 5896940635 ps
CPU time 10.25 seconds
Started Apr 18 01:52:03 PM PDT 24
Finished Apr 18 01:52:14 PM PDT 24
Peak memory 200748 kb
Host smart-eaca0be4-1811-4247-a405-95fac1d715f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979419048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.2979419048
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.2554365773
Short name T522
Test name
Test status
Simulation time 398989433009 ps
CPU time 193.59 seconds
Started Apr 18 01:52:02 PM PDT 24
Finished Apr 18 01:55:16 PM PDT 24
Peak memory 201064 kb
Host smart-0b882c3b-a7c7-46bc-abcf-9985ff2a556e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554365773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.2554365773
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.718128860
Short name T41
Test name
Test status
Simulation time 144589010285 ps
CPU time 740.91 seconds
Started Apr 18 01:51:58 PM PDT 24
Finished Apr 18 02:04:19 PM PDT 24
Peak memory 225760 kb
Host smart-a7b121ee-67f6-43bb-a324-759d675b6024
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718128860 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.718128860
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.2164468428
Short name T461
Test name
Test status
Simulation time 1696065498 ps
CPU time 1.92 seconds
Started Apr 18 01:51:55 PM PDT 24
Finished Apr 18 01:51:58 PM PDT 24
Peak memory 199840 kb
Host smart-3d667d28-d243-40a5-bad0-b1b1af7ba712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164468428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.2164468428
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.1533227926
Short name T742
Test name
Test status
Simulation time 115313664211 ps
CPU time 120.83 seconds
Started Apr 18 01:52:09 PM PDT 24
Finished Apr 18 01:54:11 PM PDT 24
Peak memory 200900 kb
Host smart-620e6316-741c-41b6-926f-fe49df26aa89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533227926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.1533227926
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.3772496870
Short name T628
Test name
Test status
Simulation time 36022485360 ps
CPU time 30.58 seconds
Started Apr 18 01:54:11 PM PDT 24
Finished Apr 18 01:54:42 PM PDT 24
Peak memory 200692 kb
Host smart-54cd29fd-78b4-4720-a13e-3d44775ba4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772496870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.3772496870
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.1455438104
Short name T34
Test name
Test status
Simulation time 20506033555 ps
CPU time 22.16 seconds
Started Apr 18 01:54:19 PM PDT 24
Finished Apr 18 01:54:41 PM PDT 24
Peak memory 200836 kb
Host smart-cbd9dbb8-9c10-46ec-bdd8-96522ca03d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455438104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.1455438104
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.1127820570
Short name T963
Test name
Test status
Simulation time 13851394970 ps
CPU time 36.59 seconds
Started Apr 18 01:54:18 PM PDT 24
Finished Apr 18 01:54:55 PM PDT 24
Peak memory 200840 kb
Host smart-3d74adce-deba-4eaf-b7cd-4e0e51395a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127820570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.1127820570
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.2111791690
Short name T8
Test name
Test status
Simulation time 91018748996 ps
CPU time 243.21 seconds
Started Apr 18 01:54:15 PM PDT 24
Finished Apr 18 01:58:19 PM PDT 24
Peak memory 200816 kb
Host smart-49be5957-3f7c-4d50-8b14-d9aad92529d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111791690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.2111791690
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.2158302372
Short name T835
Test name
Test status
Simulation time 330925346516 ps
CPU time 476.63 seconds
Started Apr 18 01:54:16 PM PDT 24
Finished Apr 18 02:02:13 PM PDT 24
Peak memory 200904 kb
Host smart-f6739cc4-b79d-477d-bf41-e6a937229904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158302372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.2158302372
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.2519303023
Short name T856
Test name
Test status
Simulation time 95757840560 ps
CPU time 55.58 seconds
Started Apr 18 01:54:20 PM PDT 24
Finished Apr 18 01:55:16 PM PDT 24
Peak memory 200912 kb
Host smart-9f0324a5-6c36-49c0-bc36-f1f15f484de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519303023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.2519303023
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.972377895
Short name T827
Test name
Test status
Simulation time 101831144554 ps
CPU time 70.66 seconds
Started Apr 18 01:54:16 PM PDT 24
Finished Apr 18 01:55:27 PM PDT 24
Peak memory 200904 kb
Host smart-73d42f9e-53e8-4c18-a5b5-870e60115cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972377895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.972377895
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.3980805706
Short name T1053
Test name
Test status
Simulation time 40348195364 ps
CPU time 73.26 seconds
Started Apr 18 01:54:16 PM PDT 24
Finished Apr 18 01:55:30 PM PDT 24
Peak memory 200900 kb
Host smart-b7eedf5a-af50-45c9-b8cf-e425808f45d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980805706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.3980805706
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.436052835
Short name T53
Test name
Test status
Simulation time 53636538935 ps
CPU time 27.44 seconds
Started Apr 18 01:54:16 PM PDT 24
Finished Apr 18 01:54:44 PM PDT 24
Peak memory 200828 kb
Host smart-c69ebdb1-ac73-492e-8a4e-2bd241a223d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436052835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.436052835
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.2824781881
Short name T1000
Test name
Test status
Simulation time 12929966 ps
CPU time 0.56 seconds
Started Apr 18 01:52:16 PM PDT 24
Finished Apr 18 01:52:17 PM PDT 24
Peak memory 196144 kb
Host smart-c6367f94-a61d-4c3a-9193-7e73a67ac8e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824781881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.2824781881
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.3845749403
Short name T625
Test name
Test status
Simulation time 238588913971 ps
CPU time 361.79 seconds
Started Apr 18 01:52:12 PM PDT 24
Finished Apr 18 01:58:15 PM PDT 24
Peak memory 200836 kb
Host smart-cba873ca-acfc-4a71-bbe3-c380b7d02cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845749403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.3845749403
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.2308571703
Short name T327
Test name
Test status
Simulation time 91372189281 ps
CPU time 46.8 seconds
Started Apr 18 01:51:54 PM PDT 24
Finished Apr 18 01:52:41 PM PDT 24
Peak memory 200876 kb
Host smart-369ca97a-5b72-45fd-b9fb-6173958d3f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308571703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2308571703
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.3341742965
Short name T209
Test name
Test status
Simulation time 48985715660 ps
CPU time 19.52 seconds
Started Apr 18 01:51:55 PM PDT 24
Finished Apr 18 01:52:15 PM PDT 24
Peak memory 200644 kb
Host smart-feb0612a-6b84-4d41-a883-644aec21f681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341742965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.3341742965
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.2210335955
Short name T4
Test name
Test status
Simulation time 125719750215 ps
CPU time 166.14 seconds
Started Apr 18 01:51:54 PM PDT 24
Finished Apr 18 01:54:40 PM PDT 24
Peak memory 200864 kb
Host smart-186d1fa1-4130-4b83-8070-416399a9cb92
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210335955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.2210335955
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.895243286
Short name T771
Test name
Test status
Simulation time 83930891459 ps
CPU time 440.12 seconds
Started Apr 18 01:51:54 PM PDT 24
Finished Apr 18 01:59:15 PM PDT 24
Peak memory 200836 kb
Host smart-82535e57-37e1-47fb-ab0b-ddec8e18f99d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=895243286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.895243286
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.1124166361
Short name T796
Test name
Test status
Simulation time 3154293844 ps
CPU time 3.54 seconds
Started Apr 18 01:52:00 PM PDT 24
Finished Apr 18 01:52:04 PM PDT 24
Peak memory 198920 kb
Host smart-5b783c25-63c2-43ab-bffb-703c5854d625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124166361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.1124166361
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.1033544681
Short name T354
Test name
Test status
Simulation time 116561237075 ps
CPU time 47.94 seconds
Started Apr 18 01:52:16 PM PDT 24
Finished Apr 18 01:53:04 PM PDT 24
Peak memory 201020 kb
Host smart-dbe4bad7-69cc-42fc-8032-705e74c46f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033544681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.1033544681
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.883555995
Short name T859
Test name
Test status
Simulation time 15214059536 ps
CPU time 210.71 seconds
Started Apr 18 01:52:01 PM PDT 24
Finished Apr 18 01:55:32 PM PDT 24
Peak memory 200872 kb
Host smart-9c6def68-16a2-4084-b0f7-e10609c2df5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=883555995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.883555995
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.1189638833
Short name T814
Test name
Test status
Simulation time 1806165153 ps
CPU time 2.57 seconds
Started Apr 18 01:51:55 PM PDT 24
Finished Apr 18 01:51:58 PM PDT 24
Peak memory 199436 kb
Host smart-83f1e1d5-cb57-4e59-8ed8-31fe75745bb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1189638833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.1189638833
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.3759976692
Short name T973
Test name
Test status
Simulation time 111992661609 ps
CPU time 187.16 seconds
Started Apr 18 01:52:02 PM PDT 24
Finished Apr 18 01:55:10 PM PDT 24
Peak memory 200780 kb
Host smart-ca4d5c8b-4641-46c2-ae1d-17f0331b3f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759976692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.3759976692
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.1995153464
Short name T369
Test name
Test status
Simulation time 1689241306 ps
CPU time 1.92 seconds
Started Apr 18 01:51:54 PM PDT 24
Finished Apr 18 01:51:57 PM PDT 24
Peak memory 196260 kb
Host smart-bea2adb4-ddf6-48ee-93df-1795cfe8dcc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995153464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.1995153464
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.742584836
Short name T7
Test name
Test status
Simulation time 704306893 ps
CPU time 1.82 seconds
Started Apr 18 01:52:18 PM PDT 24
Finished Apr 18 01:52:20 PM PDT 24
Peak memory 200716 kb
Host smart-9525ef63-9b05-4169-b50f-93633571313d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742584836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.742584836
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.1274771561
Short name T923
Test name
Test status
Simulation time 104613210393 ps
CPU time 194.81 seconds
Started Apr 18 01:51:58 PM PDT 24
Finished Apr 18 01:55:13 PM PDT 24
Peak memory 200896 kb
Host smart-46b62230-3fce-4ae0-87f6-f5f6ff2f091d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274771561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.1274771561
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.512683557
Short name T524
Test name
Test status
Simulation time 2222622466 ps
CPU time 2.41 seconds
Started Apr 18 01:51:54 PM PDT 24
Finished Apr 18 01:51:58 PM PDT 24
Peak memory 199312 kb
Host smart-79002e1a-2e0d-415b-a76f-de56199b0f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512683557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.512683557
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.2138637287
Short name T481
Test name
Test status
Simulation time 64941431750 ps
CPU time 129.32 seconds
Started Apr 18 01:52:11 PM PDT 24
Finished Apr 18 01:54:21 PM PDT 24
Peak memory 200892 kb
Host smart-887fb2a6-2646-44ab-b835-83923983d49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138637287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.2138637287
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.1963423475
Short name T169
Test name
Test status
Simulation time 73875654564 ps
CPU time 92.01 seconds
Started Apr 18 01:54:17 PM PDT 24
Finished Apr 18 01:55:50 PM PDT 24
Peak memory 200832 kb
Host smart-39f08240-e797-418b-a85e-972854fea4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963423475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.1963423475
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.2474057792
Short name T144
Test name
Test status
Simulation time 186684638505 ps
CPU time 324.97 seconds
Started Apr 18 01:54:20 PM PDT 24
Finished Apr 18 01:59:45 PM PDT 24
Peak memory 200820 kb
Host smart-9f1660df-5813-4c5f-a30f-9d1320bf7896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474057792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2474057792
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.432534723
Short name T675
Test name
Test status
Simulation time 8732932506 ps
CPU time 5.35 seconds
Started Apr 18 01:54:16 PM PDT 24
Finished Apr 18 01:54:22 PM PDT 24
Peak memory 200812 kb
Host smart-db9b8856-2e67-47f2-b757-b54fbd6e11b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432534723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.432534723
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.561649265
Short name T480
Test name
Test status
Simulation time 20450958020 ps
CPU time 34.38 seconds
Started Apr 18 01:54:20 PM PDT 24
Finished Apr 18 01:54:55 PM PDT 24
Peak memory 200268 kb
Host smart-fc2999df-cd74-4b7b-af37-d07508f51625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561649265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.561649265
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.4091090339
Short name T558
Test name
Test status
Simulation time 74258289724 ps
CPU time 33.98 seconds
Started Apr 18 01:54:17 PM PDT 24
Finished Apr 18 01:54:51 PM PDT 24
Peak memory 200664 kb
Host smart-ef1ecea0-a4d4-460e-83ac-0cf884cf2cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091090339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.4091090339
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.2839760552
Short name T1061
Test name
Test status
Simulation time 34420729335 ps
CPU time 55.9 seconds
Started Apr 18 01:54:16 PM PDT 24
Finished Apr 18 01:55:12 PM PDT 24
Peak memory 200852 kb
Host smart-554b3096-cbe4-4789-b628-44d205c9496d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839760552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.2839760552
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.4073800149
Short name T721
Test name
Test status
Simulation time 17724661978 ps
CPU time 13.82 seconds
Started Apr 18 01:54:30 PM PDT 24
Finished Apr 18 01:54:44 PM PDT 24
Peak memory 200904 kb
Host smart-163184e0-19db-4dfe-a047-e7b3bbf6a5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073800149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.4073800149
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.2428165537
Short name T289
Test name
Test status
Simulation time 163599156047 ps
CPU time 63.37 seconds
Started Apr 18 01:54:17 PM PDT 24
Finished Apr 18 01:55:21 PM PDT 24
Peak memory 200764 kb
Host smart-b953070c-cc7b-46fe-98c0-0ede201319b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428165537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.2428165537
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.850019542
Short name T292
Test name
Test status
Simulation time 19773004985 ps
CPU time 8.24 seconds
Started Apr 18 01:54:19 PM PDT 24
Finished Apr 18 01:54:27 PM PDT 24
Peak memory 200796 kb
Host smart-98a34dd1-f1a4-42b5-9f69-49267c6d8946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850019542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.850019542
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.3941829024
Short name T21
Test name
Test status
Simulation time 15132505 ps
CPU time 0.56 seconds
Started Apr 18 01:51:58 PM PDT 24
Finished Apr 18 01:51:59 PM PDT 24
Peak memory 196220 kb
Host smart-5c3ca37b-61a7-4514-a1bd-8605c1db6272
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941829024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.3941829024
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.2369069324
Short name T554
Test name
Test status
Simulation time 126592835532 ps
CPU time 166.07 seconds
Started Apr 18 01:51:52 PM PDT 24
Finished Apr 18 01:54:39 PM PDT 24
Peak memory 200876 kb
Host smart-cfab469a-b7b3-4e20-a102-672fbe2a6afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369069324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.2369069324
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.1829551503
Short name T1168
Test name
Test status
Simulation time 43656220079 ps
CPU time 62.79 seconds
Started Apr 18 01:52:11 PM PDT 24
Finished Apr 18 01:53:14 PM PDT 24
Peak memory 200808 kb
Host smart-d2a08b51-1a2c-44ef-be2a-dda331111dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829551503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.1829551503
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.554449354
Short name T971
Test name
Test status
Simulation time 41219294115 ps
CPU time 13.25 seconds
Started Apr 18 01:51:54 PM PDT 24
Finished Apr 18 01:52:08 PM PDT 24
Peak memory 200772 kb
Host smart-84b497ce-101e-463f-83a6-42d61d49f9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554449354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.554449354
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.137023259
Short name T1144
Test name
Test status
Simulation time 31903420824 ps
CPU time 16.91 seconds
Started Apr 18 01:52:18 PM PDT 24
Finished Apr 18 01:52:35 PM PDT 24
Peak memory 200840 kb
Host smart-4a32f1b6-1f4d-4167-9f63-cc08fe147786
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137023259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.137023259
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.2974709691
Short name T672
Test name
Test status
Simulation time 122106286118 ps
CPU time 275.12 seconds
Started Apr 18 01:52:12 PM PDT 24
Finished Apr 18 01:56:48 PM PDT 24
Peak memory 200900 kb
Host smart-95a72168-38ef-43d7-81b4-22e2b6de75fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2974709691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.2974709691
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.4115836605
Short name T403
Test name
Test status
Simulation time 9401350655 ps
CPU time 7.21 seconds
Started Apr 18 01:52:11 PM PDT 24
Finished Apr 18 01:52:19 PM PDT 24
Peak memory 200700 kb
Host smart-1a2d01d4-1f30-4206-b0c4-727a2da1ad43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115836605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.4115836605
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.1197913464
Short name T255
Test name
Test status
Simulation time 102896002369 ps
CPU time 98.81 seconds
Started Apr 18 01:52:09 PM PDT 24
Finished Apr 18 01:53:49 PM PDT 24
Peak memory 201072 kb
Host smart-740a156b-b85b-4acf-87ea-82c052557e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197913464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.1197913464
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.1744444557
Short name T252
Test name
Test status
Simulation time 11339960775 ps
CPU time 491.39 seconds
Started Apr 18 01:52:11 PM PDT 24
Finished Apr 18 02:00:23 PM PDT 24
Peak memory 200908 kb
Host smart-993bdaa4-bc0c-4fab-b496-253a0d701c1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1744444557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.1744444557
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.283798738
Short name T818
Test name
Test status
Simulation time 2014984025 ps
CPU time 1.21 seconds
Started Apr 18 01:52:10 PM PDT 24
Finished Apr 18 01:52:12 PM PDT 24
Peak memory 199244 kb
Host smart-fb307cc2-8999-48e3-99da-2a1c67783d9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=283798738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.283798738
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.1929199962
Short name T639
Test name
Test status
Simulation time 49415057723 ps
CPU time 23.96 seconds
Started Apr 18 01:52:03 PM PDT 24
Finished Apr 18 01:52:27 PM PDT 24
Peak memory 200824 kb
Host smart-16aadb5e-169c-4d27-86c9-9b8d84fb4b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929199962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.1929199962
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.3884361970
Short name T287
Test name
Test status
Simulation time 36941059955 ps
CPU time 53.9 seconds
Started Apr 18 01:52:17 PM PDT 24
Finished Apr 18 01:53:12 PM PDT 24
Peak memory 196648 kb
Host smart-32fd5020-cb9b-4cf3-809d-2c6d753e204d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884361970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.3884361970
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.823840329
Short name T813
Test name
Test status
Simulation time 509765400 ps
CPU time 1.31 seconds
Started Apr 18 01:52:01 PM PDT 24
Finished Apr 18 01:52:03 PM PDT 24
Peak memory 199220 kb
Host smart-8d47e2d6-6c0a-4146-ba90-e9f4e3867817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823840329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.823840329
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.3844749034
Short name T448
Test name
Test status
Simulation time 35965069801 ps
CPU time 93.8 seconds
Started Apr 18 01:51:59 PM PDT 24
Finished Apr 18 01:53:33 PM PDT 24
Peak memory 200836 kb
Host smart-043200a7-f25a-4de8-9d1c-8ef56b8b032b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844749034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.3844749034
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.2757792074
Short name T1141
Test name
Test status
Simulation time 109630333520 ps
CPU time 279.79 seconds
Started Apr 18 01:52:01 PM PDT 24
Finished Apr 18 01:56:41 PM PDT 24
Peak memory 216084 kb
Host smart-189c575e-3ded-4d22-90b0-998f27b7ac7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757792074 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.2757792074
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.3736786625
Short name T763
Test name
Test status
Simulation time 691801406 ps
CPU time 1.9 seconds
Started Apr 18 01:52:08 PM PDT 24
Finished Apr 18 01:52:10 PM PDT 24
Peak memory 199392 kb
Host smart-a31384b5-e5eb-4ba0-833a-f20ba2c45e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736786625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.3736786625
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.2142895676
Short name T649
Test name
Test status
Simulation time 99054167445 ps
CPU time 88.69 seconds
Started Apr 18 01:51:58 PM PDT 24
Finished Apr 18 01:53:27 PM PDT 24
Peak memory 200880 kb
Host smart-6f64a019-0e6e-48b7-b431-9bdd4bfa6d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142895676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.2142895676
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.2193547089
Short name T930
Test name
Test status
Simulation time 172268737757 ps
CPU time 243.29 seconds
Started Apr 18 01:54:19 PM PDT 24
Finished Apr 18 01:58:22 PM PDT 24
Peak memory 200784 kb
Host smart-18da5763-8250-4052-9bfb-b4b9938f857e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193547089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.2193547089
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.1067680450
Short name T976
Test name
Test status
Simulation time 114895279880 ps
CPU time 161.05 seconds
Started Apr 18 01:54:18 PM PDT 24
Finished Apr 18 01:56:59 PM PDT 24
Peak memory 200768 kb
Host smart-18ed467e-7c55-4fa2-91ee-35feea92e16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067680450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.1067680450
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.3159122581
Short name T171
Test name
Test status
Simulation time 29395145774 ps
CPU time 27.87 seconds
Started Apr 18 01:54:16 PM PDT 24
Finished Apr 18 01:54:45 PM PDT 24
Peak memory 200840 kb
Host smart-4552195f-0eaa-4fb8-949e-5d095227f382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159122581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.3159122581
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.3807342576
Short name T270
Test name
Test status
Simulation time 227561746319 ps
CPU time 39.41 seconds
Started Apr 18 01:54:18 PM PDT 24
Finished Apr 18 01:54:57 PM PDT 24
Peak memory 200848 kb
Host smart-d8b3dff8-1416-479b-804a-ed321650a5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807342576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.3807342576
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.3506687250
Short name T998
Test name
Test status
Simulation time 5929277417 ps
CPU time 9.73 seconds
Started Apr 18 01:54:21 PM PDT 24
Finished Apr 18 01:54:31 PM PDT 24
Peak memory 200724 kb
Host smart-3747fac3-5a61-48fc-bb26-b2833e1b848e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506687250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.3506687250
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.515556229
Short name T1162
Test name
Test status
Simulation time 183748593475 ps
CPU time 88.85 seconds
Started Apr 18 01:54:30 PM PDT 24
Finished Apr 18 01:55:59 PM PDT 24
Peak memory 200808 kb
Host smart-2c7e8365-a309-4a52-acf7-258de2061ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515556229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.515556229
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.1860202071
Short name T956
Test name
Test status
Simulation time 36742919812 ps
CPU time 64.15 seconds
Started Apr 18 01:54:22 PM PDT 24
Finished Apr 18 01:55:27 PM PDT 24
Peak memory 200848 kb
Host smart-5ea12766-d940-4fa0-93b8-9f675685254f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860202071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.1860202071
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.1946371486
Short name T286
Test name
Test status
Simulation time 83572489263 ps
CPU time 118.65 seconds
Started Apr 18 01:54:22 PM PDT 24
Finished Apr 18 01:56:21 PM PDT 24
Peak memory 200924 kb
Host smart-9b67b283-0812-44f1-85ae-6a9ba1d914f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946371486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.1946371486
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.1902375632
Short name T862
Test name
Test status
Simulation time 36347538524 ps
CPU time 13.85 seconds
Started Apr 18 01:54:20 PM PDT 24
Finished Apr 18 01:54:34 PM PDT 24
Peak memory 201020 kb
Host smart-c219bcd8-f72f-4174-860e-8eab23bd000f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902375632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.1902375632
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.492463195
Short name T1022
Test name
Test status
Simulation time 38285733 ps
CPU time 0.56 seconds
Started Apr 18 01:52:03 PM PDT 24
Finished Apr 18 01:52:04 PM PDT 24
Peak memory 195184 kb
Host smart-d3a6c7a6-3b04-4bb2-a367-c64fdb5799c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492463195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.492463195
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.3369461533
Short name T679
Test name
Test status
Simulation time 68795601233 ps
CPU time 56.74 seconds
Started Apr 18 01:51:59 PM PDT 24
Finished Apr 18 01:52:57 PM PDT 24
Peak memory 200824 kb
Host smart-3eaa8884-a531-42b1-a69a-a06727aba738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369461533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3369461533
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.2778513641
Short name T487
Test name
Test status
Simulation time 328014654295 ps
CPU time 49.98 seconds
Started Apr 18 01:51:55 PM PDT 24
Finished Apr 18 01:52:46 PM PDT 24
Peak memory 200900 kb
Host smart-fc9c814c-3f45-4fca-8751-f8b4b903fcae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778513641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.2778513641
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.1434659551
Short name T875
Test name
Test status
Simulation time 191240212279 ps
CPU time 24.28 seconds
Started Apr 18 01:52:03 PM PDT 24
Finished Apr 18 01:52:28 PM PDT 24
Peak memory 200872 kb
Host smart-bc54d51c-94e4-476e-bc60-b4468d67eea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434659551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.1434659551
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.2517356516
Short name T352
Test name
Test status
Simulation time 159483412584 ps
CPU time 405.31 seconds
Started Apr 18 01:52:03 PM PDT 24
Finished Apr 18 01:58:48 PM PDT 24
Peak memory 200884 kb
Host smart-aa857983-c74c-46ca-86ee-d6325e8be283
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2517356516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.2517356516
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.295818029
Short name T654
Test name
Test status
Simulation time 2298762425 ps
CPU time 1.54 seconds
Started Apr 18 01:52:17 PM PDT 24
Finished Apr 18 01:52:19 PM PDT 24
Peak memory 196896 kb
Host smart-155581ec-c33b-4eae-9dea-bc2c98bf1e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295818029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.295818029
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.2514354022
Short name T306
Test name
Test status
Simulation time 127280886688 ps
CPU time 53.95 seconds
Started Apr 18 01:51:57 PM PDT 24
Finished Apr 18 01:52:52 PM PDT 24
Peak memory 209016 kb
Host smart-60b57f12-a04d-41ee-aafb-350d70cb2f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514354022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.2514354022
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.4223524721
Short name T999
Test name
Test status
Simulation time 13639645932 ps
CPU time 713.92 seconds
Started Apr 18 01:51:57 PM PDT 24
Finished Apr 18 02:03:51 PM PDT 24
Peak memory 200812 kb
Host smart-84ff801a-01c0-42a4-ad0c-c1c277475b83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4223524721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.4223524721
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.2957696877
Short name T351
Test name
Test status
Simulation time 2135969286 ps
CPU time 2.16 seconds
Started Apr 18 01:52:13 PM PDT 24
Finished Apr 18 01:52:16 PM PDT 24
Peak memory 198916 kb
Host smart-ab542d49-63c1-4d28-ade2-92d01e25601f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2957696877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.2957696877
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.1401609463
Short name T439
Test name
Test status
Simulation time 184252633774 ps
CPU time 347.53 seconds
Started Apr 18 01:52:17 PM PDT 24
Finished Apr 18 01:58:05 PM PDT 24
Peak memory 200808 kb
Host smart-d6a49a8d-ed66-405f-bde8-7cad055168b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401609463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.1401609463
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.65774320
Short name T266
Test name
Test status
Simulation time 2730596107 ps
CPU time 1.93 seconds
Started Apr 18 01:52:01 PM PDT 24
Finished Apr 18 01:52:03 PM PDT 24
Peak memory 196608 kb
Host smart-bd702074-89ec-45b5-b8c6-9d66302c0e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65774320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.65774320
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.2599428304
Short name T1155
Test name
Test status
Simulation time 723841464 ps
CPU time 1.44 seconds
Started Apr 18 01:52:10 PM PDT 24
Finished Apr 18 01:52:12 PM PDT 24
Peak memory 200036 kb
Host smart-0c298aad-79af-4741-95d4-8b558dfcf3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599428304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2599428304
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.922555933
Short name T720
Test name
Test status
Simulation time 181204537849 ps
CPU time 72.34 seconds
Started Apr 18 01:52:04 PM PDT 24
Finished Apr 18 01:53:17 PM PDT 24
Peak memory 200892 kb
Host smart-af8ee9bc-9911-43b1-b2dd-c4776c5eb0db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922555933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.922555933
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.2560984880
Short name T965
Test name
Test status
Simulation time 122656853198 ps
CPU time 162.34 seconds
Started Apr 18 01:52:04 PM PDT 24
Finished Apr 18 01:54:47 PM PDT 24
Peak memory 217428 kb
Host smart-bfa245c9-b912-49da-9964-8d6547dd3e97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560984880 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.2560984880
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.3504079249
Short name T1077
Test name
Test status
Simulation time 703774105 ps
CPU time 3.2 seconds
Started Apr 18 01:51:58 PM PDT 24
Finished Apr 18 01:52:02 PM PDT 24
Peak memory 200448 kb
Host smart-c558f0da-ca89-4fdd-ad12-8b92cace940a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504079249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.3504079249
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.251999481
Short name T444
Test name
Test status
Simulation time 48809626140 ps
CPU time 32.86 seconds
Started Apr 18 01:52:05 PM PDT 24
Finished Apr 18 01:52:38 PM PDT 24
Peak memory 200416 kb
Host smart-30cb41a3-f7da-4e4f-8df4-0c1d2990263c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251999481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.251999481
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.4206404924
Short name T329
Test name
Test status
Simulation time 114398748588 ps
CPU time 112.34 seconds
Started Apr 18 01:54:31 PM PDT 24
Finished Apr 18 01:56:24 PM PDT 24
Peak memory 200880 kb
Host smart-43d5fcf1-3db5-44ad-9a8a-c37128770174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206404924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.4206404924
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.2846565160
Short name T642
Test name
Test status
Simulation time 110566188329 ps
CPU time 28.16 seconds
Started Apr 18 01:54:23 PM PDT 24
Finished Apr 18 01:54:52 PM PDT 24
Peak memory 200896 kb
Host smart-af678282-c4d9-4516-bdb5-3e92ae63bcea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846565160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.2846565160
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.543940200
Short name T160
Test name
Test status
Simulation time 176652613929 ps
CPU time 40.46 seconds
Started Apr 18 01:54:21 PM PDT 24
Finished Apr 18 01:55:02 PM PDT 24
Peak memory 200908 kb
Host smart-b1e44ef0-39b0-4e36-a551-5dd321de29c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543940200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.543940200
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.1232825295
Short name T542
Test name
Test status
Simulation time 23804956303 ps
CPU time 21.13 seconds
Started Apr 18 01:54:23 PM PDT 24
Finished Apr 18 01:54:45 PM PDT 24
Peak memory 200836 kb
Host smart-055effa6-2e71-4be1-9650-4a8eaf29a55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232825295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.1232825295
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.701878525
Short name T219
Test name
Test status
Simulation time 46102327417 ps
CPU time 86.84 seconds
Started Apr 18 01:54:23 PM PDT 24
Finished Apr 18 01:55:51 PM PDT 24
Peak memory 200816 kb
Host smart-18d37307-cbcf-48ae-ab64-b6e21688aa93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701878525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.701878525
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.3989225064
Short name T886
Test name
Test status
Simulation time 244342616898 ps
CPU time 472.34 seconds
Started Apr 18 01:54:28 PM PDT 24
Finished Apr 18 02:02:21 PM PDT 24
Peak memory 200860 kb
Host smart-0094dd7f-0763-4616-9551-7bc20ab610fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989225064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.3989225064
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.1491579894
Short name T683
Test name
Test status
Simulation time 77982448574 ps
CPU time 136.03 seconds
Started Apr 18 01:54:21 PM PDT 24
Finished Apr 18 01:56:38 PM PDT 24
Peak memory 200872 kb
Host smart-e02402ad-246c-4612-a0a6-2b18d2924be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491579894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.1491579894
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.4154414355
Short name T253
Test name
Test status
Simulation time 91131293259 ps
CPU time 47.56 seconds
Started Apr 18 01:54:23 PM PDT 24
Finished Apr 18 01:55:11 PM PDT 24
Peak memory 200816 kb
Host smart-40d4a71b-5326-468a-a686-981d86e26219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154414355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.4154414355
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.865786359
Short name T1030
Test name
Test status
Simulation time 14572713 ps
CPU time 0.59 seconds
Started Apr 18 01:52:04 PM PDT 24
Finished Apr 18 01:52:05 PM PDT 24
Peak memory 196248 kb
Host smart-78fcfd2f-0ae3-4a8a-ab1d-d6e7defe17d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865786359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.865786359
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.286300599
Short name T1113
Test name
Test status
Simulation time 31175955013 ps
CPU time 14.34 seconds
Started Apr 18 01:52:11 PM PDT 24
Finished Apr 18 01:52:26 PM PDT 24
Peak memory 200756 kb
Host smart-ccd136f6-fe68-48de-814e-20b98ed0a9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286300599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.286300599
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.950915720
Short name T394
Test name
Test status
Simulation time 73808029566 ps
CPU time 111.85 seconds
Started Apr 18 01:52:15 PM PDT 24
Finished Apr 18 01:54:07 PM PDT 24
Peak memory 200788 kb
Host smart-57dc9a67-8582-495c-bdb4-b90a5fbc5fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950915720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.950915720
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.412267837
Short name T987
Test name
Test status
Simulation time 10045764041 ps
CPU time 6.12 seconds
Started Apr 18 01:51:59 PM PDT 24
Finished Apr 18 01:52:06 PM PDT 24
Peak memory 200752 kb
Host smart-9ecb522c-2ac0-4d25-bbec-067c574144d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412267837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.412267837
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.548367652
Short name T493
Test name
Test status
Simulation time 53168084730 ps
CPU time 97.72 seconds
Started Apr 18 01:52:19 PM PDT 24
Finished Apr 18 01:53:57 PM PDT 24
Peak memory 201088 kb
Host smart-de5a2dfa-2e09-4ef5-9eb2-1fb9a83aa471
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548367652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.548367652
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.4113139457
Short name T667
Test name
Test status
Simulation time 95718739220 ps
CPU time 759.16 seconds
Started Apr 18 01:52:13 PM PDT 24
Finished Apr 18 02:04:53 PM PDT 24
Peak memory 200708 kb
Host smart-c5a2b887-964d-4fe2-aa62-a0273922c7ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4113139457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.4113139457
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.1148664877
Short name T641
Test name
Test status
Simulation time 6429097260 ps
CPU time 7.73 seconds
Started Apr 18 01:52:08 PM PDT 24
Finished Apr 18 01:52:16 PM PDT 24
Peak memory 200804 kb
Host smart-3b579322-1f9c-48c2-abb0-2c788f6ce84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148664877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.1148664877
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.2205397124
Short name T858
Test name
Test status
Simulation time 36188105429 ps
CPU time 69.44 seconds
Started Apr 18 01:52:21 PM PDT 24
Finished Apr 18 01:53:31 PM PDT 24
Peak memory 201020 kb
Host smart-4cb72066-7be7-4a34-9d4c-c5e36d4450e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205397124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.2205397124
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.1946345237
Short name T267
Test name
Test status
Simulation time 18299967049 ps
CPU time 1097.98 seconds
Started Apr 18 01:52:04 PM PDT 24
Finished Apr 18 02:10:23 PM PDT 24
Peak memory 200804 kb
Host smart-52f73002-6c4b-48af-9155-89f6414f05ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1946345237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.1946345237
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.1077562195
Short name T331
Test name
Test status
Simulation time 4527617352 ps
CPU time 12.27 seconds
Started Apr 18 01:52:03 PM PDT 24
Finished Apr 18 01:52:16 PM PDT 24
Peak memory 199124 kb
Host smart-fd42dfbe-a5b7-44f5-a26f-5933995c11d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1077562195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.1077562195
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.3676387361
Short name T135
Test name
Test status
Simulation time 118315475146 ps
CPU time 224.02 seconds
Started Apr 18 01:52:00 PM PDT 24
Finished Apr 18 01:55:44 PM PDT 24
Peak memory 200840 kb
Host smart-c5a0b886-d777-4897-b677-1d8c182848c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676387361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.3676387361
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.846597343
Short name T706
Test name
Test status
Simulation time 28949141170 ps
CPU time 13.62 seconds
Started Apr 18 01:52:15 PM PDT 24
Finished Apr 18 01:52:29 PM PDT 24
Peak memory 196968 kb
Host smart-4d0c7a51-7b5b-4071-b658-9cabaf2c6537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846597343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.846597343
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.2751804466
Short name T919
Test name
Test status
Simulation time 574220294 ps
CPU time 1.46 seconds
Started Apr 18 01:52:04 PM PDT 24
Finished Apr 18 01:52:06 PM PDT 24
Peak memory 199156 kb
Host smart-f05fe8df-fcce-4fd5-9728-1106e01f1ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751804466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.2751804466
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.1754361017
Short name T838
Test name
Test status
Simulation time 241257396238 ps
CPU time 390.59 seconds
Started Apr 18 01:52:20 PM PDT 24
Finished Apr 18 01:58:51 PM PDT 24
Peak memory 201092 kb
Host smart-7efb7af4-63e2-4cff-8740-7a3503b8b5ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754361017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.1754361017
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.3566915384
Short name T740
Test name
Test status
Simulation time 1301753912 ps
CPU time 4.68 seconds
Started Apr 18 01:51:59 PM PDT 24
Finished Apr 18 01:52:05 PM PDT 24
Peak memory 200716 kb
Host smart-0a311cb7-43a7-44d4-afc5-cb2570b64ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566915384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.3566915384
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.913545165
Short name T273
Test name
Test status
Simulation time 35396162096 ps
CPU time 58.97 seconds
Started Apr 18 01:52:07 PM PDT 24
Finished Apr 18 01:53:07 PM PDT 24
Peak memory 200908 kb
Host smart-4507e4da-3e2b-4ec0-8116-851334fac830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913545165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.913545165
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.516854246
Short name T953
Test name
Test status
Simulation time 40341754339 ps
CPU time 16.57 seconds
Started Apr 18 01:54:22 PM PDT 24
Finished Apr 18 01:54:40 PM PDT 24
Peak memory 200828 kb
Host smart-e3c4a3cc-e56c-4109-8033-70562adf1405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516854246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.516854246
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.240663626
Short name T223
Test name
Test status
Simulation time 43996945307 ps
CPU time 20.52 seconds
Started Apr 18 01:54:22 PM PDT 24
Finished Apr 18 01:54:43 PM PDT 24
Peak memory 200868 kb
Host smart-3a8ad541-344c-4964-a332-e6ebccb83ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240663626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.240663626
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.351214133
Short name T239
Test name
Test status
Simulation time 64558014441 ps
CPU time 81.19 seconds
Started Apr 18 01:54:23 PM PDT 24
Finished Apr 18 01:55:45 PM PDT 24
Peak memory 200820 kb
Host smart-ad929b2d-51a6-446d-ad47-b0957480040a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351214133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.351214133
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.679571759
Short name T572
Test name
Test status
Simulation time 16204255425 ps
CPU time 17.93 seconds
Started Apr 18 01:54:22 PM PDT 24
Finished Apr 18 01:54:40 PM PDT 24
Peak memory 200824 kb
Host smart-6b9e6ba7-897c-4595-ba49-932dbc96646f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679571759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.679571759
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.3791837114
Short name T150
Test name
Test status
Simulation time 23457353565 ps
CPU time 21.92 seconds
Started Apr 18 01:54:30 PM PDT 24
Finished Apr 18 01:54:52 PM PDT 24
Peak memory 200904 kb
Host smart-5662ba78-640d-4d27-a046-46b656dd7797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791837114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3791837114
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.3357452012
Short name T662
Test name
Test status
Simulation time 49634007672 ps
CPU time 45.77 seconds
Started Apr 18 01:54:27 PM PDT 24
Finished Apr 18 01:55:14 PM PDT 24
Peak memory 200836 kb
Host smart-2256e06e-9899-419a-bae9-53d82c062b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357452012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.3357452012
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.852861351
Short name T233
Test name
Test status
Simulation time 214833226470 ps
CPU time 144.36 seconds
Started Apr 18 01:54:36 PM PDT 24
Finished Apr 18 01:57:01 PM PDT 24
Peak memory 200856 kb
Host smart-b4a4e963-9da9-46be-86e5-b315069db0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852861351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.852861351
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.2850545510
Short name T871
Test name
Test status
Simulation time 62224023368 ps
CPU time 24.73 seconds
Started Apr 18 01:54:26 PM PDT 24
Finished Apr 18 01:54:52 PM PDT 24
Peak memory 200848 kb
Host smart-09410394-c95f-4ded-9989-8c76063dc75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850545510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.2850545510
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.618705950
Short name T894
Test name
Test status
Simulation time 10537645622 ps
CPU time 19.88 seconds
Started Apr 18 01:54:25 PM PDT 24
Finished Apr 18 01:54:45 PM PDT 24
Peak memory 200884 kb
Host smart-d17d668a-8cde-438a-b81f-aa4cc80c862c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618705950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.618705950
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.3961966478
Short name T366
Test name
Test status
Simulation time 36527943 ps
CPU time 0.56 seconds
Started Apr 18 01:51:35 PM PDT 24
Finished Apr 18 01:51:36 PM PDT 24
Peak memory 196196 kb
Host smart-a9d77814-3d54-4df3-bfd2-014ea0f6f52f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961966478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.3961966478
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.388091069
Short name T466
Test name
Test status
Simulation time 30100176755 ps
CPU time 50.4 seconds
Started Apr 18 01:51:13 PM PDT 24
Finished Apr 18 01:52:04 PM PDT 24
Peak memory 200884 kb
Host smart-495da48b-e9dc-42b0-82be-3180adb15453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388091069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.388091069
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.93971876
Short name T730
Test name
Test status
Simulation time 15346886001 ps
CPU time 5.77 seconds
Started Apr 18 01:51:25 PM PDT 24
Finished Apr 18 01:51:32 PM PDT 24
Peak memory 200788 kb
Host smart-abc1ae85-059d-4306-810e-61a3bb18acbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93971876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.93971876
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.2629364060
Short name T204
Test name
Test status
Simulation time 93409370884 ps
CPU time 39.61 seconds
Started Apr 18 01:51:18 PM PDT 24
Finished Apr 18 01:51:58 PM PDT 24
Peak memory 200828 kb
Host smart-99433102-3962-4038-aeae-39a8ada233ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629364060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.2629364060
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.3643529758
Short name T1152
Test name
Test status
Simulation time 19877409111 ps
CPU time 4.44 seconds
Started Apr 18 01:51:17 PM PDT 24
Finished Apr 18 01:51:22 PM PDT 24
Peak memory 200768 kb
Host smart-f6667c6f-1a86-442a-a760-aba7e9578888
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643529758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.3643529758
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.246283637
Short name T37
Test name
Test status
Simulation time 67358969044 ps
CPU time 723.87 seconds
Started Apr 18 01:51:25 PM PDT 24
Finished Apr 18 02:03:30 PM PDT 24
Peak memory 200784 kb
Host smart-981d5aeb-3204-4e28-b268-6eaf786073ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=246283637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.246283637
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.2663166111
Short name T933
Test name
Test status
Simulation time 2435873397 ps
CPU time 3.4 seconds
Started Apr 18 01:51:26 PM PDT 24
Finished Apr 18 01:51:31 PM PDT 24
Peak memory 198648 kb
Host smart-bec00b19-c5f4-4106-b590-aec53b52eeec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663166111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.2663166111
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.2731692831
Short name T743
Test name
Test status
Simulation time 169421786696 ps
CPU time 92.17 seconds
Started Apr 18 01:51:28 PM PDT 24
Finished Apr 18 01:53:01 PM PDT 24
Peak memory 200532 kb
Host smart-e9babc9b-45e5-45ff-a2b9-271cdf6729fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731692831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.2731692831
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.3620177516
Short name T967
Test name
Test status
Simulation time 23882637315 ps
CPU time 727.97 seconds
Started Apr 18 01:51:22 PM PDT 24
Finished Apr 18 02:03:31 PM PDT 24
Peak memory 200920 kb
Host smart-4336b6cc-25f7-451e-aaa6-cf7057765ae1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3620177516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.3620177516
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.1306229689
Short name T879
Test name
Test status
Simulation time 3812950640 ps
CPU time 3.15 seconds
Started Apr 18 01:51:11 PM PDT 24
Finished Apr 18 01:51:15 PM PDT 24
Peak memory 199304 kb
Host smart-837b26cb-b46e-4357-bb98-d64e3cdd519a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1306229689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.1306229689
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.3491592588
Short name T1073
Test name
Test status
Simulation time 43056304519 ps
CPU time 8.89 seconds
Started Apr 18 01:51:15 PM PDT 24
Finished Apr 18 01:51:24 PM PDT 24
Peak memory 199256 kb
Host smart-1b6e327a-e9c3-467e-af5f-e2fc82558dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491592588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.3491592588
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.2826501678
Short name T31
Test name
Test status
Simulation time 1789357622 ps
CPU time 1.31 seconds
Started Apr 18 01:51:15 PM PDT 24
Finished Apr 18 01:51:17 PM PDT 24
Peak memory 196260 kb
Host smart-d9eb79d1-4144-4724-9048-8c20eedb916e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826501678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.2826501678
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.3441806514
Short name T87
Test name
Test status
Simulation time 991853926 ps
CPU time 0.8 seconds
Started Apr 18 01:51:24 PM PDT 24
Finished Apr 18 01:51:26 PM PDT 24
Peak memory 218744 kb
Host smart-dabd5de8-8ffc-41ee-b67d-8ac81997da6b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441806514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.3441806514
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.43799563
Short name T793
Test name
Test status
Simulation time 6208220457 ps
CPU time 24.58 seconds
Started Apr 18 01:51:22 PM PDT 24
Finished Apr 18 01:51:48 PM PDT 24
Peak memory 200012 kb
Host smart-5e9968c0-763c-4bd4-a85c-4d0697823d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43799563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.43799563
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.935245684
Short name T96
Test name
Test status
Simulation time 15925260070 ps
CPU time 159.83 seconds
Started Apr 18 01:51:28 PM PDT 24
Finished Apr 18 01:54:09 PM PDT 24
Peak memory 217536 kb
Host smart-3dc51e2e-adf0-4277-b5ac-db080624b98e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935245684 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.935245684
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.3583063903
Short name T415
Test name
Test status
Simulation time 6735671256 ps
CPU time 17.37 seconds
Started Apr 18 01:51:24 PM PDT 24
Finished Apr 18 01:51:42 PM PDT 24
Peak memory 200772 kb
Host smart-d5f5187c-5488-4b41-ae2c-e41128c5a414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583063903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.3583063903
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.597145561
Short name T1164
Test name
Test status
Simulation time 53539956282 ps
CPU time 132.93 seconds
Started Apr 18 01:51:26 PM PDT 24
Finished Apr 18 01:53:40 PM PDT 24
Peak memory 200876 kb
Host smart-9ea0b06d-9d2d-4417-958a-2d6db6eb2447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597145561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.597145561
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.563176739
Short name T556
Test name
Test status
Simulation time 13027973 ps
CPU time 0.56 seconds
Started Apr 18 01:52:07 PM PDT 24
Finished Apr 18 01:52:08 PM PDT 24
Peak memory 195712 kb
Host smart-367367fd-e17e-4d93-a318-ba712597c5d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563176739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.563176739
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.3699197755
Short name T904
Test name
Test status
Simulation time 51196790994 ps
CPU time 10.44 seconds
Started Apr 18 01:52:06 PM PDT 24
Finished Apr 18 01:52:17 PM PDT 24
Peak memory 200844 kb
Host smart-0675e41d-7c2b-4f91-b4bb-af50c6fee50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699197755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.3699197755
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.2195676236
Short name T883
Test name
Test status
Simulation time 122297226933 ps
CPU time 125.59 seconds
Started Apr 18 01:52:02 PM PDT 24
Finished Apr 18 01:54:08 PM PDT 24
Peak memory 200824 kb
Host smart-e90e026a-54b4-4353-856c-650b20e60401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195676236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.2195676236
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.2643377421
Short name T330
Test name
Test status
Simulation time 187635807581 ps
CPU time 92.76 seconds
Started Apr 18 01:52:05 PM PDT 24
Finished Apr 18 01:53:38 PM PDT 24
Peak memory 200836 kb
Host smart-027a638b-51a9-4cf6-95f5-9f2893c2bcb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643377421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.2643377421
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.715446615
Short name T810
Test name
Test status
Simulation time 35516741802 ps
CPU time 30.72 seconds
Started Apr 18 01:52:04 PM PDT 24
Finished Apr 18 01:52:36 PM PDT 24
Peak memory 200896 kb
Host smart-34752efc-8492-4a57-8fdd-f111525076ea
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715446615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.715446615
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.4115721246
Short name T407
Test name
Test status
Simulation time 163729645069 ps
CPU time 239.28 seconds
Started Apr 18 01:52:05 PM PDT 24
Finished Apr 18 01:56:05 PM PDT 24
Peak memory 200876 kb
Host smart-b6338bb8-0b1c-462d-bbc8-ef2cfe3a7d45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4115721246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.4115721246
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.1252652407
Short name T91
Test name
Test status
Simulation time 7091167047 ps
CPU time 4.49 seconds
Started Apr 18 01:52:11 PM PDT 24
Finished Apr 18 01:52:16 PM PDT 24
Peak memory 200576 kb
Host smart-bb43ad21-8ada-480c-90e9-4b431b017f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252652407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.1252652407
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.2373052891
Short name T615
Test name
Test status
Simulation time 72593085515 ps
CPU time 140.85 seconds
Started Apr 18 01:52:13 PM PDT 24
Finished Apr 18 01:54:35 PM PDT 24
Peak memory 199964 kb
Host smart-96a87f60-04ca-4b38-8981-7d84f47151e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373052891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.2373052891
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.720852971
Short name T898
Test name
Test status
Simulation time 11030181322 ps
CPU time 275.18 seconds
Started Apr 18 01:52:04 PM PDT 24
Finished Apr 18 01:56:40 PM PDT 24
Peak memory 200884 kb
Host smart-666641c6-d7e9-41ad-9c8d-6baa4ef8f258
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=720852971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.720852971
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.3331560846
Short name T74
Test name
Test status
Simulation time 3799890662 ps
CPU time 31.58 seconds
Started Apr 18 01:52:04 PM PDT 24
Finished Apr 18 01:52:37 PM PDT 24
Peak memory 198808 kb
Host smart-819ac2e9-5973-4fc3-a44c-a66af4acc3ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3331560846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.3331560846
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.572683066
Short name T94
Test name
Test status
Simulation time 141880447090 ps
CPU time 25.42 seconds
Started Apr 18 01:52:06 PM PDT 24
Finished Apr 18 01:52:32 PM PDT 24
Peak memory 200092 kb
Host smart-40176a2c-d9b9-4d44-9274-e36db9042cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572683066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.572683066
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.1612269950
Short name T488
Test name
Test status
Simulation time 765353866 ps
CPU time 1.34 seconds
Started Apr 18 01:52:05 PM PDT 24
Finished Apr 18 01:52:07 PM PDT 24
Peak memory 196244 kb
Host smart-eadeadc9-d1a6-4663-bb13-e7eb2ba13724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612269950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.1612269950
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.1650107724
Short name T979
Test name
Test status
Simulation time 687218884 ps
CPU time 1.33 seconds
Started Apr 18 01:52:15 PM PDT 24
Finished Apr 18 01:52:17 PM PDT 24
Peak memory 200200 kb
Host smart-74b00124-0220-4e69-b37d-95a8f2143d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650107724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.1650107724
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.408251429
Short name T686
Test name
Test status
Simulation time 322389018887 ps
CPU time 346.49 seconds
Started Apr 18 01:52:15 PM PDT 24
Finished Apr 18 01:58:02 PM PDT 24
Peak memory 217432 kb
Host smart-712858a8-caa4-414f-8962-26725e828e3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408251429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.408251429
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.1078850322
Short name T60
Test name
Test status
Simulation time 39262233446 ps
CPU time 296.05 seconds
Started Apr 18 01:52:13 PM PDT 24
Finished Apr 18 01:57:10 PM PDT 24
Peak memory 209260 kb
Host smart-97893731-e962-4ab9-9fff-1ea140dd2ecd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078850322 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.1078850322
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.3050121012
Short name T548
Test name
Test status
Simulation time 778761944 ps
CPU time 2.79 seconds
Started Apr 18 01:52:05 PM PDT 24
Finished Apr 18 01:52:08 PM PDT 24
Peak memory 199576 kb
Host smart-9a93a426-79a7-4adf-a6e2-71a859bc8399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050121012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.3050121012
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.1423647168
Short name T460
Test name
Test status
Simulation time 114649827092 ps
CPU time 51.57 seconds
Started Apr 18 01:52:03 PM PDT 24
Finished Apr 18 01:52:55 PM PDT 24
Peak memory 200924 kb
Host smart-9e8178bc-a520-45da-8a79-d2a15109a34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423647168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.1423647168
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.2872179466
Short name T350
Test name
Test status
Simulation time 8549329193 ps
CPU time 7.76 seconds
Started Apr 18 01:54:27 PM PDT 24
Finished Apr 18 01:54:35 PM PDT 24
Peak memory 200904 kb
Host smart-3b0a3103-1817-4760-a94d-8b68586fc747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872179466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.2872179466
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.1974468026
Short name T841
Test name
Test status
Simulation time 36923753811 ps
CPU time 13.36 seconds
Started Apr 18 01:54:28 PM PDT 24
Finished Apr 18 01:54:43 PM PDT 24
Peak memory 200692 kb
Host smart-3ebf3473-5446-4e6b-81b6-f024be0e46a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974468026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.1974468026
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.618827861
Short name T129
Test name
Test status
Simulation time 78358971678 ps
CPU time 94.17 seconds
Started Apr 18 01:54:27 PM PDT 24
Finished Apr 18 01:56:02 PM PDT 24
Peak memory 200900 kb
Host smart-31fdfffd-b1bf-4de5-a7ff-737b3e50ebd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618827861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.618827861
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.3512519277
Short name T224
Test name
Test status
Simulation time 55605321619 ps
CPU time 48.79 seconds
Started Apr 18 01:54:28 PM PDT 24
Finished Apr 18 01:55:18 PM PDT 24
Peak memory 200676 kb
Host smart-fed5cdbe-9ff6-4740-beca-582fe0662c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512519277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.3512519277
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.3318571556
Short name T905
Test name
Test status
Simulation time 112794842852 ps
CPU time 49.61 seconds
Started Apr 18 01:54:29 PM PDT 24
Finished Apr 18 01:55:19 PM PDT 24
Peak memory 200264 kb
Host smart-a809f1ab-7f3b-4524-a811-9a423a550f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318571556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.3318571556
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.4260099637
Short name T182
Test name
Test status
Simulation time 24720686038 ps
CPU time 11.12 seconds
Started Apr 18 01:54:27 PM PDT 24
Finished Apr 18 01:54:40 PM PDT 24
Peak memory 200812 kb
Host smart-d6992057-c41a-477d-b493-d6248e482539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260099637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.4260099637
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.2422537051
Short name T560
Test name
Test status
Simulation time 35117783667 ps
CPU time 20.12 seconds
Started Apr 18 01:54:27 PM PDT 24
Finished Apr 18 01:54:48 PM PDT 24
Peak memory 200904 kb
Host smart-320fb8ec-2332-4eb1-948d-115307f6d457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422537051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2422537051
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.1759721171
Short name T623
Test name
Test status
Simulation time 116146814962 ps
CPU time 46.62 seconds
Started Apr 18 01:54:26 PM PDT 24
Finished Apr 18 01:55:13 PM PDT 24
Peak memory 200896 kb
Host smart-01604884-1f58-4fac-874e-da665f445c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759721171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1759721171
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.21784838
Short name T731
Test name
Test status
Simulation time 79346179311 ps
CPU time 128.73 seconds
Started Apr 18 01:54:28 PM PDT 24
Finished Apr 18 01:56:38 PM PDT 24
Peak memory 200856 kb
Host smart-9bdbfe3d-1f55-4069-903e-d3f3df1da60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21784838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.21784838
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.2854779480
Short name T804
Test name
Test status
Simulation time 13647552 ps
CPU time 0.56 seconds
Started Apr 18 01:52:05 PM PDT 24
Finished Apr 18 01:52:06 PM PDT 24
Peak memory 196224 kb
Host smart-362568b0-645b-4356-a5ec-e12d78761db1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854779480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.2854779480
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.585229817
Short name T569
Test name
Test status
Simulation time 73301276197 ps
CPU time 24.89 seconds
Started Apr 18 01:52:13 PM PDT 24
Finished Apr 18 01:52:39 PM PDT 24
Peak memory 200728 kb
Host smart-56cf1615-ee61-4cf9-a507-95af2c315968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585229817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.585229817
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.1056932658
Short name T1166
Test name
Test status
Simulation time 28741551486 ps
CPU time 45.65 seconds
Started Apr 18 01:52:19 PM PDT 24
Finished Apr 18 01:53:05 PM PDT 24
Peak memory 200832 kb
Host smart-e3976a38-1756-4a4f-b248-ce1881aa2ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056932658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.1056932658
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.1425846177
Short name T599
Test name
Test status
Simulation time 6818047868 ps
CPU time 5.92 seconds
Started Apr 18 01:52:19 PM PDT 24
Finished Apr 18 01:52:25 PM PDT 24
Peak memory 198628 kb
Host smart-a1bd0727-ef2c-4d6d-886e-1f2153400c0a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425846177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.1425846177
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.916815363
Short name T495
Test name
Test status
Simulation time 59627875160 ps
CPU time 122.44 seconds
Started Apr 18 01:52:05 PM PDT 24
Finished Apr 18 01:54:08 PM PDT 24
Peak memory 200840 kb
Host smart-e3a2c268-7ef9-4e17-ae98-9981d0b2b17b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=916815363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.916815363
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.2394558136
Short name T1081
Test name
Test status
Simulation time 4844856112 ps
CPU time 3.15 seconds
Started Apr 18 01:52:07 PM PDT 24
Finished Apr 18 01:52:10 PM PDT 24
Peak memory 200484 kb
Host smart-140a1da8-48a0-4477-9b8a-fda5d2ca277e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394558136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2394558136
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.2783673200
Short name T724
Test name
Test status
Simulation time 69926615065 ps
CPU time 119.4 seconds
Started Apr 18 01:52:10 PM PDT 24
Finished Apr 18 01:54:10 PM PDT 24
Peak memory 200476 kb
Host smart-21501ab3-7940-4ad5-bed9-a187cc8967f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783673200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.2783673200
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.2512507401
Short name T89
Test name
Test status
Simulation time 29663817123 ps
CPU time 319.06 seconds
Started Apr 18 01:52:20 PM PDT 24
Finished Apr 18 01:57:40 PM PDT 24
Peak memory 200852 kb
Host smart-7e128982-bf2d-470d-a45d-06cd1e49d3cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2512507401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.2512507401
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.776824546
Short name T820
Test name
Test status
Simulation time 6526722561 ps
CPU time 16.06 seconds
Started Apr 18 01:52:07 PM PDT 24
Finished Apr 18 01:52:24 PM PDT 24
Peak memory 199000 kb
Host smart-6e0c5b53-1769-41c9-b080-4b12103057b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=776824546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.776824546
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.851329050
Short name T877
Test name
Test status
Simulation time 41851335994 ps
CPU time 66.01 seconds
Started Apr 18 01:52:05 PM PDT 24
Finished Apr 18 01:53:11 PM PDT 24
Peak memory 200904 kb
Host smart-1111621a-9860-4289-9d3b-960c8aaf85e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851329050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.851329050
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.2681047490
Short name T571
Test name
Test status
Simulation time 66197351405 ps
CPU time 25.52 seconds
Started Apr 18 01:52:15 PM PDT 24
Finished Apr 18 01:52:41 PM PDT 24
Peak memory 196944 kb
Host smart-132693ac-360d-4aa5-82f8-5da1a4c16b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681047490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2681047490
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.1620400207
Short name T596
Test name
Test status
Simulation time 428576736 ps
CPU time 2.18 seconds
Started Apr 18 01:52:05 PM PDT 24
Finished Apr 18 01:52:08 PM PDT 24
Peak memory 199248 kb
Host smart-82826b73-0231-4f5a-a20c-1a1b6d40f5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620400207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.1620400207
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.737742458
Short name T168
Test name
Test status
Simulation time 537509986786 ps
CPU time 351.41 seconds
Started Apr 18 01:52:05 PM PDT 24
Finished Apr 18 01:57:57 PM PDT 24
Peak memory 200588 kb
Host smart-62d6f8f0-fa4e-429a-ad67-a4e077867bb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737742458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.737742458
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.2016999073
Short name T606
Test name
Test status
Simulation time 448067437 ps
CPU time 1.68 seconds
Started Apr 18 01:52:16 PM PDT 24
Finished Apr 18 01:52:18 PM PDT 24
Peak memory 199164 kb
Host smart-a65b4dc0-2e0b-48e4-9c64-472f34808548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016999073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.2016999073
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.777424253
Short name T1099
Test name
Test status
Simulation time 36013229496 ps
CPU time 134.32 seconds
Started Apr 18 01:52:13 PM PDT 24
Finished Apr 18 01:54:28 PM PDT 24
Peak memory 200904 kb
Host smart-e5b1ce81-4cc0-435d-b7a8-02b871d1ccdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777424253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.777424253
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.2010148095
Short name T1027
Test name
Test status
Simulation time 38320267574 ps
CPU time 14.99 seconds
Started Apr 18 01:54:30 PM PDT 24
Finished Apr 18 01:54:45 PM PDT 24
Peak memory 200616 kb
Host smart-9b9ad18a-4d26-4262-9d2b-e4a78cb026e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010148095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.2010148095
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.1223092734
Short name T673
Test name
Test status
Simulation time 114648179309 ps
CPU time 108.48 seconds
Started Apr 18 01:54:31 PM PDT 24
Finished Apr 18 01:56:19 PM PDT 24
Peak memory 200836 kb
Host smart-f867b7df-1a58-4738-bba0-7f3b011aa0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223092734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.1223092734
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.4032468452
Short name T154
Test name
Test status
Simulation time 218987171466 ps
CPU time 73.31 seconds
Started Apr 18 01:54:33 PM PDT 24
Finished Apr 18 01:55:46 PM PDT 24
Peak memory 200676 kb
Host smart-97883d2d-93b3-4db7-b077-4cb520e07d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032468452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.4032468452
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.4289169320
Short name T854
Test name
Test status
Simulation time 7570149821 ps
CPU time 13.56 seconds
Started Apr 18 01:54:31 PM PDT 24
Finished Apr 18 01:54:46 PM PDT 24
Peak memory 200900 kb
Host smart-5154524a-bb2e-492a-ab5f-c16cb514b951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289169320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.4289169320
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.1581372083
Short name T1108
Test name
Test status
Simulation time 126496861700 ps
CPU time 230.67 seconds
Started Apr 18 01:54:32 PM PDT 24
Finished Apr 18 01:58:23 PM PDT 24
Peak memory 200824 kb
Host smart-d3f716a5-c761-47c7-ae15-8704d85947c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581372083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1581372083
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.694814498
Short name T704
Test name
Test status
Simulation time 33079492180 ps
CPU time 45.14 seconds
Started Apr 18 01:54:31 PM PDT 24
Finished Apr 18 01:55:17 PM PDT 24
Peak memory 200920 kb
Host smart-a5422b6a-5b4a-4bca-9a9c-bf9f67a6577d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694814498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.694814498
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.3718923225
Short name T891
Test name
Test status
Simulation time 48808638176 ps
CPU time 138.51 seconds
Started Apr 18 01:54:30 PM PDT 24
Finished Apr 18 01:56:49 PM PDT 24
Peak memory 200856 kb
Host smart-01a5b351-f53a-4029-93fb-f74e607a6f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718923225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.3718923225
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.209655801
Short name T587
Test name
Test status
Simulation time 28247336978 ps
CPU time 46.02 seconds
Started Apr 18 01:54:35 PM PDT 24
Finished Apr 18 01:55:22 PM PDT 24
Peak memory 200832 kb
Host smart-54d34bb2-b57d-4195-be52-7260153df301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209655801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.209655801
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.1407018480
Short name T688
Test name
Test status
Simulation time 76760905 ps
CPU time 0.6 seconds
Started Apr 18 01:52:08 PM PDT 24
Finished Apr 18 01:52:09 PM PDT 24
Peak memory 196252 kb
Host smart-dff86dfc-99c7-421e-b261-998a5cd1d990
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407018480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.1407018480
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.2390223769
Short name T952
Test name
Test status
Simulation time 148316184614 ps
CPU time 72.54 seconds
Started Apr 18 01:52:03 PM PDT 24
Finished Apr 18 01:53:16 PM PDT 24
Peak memory 200896 kb
Host smart-1e2fc536-5603-4b4c-9998-206185d0cbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390223769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.2390223769
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.3412047415
Short name T934
Test name
Test status
Simulation time 43223675927 ps
CPU time 41.24 seconds
Started Apr 18 01:52:54 PM PDT 24
Finished Apr 18 01:53:36 PM PDT 24
Peak memory 200892 kb
Host smart-922c1c42-8fa5-44e3-ae08-c763a81ee842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412047415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.3412047415
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.3905367821
Short name T897
Test name
Test status
Simulation time 96685178425 ps
CPU time 178.59 seconds
Started Apr 18 01:52:20 PM PDT 24
Finished Apr 18 01:55:19 PM PDT 24
Peak memory 200904 kb
Host smart-b1409dd5-d622-4988-a8f6-187bdf1a0f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905367821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.3905367821
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.2333017388
Short name T427
Test name
Test status
Simulation time 14427167509 ps
CPU time 22.62 seconds
Started Apr 18 01:52:11 PM PDT 24
Finished Apr 18 01:52:34 PM PDT 24
Peak memory 197668 kb
Host smart-dfd326ea-d752-4cad-a3b8-c5cd018a0476
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333017388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.2333017388
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.806981099
Short name T1040
Test name
Test status
Simulation time 85210369940 ps
CPU time 171.8 seconds
Started Apr 18 01:52:17 PM PDT 24
Finished Apr 18 01:55:09 PM PDT 24
Peak memory 200836 kb
Host smart-00e6e3fb-ea90-49b8-b0fe-9f008be6f181
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=806981099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.806981099
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.3297778851
Short name T425
Test name
Test status
Simulation time 4784367550 ps
CPU time 15.66 seconds
Started Apr 18 01:52:12 PM PDT 24
Finished Apr 18 01:52:28 PM PDT 24
Peak memory 200772 kb
Host smart-79507e04-38b4-4404-8376-b2436d99d765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297778851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.3297778851
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.1206853672
Short name T648
Test name
Test status
Simulation time 113475928287 ps
CPU time 37.57 seconds
Started Apr 18 01:52:20 PM PDT 24
Finished Apr 18 01:52:58 PM PDT 24
Peak memory 200860 kb
Host smart-2ac615cb-7ca5-4c5d-a7d3-000b43c16f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206853672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.1206853672
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.2199762754
Short name T1037
Test name
Test status
Simulation time 14996031485 ps
CPU time 831.77 seconds
Started Apr 18 01:52:15 PM PDT 24
Finished Apr 18 02:06:08 PM PDT 24
Peak memory 200864 kb
Host smart-cc92a74b-36f4-414d-97ca-38883ec37ac5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2199762754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.2199762754
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.3009112427
Short name T468
Test name
Test status
Simulation time 2949089768 ps
CPU time 4.4 seconds
Started Apr 18 01:52:18 PM PDT 24
Finished Apr 18 01:52:23 PM PDT 24
Peak memory 199152 kb
Host smart-6096235e-78a8-4ae5-803a-fb063a878567
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3009112427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.3009112427
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.1380581655
Short name T520
Test name
Test status
Simulation time 27812568169 ps
CPU time 76.67 seconds
Started Apr 18 01:52:05 PM PDT 24
Finished Apr 18 01:53:22 PM PDT 24
Peak memory 200864 kb
Host smart-f5fe5536-e6fb-4d7b-8ed6-72067031ab8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380581655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.1380581655
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.3512307414
Short name T295
Test name
Test status
Simulation time 31655485341 ps
CPU time 55.43 seconds
Started Apr 18 01:52:16 PM PDT 24
Finished Apr 18 01:53:12 PM PDT 24
Peak memory 196640 kb
Host smart-fc2e0e53-e0c4-43b4-a29c-b23c6942f421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512307414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.3512307414
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.3064797290
Short name T1021
Test name
Test status
Simulation time 5367032789 ps
CPU time 8.51 seconds
Started Apr 18 01:52:02 PM PDT 24
Finished Apr 18 01:52:11 PM PDT 24
Peak memory 200760 kb
Host smart-1a290c42-b8e7-4c4b-bbab-056bea14270d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064797290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.3064797290
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.4095819116
Short name T561
Test name
Test status
Simulation time 115638955111 ps
CPU time 48.93 seconds
Started Apr 18 01:52:11 PM PDT 24
Finished Apr 18 01:53:00 PM PDT 24
Peak memory 200852 kb
Host smart-c7c65951-7a60-46b1-ab72-2007fbd004e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095819116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.4095819116
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.339436165
Short name T1032
Test name
Test status
Simulation time 2327501098 ps
CPU time 2.11 seconds
Started Apr 18 01:52:05 PM PDT 24
Finished Apr 18 01:52:07 PM PDT 24
Peak memory 199604 kb
Host smart-426d56da-e4e3-4e04-8759-8d74ca38cd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339436165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.339436165
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.3635373961
Short name T279
Test name
Test status
Simulation time 74298749867 ps
CPU time 200.22 seconds
Started Apr 18 01:52:11 PM PDT 24
Finished Apr 18 01:55:32 PM PDT 24
Peak memory 200804 kb
Host smart-dc35a047-3804-4ac1-89ed-97d394c9c670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635373961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.3635373961
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.1747694807
Short name T207
Test name
Test status
Simulation time 5217419095 ps
CPU time 13.1 seconds
Started Apr 18 01:54:35 PM PDT 24
Finished Apr 18 01:54:49 PM PDT 24
Peak memory 200832 kb
Host smart-1ec04944-324a-4f1c-af36-220af11aab6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747694807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1747694807
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.3488288141
Short name T163
Test name
Test status
Simulation time 123823218715 ps
CPU time 176.59 seconds
Started Apr 18 01:54:32 PM PDT 24
Finished Apr 18 01:57:29 PM PDT 24
Peak memory 200860 kb
Host smart-ed1fd234-8382-4069-bdd3-b5a301887a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488288141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.3488288141
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.2366420641
Short name T388
Test name
Test status
Simulation time 108987017645 ps
CPU time 186.61 seconds
Started Apr 18 01:54:35 PM PDT 24
Finished Apr 18 01:57:42 PM PDT 24
Peak memory 200828 kb
Host smart-09470f4d-4418-4450-a134-83b686622dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366420641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.2366420641
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.655985623
Short name T960
Test name
Test status
Simulation time 130556019821 ps
CPU time 158.12 seconds
Started Apr 18 01:54:34 PM PDT 24
Finished Apr 18 01:57:13 PM PDT 24
Peak memory 200752 kb
Host smart-eb6421ce-150a-4228-989f-5e78cb3238a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655985623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.655985623
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.3143410782
Short name T786
Test name
Test status
Simulation time 34313717922 ps
CPU time 35.43 seconds
Started Apr 18 01:54:35 PM PDT 24
Finished Apr 18 01:55:11 PM PDT 24
Peak memory 200896 kb
Host smart-13e277dd-c23a-45fd-a364-4cb46e81d36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143410782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.3143410782
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.194756966
Short name T855
Test name
Test status
Simulation time 239001380036 ps
CPU time 233.36 seconds
Started Apr 18 01:54:35 PM PDT 24
Finished Apr 18 01:58:29 PM PDT 24
Peak memory 200880 kb
Host smart-d5cd3abb-a28f-4637-9762-8fb0432afb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194756966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.194756966
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.2951305740
Short name T777
Test name
Test status
Simulation time 92601094811 ps
CPU time 41.28 seconds
Started Apr 18 01:54:33 PM PDT 24
Finished Apr 18 01:55:14 PM PDT 24
Peak memory 200496 kb
Host smart-e65a4108-eb83-40b7-8e05-b71d8743341b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951305740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.2951305740
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.3345346606
Short name T434
Test name
Test status
Simulation time 32657035 ps
CPU time 0.56 seconds
Started Apr 18 01:52:20 PM PDT 24
Finished Apr 18 01:52:22 PM PDT 24
Peak memory 196220 kb
Host smart-69080100-f91d-46a2-ad53-2609e2a5120c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345346606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.3345346606
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.747656988
Short name T589
Test name
Test status
Simulation time 61892419524 ps
CPU time 48.75 seconds
Started Apr 18 01:52:24 PM PDT 24
Finished Apr 18 01:53:14 PM PDT 24
Peak memory 200844 kb
Host smart-2bbae50a-d188-48ce-b226-0b32c40224fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747656988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.747656988
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.1061795115
Short name T955
Test name
Test status
Simulation time 29106134569 ps
CPU time 16.78 seconds
Started Apr 18 01:52:18 PM PDT 24
Finished Apr 18 01:52:35 PM PDT 24
Peak memory 200860 kb
Host smart-47a874eb-855a-42ad-a9e5-baaae06b1de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061795115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.1061795115
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_intr.799580941
Short name T695
Test name
Test status
Simulation time 47186177738 ps
CPU time 79.54 seconds
Started Apr 18 01:52:10 PM PDT 24
Finished Apr 18 01:53:30 PM PDT 24
Peak memory 200712 kb
Host smart-0016284f-3e1a-4027-9252-dc7c410378b3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799580941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.799580941
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.812116680
Short name T419
Test name
Test status
Simulation time 105926441844 ps
CPU time 370.07 seconds
Started Apr 18 01:52:24 PM PDT 24
Finished Apr 18 01:58:35 PM PDT 24
Peak memory 200740 kb
Host smart-b09b6af8-2a7f-4491-b866-fd0b75154699
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=812116680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.812116680
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.2187889635
Short name T1112
Test name
Test status
Simulation time 8192905181 ps
CPU time 9.91 seconds
Started Apr 18 01:52:10 PM PDT 24
Finished Apr 18 01:52:21 PM PDT 24
Peak memory 200680 kb
Host smart-47514f98-e2a3-4541-9004-40bb38c2d73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187889635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.2187889635
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.2159805135
Short name T974
Test name
Test status
Simulation time 95891601673 ps
CPU time 87.18 seconds
Started Apr 18 01:52:28 PM PDT 24
Finished Apr 18 01:53:56 PM PDT 24
Peak memory 200984 kb
Host smart-bf4874a0-1fa4-443f-98cb-48d9f8820e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159805135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.2159805135
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.750305390
Short name T1157
Test name
Test status
Simulation time 21682169189 ps
CPU time 210.99 seconds
Started Apr 18 01:52:13 PM PDT 24
Finished Apr 18 01:55:45 PM PDT 24
Peak memory 200928 kb
Host smart-29fbe3d7-0673-46ff-8a32-8893384d1c9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=750305390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.750305390
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.2306647983
Short name T595
Test name
Test status
Simulation time 2325931644 ps
CPU time 16.3 seconds
Started Apr 18 01:52:59 PM PDT 24
Finished Apr 18 01:53:16 PM PDT 24
Peak memory 198920 kb
Host smart-ad27e90e-cd2f-41ec-9ee7-64cebb4200e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2306647983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.2306647983
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.4277673589
Short name T117
Test name
Test status
Simulation time 96585216650 ps
CPU time 106.23 seconds
Started Apr 18 01:52:14 PM PDT 24
Finished Apr 18 01:54:01 PM PDT 24
Peak memory 200888 kb
Host smart-2b8c5ca9-9785-4763-a900-8e88b33f9d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277673589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.4277673589
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.368424041
Short name T297
Test name
Test status
Simulation time 2692720646 ps
CPU time 1.84 seconds
Started Apr 18 01:52:09 PM PDT 24
Finished Apr 18 01:52:12 PM PDT 24
Peak memory 196608 kb
Host smart-dc317e40-2421-4e31-8ed4-ae89360b6724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368424041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.368424041
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.696642889
Short name T843
Test name
Test status
Simulation time 5743803772 ps
CPU time 20.03 seconds
Started Apr 18 01:52:31 PM PDT 24
Finished Apr 18 01:52:51 PM PDT 24
Peak memory 199940 kb
Host smart-cd10cdd6-52e7-42c9-821a-121dcdc6c0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696642889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.696642889
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.4269039376
Short name T1124
Test name
Test status
Simulation time 156923559896 ps
CPU time 1149.96 seconds
Started Apr 18 01:52:20 PM PDT 24
Finished Apr 18 02:11:31 PM PDT 24
Peak memory 200888 kb
Host smart-cd624a6d-086f-41a9-9729-be36f76825c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269039376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.4269039376
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.2141837827
Short name T28
Test name
Test status
Simulation time 87610929933 ps
CPU time 487.03 seconds
Started Apr 18 01:52:19 PM PDT 24
Finished Apr 18 02:00:27 PM PDT 24
Peak memory 217608 kb
Host smart-f5027511-c20b-42ce-b0dd-86ee7f9954c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141837827 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.2141837827
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.984394950
Short name T774
Test name
Test status
Simulation time 1729908401 ps
CPU time 1.68 seconds
Started Apr 18 01:52:20 PM PDT 24
Finished Apr 18 01:52:22 PM PDT 24
Peak memory 199528 kb
Host smart-2a7c758c-cf13-4ffa-8605-b896ce6e9939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984394950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.984394950
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.3235725463
Short name T1011
Test name
Test status
Simulation time 26569380521 ps
CPU time 44.64 seconds
Started Apr 18 01:52:11 PM PDT 24
Finished Apr 18 01:52:56 PM PDT 24
Peak memory 200804 kb
Host smart-dc8133e1-8919-4f62-8ac3-2fd578a6a712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235725463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.3235725463
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.1741512894
Short name T1151
Test name
Test status
Simulation time 15486285305 ps
CPU time 21.69 seconds
Started Apr 18 01:54:32 PM PDT 24
Finished Apr 18 01:54:54 PM PDT 24
Peak memory 200832 kb
Host smart-704e6f79-69df-4c54-ae86-f7cc413fd72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741512894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.1741512894
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.967161107
Short name T189
Test name
Test status
Simulation time 180887235304 ps
CPU time 145.55 seconds
Started Apr 18 01:54:39 PM PDT 24
Finished Apr 18 01:57:05 PM PDT 24
Peak memory 200720 kb
Host smart-fd90cd33-8641-4218-a699-8b6e9ed4c592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967161107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.967161107
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.3720614797
Short name T990
Test name
Test status
Simulation time 116913139915 ps
CPU time 38.77 seconds
Started Apr 18 01:54:38 PM PDT 24
Finished Apr 18 01:55:17 PM PDT 24
Peak memory 200940 kb
Host smart-1cd47c2a-e9dd-464c-923d-3c25484422c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720614797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.3720614797
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.3381033941
Short name T1156
Test name
Test status
Simulation time 31424735891 ps
CPU time 52.8 seconds
Started Apr 18 01:54:36 PM PDT 24
Finished Apr 18 01:55:29 PM PDT 24
Peak memory 200844 kb
Host smart-8207b93e-7bbf-4a05-92fb-d571df01d1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381033941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.3381033941
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.3148168350
Short name T961
Test name
Test status
Simulation time 45414847729 ps
CPU time 18.52 seconds
Started Apr 18 01:54:36 PM PDT 24
Finished Apr 18 01:54:55 PM PDT 24
Peak memory 200876 kb
Host smart-46e02101-ed56-4900-b053-dd524ee4118f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148168350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.3148168350
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.1893581247
Short name T172
Test name
Test status
Simulation time 116979300176 ps
CPU time 162.77 seconds
Started Apr 18 01:54:37 PM PDT 24
Finished Apr 18 01:57:20 PM PDT 24
Peak memory 200872 kb
Host smart-217e0631-5a93-40e4-b376-ca7748ac93b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893581247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.1893581247
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.374632267
Short name T598
Test name
Test status
Simulation time 21960367284 ps
CPU time 39.94 seconds
Started Apr 18 01:54:38 PM PDT 24
Finished Apr 18 01:55:18 PM PDT 24
Peak memory 200764 kb
Host smart-fcc63cf0-616b-46ef-9995-d51ab7170a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374632267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.374632267
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.549678179
Short name T659
Test name
Test status
Simulation time 68670443255 ps
CPU time 28.48 seconds
Started Apr 18 01:54:38 PM PDT 24
Finished Apr 18 01:55:07 PM PDT 24
Peak memory 200800 kb
Host smart-c0fe5559-f152-4e2c-b644-235b660e4056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549678179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.549678179
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.2343304526
Short name T666
Test name
Test status
Simulation time 87522596330 ps
CPU time 138.91 seconds
Started Apr 18 01:54:39 PM PDT 24
Finished Apr 18 01:56:58 PM PDT 24
Peak memory 200896 kb
Host smart-8bb0c275-224d-4be0-abbb-26e0c5d78ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343304526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.2343304526
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.3034567166
Short name T619
Test name
Test status
Simulation time 98313998801 ps
CPU time 22.01 seconds
Started Apr 18 01:54:36 PM PDT 24
Finished Apr 18 01:54:59 PM PDT 24
Peak memory 200880 kb
Host smart-9959b45e-a9ed-4122-adf7-df7e17b5438d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034567166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.3034567166
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.4072620771
Short name T552
Test name
Test status
Simulation time 22944761 ps
CPU time 0.54 seconds
Started Apr 18 01:52:17 PM PDT 24
Finished Apr 18 01:52:18 PM PDT 24
Peak memory 196248 kb
Host smart-54f3625f-196c-4ab4-9a2b-2c1b82915b09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072620771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.4072620771
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.478357817
Short name T10
Test name
Test status
Simulation time 13360158725 ps
CPU time 19.84 seconds
Started Apr 18 01:52:11 PM PDT 24
Finished Apr 18 01:52:32 PM PDT 24
Peak memory 200840 kb
Host smart-b23af784-2d2b-4476-a695-2be02fd1f241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478357817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.478357817
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.1731431338
Short name T435
Test name
Test status
Simulation time 86407593467 ps
CPU time 112.84 seconds
Started Apr 18 01:52:10 PM PDT 24
Finished Apr 18 01:54:03 PM PDT 24
Peak memory 200896 kb
Host smart-e0928937-c656-4e85-bbb2-c17e13e917fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731431338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.1731431338
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.812295510
Short name T264
Test name
Test status
Simulation time 105056515304 ps
CPU time 76.62 seconds
Started Apr 18 01:52:15 PM PDT 24
Finished Apr 18 01:53:32 PM PDT 24
Peak memory 200816 kb
Host smart-ae6dd5e5-4b40-44c7-a590-4e58434449e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812295510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.812295510
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.549172422
Short name T993
Test name
Test status
Simulation time 318578402298 ps
CPU time 143.17 seconds
Started Apr 18 01:52:22 PM PDT 24
Finished Apr 18 01:54:47 PM PDT 24
Peak memory 199404 kb
Host smart-e6f2f950-f392-438b-9d6d-f873113c1cbb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549172422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.549172422
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.97145286
Short name T271
Test name
Test status
Simulation time 75825510295 ps
CPU time 688.78 seconds
Started Apr 18 01:52:23 PM PDT 24
Finished Apr 18 02:03:53 PM PDT 24
Peak memory 200832 kb
Host smart-0b13ab87-6b63-4620-87fb-95731980d2f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=97145286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.97145286
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.3041060922
Short name T390
Test name
Test status
Simulation time 5127144133 ps
CPU time 17.93 seconds
Started Apr 18 01:52:10 PM PDT 24
Finished Apr 18 01:52:29 PM PDT 24
Peak memory 199260 kb
Host smart-904f9bae-3ce1-4a8d-8be5-cac973d94aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041060922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3041060922
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.653172201
Short name T326
Test name
Test status
Simulation time 6540256252 ps
CPU time 11.26 seconds
Started Apr 18 01:52:13 PM PDT 24
Finished Apr 18 01:52:24 PM PDT 24
Peak memory 200792 kb
Host smart-736d0562-11dd-44a6-a95d-7f1184768f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653172201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.653172201
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.2448067854
Short name T1161
Test name
Test status
Simulation time 4953564803 ps
CPU time 181.5 seconds
Started Apr 18 01:52:19 PM PDT 24
Finished Apr 18 01:55:21 PM PDT 24
Peak memory 200928 kb
Host smart-535719fa-83a9-4ebe-9637-a544067482c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2448067854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2448067854
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.1358288336
Short name T549
Test name
Test status
Simulation time 3282941398 ps
CPU time 5.38 seconds
Started Apr 18 01:52:20 PM PDT 24
Finished Apr 18 01:52:27 PM PDT 24
Peak memory 198956 kb
Host smart-a61e78f9-c552-483f-b77d-6754ea870cc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1358288336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1358288336
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.1389082432
Short name T93
Test name
Test status
Simulation time 88241517746 ps
CPU time 164.02 seconds
Started Apr 18 01:52:13 PM PDT 24
Finished Apr 18 01:54:58 PM PDT 24
Peak memory 200872 kb
Host smart-8e5fe3ec-22ac-4825-9951-cc420b2325a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389082432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1389082432
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.3224079587
Short name T872
Test name
Test status
Simulation time 1051854329 ps
CPU time 1.58 seconds
Started Apr 18 01:52:20 PM PDT 24
Finished Apr 18 01:52:23 PM PDT 24
Peak memory 196284 kb
Host smart-c1a24ee0-d4ea-4e4c-815a-32713f7e9ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224079587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.3224079587
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.2183928298
Short name T51
Test name
Test status
Simulation time 558798659 ps
CPU time 1.79 seconds
Started Apr 18 01:52:25 PM PDT 24
Finished Apr 18 01:52:27 PM PDT 24
Peak memory 199696 kb
Host smart-62ff1c2a-937a-4fa6-88f8-7cfde00c3061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183928298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.2183928298
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.1057556940
Short name T889
Test name
Test status
Simulation time 215082284704 ps
CPU time 986.53 seconds
Started Apr 18 01:52:14 PM PDT 24
Finished Apr 18 02:08:41 PM PDT 24
Peak memory 200864 kb
Host smart-43f6b85e-2758-48a8-b399-7326245757e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057556940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.1057556940
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.605311709
Short name T482
Test name
Test status
Simulation time 297903163001 ps
CPU time 1000.19 seconds
Started Apr 18 01:52:22 PM PDT 24
Finished Apr 18 02:09:03 PM PDT 24
Peak memory 225656 kb
Host smart-182a7997-313f-49d5-8c05-790c011e7a04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605311709 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.605311709
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.2054130642
Short name T1136
Test name
Test status
Simulation time 806983591 ps
CPU time 1.76 seconds
Started Apr 18 01:52:12 PM PDT 24
Finished Apr 18 01:52:14 PM PDT 24
Peak memory 199760 kb
Host smart-5325836e-197f-463f-b95e-d362a3a2c104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054130642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.2054130642
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.2250623981
Short name T664
Test name
Test status
Simulation time 31315247282 ps
CPU time 65.06 seconds
Started Apr 18 01:52:18 PM PDT 24
Finished Apr 18 01:53:23 PM PDT 24
Peak memory 200896 kb
Host smart-c2cb8757-829b-4ed4-bfa6-1b94df4efb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250623981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.2250623981
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.4228713808
Short name T228
Test name
Test status
Simulation time 205502654628 ps
CPU time 47.44 seconds
Started Apr 18 01:54:36 PM PDT 24
Finished Apr 18 01:55:24 PM PDT 24
Peak memory 200860 kb
Host smart-c6d30fc1-5e8e-4da1-80e8-b04efcb84f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228713808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.4228713808
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.694800249
Short name T128
Test name
Test status
Simulation time 135969267309 ps
CPU time 59.49 seconds
Started Apr 18 01:54:37 PM PDT 24
Finished Apr 18 01:55:37 PM PDT 24
Peak memory 200844 kb
Host smart-d23baaac-a6b3-477c-b0f9-b2bbf6659a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694800249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.694800249
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.2917938969
Short name T922
Test name
Test status
Simulation time 18143100790 ps
CPU time 32.23 seconds
Started Apr 18 01:54:41 PM PDT 24
Finished Apr 18 01:55:13 PM PDT 24
Peak memory 200828 kb
Host smart-994a68c9-44f4-4ddf-8690-967f0711647c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917938969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.2917938969
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.3992545161
Short name T146
Test name
Test status
Simulation time 20221326959 ps
CPU time 13.71 seconds
Started Apr 18 01:54:38 PM PDT 24
Finished Apr 18 01:54:52 PM PDT 24
Peak memory 200788 kb
Host smart-a2330936-6fe5-41df-887e-135e8c7d346a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992545161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.3992545161
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.2284010651
Short name T1163
Test name
Test status
Simulation time 29597831630 ps
CPU time 13.82 seconds
Started Apr 18 01:54:43 PM PDT 24
Finished Apr 18 01:54:57 PM PDT 24
Peak memory 200668 kb
Host smart-4e429de1-801b-4b95-a97a-e016bbf36367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284010651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.2284010651
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.588837061
Short name T155
Test name
Test status
Simulation time 43473054427 ps
CPU time 20.46 seconds
Started Apr 18 01:54:41 PM PDT 24
Finished Apr 18 01:55:02 PM PDT 24
Peak memory 200816 kb
Host smart-17b57373-b68f-4da0-86be-4873264377fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588837061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.588837061
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.3943728182
Short name T868
Test name
Test status
Simulation time 90370189381 ps
CPU time 37.95 seconds
Started Apr 18 01:54:42 PM PDT 24
Finished Apr 18 01:55:21 PM PDT 24
Peak memory 200732 kb
Host smart-1afc1af5-4281-4fa7-9821-8ec6e839425d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943728182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.3943728182
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.1730751202
Short name T951
Test name
Test status
Simulation time 32240153672 ps
CPU time 76.32 seconds
Started Apr 18 01:54:43 PM PDT 24
Finished Apr 18 01:55:59 PM PDT 24
Peak memory 200828 kb
Host smart-49e38656-8f04-4fe1-8ce6-26520793164c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730751202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.1730751202
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.3998556040
Short name T928
Test name
Test status
Simulation time 30166874290 ps
CPU time 10.89 seconds
Started Apr 18 01:54:41 PM PDT 24
Finished Apr 18 01:54:52 PM PDT 24
Peak memory 200784 kb
Host smart-a58eb57b-9b1a-4818-84f5-db85deb721f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998556040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.3998556040
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.173484552
Short name T931
Test name
Test status
Simulation time 22645764 ps
CPU time 0.57 seconds
Started Apr 18 01:52:26 PM PDT 24
Finished Apr 18 01:52:27 PM PDT 24
Peak memory 196088 kb
Host smart-7740755c-3fc0-4703-a82a-9e68d24bc382
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173484552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.173484552
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.2831095724
Short name T409
Test name
Test status
Simulation time 64452546596 ps
CPU time 51.37 seconds
Started Apr 18 01:52:19 PM PDT 24
Finished Apr 18 01:53:11 PM PDT 24
Peak memory 200692 kb
Host smart-b1b765bd-3bef-475e-889e-264388dae9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831095724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.2831095724
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.3488664065
Short name T131
Test name
Test status
Simulation time 14541213172 ps
CPU time 23.19 seconds
Started Apr 18 01:52:23 PM PDT 24
Finished Apr 18 01:52:47 PM PDT 24
Peak memory 200828 kb
Host smart-919179e0-d009-43d1-b2c9-70c0f95a48c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488664065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.3488664065
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.3694669597
Short name T178
Test name
Test status
Simulation time 144471283986 ps
CPU time 253.6 seconds
Started Apr 18 01:52:22 PM PDT 24
Finished Apr 18 01:56:38 PM PDT 24
Peak memory 200304 kb
Host smart-0a82dad5-e47f-4a81-bf9b-d209f910b44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694669597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.3694669597
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.3130218427
Short name T105
Test name
Test status
Simulation time 51472169144 ps
CPU time 98.45 seconds
Started Apr 18 01:52:22 PM PDT 24
Finished Apr 18 01:54:02 PM PDT 24
Peak memory 200796 kb
Host smart-8b377ce0-e8a4-4b08-a1e0-d1ece44b27cc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130218427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.3130218427
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.2763778708
Short name T256
Test name
Test status
Simulation time 92542826970 ps
CPU time 245.61 seconds
Started Apr 18 01:52:25 PM PDT 24
Finished Apr 18 01:56:31 PM PDT 24
Peak memory 200800 kb
Host smart-8314d883-3d97-4e99-a584-a308d2dd6d29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2763778708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.2763778708
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.2453685194
Short name T453
Test name
Test status
Simulation time 13213819475 ps
CPU time 10.98 seconds
Started Apr 18 01:52:13 PM PDT 24
Finished Apr 18 01:52:25 PM PDT 24
Peak memory 200224 kb
Host smart-37488065-19d5-474c-abfc-a22cf4b10032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453685194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.2453685194
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.2254628432
Short name T848
Test name
Test status
Simulation time 78349623418 ps
CPU time 43.8 seconds
Started Apr 18 01:52:29 PM PDT 24
Finished Apr 18 01:53:13 PM PDT 24
Peak memory 200680 kb
Host smart-ee9d8886-7a9d-43de-8a56-0a227963a576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254628432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.2254628432
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.3846408302
Short name T837
Test name
Test status
Simulation time 8658421038 ps
CPU time 115.64 seconds
Started Apr 18 01:52:20 PM PDT 24
Finished Apr 18 01:54:16 PM PDT 24
Peak memory 200884 kb
Host smart-b35d3ecd-c374-41a0-9360-9d8790c4fd7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3846408302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.3846408302
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.4294252984
Short name T573
Test name
Test status
Simulation time 5846473285 ps
CPU time 48.19 seconds
Started Apr 18 01:52:16 PM PDT 24
Finished Apr 18 01:53:05 PM PDT 24
Peak memory 199056 kb
Host smart-21e5b801-f116-4788-94e2-ce958b54b499
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4294252984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.4294252984
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.1818904215
Short name T750
Test name
Test status
Simulation time 109447950579 ps
CPU time 39.02 seconds
Started Apr 18 01:52:16 PM PDT 24
Finished Apr 18 01:52:55 PM PDT 24
Peak memory 200828 kb
Host smart-65d70f80-6723-4adf-bd5a-fc889fdde991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818904215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.1818904215
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.2728751174
Short name T527
Test name
Test status
Simulation time 4996120068 ps
CPU time 3.87 seconds
Started Apr 18 01:52:21 PM PDT 24
Finished Apr 18 01:52:26 PM PDT 24
Peak memory 196924 kb
Host smart-e6a4f75e-cdf3-4ec2-8f10-128591edf7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728751174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.2728751174
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.2626980567
Short name T1058
Test name
Test status
Simulation time 118648007 ps
CPU time 0.99 seconds
Started Apr 18 01:52:14 PM PDT 24
Finished Apr 18 01:52:16 PM PDT 24
Peak memory 199656 kb
Host smart-f1f74725-e5a6-48b4-be22-bcacd93431fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626980567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.2626980567
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.639636662
Short name T184
Test name
Test status
Simulation time 49103286907 ps
CPU time 97.86 seconds
Started Apr 18 01:52:14 PM PDT 24
Finished Apr 18 01:53:52 PM PDT 24
Peak memory 200832 kb
Host smart-e9757a36-aef8-47ac-807a-6462175dea89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639636662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.639636662
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.2394887610
Short name T1101
Test name
Test status
Simulation time 314993776201 ps
CPU time 578.49 seconds
Started Apr 18 01:52:15 PM PDT 24
Finished Apr 18 02:01:55 PM PDT 24
Peak memory 227548 kb
Host smart-86653beb-891d-4177-a4d9-63c7dec15301
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394887610 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.2394887610
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.3919208375
Short name T276
Test name
Test status
Simulation time 6029572304 ps
CPU time 17.98 seconds
Started Apr 18 01:52:22 PM PDT 24
Finished Apr 18 01:52:40 PM PDT 24
Peak memory 200828 kb
Host smart-86ab3c34-ce7f-471e-bce4-654e6041e1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919208375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.3919208375
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.2633415688
Short name T414
Test name
Test status
Simulation time 113336320284 ps
CPU time 25.71 seconds
Started Apr 18 01:52:14 PM PDT 24
Finished Apr 18 01:52:40 PM PDT 24
Peak memory 200808 kb
Host smart-212a361d-b643-4b33-8931-f63fbb6ad9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633415688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.2633415688
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.2696863847
Short name T130
Test name
Test status
Simulation time 92523984245 ps
CPU time 39.51 seconds
Started Apr 18 01:54:41 PM PDT 24
Finished Apr 18 01:55:21 PM PDT 24
Peak memory 200908 kb
Host smart-3db31f92-5a87-4bcb-a825-d97b979e4e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696863847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2696863847
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.3578911782
Short name T454
Test name
Test status
Simulation time 52339985031 ps
CPU time 34.84 seconds
Started Apr 18 01:54:44 PM PDT 24
Finished Apr 18 01:55:19 PM PDT 24
Peak memory 200892 kb
Host smart-513b4b71-0138-4beb-b4ea-7ebdb27293fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578911782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.3578911782
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.226878723
Short name T635
Test name
Test status
Simulation time 57346160932 ps
CPU time 66.11 seconds
Started Apr 18 01:54:43 PM PDT 24
Finished Apr 18 01:55:49 PM PDT 24
Peak memory 200884 kb
Host smart-5eabe66e-b307-4079-82f2-27f7ed45f9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226878723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.226878723
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.2250105586
Short name T325
Test name
Test status
Simulation time 84955925248 ps
CPU time 291.86 seconds
Started Apr 18 01:54:41 PM PDT 24
Finished Apr 18 01:59:34 PM PDT 24
Peak memory 200840 kb
Host smart-2f702fa6-ad1b-46df-a3bc-44c21bd9e3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250105586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.2250105586
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.2482330567
Short name T1123
Test name
Test status
Simulation time 100323009264 ps
CPU time 95.46 seconds
Started Apr 18 01:54:42 PM PDT 24
Finished Apr 18 01:56:18 PM PDT 24
Peak memory 201044 kb
Host smart-d996713f-923d-4ccb-a9f3-b0580505b7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482330567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.2482330567
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.876878999
Short name T218
Test name
Test status
Simulation time 112358853072 ps
CPU time 594.6 seconds
Started Apr 18 01:54:47 PM PDT 24
Finished Apr 18 02:04:42 PM PDT 24
Peak memory 200796 kb
Host smart-4045a65e-ab55-49e0-9f8d-64b6ce476a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876878999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.876878999
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.3238948761
Short name T752
Test name
Test status
Simulation time 104664188992 ps
CPU time 163.02 seconds
Started Apr 18 01:54:42 PM PDT 24
Finished Apr 18 01:57:25 PM PDT 24
Peak memory 200856 kb
Host smart-7b3cbb17-7bb1-487c-9b14-b5743b7045cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238948761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.3238948761
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.1216472941
Short name T173
Test name
Test status
Simulation time 86032232664 ps
CPU time 153.48 seconds
Started Apr 18 01:54:42 PM PDT 24
Finished Apr 18 01:57:16 PM PDT 24
Peak memory 200868 kb
Host smart-185c2b5a-001e-4bc5-b7c3-97dc321d016e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216472941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.1216472941
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.4158165070
Short name T333
Test name
Test status
Simulation time 95356731 ps
CPU time 0.55 seconds
Started Apr 18 01:52:18 PM PDT 24
Finished Apr 18 01:52:19 PM PDT 24
Peak memory 195612 kb
Host smart-8705a59b-64e3-4fa0-8667-19ff31974ccb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158165070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.4158165070
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.587517340
Short name T157
Test name
Test status
Simulation time 97115219384 ps
CPU time 60.18 seconds
Started Apr 18 01:52:22 PM PDT 24
Finished Apr 18 01:53:24 PM PDT 24
Peak memory 200884 kb
Host smart-5a6f9e32-be98-4262-a571-cdd6dfa75c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587517340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.587517340
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.2725103992
Short name T1173
Test name
Test status
Simulation time 21191076358 ps
CPU time 9.93 seconds
Started Apr 18 01:52:23 PM PDT 24
Finished Apr 18 01:52:34 PM PDT 24
Peak memory 199896 kb
Host smart-adc0ee89-90e5-4979-a03d-3df9f5ff4bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725103992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.2725103992
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.1997095534
Short name T158
Test name
Test status
Simulation time 119592449742 ps
CPU time 191.25 seconds
Started Apr 18 01:52:27 PM PDT 24
Finished Apr 18 01:55:38 PM PDT 24
Peak memory 200824 kb
Host smart-2bc3b358-1916-4a27-a6c0-ca3d66da5bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997095534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.1997095534
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.1877439712
Short name T612
Test name
Test status
Simulation time 6896669037 ps
CPU time 14.39 seconds
Started Apr 18 01:52:19 PM PDT 24
Finished Apr 18 01:52:34 PM PDT 24
Peak memory 200900 kb
Host smart-e7d07abf-9080-4cfb-b941-b476e4bcc6db
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877439712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.1877439712
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.3945961743
Short name T792
Test name
Test status
Simulation time 127154827081 ps
CPU time 704.74 seconds
Started Apr 18 01:52:19 PM PDT 24
Finished Apr 18 02:04:05 PM PDT 24
Peak memory 200896 kb
Host smart-c2136af8-29b7-42cc-9c80-ab8b79367722
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3945961743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.3945961743
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.3697389357
Short name T1038
Test name
Test status
Simulation time 6761897999 ps
CPU time 4.76 seconds
Started Apr 18 01:52:26 PM PDT 24
Finished Apr 18 01:52:31 PM PDT 24
Peak memory 200804 kb
Host smart-c083154e-c4d7-45e9-a1dc-4c945e57f1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697389357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.3697389357
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.1485651935
Short name T970
Test name
Test status
Simulation time 33344860596 ps
CPU time 44 seconds
Started Apr 18 01:52:24 PM PDT 24
Finished Apr 18 01:53:09 PM PDT 24
Peak memory 199028 kb
Host smart-0ce356a2-c8a5-4bdd-bcb1-454a44dcc7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485651935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.1485651935
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.1732423710
Short name T476
Test name
Test status
Simulation time 30342335438 ps
CPU time 758.47 seconds
Started Apr 18 01:52:20 PM PDT 24
Finished Apr 18 02:04:59 PM PDT 24
Peak memory 200900 kb
Host smart-b695bfd5-6342-4eec-b499-204c0d84c239
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1732423710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.1732423710
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.1647984945
Short name T374
Test name
Test status
Simulation time 1930133770 ps
CPU time 3.6 seconds
Started Apr 18 01:52:23 PM PDT 24
Finished Apr 18 01:52:28 PM PDT 24
Peak memory 200252 kb
Host smart-81d1760c-7949-422e-ad60-03b2964179b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1647984945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.1647984945
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.253635703
Short name T873
Test name
Test status
Simulation time 44952582998 ps
CPU time 70.05 seconds
Started Apr 18 01:52:21 PM PDT 24
Finished Apr 18 01:53:31 PM PDT 24
Peak memory 200776 kb
Host smart-cb08fe6e-3ea4-4718-8abd-393b65be96be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253635703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.253635703
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.2616607980
Short name T1174
Test name
Test status
Simulation time 35504965409 ps
CPU time 57.89 seconds
Started Apr 18 01:52:20 PM PDT 24
Finished Apr 18 01:53:18 PM PDT 24
Peak memory 196620 kb
Host smart-45d196e5-18bf-43de-b256-525628252784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616607980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.2616607980
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.243874160
Short name T734
Test name
Test status
Simulation time 6069682813 ps
CPU time 8.49 seconds
Started Apr 18 01:52:15 PM PDT 24
Finished Apr 18 01:52:24 PM PDT 24
Peak memory 200064 kb
Host smart-56e9057d-5c50-4395-bffe-1bfcfb869d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243874160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.243874160
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.314150434
Short name T101
Test name
Test status
Simulation time 177275166760 ps
CPU time 775.81 seconds
Started Apr 18 01:52:23 PM PDT 24
Finished Apr 18 02:05:20 PM PDT 24
Peak memory 225788 kb
Host smart-903996d4-3b66-494c-99f2-960e2a521f1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314150434 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.314150434
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.2312530625
Short name T785
Test name
Test status
Simulation time 620285887 ps
CPU time 2.08 seconds
Started Apr 18 01:52:19 PM PDT 24
Finished Apr 18 01:52:21 PM PDT 24
Peak memory 199144 kb
Host smart-91acd7ab-8fe3-4d11-919a-4d62235bf4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312530625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2312530625
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.862462972
Short name T1010
Test name
Test status
Simulation time 64073467226 ps
CPU time 87.82 seconds
Started Apr 18 01:52:21 PM PDT 24
Finished Apr 18 01:53:50 PM PDT 24
Peak memory 200760 kb
Host smart-98a3a6ad-6786-40c0-bc44-1115904a197d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862462972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.862462972
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.3429865171
Short name T1165
Test name
Test status
Simulation time 127221358537 ps
CPU time 56.28 seconds
Started Apr 18 01:54:49 PM PDT 24
Finished Apr 18 01:55:45 PM PDT 24
Peak memory 200672 kb
Host smart-58bda758-17a3-490a-acdf-f497a7e8d1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429865171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.3429865171
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.2448479565
Short name T822
Test name
Test status
Simulation time 58677759859 ps
CPU time 30.12 seconds
Started Apr 18 01:54:46 PM PDT 24
Finished Apr 18 01:55:17 PM PDT 24
Peak memory 200900 kb
Host smart-b2c10df5-41ba-4c1f-95f6-bb622b9d2b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448479565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.2448479565
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.1822179484
Short name T215
Test name
Test status
Simulation time 108851918420 ps
CPU time 162.97 seconds
Started Apr 18 01:54:46 PM PDT 24
Finished Apr 18 01:57:30 PM PDT 24
Peak memory 200832 kb
Host smart-85c68880-e7ad-4e65-b3b2-7e042162d29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822179484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.1822179484
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.86426525
Short name T197
Test name
Test status
Simulation time 105664384634 ps
CPU time 81.64 seconds
Started Apr 18 01:54:48 PM PDT 24
Finished Apr 18 01:56:11 PM PDT 24
Peak memory 200712 kb
Host smart-d4901c35-1b9f-40c0-980d-412ecdf4977f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86426525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.86426525
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.2644144579
Short name T1057
Test name
Test status
Simulation time 15741152165 ps
CPU time 6.34 seconds
Started Apr 18 01:54:47 PM PDT 24
Finished Apr 18 01:54:54 PM PDT 24
Peak memory 199880 kb
Host smart-3319d892-4f07-4a23-a0ae-84bb0cb7ddfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644144579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.2644144579
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.581845976
Short name T9
Test name
Test status
Simulation time 40860278390 ps
CPU time 42.11 seconds
Started Apr 18 01:54:49 PM PDT 24
Finished Apr 18 01:55:31 PM PDT 24
Peak memory 200824 kb
Host smart-fef0229f-0d75-42a4-97d9-e7c7c26ececc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581845976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.581845976
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.2217978326
Short name T462
Test name
Test status
Simulation time 32865453 ps
CPU time 0.55 seconds
Started Apr 18 01:52:27 PM PDT 24
Finished Apr 18 01:52:28 PM PDT 24
Peak memory 195644 kb
Host smart-7e6cda88-4526-4832-bd64-d6f4ae833c80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217978326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.2217978326
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.1665039182
Short name T809
Test name
Test status
Simulation time 19383198958 ps
CPU time 31.92 seconds
Started Apr 18 01:52:23 PM PDT 24
Finished Apr 18 01:52:56 PM PDT 24
Peak memory 200864 kb
Host smart-f53deefe-4f3f-4039-b1d1-67414e9c7025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665039182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.1665039182
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.4176058820
Short name T281
Test name
Test status
Simulation time 25297764813 ps
CPU time 42.74 seconds
Started Apr 18 01:52:24 PM PDT 24
Finished Apr 18 01:53:08 PM PDT 24
Peak memory 200896 kb
Host smart-18cb5e7d-99bf-4478-ad58-f36739abc273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176058820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.4176058820
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.1853038035
Short name T794
Test name
Test status
Simulation time 83588254338 ps
CPU time 22.25 seconds
Started Apr 18 01:52:23 PM PDT 24
Finished Apr 18 01:52:47 PM PDT 24
Peak memory 200916 kb
Host smart-5b04dd81-26bf-4b5d-b54f-174675b8c269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853038035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.1853038035
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.1190082201
Short name T574
Test name
Test status
Simulation time 218900856127 ps
CPU time 92.77 seconds
Started Apr 18 01:52:25 PM PDT 24
Finished Apr 18 01:53:59 PM PDT 24
Peak memory 200904 kb
Host smart-6756103c-8089-42ee-9c35-10ac3f6f3e4a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190082201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.1190082201
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.2593892177
Short name T988
Test name
Test status
Simulation time 143832850261 ps
CPU time 245.46 seconds
Started Apr 18 01:52:24 PM PDT 24
Finished Apr 18 01:56:31 PM PDT 24
Peak memory 200820 kb
Host smart-a2044c54-3fd1-4e7b-ba0a-038cf9eebfe2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2593892177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2593892177
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.4136958534
Short name T412
Test name
Test status
Simulation time 8071163564 ps
CPU time 13.7 seconds
Started Apr 18 01:52:21 PM PDT 24
Finished Apr 18 01:52:35 PM PDT 24
Peak memory 200096 kb
Host smart-73ad147d-1305-432f-9f11-c986f8333cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136958534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.4136958534
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.1072542248
Short name T564
Test name
Test status
Simulation time 3127273762 ps
CPU time 6.03 seconds
Started Apr 18 01:52:20 PM PDT 24
Finished Apr 18 01:52:27 PM PDT 24
Peak memory 197212 kb
Host smart-1a7e56ea-2cb6-426c-a0df-512f46a2598e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072542248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.1072542248
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.545882715
Short name T775
Test name
Test status
Simulation time 30027997941 ps
CPU time 752.36 seconds
Started Apr 18 01:52:25 PM PDT 24
Finished Apr 18 02:04:58 PM PDT 24
Peak memory 200896 kb
Host smart-55c632ec-b645-436a-b6b2-309fefe9a5f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=545882715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.545882715
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.1817602690
Short name T968
Test name
Test status
Simulation time 7232171744 ps
CPU time 12.99 seconds
Started Apr 18 01:52:22 PM PDT 24
Finished Apr 18 01:52:35 PM PDT 24
Peak memory 199172 kb
Host smart-c3f556ff-25d8-4edd-b3cb-135b482939e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1817602690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.1817602690
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.2021025906
Short name T887
Test name
Test status
Simulation time 235003251244 ps
CPU time 53.19 seconds
Started Apr 18 01:52:21 PM PDT 24
Finished Apr 18 01:53:15 PM PDT 24
Peak memory 200848 kb
Host smart-78f97070-762c-45b5-af5c-b8075cf01345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021025906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.2021025906
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.1371633895
Short name T582
Test name
Test status
Simulation time 623382465 ps
CPU time 1.08 seconds
Started Apr 18 01:52:18 PM PDT 24
Finished Apr 18 01:52:20 PM PDT 24
Peak memory 196264 kb
Host smart-230be5b0-1997-4722-978f-36f3e763d371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371633895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.1371633895
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.594351413
Short name T1048
Test name
Test status
Simulation time 475994768 ps
CPU time 1.47 seconds
Started Apr 18 01:52:22 PM PDT 24
Finished Apr 18 01:52:26 PM PDT 24
Peak memory 199264 kb
Host smart-47b87264-aafa-48e1-84d0-9b6d95d91c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594351413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.594351413
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.1695365352
Short name T825
Test name
Test status
Simulation time 154728869541 ps
CPU time 1518.94 seconds
Started Apr 18 01:52:31 PM PDT 24
Finished Apr 18 02:17:50 PM PDT 24
Peak memory 200724 kb
Host smart-9abc240f-64bf-415e-9c91-119ba5c27a06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695365352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.1695365352
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.1306579280
Short name T479
Test name
Test status
Simulation time 65185164378 ps
CPU time 632.29 seconds
Started Apr 18 01:52:24 PM PDT 24
Finished Apr 18 02:02:57 PM PDT 24
Peak memory 225732 kb
Host smart-e450b450-cd9b-4c01-a95e-d4ab19a67e20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306579280 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.1306579280
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.926575197
Short name T299
Test name
Test status
Simulation time 3234535863 ps
CPU time 2.06 seconds
Started Apr 18 01:52:21 PM PDT 24
Finished Apr 18 01:52:23 PM PDT 24
Peak memory 199740 kb
Host smart-b3151298-c588-4e6a-a8a4-c6021e4f273b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926575197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.926575197
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.3799411788
Short name T457
Test name
Test status
Simulation time 65774935659 ps
CPU time 30.53 seconds
Started Apr 18 01:52:28 PM PDT 24
Finished Apr 18 01:52:59 PM PDT 24
Peak memory 200908 kb
Host smart-861a990b-a55b-4fcd-ad3d-4b8b4e920601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799411788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.3799411788
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.3635052649
Short name T1015
Test name
Test status
Simulation time 114379800873 ps
CPU time 52.87 seconds
Started Apr 18 01:54:46 PM PDT 24
Finished Apr 18 01:55:39 PM PDT 24
Peak memory 200792 kb
Host smart-88eade2b-3a57-4c83-b609-9deb56dc18f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635052649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.3635052649
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.434830107
Short name T568
Test name
Test status
Simulation time 28291789650 ps
CPU time 13.85 seconds
Started Apr 18 01:54:50 PM PDT 24
Finished Apr 18 01:55:05 PM PDT 24
Peak memory 200852 kb
Host smart-b496d8fb-7dd8-4eba-b204-88a9338a6860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434830107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.434830107
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.475194746
Short name T470
Test name
Test status
Simulation time 59861727829 ps
CPU time 82.58 seconds
Started Apr 18 01:54:48 PM PDT 24
Finished Apr 18 01:56:11 PM PDT 24
Peak memory 200888 kb
Host smart-0502fa96-3c7b-4252-aa20-7460793888e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475194746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.475194746
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.1964524049
Short name T212
Test name
Test status
Simulation time 101903304649 ps
CPU time 109.89 seconds
Started Apr 18 01:54:48 PM PDT 24
Finished Apr 18 01:56:39 PM PDT 24
Peak memory 200808 kb
Host smart-20d906be-b417-458d-be2a-9d28a010b29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964524049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.1964524049
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.2704755933
Short name T948
Test name
Test status
Simulation time 90558205622 ps
CPU time 29.66 seconds
Started Apr 18 01:54:46 PM PDT 24
Finished Apr 18 01:55:17 PM PDT 24
Peak memory 200752 kb
Host smart-664cd387-171d-45c4-a4e9-974fca2a4769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704755933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.2704755933
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.3188683708
Short name T722
Test name
Test status
Simulation time 21451626682 ps
CPU time 30.48 seconds
Started Apr 18 01:54:46 PM PDT 24
Finished Apr 18 01:55:17 PM PDT 24
Peak memory 200880 kb
Host smart-defa9df0-ac5e-4623-9b9f-bab67445cc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188683708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.3188683708
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.3141263900
Short name T1135
Test name
Test status
Simulation time 96035554521 ps
CPU time 152.68 seconds
Started Apr 18 01:54:50 PM PDT 24
Finished Apr 18 01:57:24 PM PDT 24
Peak memory 200900 kb
Host smart-16d1ade1-9162-4f5c-a60d-0d4d23594fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141263900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.3141263900
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.2809985715
Short name T699
Test name
Test status
Simulation time 36485402008 ps
CPU time 16.75 seconds
Started Apr 18 01:54:48 PM PDT 24
Finished Apr 18 01:55:05 PM PDT 24
Peak memory 200924 kb
Host smart-4bb20d37-f34b-43d2-b627-7df5f3e420e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809985715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2809985715
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.3521098984
Short name T903
Test name
Test status
Simulation time 119623604228 ps
CPU time 341.02 seconds
Started Apr 18 01:54:53 PM PDT 24
Finished Apr 18 02:00:35 PM PDT 24
Peak memory 200844 kb
Host smart-c1db6dd7-5e94-4014-8542-57040d22e161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521098984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.3521098984
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.4168684404
Short name T534
Test name
Test status
Simulation time 20057168 ps
CPU time 0.55 seconds
Started Apr 18 01:52:33 PM PDT 24
Finished Apr 18 01:52:35 PM PDT 24
Peak memory 196216 kb
Host smart-c530c823-8ccf-47b5-ac80-7bf4ab6bf606
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168684404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.4168684404
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.3142817699
Short name T713
Test name
Test status
Simulation time 56627286537 ps
CPU time 24.68 seconds
Started Apr 18 01:52:26 PM PDT 24
Finished Apr 18 01:52:51 PM PDT 24
Peak memory 200936 kb
Host smart-c730b38c-486a-447a-a641-7f0474ab161f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142817699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.3142817699
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.3481320229
Short name T1176
Test name
Test status
Simulation time 42210649683 ps
CPU time 72.33 seconds
Started Apr 18 01:52:46 PM PDT 24
Finished Apr 18 01:53:59 PM PDT 24
Peak memory 200820 kb
Host smart-1d7db396-f31f-4146-b7f3-dc8327e77de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481320229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.3481320229
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_intr.1867128841
Short name T322
Test name
Test status
Simulation time 34217651624 ps
CPU time 31.09 seconds
Started Apr 18 01:52:24 PM PDT 24
Finished Apr 18 01:52:56 PM PDT 24
Peak memory 200852 kb
Host smart-6dca72d6-2be8-4bff-9d53-2b430579cf3f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867128841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.1867128841
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.1095309445
Short name T671
Test name
Test status
Simulation time 65851210289 ps
CPU time 379.34 seconds
Started Apr 18 01:52:37 PM PDT 24
Finished Apr 18 01:58:57 PM PDT 24
Peak memory 200852 kb
Host smart-9a5dfa5f-5242-47aa-b5b4-95ef95a248c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1095309445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.1095309445
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.1637181272
Short name T379
Test name
Test status
Simulation time 2987991176 ps
CPU time 5.79 seconds
Started Apr 18 01:52:30 PM PDT 24
Finished Apr 18 01:52:36 PM PDT 24
Peak memory 196980 kb
Host smart-5589ab8a-eed6-4fec-a779-4f90f5879881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637181272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.1637181272
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.4209900363
Short name T261
Test name
Test status
Simulation time 151027981072 ps
CPU time 77.11 seconds
Started Apr 18 01:52:24 PM PDT 24
Finished Apr 18 01:53:42 PM PDT 24
Peak memory 200208 kb
Host smart-a8d9c1b9-682c-4cc6-ba0f-1114917fd024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209900363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.4209900363
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.2320513026
Short name T288
Test name
Test status
Simulation time 16732061696 ps
CPU time 526.74 seconds
Started Apr 18 01:52:33 PM PDT 24
Finished Apr 18 02:01:20 PM PDT 24
Peak memory 200924 kb
Host smart-adff30fc-f426-4c98-afb8-6b0e97d80c95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2320513026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.2320513026
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.1938035578
Short name T663
Test name
Test status
Simulation time 4115905112 ps
CPU time 8.87 seconds
Started Apr 18 01:52:27 PM PDT 24
Finished Apr 18 01:52:36 PM PDT 24
Peak memory 199000 kb
Host smart-64893c1c-9a43-492a-bdcc-88d4ca2e8d25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1938035578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.1938035578
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.2129728896
Short name T164
Test name
Test status
Simulation time 121274471770 ps
CPU time 48.05 seconds
Started Apr 18 01:52:28 PM PDT 24
Finished Apr 18 01:53:17 PM PDT 24
Peak memory 200744 kb
Host smart-88cf6b3d-d6be-4aad-899f-817bdd5b016c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129728896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.2129728896
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.2029953374
Short name T431
Test name
Test status
Simulation time 29632674034 ps
CPU time 5.24 seconds
Started Apr 18 01:52:30 PM PDT 24
Finished Apr 18 01:52:35 PM PDT 24
Peak memory 197180 kb
Host smart-cdbd1c18-7b83-4dc8-b366-2c3c874be7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029953374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.2029953374
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.4143666548
Short name T302
Test name
Test status
Simulation time 926584861 ps
CPU time 1.79 seconds
Started Apr 18 01:52:26 PM PDT 24
Finished Apr 18 01:52:28 PM PDT 24
Peak memory 199236 kb
Host smart-25fa9e5f-5429-4942-8634-bfc4500c3846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143666548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.4143666548
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.3908600916
Short name T950
Test name
Test status
Simulation time 627397034616 ps
CPU time 273.97 seconds
Started Apr 18 01:52:34 PM PDT 24
Finished Apr 18 01:57:09 PM PDT 24
Peak memory 200808 kb
Host smart-b2a433cd-dd4a-4abf-904a-b3e96b46c44c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908600916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.3908600916
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.2616957112
Short name T44
Test name
Test status
Simulation time 53947856198 ps
CPU time 726.9 seconds
Started Apr 18 01:52:32 PM PDT 24
Finished Apr 18 02:04:39 PM PDT 24
Peak memory 226400 kb
Host smart-fc809b53-e383-409d-b990-c90b712b6a16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616957112 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.2616957112
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.1902580591
Short name T989
Test name
Test status
Simulation time 964132585 ps
CPU time 3.74 seconds
Started Apr 18 01:52:27 PM PDT 24
Finished Apr 18 01:52:31 PM PDT 24
Peak memory 199292 kb
Host smart-ba2151a8-7ea0-41bc-b621-04b34a06858d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902580591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.1902580591
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.954536619
Short name T33
Test name
Test status
Simulation time 70538094651 ps
CPU time 61.4 seconds
Started Apr 18 01:52:25 PM PDT 24
Finished Apr 18 01:53:27 PM PDT 24
Peak memory 200784 kb
Host smart-6ed51469-17b6-47f6-a01d-bbb86bdb2e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954536619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.954536619
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.272543115
Short name T1062
Test name
Test status
Simulation time 10708507384 ps
CPU time 13.7 seconds
Started Apr 18 01:54:54 PM PDT 24
Finished Apr 18 01:55:08 PM PDT 24
Peak memory 200636 kb
Host smart-9a69a2c3-0a93-410c-bd20-09dae4850eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272543115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.272543115
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.897274565
Short name T193
Test name
Test status
Simulation time 140289998973 ps
CPU time 17.08 seconds
Started Apr 18 01:54:53 PM PDT 24
Finished Apr 18 01:55:11 PM PDT 24
Peak memory 200592 kb
Host smart-f8f6b75e-a001-4a60-86f1-95bbfcf0b369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897274565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.897274565
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.2312843788
Short name T718
Test name
Test status
Simulation time 33564753388 ps
CPU time 28.05 seconds
Started Apr 18 01:54:54 PM PDT 24
Finished Apr 18 01:55:23 PM PDT 24
Peak memory 200828 kb
Host smart-920448d3-d3ff-447a-b5de-6c82d30e453c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312843788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2312843788
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.187767187
Short name T170
Test name
Test status
Simulation time 80819489224 ps
CPU time 422.94 seconds
Started Apr 18 01:55:14 PM PDT 24
Finished Apr 18 02:02:17 PM PDT 24
Peak memory 200916 kb
Host smart-8991bce7-2462-4417-8324-ae240346daa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187767187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.187767187
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.699487458
Short name T1103
Test name
Test status
Simulation time 25001068845 ps
CPU time 10.74 seconds
Started Apr 18 01:54:55 PM PDT 24
Finished Apr 18 01:55:06 PM PDT 24
Peak memory 200780 kb
Host smart-a13da5ff-0288-4fc2-9a45-3e9d99001318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699487458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.699487458
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.35454184
Short name T274
Test name
Test status
Simulation time 19377532905 ps
CPU time 28.62 seconds
Started Apr 18 01:54:58 PM PDT 24
Finished Apr 18 01:55:27 PM PDT 24
Peak memory 200884 kb
Host smart-75644b30-bd09-42db-9fee-6ffb251e980e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35454184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.35454184
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.3864875595
Short name T1005
Test name
Test status
Simulation time 151924539970 ps
CPU time 118.92 seconds
Started Apr 18 01:54:54 PM PDT 24
Finished Apr 18 01:56:54 PM PDT 24
Peak memory 200824 kb
Host smart-c8d1bacb-2ab4-4797-8ccd-2a006203dc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864875595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.3864875595
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.2064776669
Short name T324
Test name
Test status
Simulation time 97800537295 ps
CPU time 350.24 seconds
Started Apr 18 01:54:53 PM PDT 24
Finished Apr 18 02:00:44 PM PDT 24
Peak memory 200836 kb
Host smart-55f56303-9a88-4b6d-9680-1f7804fd5ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064776669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.2064776669
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.2720453463
Short name T143
Test name
Test status
Simulation time 134248952899 ps
CPU time 77.91 seconds
Started Apr 18 01:54:55 PM PDT 24
Finished Apr 18 01:56:14 PM PDT 24
Peak memory 200872 kb
Host smart-c3820d3b-8544-4c14-a6b3-7e5fc5054357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720453463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.2720453463
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.621838950
Short name T125
Test name
Test status
Simulation time 31980337202 ps
CPU time 13.32 seconds
Started Apr 18 01:54:52 PM PDT 24
Finished Apr 18 01:55:06 PM PDT 24
Peak memory 200876 kb
Host smart-66d5aa2c-dcaa-4bce-9cf9-1da2f4371868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621838950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.621838950
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.3365023590
Short name T847
Test name
Test status
Simulation time 21388100 ps
CPU time 0.58 seconds
Started Apr 18 01:52:35 PM PDT 24
Finished Apr 18 01:52:36 PM PDT 24
Peak memory 196236 kb
Host smart-a4483d1f-8817-44ad-bf85-e4cfec2b52bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365023590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.3365023590
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.2953142459
Short name T769
Test name
Test status
Simulation time 41496638086 ps
CPU time 17.86 seconds
Started Apr 18 01:52:33 PM PDT 24
Finished Apr 18 01:52:52 PM PDT 24
Peak memory 200844 kb
Host smart-256b9d45-dcce-4a34-8dbd-caaf7cc2f06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953142459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.2953142459
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.2266229851
Short name T546
Test name
Test status
Simulation time 89855250702 ps
CPU time 36.26 seconds
Started Apr 18 01:52:32 PM PDT 24
Finished Apr 18 01:53:09 PM PDT 24
Peak memory 200440 kb
Host smart-021186c5-5612-4e3f-b417-60dde1e4defd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266229851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.2266229851
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.429507609
Short name T229
Test name
Test status
Simulation time 40902664111 ps
CPU time 31.34 seconds
Started Apr 18 01:52:33 PM PDT 24
Finished Apr 18 01:53:05 PM PDT 24
Peak memory 200904 kb
Host smart-ddb5bce1-b38b-43d4-a8d4-998cb69d36a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429507609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.429507609
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.2304127277
Short name T1043
Test name
Test status
Simulation time 23334826947 ps
CPU time 6.08 seconds
Started Apr 18 01:52:31 PM PDT 24
Finished Apr 18 01:52:37 PM PDT 24
Peak memory 200732 kb
Host smart-51720c83-13a7-4236-a961-f4c2bf7415fe
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304127277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.2304127277
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.2454597412
Short name T517
Test name
Test status
Simulation time 114523331381 ps
CPU time 789.13 seconds
Started Apr 18 01:52:37 PM PDT 24
Finished Apr 18 02:05:46 PM PDT 24
Peak memory 200788 kb
Host smart-b4eb3280-ec16-4d68-900a-8629610ab4b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2454597412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2454597412
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.3149555231
Short name T604
Test name
Test status
Simulation time 6944958310 ps
CPU time 13.86 seconds
Started Apr 18 01:52:34 PM PDT 24
Finished Apr 18 01:52:49 PM PDT 24
Peak memory 199008 kb
Host smart-6bf1c663-c655-4ffd-b270-42538882dcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149555231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.3149555231
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.2228004323
Short name T698
Test name
Test status
Simulation time 33471624141 ps
CPU time 26.67 seconds
Started Apr 18 01:52:32 PM PDT 24
Finished Apr 18 01:53:00 PM PDT 24
Peak memory 199216 kb
Host smart-c9a695f7-cbe2-4bd5-8f95-ddfce1dba05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228004323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.2228004323
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.773093790
Short name T1083
Test name
Test status
Simulation time 21173923997 ps
CPU time 835.9 seconds
Started Apr 18 01:52:49 PM PDT 24
Finished Apr 18 02:06:46 PM PDT 24
Peak memory 200804 kb
Host smart-23f779a1-9043-4089-9e7b-fd7a5624f6c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=773093790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.773093790
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.2964238871
Short name T901
Test name
Test status
Simulation time 2124517264 ps
CPU time 12.62 seconds
Started Apr 18 01:52:34 PM PDT 24
Finished Apr 18 01:52:47 PM PDT 24
Peak memory 198632 kb
Host smart-316d5595-0dfe-430a-b1d8-7bb8ff432155
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2964238871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.2964238871
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.2947702472
Short name T367
Test name
Test status
Simulation time 55605263828 ps
CPU time 23.49 seconds
Started Apr 18 01:52:32 PM PDT 24
Finished Apr 18 01:52:57 PM PDT 24
Peak memory 199948 kb
Host smart-41acd59f-628a-4c0d-bfb5-b23157f7ad9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947702472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.2947702472
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.606827535
Short name T1142
Test name
Test status
Simulation time 1691114245 ps
CPU time 3.34 seconds
Started Apr 18 01:52:33 PM PDT 24
Finished Apr 18 01:52:37 PM PDT 24
Peak memory 196316 kb
Host smart-583d7bd7-240a-46c5-99ea-653bae6cb75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606827535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.606827535
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.3299380847
Short name T312
Test name
Test status
Simulation time 500900424 ps
CPU time 1.33 seconds
Started Apr 18 01:52:36 PM PDT 24
Finished Apr 18 01:52:37 PM PDT 24
Peak memory 199380 kb
Host smart-e95cd7d2-b335-4fa2-8645-ac2a0c42a95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299380847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.3299380847
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.37931993
Short name T1126
Test name
Test status
Simulation time 238612937991 ps
CPU time 134.52 seconds
Started Apr 18 01:52:32 PM PDT 24
Finished Apr 18 01:54:47 PM PDT 24
Peak memory 209304 kb
Host smart-24770818-7b99-4bdc-a9cd-6fbc4ae394fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37931993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.37931993
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.663095662
Short name T760
Test name
Test status
Simulation time 88145504742 ps
CPU time 544.05 seconds
Started Apr 18 01:52:34 PM PDT 24
Finished Apr 18 02:01:39 PM PDT 24
Peak memory 217296 kb
Host smart-0257456c-690e-4076-bb19-839ebf30fd43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663095662 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.663095662
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.1681687567
Short name T15
Test name
Test status
Simulation time 611906087 ps
CPU time 1.77 seconds
Started Apr 18 01:52:31 PM PDT 24
Finished Apr 18 01:52:33 PM PDT 24
Peak memory 198952 kb
Host smart-f475b158-665f-42bf-9412-775e47464038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681687567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1681687567
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.1893128016
Short name T298
Test name
Test status
Simulation time 71429884549 ps
CPU time 140.76 seconds
Started Apr 18 01:52:34 PM PDT 24
Finished Apr 18 01:54:56 PM PDT 24
Peak memory 200884 kb
Host smart-1e5c7181-2056-4034-b852-0b3fcda2da1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893128016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.1893128016
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.2422202691
Short name T304
Test name
Test status
Simulation time 161339148417 ps
CPU time 182.9 seconds
Started Apr 18 01:54:54 PM PDT 24
Finished Apr 18 01:57:57 PM PDT 24
Peak memory 200828 kb
Host smart-56f02109-207e-4a77-87b9-606ffeec79ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422202691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.2422202691
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1083477289
Short name T260
Test name
Test status
Simulation time 53064180140 ps
CPU time 17.9 seconds
Started Apr 18 01:55:02 PM PDT 24
Finished Apr 18 01:55:20 PM PDT 24
Peak memory 200872 kb
Host smart-040b6138-de25-484d-869c-c7797c95cfca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083477289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1083477289
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.4056570568
Short name T188
Test name
Test status
Simulation time 38098977668 ps
CPU time 18.85 seconds
Started Apr 18 01:54:53 PM PDT 24
Finished Apr 18 01:55:12 PM PDT 24
Peak memory 200908 kb
Host smart-fbc8d2a2-5370-4e11-8449-98721bf474aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056570568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.4056570568
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.2590292652
Short name T694
Test name
Test status
Simulation time 72187928220 ps
CPU time 36.19 seconds
Started Apr 18 01:54:55 PM PDT 24
Finished Apr 18 01:55:31 PM PDT 24
Peak memory 200844 kb
Host smart-c12e282f-c87d-4eab-a504-e388043e1a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590292652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.2590292652
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.3648239141
Short name T732
Test name
Test status
Simulation time 23735391649 ps
CPU time 33.34 seconds
Started Apr 18 01:54:53 PM PDT 24
Finished Apr 18 01:55:27 PM PDT 24
Peak memory 200888 kb
Host smart-cb2393f6-118d-4f6d-990c-6d5b6e6d45c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648239141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.3648239141
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.1653072064
Short name T516
Test name
Test status
Simulation time 100060174215 ps
CPU time 43.94 seconds
Started Apr 18 01:54:55 PM PDT 24
Finished Apr 18 01:55:40 PM PDT 24
Peak memory 200884 kb
Host smart-63276fe9-b849-47bc-a00a-5f8afd369a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653072064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.1653072064
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.2180930908
Short name T445
Test name
Test status
Simulation time 21243957075 ps
CPU time 34.26 seconds
Started Apr 18 01:54:58 PM PDT 24
Finished Apr 18 01:55:33 PM PDT 24
Peak memory 200848 kb
Host smart-6f2b372c-ed83-41f1-97cb-efd56f7b1516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180930908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.2180930908
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.1580212077
Short name T1013
Test name
Test status
Simulation time 20127852896 ps
CPU time 20.9 seconds
Started Apr 18 01:55:06 PM PDT 24
Finished Apr 18 01:55:28 PM PDT 24
Peak memory 200872 kb
Host smart-fce33387-b967-4ba0-8b4e-d84eaadd7511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580212077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.1580212077
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.342439165
Short name T747
Test name
Test status
Simulation time 14018541 ps
CPU time 0.55 seconds
Started Apr 18 01:51:28 PM PDT 24
Finished Apr 18 01:51:34 PM PDT 24
Peak memory 195508 kb
Host smart-c9930017-8609-4f6f-9473-00a27bef11dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342439165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.342439165
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.1023003435
Short name T798
Test name
Test status
Simulation time 80291416968 ps
CPU time 60.52 seconds
Started Apr 18 01:51:25 PM PDT 24
Finished Apr 18 01:52:26 PM PDT 24
Peak memory 200856 kb
Host smart-db1a5172-413a-4159-bf4f-9cca2b7af7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023003435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.1023003435
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.2932261475
Short name T505
Test name
Test status
Simulation time 24531298595 ps
CPU time 10.48 seconds
Started Apr 18 01:51:26 PM PDT 24
Finished Apr 18 01:51:38 PM PDT 24
Peak memory 200620 kb
Host smart-76a2cd0c-f56e-4320-aaf2-8dbab9c5f2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932261475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.2932261475
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.1009459311
Short name T186
Test name
Test status
Simulation time 189303029241 ps
CPU time 19.47 seconds
Started Apr 18 01:51:24 PM PDT 24
Finished Apr 18 01:51:45 PM PDT 24
Peak memory 200892 kb
Host smart-8c2f52dd-5b36-4d61-9fe9-52f8c8288486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009459311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.1009459311
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.2902143429
Short name T857
Test name
Test status
Simulation time 32183899942 ps
CPU time 56.73 seconds
Started Apr 18 01:51:25 PM PDT 24
Finished Apr 18 01:52:23 PM PDT 24
Peak memory 200820 kb
Host smart-16178a48-bfe6-4b33-8b26-3dc4ee5b7039
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902143429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.2902143429
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.2041284326
Short name T519
Test name
Test status
Simulation time 217431502841 ps
CPU time 171.7 seconds
Started Apr 18 01:51:18 PM PDT 24
Finished Apr 18 01:54:10 PM PDT 24
Peak memory 200896 kb
Host smart-be4eac6f-50e3-4516-aa55-d68affac922a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2041284326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.2041284326
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.3556621127
Short name T1085
Test name
Test status
Simulation time 11508314118 ps
CPU time 14.79 seconds
Started Apr 18 01:51:25 PM PDT 24
Finished Apr 18 01:51:41 PM PDT 24
Peak memory 199568 kb
Host smart-ea4e342b-b2ff-4ed0-9c40-aaecad39697a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556621127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.3556621127
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.140396083
Short name T1154
Test name
Test status
Simulation time 48077903689 ps
CPU time 47.51 seconds
Started Apr 18 01:51:19 PM PDT 24
Finished Apr 18 01:52:07 PM PDT 24
Peak memory 199732 kb
Host smart-6537a48b-07bd-43be-8fb8-4106b986aee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140396083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.140396083
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.3661302244
Short name T846
Test name
Test status
Simulation time 11638457938 ps
CPU time 354.65 seconds
Started Apr 18 01:51:20 PM PDT 24
Finished Apr 18 01:57:15 PM PDT 24
Peak memory 200900 kb
Host smart-a666b68a-9238-47b3-b8c2-e110810df8cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3661302244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.3661302244
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.1246727174
Short name T382
Test name
Test status
Simulation time 6212742493 ps
CPU time 14.1 seconds
Started Apr 18 01:51:20 PM PDT 24
Finished Apr 18 01:51:35 PM PDT 24
Peak memory 199964 kb
Host smart-3b2866fe-a76a-4c24-b2b1-e2ed3efc730a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1246727174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.1246727174
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.3797587197
Short name T669
Test name
Test status
Simulation time 154829947902 ps
CPU time 27.26 seconds
Started Apr 18 01:51:29 PM PDT 24
Finished Apr 18 01:51:57 PM PDT 24
Peak memory 200832 kb
Host smart-4991cc22-1d68-4aef-8de2-ba62d020f85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797587197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.3797587197
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.1676981649
Short name T280
Test name
Test status
Simulation time 34278851424 ps
CPU time 15.99 seconds
Started Apr 18 01:51:23 PM PDT 24
Finished Apr 18 01:51:40 PM PDT 24
Peak memory 196708 kb
Host smart-acfba3b7-20e3-477d-ab5a-827f58d8168c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676981649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.1676981649
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.1695940860
Short name T24
Test name
Test status
Simulation time 330775517 ps
CPU time 0.92 seconds
Started Apr 18 01:51:22 PM PDT 24
Finished Apr 18 01:51:24 PM PDT 24
Peak memory 218996 kb
Host smart-679404bc-bc12-47f4-8fec-0077685100a9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695940860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.1695940860
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.1515760551
Short name T978
Test name
Test status
Simulation time 252023150 ps
CPU time 1.4 seconds
Started Apr 18 01:51:22 PM PDT 24
Finished Apr 18 01:51:25 PM PDT 24
Peak memory 199096 kb
Host smart-48c9db23-970b-44bf-8887-c2cf0a4dfadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515760551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.1515760551
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.3620044539
Short name T323
Test name
Test status
Simulation time 295750986763 ps
CPU time 189.03 seconds
Started Apr 18 01:51:21 PM PDT 24
Finished Apr 18 01:54:31 PM PDT 24
Peak memory 200832 kb
Host smart-13ca3b35-43cc-4a91-a062-2bc3cf5f95dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620044539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.3620044539
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.4028400102
Short name T16
Test name
Test status
Simulation time 77227454090 ps
CPU time 812.17 seconds
Started Apr 18 01:51:22 PM PDT 24
Finished Apr 18 02:04:55 PM PDT 24
Peak memory 217352 kb
Host smart-d1f19547-016d-4144-962d-ae9ed0bc4366
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028400102 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.4028400102
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.2665185761
Short name T995
Test name
Test status
Simulation time 2761109797 ps
CPU time 1.62 seconds
Started Apr 18 01:51:24 PM PDT 24
Finished Apr 18 01:51:26 PM PDT 24
Peak memory 200704 kb
Host smart-048bceff-e2cc-4bc6-832a-f601fce53864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665185761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2665185761
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.1948015286
Short name T926
Test name
Test status
Simulation time 62623890821 ps
CPU time 110.42 seconds
Started Apr 18 01:51:16 PM PDT 24
Finished Apr 18 01:53:07 PM PDT 24
Peak memory 200816 kb
Host smart-e001e0cc-856d-4570-ba6f-36682539a0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948015286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.1948015286
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.2369359921
Short name T365
Test name
Test status
Simulation time 16996020 ps
CPU time 0.59 seconds
Started Apr 18 01:52:41 PM PDT 24
Finished Apr 18 01:52:42 PM PDT 24
Peak memory 195596 kb
Host smart-9f430284-e830-40e2-aa88-90a42bd8df4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369359921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.2369359921
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.3549293999
Short name T700
Test name
Test status
Simulation time 68865909238 ps
CPU time 124.69 seconds
Started Apr 18 01:52:33 PM PDT 24
Finished Apr 18 01:54:39 PM PDT 24
Peak memory 200868 kb
Host smart-308d6aa5-0a12-4d0e-8567-5bb39c764f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549293999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3549293999
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.2935075900
Short name T391
Test name
Test status
Simulation time 158542952786 ps
CPU time 271.49 seconds
Started Apr 18 01:52:32 PM PDT 24
Finished Apr 18 01:57:04 PM PDT 24
Peak memory 200812 kb
Host smart-380f9f3c-0f4c-4b8e-95d2-d2f53b9bc0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935075900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.2935075900
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.1926039861
Short name T1167
Test name
Test status
Simulation time 135485019038 ps
CPU time 52.42 seconds
Started Apr 18 01:52:34 PM PDT 24
Finished Apr 18 01:53:27 PM PDT 24
Peak memory 200896 kb
Host smart-43f44139-b03a-4f82-ac59-d888dea02378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926039861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.1926039861
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.3746221107
Short name T783
Test name
Test status
Simulation time 56608189784 ps
CPU time 96.57 seconds
Started Apr 18 01:52:34 PM PDT 24
Finished Apr 18 01:54:11 PM PDT 24
Peak memory 200812 kb
Host smart-4f1dae54-1d6b-46a3-9b82-57931215ba13
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746221107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.3746221107
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.492517421
Short name T1114
Test name
Test status
Simulation time 178364293007 ps
CPU time 412.71 seconds
Started Apr 18 01:52:47 PM PDT 24
Finished Apr 18 01:59:41 PM PDT 24
Peak memory 200892 kb
Host smart-701ee4c3-a029-42c1-8495-e0f9d7ead981
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=492517421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.492517421
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.2683419075
Short name T915
Test name
Test status
Simulation time 7732785454 ps
CPU time 2.22 seconds
Started Apr 18 01:52:43 PM PDT 24
Finished Apr 18 01:52:46 PM PDT 24
Peak memory 199584 kb
Host smart-dc09f94c-9034-4624-8f5d-0349c8e5ea2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683419075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.2683419075
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.1672816418
Short name T1080
Test name
Test status
Simulation time 46366260867 ps
CPU time 78.97 seconds
Started Apr 18 01:52:35 PM PDT 24
Finished Apr 18 01:53:54 PM PDT 24
Peak memory 216584 kb
Host smart-114ea825-892d-48b9-bb86-c0c22806bc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672816418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.1672816418
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.2818810452
Short name T1044
Test name
Test status
Simulation time 29467797616 ps
CPU time 424.77 seconds
Started Apr 18 01:52:49 PM PDT 24
Finished Apr 18 01:59:55 PM PDT 24
Peak memory 200888 kb
Host smart-5b4cd0cf-b6e7-4dbe-8ec2-dfd99209160f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2818810452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.2818810452
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.2172023318
Short name T420
Test name
Test status
Simulation time 5755243875 ps
CPU time 50.25 seconds
Started Apr 18 01:52:32 PM PDT 24
Finished Apr 18 01:53:23 PM PDT 24
Peak memory 200152 kb
Host smart-180b090a-375c-4722-8211-b06618f01d84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2172023318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.2172023318
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.2871939531
Short name T947
Test name
Test status
Simulation time 144763579874 ps
CPU time 196.86 seconds
Started Apr 18 01:52:37 PM PDT 24
Finished Apr 18 01:55:54 PM PDT 24
Peak memory 200796 kb
Host smart-a1b2e26e-4fc1-445c-b5fd-e9c4aed303cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871939531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.2871939531
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.2066608486
Short name T797
Test name
Test status
Simulation time 5924263450 ps
CPU time 3.24 seconds
Started Apr 18 01:52:35 PM PDT 24
Finished Apr 18 01:52:38 PM PDT 24
Peak memory 196952 kb
Host smart-14fb3cbf-3bd9-445e-b464-06b9466425fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066608486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.2066608486
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.224795880
Short name T954
Test name
Test status
Simulation time 718665293 ps
CPU time 1.6 seconds
Started Apr 18 01:52:32 PM PDT 24
Finished Apr 18 01:52:34 PM PDT 24
Peak memory 200768 kb
Host smart-0b70af92-6ef9-4ff8-bc24-d6a9e84e1ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224795880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.224795880
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.3199566192
Short name T61
Test name
Test status
Simulation time 281722669856 ps
CPU time 758.02 seconds
Started Apr 18 01:52:47 PM PDT 24
Finished Apr 18 02:05:27 PM PDT 24
Peak memory 225700 kb
Host smart-6047fc45-8fd5-4658-a667-a247af52ca2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199566192 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.3199566192
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.2822830997
Short name T629
Test name
Test status
Simulation time 1627563810 ps
CPU time 3.02 seconds
Started Apr 18 01:52:37 PM PDT 24
Finished Apr 18 01:52:41 PM PDT 24
Peak memory 200652 kb
Host smart-06767210-0597-423e-99ca-6605162b51e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822830997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2822830997
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.1429485791
Short name T283
Test name
Test status
Simulation time 66879861156 ps
CPU time 108.09 seconds
Started Apr 18 01:52:34 PM PDT 24
Finished Apr 18 01:54:23 PM PDT 24
Peak memory 200932 kb
Host smart-edabc9ee-0d07-4721-95f1-f68537489798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429485791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.1429485791
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.4251693131
Short name T660
Test name
Test status
Simulation time 20162936 ps
CPU time 0.53 seconds
Started Apr 18 01:52:37 PM PDT 24
Finished Apr 18 01:52:38 PM PDT 24
Peak memory 195540 kb
Host smart-6612c3d2-911a-4c41-b947-f13bbf40a0a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251693131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.4251693131
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.1741899880
Short name T167
Test name
Test status
Simulation time 147699748018 ps
CPU time 55.46 seconds
Started Apr 18 01:52:44 PM PDT 24
Finished Apr 18 01:53:40 PM PDT 24
Peak memory 200824 kb
Host smart-b4301954-8514-46c9-a365-c45ad8a10aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741899880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.1741899880
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.2995782088
Short name T913
Test name
Test status
Simulation time 111350404132 ps
CPU time 172.98 seconds
Started Apr 18 01:52:52 PM PDT 24
Finished Apr 18 01:55:46 PM PDT 24
Peak memory 200856 kb
Host smart-2b908f40-0805-4c70-9bfb-bc0d3a61f3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995782088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.2995782088
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.1518070291
Short name T1074
Test name
Test status
Simulation time 64169950087 ps
CPU time 107.98 seconds
Started Apr 18 01:52:37 PM PDT 24
Finished Apr 18 01:54:25 PM PDT 24
Peak memory 200812 kb
Host smart-a936ff82-dfcd-44c1-ad7d-c28bbf9244d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518070291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.1518070291
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.3025743866
Short name T980
Test name
Test status
Simulation time 14669022362 ps
CPU time 4.88 seconds
Started Apr 18 01:52:48 PM PDT 24
Finished Apr 18 01:52:54 PM PDT 24
Peak memory 200456 kb
Host smart-d35e8121-4ca1-4d62-bdf5-e8c34104b132
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025743866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.3025743866
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.1032623211
Short name T851
Test name
Test status
Simulation time 61066976743 ps
CPU time 275.19 seconds
Started Apr 18 01:52:47 PM PDT 24
Finished Apr 18 01:57:24 PM PDT 24
Peak memory 200884 kb
Host smart-5c487846-1c24-4f28-ab06-131fdb118424
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1032623211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.1032623211
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.42993147
Short name T501
Test name
Test status
Simulation time 68932338 ps
CPU time 0.68 seconds
Started Apr 18 01:52:41 PM PDT 24
Finished Apr 18 01:52:42 PM PDT 24
Peak memory 196728 kb
Host smart-114e8af9-99db-4f8e-8f00-d8518b309db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42993147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.42993147
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.3558106012
Short name T386
Test name
Test status
Simulation time 19960830903 ps
CPU time 8.16 seconds
Started Apr 18 01:52:47 PM PDT 24
Finished Apr 18 01:52:57 PM PDT 24
Peak memory 196580 kb
Host smart-8bd7a845-6b0f-46ba-a32e-711efe174623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558106012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3558106012
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.2114270366
Short name T1016
Test name
Test status
Simulation time 23589911908 ps
CPU time 76.88 seconds
Started Apr 18 01:52:49 PM PDT 24
Finished Apr 18 01:54:07 PM PDT 24
Peak memory 200868 kb
Host smart-7e311df1-66af-4129-b8ae-ede3cc86f238
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2114270366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.2114270366
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.3357493236
Short name T982
Test name
Test status
Simulation time 5444571331 ps
CPU time 9.67 seconds
Started Apr 18 01:52:45 PM PDT 24
Finished Apr 18 01:52:56 PM PDT 24
Peak memory 198936 kb
Host smart-39758d19-e4c2-4ae3-b568-ff9b23ee22af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3357493236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.3357493236
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.2476122285
Short name T618
Test name
Test status
Simulation time 139730660252 ps
CPU time 161.45 seconds
Started Apr 18 01:52:45 PM PDT 24
Finished Apr 18 01:55:27 PM PDT 24
Peak memory 200816 kb
Host smart-0d2ebbb2-6902-4522-9d17-5cc493e3f8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476122285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.2476122285
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.1544622737
Short name T890
Test name
Test status
Simulation time 39243927106 ps
CPU time 32.93 seconds
Started Apr 18 01:52:48 PM PDT 24
Finished Apr 18 01:53:22 PM PDT 24
Peak memory 196964 kb
Host smart-79b08c9a-d4cb-4acd-a7dd-bd5d3050ab5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544622737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.1544622737
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.2490328158
Short name T929
Test name
Test status
Simulation time 742937697 ps
CPU time 1.19 seconds
Started Apr 18 01:52:50 PM PDT 24
Finished Apr 18 01:52:52 PM PDT 24
Peak memory 199604 kb
Host smart-c8e666d7-0c77-4c83-95dc-d46ef6242063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490328158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.2490328158
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.1610172901
Short name T498
Test name
Test status
Simulation time 30051608830 ps
CPU time 55.76 seconds
Started Apr 18 01:52:47 PM PDT 24
Finished Apr 18 01:53:44 PM PDT 24
Peak memory 200864 kb
Host smart-da3dfd0f-e789-4aca-bd24-fc67576f5d5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610172901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.1610172901
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.103060178
Short name T917
Test name
Test status
Simulation time 209749498976 ps
CPU time 821.82 seconds
Started Apr 18 01:52:46 PM PDT 24
Finished Apr 18 02:06:29 PM PDT 24
Peak memory 217292 kb
Host smart-da94d64c-47fe-42da-a27b-7b5124b6b2b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103060178 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.103060178
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.2350958495
Short name T1160
Test name
Test status
Simulation time 2492383089 ps
CPU time 2.97 seconds
Started Apr 18 01:52:37 PM PDT 24
Finished Apr 18 01:52:41 PM PDT 24
Peak memory 199664 kb
Host smart-4748d4f5-2550-4bb2-a462-e66b4c535215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350958495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.2350958495
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.3292616041
Short name T528
Test name
Test status
Simulation time 70047914794 ps
CPU time 113.81 seconds
Started Apr 18 01:52:38 PM PDT 24
Finished Apr 18 01:54:32 PM PDT 24
Peak memory 200840 kb
Host smart-639ae3df-57ea-4d96-9d23-b57c29b7491f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292616041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.3292616041
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.477021257
Short name T1147
Test name
Test status
Simulation time 14755516 ps
CPU time 0.56 seconds
Started Apr 18 01:52:47 PM PDT 24
Finished Apr 18 01:52:49 PM PDT 24
Peak memory 196152 kb
Host smart-98d172e1-f583-4d42-865c-c674f860a662
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477021257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.477021257
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.3949194360
Short name T936
Test name
Test status
Simulation time 33852162511 ps
CPU time 62.26 seconds
Started Apr 18 01:52:44 PM PDT 24
Finished Apr 18 01:53:47 PM PDT 24
Peak memory 200896 kb
Host smart-82263232-a36c-458e-aaa2-c052c7c09500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949194360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.3949194360
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.2088330920
Short name T710
Test name
Test status
Simulation time 140148517412 ps
CPU time 238.71 seconds
Started Apr 18 01:52:36 PM PDT 24
Finished Apr 18 01:56:36 PM PDT 24
Peak memory 200864 kb
Host smart-49b20668-4f80-4dcc-9b18-d73f433131eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088330920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2088330920
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.2631854144
Short name T205
Test name
Test status
Simulation time 64079650811 ps
CPU time 29.99 seconds
Started Apr 18 01:52:49 PM PDT 24
Finished Apr 18 01:53:20 PM PDT 24
Peak memory 200500 kb
Host smart-19397e52-a400-4535-8bbd-90968366a3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631854144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.2631854144
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.4055058139
Short name T109
Test name
Test status
Simulation time 56945859062 ps
CPU time 7.25 seconds
Started Apr 18 01:52:46 PM PDT 24
Finished Apr 18 01:52:55 PM PDT 24
Peak memory 199772 kb
Host smart-e01f9a74-2cf6-4b0c-9653-79d18e1579ce
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055058139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.4055058139
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.3365524220
Short name T52
Test name
Test status
Simulation time 120580265569 ps
CPU time 532.23 seconds
Started Apr 18 01:52:48 PM PDT 24
Finished Apr 18 02:01:42 PM PDT 24
Peak memory 200888 kb
Host smart-fb2c781d-060d-4f4f-a2f0-6c5da09b7d58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3365524220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.3365524220
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.2512934423
Short name T429
Test name
Test status
Simulation time 4532900958 ps
CPU time 9.32 seconds
Started Apr 18 01:52:47 PM PDT 24
Finished Apr 18 01:52:57 PM PDT 24
Peak memory 198388 kb
Host smart-c48c16ba-9b6d-4500-9d4b-a90abd6a096f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512934423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.2512934423
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.3241126892
Short name T526
Test name
Test status
Simulation time 48729227684 ps
CPU time 19.38 seconds
Started Apr 18 01:52:37 PM PDT 24
Finished Apr 18 01:52:57 PM PDT 24
Peak memory 199996 kb
Host smart-475a45ea-4750-4ba5-acf4-663e899f42a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241126892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.3241126892
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.3361612693
Short name T400
Test name
Test status
Simulation time 4756334026 ps
CPU time 232.51 seconds
Started Apr 18 01:52:48 PM PDT 24
Finished Apr 18 01:56:42 PM PDT 24
Peak memory 200808 kb
Host smart-3ac2ed94-991f-44e5-a95b-8ad33d28617f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3361612693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.3361612693
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.894053113
Short name T1023
Test name
Test status
Simulation time 7401024883 ps
CPU time 67.49 seconds
Started Apr 18 01:52:46 PM PDT 24
Finished Apr 18 01:53:55 PM PDT 24
Peak memory 200076 kb
Host smart-75bc3aea-0032-4bf0-9b5e-bd7b5a6be2c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=894053113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.894053113
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.987181814
Short name T776
Test name
Test status
Simulation time 24729728919 ps
CPU time 22.2 seconds
Started Apr 18 01:52:46 PM PDT 24
Finished Apr 18 01:53:09 PM PDT 24
Peak memory 200880 kb
Host smart-320ee4c4-4434-4c64-abc2-bfdbfa2e5400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987181814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.987181814
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.4131435345
Short name T653
Test name
Test status
Simulation time 41499184987 ps
CPU time 62.57 seconds
Started Apr 18 01:52:47 PM PDT 24
Finished Apr 18 01:53:51 PM PDT 24
Peak memory 196916 kb
Host smart-f9c38498-0be1-4c08-96a2-e47196a5c345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131435345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.4131435345
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.1736673511
Short name T497
Test name
Test status
Simulation time 276801921 ps
CPU time 1.03 seconds
Started Apr 18 01:52:47 PM PDT 24
Finished Apr 18 01:52:49 PM PDT 24
Peak memory 199120 kb
Host smart-f0cb9083-71c1-4549-bafe-0f367e927f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736673511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.1736673511
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.1926826518
Short name T744
Test name
Test status
Simulation time 346295125712 ps
CPU time 541.96 seconds
Started Apr 18 01:52:48 PM PDT 24
Finished Apr 18 02:01:51 PM PDT 24
Peak memory 201036 kb
Host smart-905e9f1f-ce2f-4c34-9895-c569a0c7a11a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926826518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.1926826518
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.433099562
Short name T1079
Test name
Test status
Simulation time 392221828735 ps
CPU time 1240.63 seconds
Started Apr 18 01:52:45 PM PDT 24
Finished Apr 18 02:13:27 PM PDT 24
Peak memory 227956 kb
Host smart-dbfb8e2c-44ac-4ef9-895d-98942d02ece3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433099562 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.433099562
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.2130531198
Short name T344
Test name
Test status
Simulation time 2005908963 ps
CPU time 1.95 seconds
Started Apr 18 01:52:47 PM PDT 24
Finished Apr 18 01:52:50 PM PDT 24
Peak memory 200760 kb
Host smart-624f29ed-45bb-49e1-93a7-70a0d1647181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130531198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.2130531198
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.4225458478
Short name T6
Test name
Test status
Simulation time 106565515808 ps
CPU time 87.84 seconds
Started Apr 18 01:52:35 PM PDT 24
Finished Apr 18 01:54:04 PM PDT 24
Peak memory 200868 kb
Host smart-74665e36-73a2-490a-8bf1-c7ba8bccb795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225458478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.4225458478
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.1762165282
Short name T658
Test name
Test status
Simulation time 30826656 ps
CPU time 0.54 seconds
Started Apr 18 01:52:45 PM PDT 24
Finished Apr 18 01:52:46 PM PDT 24
Peak memory 195224 kb
Host smart-4516b22c-aa40-489c-9762-fb3ffea8d4ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762165282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.1762165282
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.3626243634
Short name T376
Test name
Test status
Simulation time 31736646140 ps
CPU time 27.98 seconds
Started Apr 18 01:52:45 PM PDT 24
Finished Apr 18 01:53:14 PM PDT 24
Peak memory 200808 kb
Host smart-6b960180-323e-4240-8e41-fa9cb399ac69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626243634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.3626243634
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.912268168
Short name T179
Test name
Test status
Simulation time 35665305452 ps
CPU time 28.85 seconds
Started Apr 18 01:52:46 PM PDT 24
Finished Apr 18 01:53:16 PM PDT 24
Peak memory 200892 kb
Host smart-6faa8d4b-f2d4-4d55-b853-863e7b03fe2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912268168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.912268168
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.3028846944
Short name T395
Test name
Test status
Simulation time 99900447733 ps
CPU time 42.43 seconds
Started Apr 18 01:52:46 PM PDT 24
Finished Apr 18 01:53:29 PM PDT 24
Peak memory 199080 kb
Host smart-59bfd8aa-9ca3-40f2-abc0-1a9bd1c99ec3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028846944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.3028846944
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.1037391290
Short name T585
Test name
Test status
Simulation time 106024873532 ps
CPU time 171.51 seconds
Started Apr 18 01:52:47 PM PDT 24
Finished Apr 18 01:55:40 PM PDT 24
Peak memory 200900 kb
Host smart-a71876cc-49f8-49cb-bb8f-db746b25273b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1037391290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.1037391290
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.2233426418
Short name T762
Test name
Test status
Simulation time 2307771162 ps
CPU time 2.37 seconds
Started Apr 18 01:52:51 PM PDT 24
Finished Apr 18 01:52:54 PM PDT 24
Peak memory 197192 kb
Host smart-1baeb047-1a41-4b0f-9877-a520e27562c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233426418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.2233426418
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.2333057440
Short name T538
Test name
Test status
Simulation time 100526444320 ps
CPU time 48.94 seconds
Started Apr 18 01:52:46 PM PDT 24
Finished Apr 18 01:53:36 PM PDT 24
Peak memory 201056 kb
Host smart-cc2cb3ba-595c-4c1e-a453-ca2499dd34c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333057440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.2333057440
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.357928439
Short name T787
Test name
Test status
Simulation time 12687461736 ps
CPU time 714.88 seconds
Started Apr 18 01:52:48 PM PDT 24
Finished Apr 18 02:04:44 PM PDT 24
Peak memory 200896 kb
Host smart-9b17d649-9181-4cd3-86de-0701f64329c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=357928439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.357928439
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.3027115408
Short name T455
Test name
Test status
Simulation time 5524355233 ps
CPU time 49.67 seconds
Started Apr 18 01:52:44 PM PDT 24
Finished Apr 18 01:53:34 PM PDT 24
Peak memory 200108 kb
Host smart-3140b935-f855-4cd3-b478-4588f8d78373
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3027115408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.3027115408
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.3245098256
Short name T852
Test name
Test status
Simulation time 92818123012 ps
CPU time 35.96 seconds
Started Apr 18 01:52:47 PM PDT 24
Finished Apr 18 01:53:24 PM PDT 24
Peak memory 200860 kb
Host smart-cbedb399-6c7b-4ff3-ba89-e5e8602f8f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245098256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.3245098256
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.118257901
Short name T607
Test name
Test status
Simulation time 3387675189 ps
CPU time 6.37 seconds
Started Apr 18 01:52:46 PM PDT 24
Finished Apr 18 01:52:54 PM PDT 24
Peak memory 196872 kb
Host smart-e78d1656-3b7b-4190-b01c-7780934e9fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118257901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.118257901
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.58324680
Short name T597
Test name
Test status
Simulation time 482654696 ps
CPU time 2.62 seconds
Started Apr 18 01:52:45 PM PDT 24
Finished Apr 18 01:52:48 PM PDT 24
Peak memory 199568 kb
Host smart-2518b9b5-a988-40f9-bd71-39ed7d89770a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58324680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.58324680
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.4142511282
Short name T126
Test name
Test status
Simulation time 118192246895 ps
CPU time 92.78 seconds
Started Apr 18 01:52:47 PM PDT 24
Finished Apr 18 01:54:21 PM PDT 24
Peak memory 200864 kb
Host smart-ba4b75ab-2049-415b-b2dd-3e02ee925a88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142511282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.4142511282
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.1441962317
Short name T551
Test name
Test status
Simulation time 59118507859 ps
CPU time 729.2 seconds
Started Apr 18 01:52:45 PM PDT 24
Finished Apr 18 02:04:56 PM PDT 24
Peak memory 216904 kb
Host smart-823884ef-524e-4a93-a87d-2249d9a93e7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441962317 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.1441962317
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.3689859400
Short name T781
Test name
Test status
Simulation time 1007522711 ps
CPU time 1.89 seconds
Started Apr 18 01:52:46 PM PDT 24
Finished Apr 18 01:52:50 PM PDT 24
Peak memory 199548 kb
Host smart-69de2055-2866-480a-808a-6ff455b7f98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689859400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.3689859400
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.1956906151
Short name T1137
Test name
Test status
Simulation time 63373602051 ps
CPU time 25.36 seconds
Started Apr 18 01:52:47 PM PDT 24
Finished Apr 18 01:53:14 PM PDT 24
Peak memory 200800 kb
Host smart-a3e89da2-3218-4132-be9b-dcf730ad04bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956906151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.1956906151
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.1971521599
Short name T1104
Test name
Test status
Simulation time 51262718 ps
CPU time 0.57 seconds
Started Apr 18 01:52:48 PM PDT 24
Finished Apr 18 01:52:50 PM PDT 24
Peak memory 196252 kb
Host smart-60f7ef7a-dc7a-4dbe-a77f-43aa58c1f1c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971521599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1971521599
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.3606043460
Short name T627
Test name
Test status
Simulation time 129472890410 ps
CPU time 42.4 seconds
Started Apr 18 01:52:43 PM PDT 24
Finished Apr 18 01:53:25 PM PDT 24
Peak memory 200872 kb
Host smart-19341871-c693-43f6-a031-c4b94904449f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606043460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.3606043460
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.2026656813
Short name T484
Test name
Test status
Simulation time 138043223537 ps
CPU time 70.86 seconds
Started Apr 18 01:52:45 PM PDT 24
Finished Apr 18 01:53:57 PM PDT 24
Peak memory 200816 kb
Host smart-e51c95a2-7efe-454d-befa-c6fa5ae8585b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026656813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.2026656813
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.2792480036
Short name T201
Test name
Test status
Simulation time 5445623539 ps
CPU time 10.04 seconds
Started Apr 18 01:52:46 PM PDT 24
Finished Apr 18 01:52:57 PM PDT 24
Peak memory 200648 kb
Host smart-1c13d5ec-36f3-422d-81e7-d3742c6b9d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792480036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.2792480036
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.1455622299
Short name T689
Test name
Test status
Simulation time 262727269300 ps
CPU time 362.93 seconds
Started Apr 18 01:52:45 PM PDT 24
Finished Apr 18 01:58:49 PM PDT 24
Peak memory 199224 kb
Host smart-b291b9ec-19bd-45eb-93b9-6cb75e7d60c0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455622299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.1455622299
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.514547114
Short name T347
Test name
Test status
Simulation time 182000657020 ps
CPU time 371.81 seconds
Started Apr 18 01:52:48 PM PDT 24
Finished Apr 18 01:59:01 PM PDT 24
Peak memory 200836 kb
Host smart-3e9a3268-77bb-410a-a7b9-253117e47fa1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=514547114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.514547114
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.2452075043
Short name T943
Test name
Test status
Simulation time 3558778823 ps
CPU time 12.64 seconds
Started Apr 18 01:52:45 PM PDT 24
Finished Apr 18 01:52:58 PM PDT 24
Peak memory 200772 kb
Host smart-80973918-ddf1-4e4d-a2a6-d18b6e9adb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452075043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.2452075043
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.3553854530
Short name T1140
Test name
Test status
Simulation time 109797590689 ps
CPU time 262.06 seconds
Started Apr 18 01:52:47 PM PDT 24
Finished Apr 18 01:57:10 PM PDT 24
Peak memory 216860 kb
Host smart-7e5a6214-9ece-4143-902a-5b86a651c476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553854530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.3553854530
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.4262491247
Short name T465
Test name
Test status
Simulation time 17312150823 ps
CPU time 201.25 seconds
Started Apr 18 01:52:47 PM PDT 24
Finished Apr 18 01:56:10 PM PDT 24
Peak memory 200772 kb
Host smart-ac566a79-99cc-4414-bc41-14f324ff08ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4262491247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.4262491247
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.2710959001
Short name T341
Test name
Test status
Simulation time 2755122794 ps
CPU time 5.55 seconds
Started Apr 18 01:52:48 PM PDT 24
Finished Apr 18 01:52:55 PM PDT 24
Peak memory 198736 kb
Host smart-c817285c-cd82-47e4-8d4f-bb7d44729069
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2710959001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.2710959001
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.145706303
Short name T1051
Test name
Test status
Simulation time 14994224962 ps
CPU time 21.98 seconds
Started Apr 18 01:52:45 PM PDT 24
Finished Apr 18 01:53:09 PM PDT 24
Peak memory 200864 kb
Host smart-d65e7a4e-5a32-4224-b154-4c4234e9c42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145706303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.145706303
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.365066176
Short name T709
Test name
Test status
Simulation time 1768609746 ps
CPU time 3.11 seconds
Started Apr 18 01:52:48 PM PDT 24
Finished Apr 18 01:52:52 PM PDT 24
Peak memory 196140 kb
Host smart-b575b563-2f36-425d-b474-de531cc23f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365066176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.365066176
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.183224736
Short name T282
Test name
Test status
Simulation time 5983022148 ps
CPU time 14.84 seconds
Started Apr 18 01:52:44 PM PDT 24
Finished Apr 18 01:53:00 PM PDT 24
Peak memory 200504 kb
Host smart-a956d45a-26bf-4223-a5e0-f6110c28def6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183224736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.183224736
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.574092935
Short name T272
Test name
Test status
Simulation time 224026214633 ps
CPU time 186.82 seconds
Started Apr 18 01:52:49 PM PDT 24
Finished Apr 18 01:55:57 PM PDT 24
Peak memory 200728 kb
Host smart-485f44a3-c674-42bf-a394-eb754265b120
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574092935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.574092935
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.3051708036
Short name T438
Test name
Test status
Simulation time 6378948108 ps
CPU time 1.51 seconds
Started Apr 18 01:52:47 PM PDT 24
Finished Apr 18 01:52:50 PM PDT 24
Peak memory 200184 kb
Host smart-3c89b9cf-f4a6-4bc0-88f8-55237c152f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051708036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.3051708036
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.3523992505
Short name T447
Test name
Test status
Simulation time 17272563252 ps
CPU time 24.57 seconds
Started Apr 18 01:52:45 PM PDT 24
Finished Apr 18 01:53:11 PM PDT 24
Peak memory 200884 kb
Host smart-5173bb87-a54a-40fb-abc6-871f3c8a63cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523992505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.3523992505
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.2159730892
Short name T728
Test name
Test status
Simulation time 24869194 ps
CPU time 0.52 seconds
Started Apr 18 01:52:53 PM PDT 24
Finished Apr 18 01:52:54 PM PDT 24
Peak memory 196176 kb
Host smart-13e83180-fce0-4489-8b11-ddd0bee90290
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159730892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.2159730892
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.595887911
Short name T1115
Test name
Test status
Simulation time 171014196481 ps
CPU time 625.82 seconds
Started Apr 18 01:52:48 PM PDT 24
Finished Apr 18 02:03:15 PM PDT 24
Peak memory 200904 kb
Host smart-3dc0d09f-dfea-4a2f-82bb-384db9d864ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595887911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.595887911
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.453153123
Short name T865
Test name
Test status
Simulation time 300404997750 ps
CPU time 76.17 seconds
Started Apr 18 01:52:49 PM PDT 24
Finished Apr 18 01:54:06 PM PDT 24
Peak memory 200472 kb
Host smart-ce8f9cf0-1faf-4829-b9d6-f689c6a33ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453153123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.453153123
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.2689208370
Short name T800
Test name
Test status
Simulation time 33021127443 ps
CPU time 18.53 seconds
Started Apr 18 01:52:47 PM PDT 24
Finished Apr 18 01:53:07 PM PDT 24
Peak memory 200632 kb
Host smart-6554c852-6295-44a5-9428-0b4ec994bc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689208370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.2689208370
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.3701658790
Short name T1036
Test name
Test status
Simulation time 118518077153 ps
CPU time 54.18 seconds
Started Apr 18 01:52:54 PM PDT 24
Finished Apr 18 01:53:49 PM PDT 24
Peak memory 200612 kb
Host smart-9f82cd48-eae0-4484-a14c-3530273be87d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701658790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.3701658790
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.2734187866
Short name T603
Test name
Test status
Simulation time 58392089721 ps
CPU time 87.89 seconds
Started Apr 18 01:52:50 PM PDT 24
Finished Apr 18 01:54:19 PM PDT 24
Peak memory 200896 kb
Host smart-bc02629f-6010-48ee-b54d-b4e43bd43616
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2734187866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.2734187866
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.2483412182
Short name T914
Test name
Test status
Simulation time 14000307352 ps
CPU time 41.3 seconds
Started Apr 18 01:52:52 PM PDT 24
Finished Apr 18 01:53:33 PM PDT 24
Peak memory 200752 kb
Host smart-b32e6491-39b7-410c-970d-00d5181f6581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483412182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.2483412182
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.2273051431
Short name T348
Test name
Test status
Simulation time 4133148971 ps
CPU time 3.85 seconds
Started Apr 18 01:52:50 PM PDT 24
Finished Apr 18 01:52:55 PM PDT 24
Peak memory 200832 kb
Host smart-cc1e7ed7-6686-441c-a95f-873ca55572c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273051431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.2273051431
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.3589758032
Short name T701
Test name
Test status
Simulation time 4212795222 ps
CPU time 189.15 seconds
Started Apr 18 01:52:50 PM PDT 24
Finished Apr 18 01:56:00 PM PDT 24
Peak memory 200900 kb
Host smart-e1bb96c7-fec0-4a09-93e3-58b69438ace4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3589758032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.3589758032
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.2422586041
Short name T320
Test name
Test status
Simulation time 3857232187 ps
CPU time 15.15 seconds
Started Apr 18 01:52:46 PM PDT 24
Finished Apr 18 01:53:03 PM PDT 24
Peak memory 198900 kb
Host smart-42194176-ea55-4539-83d9-b8673f3266f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2422586041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.2422586041
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.205562170
Short name T1109
Test name
Test status
Simulation time 39027188910 ps
CPU time 19.87 seconds
Started Apr 18 01:52:48 PM PDT 24
Finished Apr 18 01:53:09 PM PDT 24
Peak memory 200688 kb
Host smart-233d76b1-08ce-4a4a-aaae-c0134f84cc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205562170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.205562170
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.2312478825
Short name T626
Test name
Test status
Simulation time 2079490914 ps
CPU time 1.51 seconds
Started Apr 18 01:52:52 PM PDT 24
Finished Apr 18 01:52:54 PM PDT 24
Peak memory 196248 kb
Host smart-872ca51d-c840-4793-b368-0e3db087271c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312478825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.2312478825
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.1994749052
Short name T451
Test name
Test status
Simulation time 5468839040 ps
CPU time 7.88 seconds
Started Apr 18 01:52:46 PM PDT 24
Finished Apr 18 01:52:56 PM PDT 24
Peak memory 200728 kb
Host smart-766103f7-d533-4767-a8aa-20b2b49691f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994749052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.1994749052
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.1010637397
Short name T832
Test name
Test status
Simulation time 318388232004 ps
CPU time 957.01 seconds
Started Apr 18 01:52:47 PM PDT 24
Finished Apr 18 02:08:46 PM PDT 24
Peak memory 201096 kb
Host smart-a921b86c-27c5-406a-99e5-109fdf923280
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010637397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.1010637397
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.1976928236
Short name T442
Test name
Test status
Simulation time 799278799 ps
CPU time 1.44 seconds
Started Apr 18 01:52:46 PM PDT 24
Finished Apr 18 01:52:49 PM PDT 24
Peak memory 200492 kb
Host smart-508a75f0-d429-4f91-824e-454dd263caae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976928236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.1976928236
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.3438896676
Short name T56
Test name
Test status
Simulation time 119628645896 ps
CPU time 41.06 seconds
Started Apr 18 01:52:51 PM PDT 24
Finished Apr 18 01:53:32 PM PDT 24
Peak memory 200884 kb
Host smart-0f44adb1-5af8-453e-a43d-3e7b6653107f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438896676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.3438896676
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.983220390
Short name T335
Test name
Test status
Simulation time 27539764 ps
CPU time 0.53 seconds
Started Apr 18 01:52:53 PM PDT 24
Finished Apr 18 01:52:54 PM PDT 24
Peak memory 195188 kb
Host smart-465fcdfb-ffb7-45df-a0af-83f307b7b9f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983220390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.983220390
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.1159518252
Short name T621
Test name
Test status
Simulation time 87741709847 ps
CPU time 40.06 seconds
Started Apr 18 01:52:53 PM PDT 24
Finished Apr 18 01:53:34 PM PDT 24
Peak memory 200848 kb
Host smart-c7810f49-1e94-4426-bf9a-594931e2a610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159518252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.1159518252
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.592642801
Short name T115
Test name
Test status
Simulation time 65128299428 ps
CPU time 24.48 seconds
Started Apr 18 01:52:55 PM PDT 24
Finished Apr 18 01:53:20 PM PDT 24
Peak memory 200792 kb
Host smart-01006428-909d-4a0c-8621-be5ed02677a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592642801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.592642801
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.983330373
Short name T119
Test name
Test status
Simulation time 23770419832 ps
CPU time 43.4 seconds
Started Apr 18 01:52:52 PM PDT 24
Finished Apr 18 01:53:36 PM PDT 24
Peak memory 200724 kb
Host smart-24dc5aba-00f1-4cd5-8881-1d58c7aa0d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983330373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.983330373
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.3210402180
Short name T389
Test name
Test status
Simulation time 24839012322 ps
CPU time 21.94 seconds
Started Apr 18 01:52:59 PM PDT 24
Finished Apr 18 01:53:21 PM PDT 24
Peak memory 200816 kb
Host smart-19687044-5857-46fe-b7f6-ce262f0ddd41
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210402180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.3210402180
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.3936345944
Short name T715
Test name
Test status
Simulation time 60282732593 ps
CPU time 266.16 seconds
Started Apr 18 01:53:21 PM PDT 24
Finished Apr 18 01:57:47 PM PDT 24
Peak memory 200828 kb
Host smart-967b3750-6c5d-490e-838b-8bf3a1677dd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3936345944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.3936345944
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.103309939
Short name T907
Test name
Test status
Simulation time 7478965648 ps
CPU time 5.5 seconds
Started Apr 18 01:52:54 PM PDT 24
Finished Apr 18 01:53:00 PM PDT 24
Peak memory 200720 kb
Host smart-57fd6941-2f5e-4abf-8390-02a6ea04bee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103309939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.103309939
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.924555154
Short name T942
Test name
Test status
Simulation time 33595843080 ps
CPU time 61 seconds
Started Apr 18 01:52:56 PM PDT 24
Finished Apr 18 01:53:57 PM PDT 24
Peak memory 200996 kb
Host smart-54ef08dd-a5a5-4979-9a29-3f24058435c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924555154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.924555154
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.3697914664
Short name T640
Test name
Test status
Simulation time 16819821258 ps
CPU time 786.18 seconds
Started Apr 18 01:52:53 PM PDT 24
Finished Apr 18 02:06:00 PM PDT 24
Peak memory 200912 kb
Host smart-27d9b73b-2d50-4820-bbc0-5793d3c1e8c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3697914664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.3697914664
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.82194327
Short name T1094
Test name
Test status
Simulation time 2019812537 ps
CPU time 15.6 seconds
Started Apr 18 01:52:54 PM PDT 24
Finished Apr 18 01:53:10 PM PDT 24
Peak memory 200012 kb
Host smart-675adacf-d214-46e8-927e-559e86a00e1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=82194327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.82194327
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.3478924213
Short name T251
Test name
Test status
Simulation time 68509980963 ps
CPU time 41.36 seconds
Started Apr 18 01:52:54 PM PDT 24
Finished Apr 18 01:53:36 PM PDT 24
Peak memory 200740 kb
Host smart-e4c6a3c4-c001-41fa-806f-c65823119235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478924213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.3478924213
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.3493720786
Short name T680
Test name
Test status
Simulation time 2555491721 ps
CPU time 1.65 seconds
Started Apr 18 01:52:53 PM PDT 24
Finished Apr 18 01:52:55 PM PDT 24
Peak memory 196660 kb
Host smart-53817437-33da-468a-844a-abe85f840fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493720786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3493720786
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.2563127046
Short name T436
Test name
Test status
Simulation time 926635929 ps
CPU time 1.89 seconds
Started Apr 18 01:52:54 PM PDT 24
Finished Apr 18 01:52:57 PM PDT 24
Peak memory 199728 kb
Host smart-9a1aeae5-04c0-482f-a9c6-f56276d6afb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563127046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.2563127046
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.3703515624
Short name T1059
Test name
Test status
Simulation time 93292045738 ps
CPU time 310.44 seconds
Started Apr 18 01:52:54 PM PDT 24
Finished Apr 18 01:58:06 PM PDT 24
Peak memory 216500 kb
Host smart-7623a0c8-e654-4f5a-bc31-01e90f9cf6c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703515624 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.3703515624
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.1113285979
Short name T986
Test name
Test status
Simulation time 12769527323 ps
CPU time 33.68 seconds
Started Apr 18 01:52:52 PM PDT 24
Finished Apr 18 01:53:26 PM PDT 24
Peak memory 200824 kb
Host smart-4c06789e-3aba-4a9d-a3a5-bc841e5b31e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113285979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.1113285979
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.3774833724
Short name T477
Test name
Test status
Simulation time 9290787702 ps
CPU time 15.41 seconds
Started Apr 18 01:52:58 PM PDT 24
Finished Apr 18 01:53:14 PM PDT 24
Peak memory 197808 kb
Host smart-135d7ae0-8bde-4a47-9edd-4fe33721c227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774833724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.3774833724
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.1820633228
Short name T991
Test name
Test status
Simulation time 14033216 ps
CPU time 0.54 seconds
Started Apr 18 01:53:00 PM PDT 24
Finished Apr 18 01:53:01 PM PDT 24
Peak memory 196212 kb
Host smart-9a683134-7d0b-44ff-80cc-f25e842bc434
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820633228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.1820633228
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.2491283465
Short name T35
Test name
Test status
Simulation time 34014820110 ps
CPU time 15.89 seconds
Started Apr 18 01:52:54 PM PDT 24
Finished Apr 18 01:53:11 PM PDT 24
Peak memory 200896 kb
Host smart-9f4e68de-a353-4a96-bfe0-cea8a0f7eff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491283465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.2491283465
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.3310809306
Short name T1169
Test name
Test status
Simulation time 149816042701 ps
CPU time 68.11 seconds
Started Apr 18 01:52:59 PM PDT 24
Finished Apr 18 01:54:08 PM PDT 24
Peak memory 200856 kb
Host smart-94643df0-e523-45c3-b0f4-9e5d89163420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310809306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.3310809306
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.1461195444
Short name T238
Test name
Test status
Simulation time 29906915688 ps
CPU time 19.12 seconds
Started Apr 18 01:52:53 PM PDT 24
Finished Apr 18 01:53:13 PM PDT 24
Peak memory 200824 kb
Host smart-83ff9478-a174-402d-a22d-a80b78efb427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461195444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.1461195444
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.1091069532
Short name T845
Test name
Test status
Simulation time 117885334000 ps
CPU time 180.18 seconds
Started Apr 18 01:52:57 PM PDT 24
Finished Apr 18 01:55:58 PM PDT 24
Peak memory 200544 kb
Host smart-32b8dfea-5b39-4b5b-9c9f-28003c74bdb5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091069532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.1091069532
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.308828048
Short name T321
Test name
Test status
Simulation time 118773760720 ps
CPU time 557.37 seconds
Started Apr 18 01:52:58 PM PDT 24
Finished Apr 18 02:02:17 PM PDT 24
Peak memory 200868 kb
Host smart-28aa2107-96ba-4ed9-89b2-f96a71e083b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=308828048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.308828048
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.639233221
Short name T471
Test name
Test status
Simulation time 4105599296 ps
CPU time 4.31 seconds
Started Apr 18 01:52:59 PM PDT 24
Finished Apr 18 01:53:04 PM PDT 24
Peak memory 198876 kb
Host smart-a9ba2cdb-71d5-4f29-a657-ec7de88e01b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639233221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.639233221
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.1604461985
Short name T866
Test name
Test status
Simulation time 89199452026 ps
CPU time 47.29 seconds
Started Apr 18 01:52:59 PM PDT 24
Finished Apr 18 01:53:47 PM PDT 24
Peak memory 200324 kb
Host smart-8d6f32ff-810e-4fbd-adc2-f523fa1a7b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604461985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.1604461985
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.2390979866
Short name T38
Test name
Test status
Simulation time 16551476195 ps
CPU time 424.07 seconds
Started Apr 18 01:53:02 PM PDT 24
Finished Apr 18 02:00:07 PM PDT 24
Peak memory 200884 kb
Host smart-ec8509f6-01c7-435b-b0b7-10cb4f648e8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2390979866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.2390979866
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.3377551933
Short name T799
Test name
Test status
Simulation time 5759344163 ps
CPU time 11.09 seconds
Started Apr 18 01:53:01 PM PDT 24
Finished Apr 18 01:53:12 PM PDT 24
Peak memory 200084 kb
Host smart-15441784-c786-466c-b54f-eb49fff84d80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3377551933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.3377551933
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.3240680276
Short name T1138
Test name
Test status
Simulation time 62845306251 ps
CPU time 97.11 seconds
Started Apr 18 01:53:00 PM PDT 24
Finished Apr 18 01:54:38 PM PDT 24
Peak memory 200816 kb
Host smart-2bfefe2a-dd57-4a25-9942-4aa64745a671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240680276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3240680276
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.1456955293
Short name T707
Test name
Test status
Simulation time 54479289439 ps
CPU time 44.87 seconds
Started Apr 18 01:52:59 PM PDT 24
Finished Apr 18 01:53:44 PM PDT 24
Peak memory 196904 kb
Host smart-da89b2d1-2b5c-440c-8aca-f7529dab51f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456955293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.1456955293
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.2653954395
Short name T417
Test name
Test status
Simulation time 11581023120 ps
CPU time 21.98 seconds
Started Apr 18 01:52:59 PM PDT 24
Finished Apr 18 01:53:21 PM PDT 24
Peak memory 200464 kb
Host smart-cf147202-2b13-4210-a557-02b97d4d869f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653954395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.2653954395
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.116845864
Short name T314
Test name
Test status
Simulation time 137893966527 ps
CPU time 1637.17 seconds
Started Apr 18 01:53:13 PM PDT 24
Finished Apr 18 02:20:31 PM PDT 24
Peak memory 200828 kb
Host smart-94eb4f06-f07d-4973-b10e-4ddf57e8e183
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116845864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.116845864
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.3870771535
Short name T1172
Test name
Test status
Simulation time 55154660876 ps
CPU time 633.11 seconds
Started Apr 18 01:52:59 PM PDT 24
Finished Apr 18 02:03:32 PM PDT 24
Peak memory 217284 kb
Host smart-4b26d56f-0621-4386-a21b-fb3f9dbc75ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870771535 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.3870771535
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.125864602
Short name T821
Test name
Test status
Simulation time 7492793635 ps
CPU time 12.26 seconds
Started Apr 18 01:53:01 PM PDT 24
Finished Apr 18 01:53:14 PM PDT 24
Peak memory 200740 kb
Host smart-2e73061a-f20a-4772-84f6-265056496d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125864602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.125864602
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.2820316686
Short name T755
Test name
Test status
Simulation time 12148784372 ps
CPU time 5.99 seconds
Started Apr 18 01:52:58 PM PDT 24
Finished Apr 18 01:53:05 PM PDT 24
Peak memory 198504 kb
Host smart-493e598d-6d48-4570-a417-94357177a037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820316686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.2820316686
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.2799951081
Short name T584
Test name
Test status
Simulation time 17527442 ps
CPU time 0.54 seconds
Started Apr 18 01:53:01 PM PDT 24
Finished Apr 18 01:53:02 PM PDT 24
Peak memory 196184 kb
Host smart-e1ef3d2f-d186-4d16-9776-82627ffce00b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799951081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.2799951081
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.2250246246
Short name T452
Test name
Test status
Simulation time 338313534706 ps
CPU time 115.57 seconds
Started Apr 18 01:52:57 PM PDT 24
Finished Apr 18 01:54:53 PM PDT 24
Peak memory 200872 kb
Host smart-986207e4-de52-454c-acef-2ba8d3c0e8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250246246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.2250246246
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.3101662107
Short name T808
Test name
Test status
Simulation time 76618787992 ps
CPU time 125.5 seconds
Started Apr 18 01:52:59 PM PDT 24
Finished Apr 18 01:55:06 PM PDT 24
Peak memory 200772 kb
Host smart-3eeefc56-ba3d-4351-b06c-6682c4e78081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101662107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.3101662107
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.493733207
Short name T651
Test name
Test status
Simulation time 36777090674 ps
CPU time 13.43 seconds
Started Apr 18 01:52:58 PM PDT 24
Finished Apr 18 01:53:12 PM PDT 24
Peak memory 200896 kb
Host smart-d14a69d3-9c41-4338-a529-6312d75ec2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493733207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.493733207
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.1977039366
Short name T336
Test name
Test status
Simulation time 32142141517 ps
CPU time 41.42 seconds
Started Apr 18 01:52:59 PM PDT 24
Finished Apr 18 01:53:41 PM PDT 24
Peak memory 200260 kb
Host smart-6768e23d-3520-4f19-8493-68ff95864b74
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977039366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.1977039366
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.3533388691
Short name T957
Test name
Test status
Simulation time 79446768875 ps
CPU time 198.25 seconds
Started Apr 18 01:53:03 PM PDT 24
Finished Apr 18 01:56:22 PM PDT 24
Peak memory 200820 kb
Host smart-0c6fdc17-23cc-4b04-a510-3ca05c956ff5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3533388691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.3533388691
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.2930450540
Short name T1008
Test name
Test status
Simulation time 8176734149 ps
CPU time 22.08 seconds
Started Apr 18 01:52:59 PM PDT 24
Finished Apr 18 01:53:22 PM PDT 24
Peak memory 200788 kb
Host smart-a3bb0f0b-0924-4057-be53-170cfb2f4bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930450540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.2930450540
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.1091022188
Short name T509
Test name
Test status
Simulation time 24709783543 ps
CPU time 8.75 seconds
Started Apr 18 01:53:13 PM PDT 24
Finished Apr 18 01:53:23 PM PDT 24
Peak memory 199368 kb
Host smart-f2eb821d-b4ce-4325-88c1-d0e41b835221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091022188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.1091022188
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.3162144628
Short name T263
Test name
Test status
Simulation time 28526662320 ps
CPU time 825.15 seconds
Started Apr 18 01:53:03 PM PDT 24
Finished Apr 18 02:06:49 PM PDT 24
Peak memory 200892 kb
Host smart-020bb239-ffa7-4066-aa1d-b9c1c2c0b8e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3162144628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.3162144628
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.379152171
Short name T426
Test name
Test status
Simulation time 3876102977 ps
CPU time 15.41 seconds
Started Apr 18 01:53:01 PM PDT 24
Finished Apr 18 01:53:16 PM PDT 24
Peak memory 199932 kb
Host smart-5b50c712-12db-47e4-b69e-352fea98bf68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=379152171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.379152171
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.1545459324
Short name T616
Test name
Test status
Simulation time 43247195201 ps
CPU time 36.31 seconds
Started Apr 18 01:53:11 PM PDT 24
Finished Apr 18 01:53:48 PM PDT 24
Peak memory 200860 kb
Host smart-b75b13c5-9691-4b35-92ca-0d362143782d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545459324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.1545459324
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.76518161
Short name T1127
Test name
Test status
Simulation time 2542753577 ps
CPU time 5.03 seconds
Started Apr 18 01:52:58 PM PDT 24
Finished Apr 18 01:53:03 PM PDT 24
Peak memory 196892 kb
Host smart-d49a2266-7c8e-4e3e-afe1-80d9df3c9b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76518161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.76518161
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.4227589609
Short name T1091
Test name
Test status
Simulation time 5531952923 ps
CPU time 14.92 seconds
Started Apr 18 01:53:02 PM PDT 24
Finished Apr 18 01:53:18 PM PDT 24
Peak memory 200744 kb
Host smart-7b464848-0c90-40c0-b14c-793960411bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227589609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.4227589609
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.17604996
Short name T413
Test name
Test status
Simulation time 17789875664 ps
CPU time 4.62 seconds
Started Apr 18 01:53:02 PM PDT 24
Finished Apr 18 01:53:07 PM PDT 24
Peak memory 200796 kb
Host smart-40bb562e-7cdb-4ff3-b2bc-7cf297fd489f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17604996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.17604996
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.1702531662
Short name T682
Test name
Test status
Simulation time 92959848021 ps
CPU time 414.57 seconds
Started Apr 18 01:53:03 PM PDT 24
Finished Apr 18 01:59:58 PM PDT 24
Peak memory 225684 kb
Host smart-bf382061-ea81-4e73-90f3-6c757f5a700e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702531662 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.1702531662
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.3999477988
Short name T1034
Test name
Test status
Simulation time 6387535917 ps
CPU time 16.78 seconds
Started Apr 18 01:52:58 PM PDT 24
Finished Apr 18 01:53:16 PM PDT 24
Peak memory 200292 kb
Host smart-c8ea0d86-39e9-4b80-a518-ee0f089891f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999477988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.3999477988
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.2993717543
Short name T949
Test name
Test status
Simulation time 135237340052 ps
CPU time 66.2 seconds
Started Apr 18 01:53:01 PM PDT 24
Finished Apr 18 01:54:07 PM PDT 24
Peak memory 200816 kb
Host smart-a9676d09-baca-49b5-99ef-91e2f1c3e2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993717543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.2993717543
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.995231381
Short name T1014
Test name
Test status
Simulation time 13414148 ps
CPU time 0.58 seconds
Started Apr 18 01:53:07 PM PDT 24
Finished Apr 18 01:53:08 PM PDT 24
Peak memory 196216 kb
Host smart-69810b20-27f1-4ece-8b90-97509186e36a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995231381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.995231381
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.1016369616
Short name T992
Test name
Test status
Simulation time 179774291866 ps
CPU time 141.99 seconds
Started Apr 18 01:53:01 PM PDT 24
Finished Apr 18 01:55:23 PM PDT 24
Peak memory 200768 kb
Host smart-12f92a65-bb48-44e6-b4a9-23ebbb3d3704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016369616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.1016369616
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.3732204054
Short name T449
Test name
Test status
Simulation time 4323505992 ps
CPU time 8.88 seconds
Started Apr 18 01:52:59 PM PDT 24
Finished Apr 18 01:53:09 PM PDT 24
Peak memory 200884 kb
Host smart-9c46e62b-c33c-4286-90bd-c35741ee6c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732204054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.3732204054
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.855670143
Short name T575
Test name
Test status
Simulation time 134235645591 ps
CPU time 49.7 seconds
Started Apr 18 01:52:57 PM PDT 24
Finished Apr 18 01:53:48 PM PDT 24
Peak memory 200900 kb
Host smart-082a1b06-c140-4ebd-8995-0b153a8417bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855670143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.855670143
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.4027693538
Short name T459
Test name
Test status
Simulation time 16598173531 ps
CPU time 13.88 seconds
Started Apr 18 01:53:00 PM PDT 24
Finished Apr 18 01:53:14 PM PDT 24
Peak memory 198852 kb
Host smart-85ce087f-0770-4f59-8215-9056bdc8ef71
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027693538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.4027693538
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.2746432754
Short name T876
Test name
Test status
Simulation time 97925368792 ps
CPU time 671.15 seconds
Started Apr 18 01:53:04 PM PDT 24
Finished Apr 18 02:04:15 PM PDT 24
Peak memory 200768 kb
Host smart-f6f2813b-608f-49c9-a734-2b61eb9f01c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2746432754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.2746432754
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.3843565822
Short name T853
Test name
Test status
Simulation time 4829331275 ps
CPU time 8.85 seconds
Started Apr 18 01:53:13 PM PDT 24
Finished Apr 18 01:53:23 PM PDT 24
Peak memory 198644 kb
Host smart-881a8c0d-afe6-464b-bb38-891565cb7632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843565822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.3843565822
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.3330585495
Short name T1025
Test name
Test status
Simulation time 91926688605 ps
CPU time 195.54 seconds
Started Apr 18 01:52:59 PM PDT 24
Finished Apr 18 01:56:15 PM PDT 24
Peak memory 199396 kb
Host smart-91934b39-c163-4ed8-a272-62ff9ab1ee35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330585495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.3330585495
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.56304858
Short name T780
Test name
Test status
Simulation time 25878399795 ps
CPU time 671.8 seconds
Started Apr 18 01:53:04 PM PDT 24
Finished Apr 18 02:04:16 PM PDT 24
Peak memory 200892 kb
Host smart-1d9d6ba4-2925-4bcc-abd8-a6c2645df83d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=56304858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.56304858
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.60923402
Short name T362
Test name
Test status
Simulation time 4952945110 ps
CPU time 10.78 seconds
Started Apr 18 01:52:59 PM PDT 24
Finished Apr 18 01:53:10 PM PDT 24
Peak memory 199004 kb
Host smart-599b1b4d-dd8b-4f29-a850-44ec93f1e63a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=60923402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.60923402
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.3295804129
Short name T1134
Test name
Test status
Simulation time 37361773469 ps
CPU time 15.12 seconds
Started Apr 18 01:53:02 PM PDT 24
Finished Apr 18 01:53:18 PM PDT 24
Peak memory 200560 kb
Host smart-b1f397c1-17c7-425f-b853-5ee793009137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295804129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.3295804129
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.3563497648
Short name T657
Test name
Test status
Simulation time 50241336195 ps
CPU time 22.29 seconds
Started Apr 18 01:53:03 PM PDT 24
Finished Apr 18 01:53:26 PM PDT 24
Peak memory 196904 kb
Host smart-fff5b3af-fbc3-4188-809e-36d6330edb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563497648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.3563497648
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.3828515305
Short name T486
Test name
Test status
Simulation time 320169920 ps
CPU time 1.73 seconds
Started Apr 18 01:52:59 PM PDT 24
Finished Apr 18 01:53:02 PM PDT 24
Peak memory 199600 kb
Host smart-c46a416b-0b19-4e33-8161-8a40cf11a5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828515305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.3828515305
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.599344665
Short name T269
Test name
Test status
Simulation time 2461195636 ps
CPU time 2.17 seconds
Started Apr 18 01:53:05 PM PDT 24
Finished Apr 18 01:53:07 PM PDT 24
Peak memory 199296 kb
Host smart-f837b7ba-27f4-4ce1-a12d-a6e414dfa1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599344665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.599344665
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.2388964080
Short name T92
Test name
Test status
Simulation time 87635180698 ps
CPU time 217.43 seconds
Started Apr 18 01:53:03 PM PDT 24
Finished Apr 18 01:56:41 PM PDT 24
Peak memory 200880 kb
Host smart-fb7cc8a9-161f-415d-9feb-7fb0262b4f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388964080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.2388964080
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.3728547242
Short name T507
Test name
Test status
Simulation time 23887735 ps
CPU time 0.58 seconds
Started Apr 18 01:51:50 PM PDT 24
Finished Apr 18 01:51:51 PM PDT 24
Peak memory 196224 kb
Host smart-93722a69-63d3-4194-8d64-a450dfe15d45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728547242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.3728547242
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.1951053045
Short name T136
Test name
Test status
Simulation time 111830603304 ps
CPU time 57.63 seconds
Started Apr 18 01:51:59 PM PDT 24
Finished Apr 18 01:52:57 PM PDT 24
Peak memory 200852 kb
Host smart-37150ffd-9c66-4796-acdb-cfc8f33d9532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951053045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.1951053045
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.1510647863
Short name T594
Test name
Test status
Simulation time 57073859100 ps
CPU time 34.94 seconds
Started Apr 18 01:51:26 PM PDT 24
Finished Apr 18 01:52:02 PM PDT 24
Peak memory 200864 kb
Host smart-491aeea1-0a06-44e2-8dbd-8fc9d3dac8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510647863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1510647863
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.1987531793
Short name T601
Test name
Test status
Simulation time 137772235873 ps
CPU time 94.49 seconds
Started Apr 18 01:51:24 PM PDT 24
Finished Apr 18 01:52:59 PM PDT 24
Peak memory 200860 kb
Host smart-7989ca86-d778-4fea-81e5-8e6d2f60501c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987531793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.1987531793
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.98277808
Short name T1150
Test name
Test status
Simulation time 20616046339 ps
CPU time 5.65 seconds
Started Apr 18 01:51:28 PM PDT 24
Finished Apr 18 01:51:34 PM PDT 24
Peak memory 198500 kb
Host smart-00190f69-d60e-472f-bc6f-717a9a2fe4a5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98277808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.98277808
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.2640801849
Short name T411
Test name
Test status
Simulation time 47532643158 ps
CPU time 104.24 seconds
Started Apr 18 01:51:34 PM PDT 24
Finished Apr 18 01:53:18 PM PDT 24
Peak memory 200780 kb
Host smart-c4828cfe-d892-4f72-9eca-99dec4560731
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2640801849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.2640801849
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.3751299628
Short name T332
Test name
Test status
Simulation time 9424518565 ps
CPU time 4.24 seconds
Started Apr 18 01:51:28 PM PDT 24
Finished Apr 18 01:51:33 PM PDT 24
Peak memory 199664 kb
Host smart-d405c13d-9bd7-45e7-b3b3-5c590a957925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751299628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.3751299628
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.1844579682
Short name T1153
Test name
Test status
Simulation time 30601217983 ps
CPU time 12.41 seconds
Started Apr 18 01:51:33 PM PDT 24
Finished Apr 18 01:51:45 PM PDT 24
Peak memory 200840 kb
Host smart-0a8557c3-0cc5-49af-a342-e652447d6183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844579682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.1844579682
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.3982539413
Short name T499
Test name
Test status
Simulation time 24847842493 ps
CPU time 666.82 seconds
Started Apr 18 01:51:35 PM PDT 24
Finished Apr 18 02:02:42 PM PDT 24
Peak memory 200912 kb
Host smart-91707171-26ca-40f8-8122-ea50aee9fa67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3982539413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.3982539413
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.443663663
Short name T334
Test name
Test status
Simulation time 2425874899 ps
CPU time 8.21 seconds
Started Apr 18 01:51:23 PM PDT 24
Finished Apr 18 01:51:31 PM PDT 24
Peak memory 198900 kb
Host smart-ef962afc-7ee6-4024-be38-82e9f8783443
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=443663663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.443663663
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.1134055353
Short name T751
Test name
Test status
Simulation time 96217565088 ps
CPU time 41.44 seconds
Started Apr 18 01:51:26 PM PDT 24
Finished Apr 18 01:52:08 PM PDT 24
Peak memory 200672 kb
Host smart-cfc4fd7e-9e2c-40b0-aed6-f72e72a4634c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134055353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.1134055353
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.4164907756
Short name T398
Test name
Test status
Simulation time 650011438 ps
CPU time 0.86 seconds
Started Apr 18 01:51:26 PM PDT 24
Finished Apr 18 01:51:28 PM PDT 24
Peak memory 196268 kb
Host smart-db3d1abc-1d0d-45a3-bfa1-9eebee87fe17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164907756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.4164907756
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.3658139722
Short name T86
Test name
Test status
Simulation time 1875046854 ps
CPU time 1.03 seconds
Started Apr 18 01:51:24 PM PDT 24
Finished Apr 18 01:51:26 PM PDT 24
Peak memory 218892 kb
Host smart-b45002a3-ba92-4bfb-ab26-6041e03e6207
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658139722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.3658139722
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.1432046579
Short name T359
Test name
Test status
Simulation time 448782021 ps
CPU time 1.54 seconds
Started Apr 18 01:51:35 PM PDT 24
Finished Apr 18 01:51:37 PM PDT 24
Peak memory 200324 kb
Host smart-f795a005-c2ee-4f1b-8a97-ac7389d113e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432046579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.1432046579
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.702897508
Short name T819
Test name
Test status
Simulation time 421252743879 ps
CPU time 200.82 seconds
Started Apr 18 01:51:26 PM PDT 24
Finished Apr 18 01:54:48 PM PDT 24
Peak memory 200908 kb
Host smart-33031542-9576-40cd-a63e-e7cfca2f3a6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702897508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.702897508
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.439321535
Short name T241
Test name
Test status
Simulation time 29810552029 ps
CPU time 361.66 seconds
Started Apr 18 01:51:28 PM PDT 24
Finished Apr 18 01:57:31 PM PDT 24
Peak memory 217320 kb
Host smart-745b8303-d3ee-4a28-803c-2a8e7257d9af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439321535 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.439321535
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.1793121253
Short name T555
Test name
Test status
Simulation time 1395509390 ps
CPU time 2.08 seconds
Started Apr 18 01:51:23 PM PDT 24
Finished Apr 18 01:51:25 PM PDT 24
Peak memory 199752 kb
Host smart-b4845d45-6957-48f1-86f9-bf2deae1b4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793121253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.1793121253
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.2688613136
Short name T909
Test name
Test status
Simulation time 28053686189 ps
CPU time 54.3 seconds
Started Apr 18 01:51:25 PM PDT 24
Finished Apr 18 01:52:21 PM PDT 24
Peak memory 200880 kb
Host smart-c18da060-d78e-4cf3-b9fe-26db46d2659a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688613136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.2688613136
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.3737841391
Short name T687
Test name
Test status
Simulation time 13396044 ps
CPU time 0.57 seconds
Started Apr 18 01:53:13 PM PDT 24
Finished Apr 18 01:53:15 PM PDT 24
Peak memory 196212 kb
Host smart-ce49f7f6-a121-40fe-a93a-0087330e8e8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737841391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.3737841391
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.438590923
Short name T124
Test name
Test status
Simulation time 44002767996 ps
CPU time 74.39 seconds
Started Apr 18 01:53:02 PM PDT 24
Finished Apr 18 01:54:16 PM PDT 24
Peak memory 200924 kb
Host smart-0de61e10-0f22-467e-9680-bb13ca9471d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438590923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.438590923
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.1628838345
Short name T583
Test name
Test status
Simulation time 98882673018 ps
CPU time 142.46 seconds
Started Apr 18 01:53:02 PM PDT 24
Finished Apr 18 01:55:25 PM PDT 24
Peak memory 200876 kb
Host smart-9ee99cb9-6547-4d5a-b217-444359db0f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628838345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.1628838345
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.3498498991
Short name T139
Test name
Test status
Simulation time 86312239888 ps
CPU time 37.16 seconds
Started Apr 18 01:53:02 PM PDT 24
Finished Apr 18 01:53:40 PM PDT 24
Peak memory 200672 kb
Host smart-625af1c1-e7a6-4290-80e7-185079014169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498498991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.3498498991
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.1084723208
Short name T753
Test name
Test status
Simulation time 59737745438 ps
CPU time 107.18 seconds
Started Apr 18 01:53:04 PM PDT 24
Finished Apr 18 01:54:52 PM PDT 24
Peak memory 200784 kb
Host smart-98fbde09-6267-4e52-8109-e935f80e0312
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084723208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.1084723208
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.2740778882
Short name T1096
Test name
Test status
Simulation time 55842593166 ps
CPU time 442.01 seconds
Started Apr 18 01:53:03 PM PDT 24
Finished Apr 18 02:00:26 PM PDT 24
Peak memory 200896 kb
Host smart-5dd5ff52-7c66-4f25-8789-12ebc6caa185
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2740778882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2740778882
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.2003621240
Short name T361
Test name
Test status
Simulation time 10922556503 ps
CPU time 7.09 seconds
Started Apr 18 01:53:03 PM PDT 24
Finished Apr 18 01:53:11 PM PDT 24
Peak memory 200912 kb
Host smart-a97e52bc-81ff-4897-bbf0-dbdeee28c1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003621240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.2003621240
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.1204918542
Short name T328
Test name
Test status
Simulation time 119469067067 ps
CPU time 50.8 seconds
Started Apr 18 01:53:13 PM PDT 24
Finished Apr 18 01:54:05 PM PDT 24
Peak memory 201080 kb
Host smart-538eb18b-0066-4a48-8eed-e63f374b219c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204918542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.1204918542
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.2793183853
Short name T88
Test name
Test status
Simulation time 15777183588 ps
CPU time 222.97 seconds
Started Apr 18 01:53:04 PM PDT 24
Finished Apr 18 01:56:47 PM PDT 24
Peak memory 200852 kb
Host smart-ef8f524e-1f23-414a-a830-3346204be0cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2793183853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.2793183853
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.3179727829
Short name T75
Test name
Test status
Simulation time 2816775801 ps
CPU time 2.37 seconds
Started Apr 18 01:53:13 PM PDT 24
Finished Apr 18 01:53:17 PM PDT 24
Peak memory 198940 kb
Host smart-6f170b06-c6ad-49e0-ab85-56144b0d8abd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3179727829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.3179727829
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.2833797854
Short name T691
Test name
Test status
Simulation time 206555274725 ps
CPU time 58.07 seconds
Started Apr 18 01:53:05 PM PDT 24
Finished Apr 18 01:54:03 PM PDT 24
Peak memory 200832 kb
Host smart-d9806066-804e-4361-8971-d6aba7d4fca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833797854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.2833797854
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.708654518
Short name T490
Test name
Test status
Simulation time 3346484859 ps
CPU time 3.59 seconds
Started Apr 18 01:53:04 PM PDT 24
Finished Apr 18 01:53:08 PM PDT 24
Peak memory 196772 kb
Host smart-e88b96d4-eb62-4f80-a777-92e5ec5626a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708654518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.708654518
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.844228833
Short name T541
Test name
Test status
Simulation time 469743762 ps
CPU time 2.1 seconds
Started Apr 18 01:53:03 PM PDT 24
Finished Apr 18 01:53:06 PM PDT 24
Peak memory 199388 kb
Host smart-32923da2-b597-4eb2-92d1-e52df2e05a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844228833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.844228833
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.1103683945
Short name T474
Test name
Test status
Simulation time 231535464569 ps
CPU time 565.14 seconds
Started Apr 18 01:53:07 PM PDT 24
Finished Apr 18 02:02:34 PM PDT 24
Peak memory 209300 kb
Host smart-b1285bae-762a-4c6f-a73d-322b2287ed9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103683945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.1103683945
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.716062705
Short name T1003
Test name
Test status
Simulation time 293278458534 ps
CPU time 679.58 seconds
Started Apr 18 01:53:02 PM PDT 24
Finished Apr 18 02:04:21 PM PDT 24
Peak memory 225748 kb
Host smart-b6ad01bb-89f7-4400-b29c-81009f8e7a25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716062705 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.716062705
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.2107529387
Short name T503
Test name
Test status
Simulation time 7558702775 ps
CPU time 10.6 seconds
Started Apr 18 01:53:02 PM PDT 24
Finished Apr 18 01:53:13 PM PDT 24
Peak memory 200612 kb
Host smart-6ea0dbcc-4159-4f5b-895a-ed708f64a6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107529387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.2107529387
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.1967788676
Short name T290
Test name
Test status
Simulation time 192849498134 ps
CPU time 31.19 seconds
Started Apr 18 01:53:04 PM PDT 24
Finished Apr 18 01:53:35 PM PDT 24
Peak memory 200876 kb
Host smart-0028ab8a-11e4-4beb-bf75-57fb556978d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967788676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.1967788676
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.1113481546
Short name T565
Test name
Test status
Simulation time 162883428 ps
CPU time 0.58 seconds
Started Apr 18 01:53:13 PM PDT 24
Finished Apr 18 01:53:15 PM PDT 24
Peak memory 196188 kb
Host smart-a6750941-4571-4f9f-adf9-d728aab3df02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113481546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.1113481546
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.3784697023
Short name T162
Test name
Test status
Simulation time 148024079797 ps
CPU time 76.94 seconds
Started Apr 18 01:53:12 PM PDT 24
Finished Apr 18 01:54:29 PM PDT 24
Peak memory 200876 kb
Host smart-58456812-a547-4ccb-ab33-0e6aeeb30e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784697023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3784697023
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.1548840202
Short name T850
Test name
Test status
Simulation time 54979908240 ps
CPU time 95.91 seconds
Started Apr 18 01:53:09 PM PDT 24
Finished Apr 18 01:54:46 PM PDT 24
Peak memory 200632 kb
Host smart-89f52bd9-1e4d-4f5b-b97d-88efa174e16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548840202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.1548840202
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.3057825852
Short name T360
Test name
Test status
Simulation time 29086549059 ps
CPU time 529.3 seconds
Started Apr 18 01:53:42 PM PDT 24
Finished Apr 18 02:02:32 PM PDT 24
Peak memory 200848 kb
Host smart-e805c782-fd8f-4de2-9c1b-352ab22b77e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057825852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3057825852
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.3717795425
Short name T502
Test name
Test status
Simulation time 45154775143 ps
CPU time 92.16 seconds
Started Apr 18 01:53:09 PM PDT 24
Finished Apr 18 01:54:41 PM PDT 24
Peak memory 200876 kb
Host smart-4870d612-5689-44d9-8757-a9e10cc14959
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717795425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.3717795425
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.2651071110
Short name T458
Test name
Test status
Simulation time 149862511887 ps
CPU time 159.69 seconds
Started Apr 18 01:53:11 PM PDT 24
Finished Apr 18 01:55:51 PM PDT 24
Peak memory 200892 kb
Host smart-f006e7e4-26eb-4f19-860a-807f1325f040
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2651071110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.2651071110
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.2946074731
Short name T863
Test name
Test status
Simulation time 8583769718 ps
CPU time 12.76 seconds
Started Apr 18 01:53:08 PM PDT 24
Finished Apr 18 01:53:21 PM PDT 24
Peak memory 200780 kb
Host smart-98e04573-3d19-4257-8f96-19ba747c5520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946074731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.2946074731
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.2035141793
Short name T410
Test name
Test status
Simulation time 38346229330 ps
CPU time 18.36 seconds
Started Apr 18 01:53:11 PM PDT 24
Finished Apr 18 01:53:30 PM PDT 24
Peak memory 196872 kb
Host smart-af3e74d7-8478-425a-9b95-d39b34ed6e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035141793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.2035141793
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.3365569650
Short name T1121
Test name
Test status
Simulation time 8605768836 ps
CPU time 433.59 seconds
Started Apr 18 01:53:09 PM PDT 24
Finished Apr 18 02:00:23 PM PDT 24
Peak memory 200868 kb
Host smart-8cd57155-dd75-4184-9232-8f3c95583f8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3365569650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.3365569650
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.695487398
Short name T1130
Test name
Test status
Simulation time 7123044630 ps
CPU time 15.5 seconds
Started Apr 18 01:53:08 PM PDT 24
Finished Apr 18 01:53:24 PM PDT 24
Peak memory 199652 kb
Host smart-a3e92d4b-1066-40df-ab3a-bedb59d831da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=695487398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.695487398
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.1662140727
Short name T1082
Test name
Test status
Simulation time 4104973519 ps
CPU time 4.12 seconds
Started Apr 18 01:53:10 PM PDT 24
Finished Apr 18 01:53:15 PM PDT 24
Peak memory 197180 kb
Host smart-b1c56377-592d-4325-ba94-5470df70d4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662140727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.1662140727
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.1413707281
Short name T500
Test name
Test status
Simulation time 570777264 ps
CPU time 1.34 seconds
Started Apr 18 01:53:13 PM PDT 24
Finished Apr 18 01:53:16 PM PDT 24
Peak memory 199104 kb
Host smart-cebab695-2030-4d77-93fd-23eb78a93033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413707281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.1413707281
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.3368132222
Short name T151
Test name
Test status
Simulation time 147493739033 ps
CPU time 135.01 seconds
Started Apr 18 01:53:09 PM PDT 24
Finished Apr 18 01:55:25 PM PDT 24
Peak memory 200880 kb
Host smart-338398fb-e46e-47f0-ba9c-6b3b804e031c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368132222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.3368132222
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.3210777755
Short name T317
Test name
Test status
Simulation time 35858244629 ps
CPU time 408.17 seconds
Started Apr 18 01:53:10 PM PDT 24
Finished Apr 18 01:59:59 PM PDT 24
Peak memory 217736 kb
Host smart-2a0805fc-6fcb-409b-8c17-b13f61799271
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210777755 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.3210777755
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.3603061863
Short name T433
Test name
Test status
Simulation time 863831808 ps
CPU time 1.3 seconds
Started Apr 18 01:53:11 PM PDT 24
Finished Apr 18 01:53:13 PM PDT 24
Peak memory 199436 kb
Host smart-9e735da9-94bf-4074-97a4-4c43f81e2782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603061863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.3603061863
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.3338115173
Short name T258
Test name
Test status
Simulation time 28215362187 ps
CPU time 46.43 seconds
Started Apr 18 01:53:09 PM PDT 24
Finished Apr 18 01:53:56 PM PDT 24
Peak memory 200888 kb
Host smart-8280d255-0161-4013-9c65-febfba37608e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338115173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.3338115173
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.2984391884
Short name T1035
Test name
Test status
Simulation time 12579447 ps
CPU time 0.58 seconds
Started Apr 18 01:53:18 PM PDT 24
Finished Apr 18 01:53:20 PM PDT 24
Peak memory 196216 kb
Host smart-0bd6f919-6955-42ca-bd0e-42aacd4a1edc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984391884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.2984391884
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.731004220
Short name T708
Test name
Test status
Simulation time 159894237726 ps
CPU time 229.8 seconds
Started Apr 18 01:53:15 PM PDT 24
Finished Apr 18 01:57:06 PM PDT 24
Peak memory 200928 kb
Host smart-5a43c35b-5593-4826-8f73-193a70ca5238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731004220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.731004220
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.2513675971
Short name T58
Test name
Test status
Simulation time 48739049958 ps
CPU time 22.76 seconds
Started Apr 18 01:53:09 PM PDT 24
Finished Apr 18 01:53:33 PM PDT 24
Peak memory 200396 kb
Host smart-4f428bd2-cd6c-4bbc-974d-d69f8f6c916b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513675971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.2513675971
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.321857182
Short name T869
Test name
Test status
Simulation time 59651222622 ps
CPU time 34.48 seconds
Started Apr 18 01:53:13 PM PDT 24
Finished Apr 18 01:53:48 PM PDT 24
Peak memory 200824 kb
Host smart-0394c9c9-6183-4003-9cd1-e1fa17069e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321857182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.321857182
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.4053606245
Short name T1125
Test name
Test status
Simulation time 12073135084 ps
CPU time 17.98 seconds
Started Apr 18 01:53:08 PM PDT 24
Finished Apr 18 01:53:27 PM PDT 24
Peak memory 198580 kb
Host smart-bbecfed9-69a4-4ef6-b434-3ad088fc890c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053606245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.4053606245
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.1892035010
Short name T408
Test name
Test status
Simulation time 82760818771 ps
CPU time 614.94 seconds
Started Apr 18 01:53:16 PM PDT 24
Finished Apr 18 02:03:32 PM PDT 24
Peak memory 200916 kb
Host smart-914729ea-8ce7-4e3a-b8c9-bf980751f64b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1892035010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.1892035010
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.1910580216
Short name T57
Test name
Test status
Simulation time 641039152 ps
CPU time 2.07 seconds
Started Apr 18 01:53:18 PM PDT 24
Finished Apr 18 01:53:21 PM PDT 24
Peak memory 198544 kb
Host smart-9ee712aa-492f-44ad-a1b2-fd826713c621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910580216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.1910580216
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.1704238786
Short name T443
Test name
Test status
Simulation time 118429561953 ps
CPU time 240.23 seconds
Started Apr 18 01:53:11 PM PDT 24
Finished Apr 18 01:57:12 PM PDT 24
Peak memory 200388 kb
Host smart-5bc3dc2a-7281-4628-a72b-df7daf59af9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704238786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.1704238786
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.2442741530
Short name T1012
Test name
Test status
Simulation time 11639975277 ps
CPU time 183.65 seconds
Started Apr 18 01:53:16 PM PDT 24
Finished Apr 18 01:56:20 PM PDT 24
Peak memory 200860 kb
Host smart-a77b0c2b-09e8-4d4a-8dc1-d186e12cdecd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2442741530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.2442741530
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.3030436208
Short name T656
Test name
Test status
Simulation time 3690967002 ps
CPU time 11.63 seconds
Started Apr 18 01:53:09 PM PDT 24
Finished Apr 18 01:53:21 PM PDT 24
Peak memory 198820 kb
Host smart-a0a30b40-4d89-400a-92a1-c655d9f85c1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3030436208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3030436208
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.3579506966
Short name T515
Test name
Test status
Simulation time 8096809826 ps
CPU time 12.22 seconds
Started Apr 18 01:53:11 PM PDT 24
Finished Apr 18 01:53:24 PM PDT 24
Peak memory 200892 kb
Host smart-f3efe883-f392-4b2d-a42c-be0f7382a01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579506966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.3579506966
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.545281778
Short name T631
Test name
Test status
Simulation time 37246444799 ps
CPU time 34.82 seconds
Started Apr 18 01:53:13 PM PDT 24
Finished Apr 18 01:53:48 PM PDT 24
Peak memory 196668 kb
Host smart-dd8a014f-dfda-405d-87d6-83545524a9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545281778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.545281778
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.3697306305
Short name T293
Test name
Test status
Simulation time 266604599 ps
CPU time 1.42 seconds
Started Apr 18 01:53:08 PM PDT 24
Finished Apr 18 01:53:10 PM PDT 24
Peak memory 199224 kb
Host smart-4bde4722-3eac-4cf7-a2c2-3870c1d47dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697306305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.3697306305
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.1783258757
Short name T962
Test name
Test status
Simulation time 152079178162 ps
CPU time 275.5 seconds
Started Apr 18 01:53:18 PM PDT 24
Finished Apr 18 01:57:55 PM PDT 24
Peak memory 200760 kb
Host smart-68189764-ec21-4052-a0e7-e8a20849dbd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783258757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.1783258757
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.1590036546
Short name T908
Test name
Test status
Simulation time 122651379127 ps
CPU time 764.29 seconds
Started Apr 18 01:53:19 PM PDT 24
Finished Apr 18 02:06:04 PM PDT 24
Peak memory 217336 kb
Host smart-6c83f83a-43ae-4588-8b5b-123bd32a2ddc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590036546 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.1590036546
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.2236185823
Short name T620
Test name
Test status
Simulation time 597809406 ps
CPU time 2.12 seconds
Started Apr 18 01:53:09 PM PDT 24
Finished Apr 18 01:53:12 PM PDT 24
Peak memory 199368 kb
Host smart-f3efc117-af19-4a06-969d-ed9e87fee502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236185823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.2236185823
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.1278986169
Short name T1093
Test name
Test status
Simulation time 160017230658 ps
CPU time 62.55 seconds
Started Apr 18 01:53:10 PM PDT 24
Finished Apr 18 01:54:13 PM PDT 24
Peak memory 200808 kb
Host smart-07863b1e-638e-4f39-bdb9-3397a1c5f638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278986169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.1278986169
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.2181597308
Short name T463
Test name
Test status
Simulation time 31547310 ps
CPU time 0.53 seconds
Started Apr 18 01:53:16 PM PDT 24
Finished Apr 18 01:53:17 PM PDT 24
Peak memory 195188 kb
Host smart-c585dee3-3548-4060-b402-1d2db992d578
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181597308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.2181597308
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.3611597834
Short name T529
Test name
Test status
Simulation time 94893802205 ps
CPU time 36.52 seconds
Started Apr 18 01:53:16 PM PDT 24
Finished Apr 18 01:53:53 PM PDT 24
Peak memory 200764 kb
Host smart-282ede67-a8dc-4532-bc66-307d7e085741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611597834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.3611597834
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.1824738152
Short name T918
Test name
Test status
Simulation time 15813602024 ps
CPU time 26.46 seconds
Started Apr 18 01:53:16 PM PDT 24
Finished Apr 18 01:53:43 PM PDT 24
Peak memory 200864 kb
Host smart-e66e3cca-e2d1-48f8-b340-af0a87db9e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824738152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1824738152
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.2755206862
Short name T946
Test name
Test status
Simulation time 59755002730 ps
CPU time 105.41 seconds
Started Apr 18 01:53:19 PM PDT 24
Finished Apr 18 01:55:05 PM PDT 24
Peak memory 200852 kb
Host smart-5fb0ffe4-3ae1-42d9-8e2b-b1a61a072ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755206862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.2755206862
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.4103006561
Short name T816
Test name
Test status
Simulation time 69605633474 ps
CPU time 53.58 seconds
Started Apr 18 01:53:17 PM PDT 24
Finished Apr 18 01:54:11 PM PDT 24
Peak memory 196948 kb
Host smart-c06639e2-19fb-4b32-b57c-93cdda59f1a8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103006561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.4103006561
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.1595532308
Short name T55
Test name
Test status
Simulation time 98456423530 ps
CPU time 331.68 seconds
Started Apr 18 01:53:17 PM PDT 24
Finished Apr 18 01:58:49 PM PDT 24
Peak memory 200812 kb
Host smart-c649f72b-be37-410f-b25f-a90e9f6435fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1595532308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.1595532308
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.3468788699
Short name T1019
Test name
Test status
Simulation time 8815337821 ps
CPU time 9.06 seconds
Started Apr 18 01:53:17 PM PDT 24
Finished Apr 18 01:53:26 PM PDT 24
Peak memory 200844 kb
Host smart-aea706a4-8581-4d8d-a8a0-fa83ab56b945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468788699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.3468788699
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.2047124029
Short name T36
Test name
Test status
Simulation time 98482941193 ps
CPU time 9.96 seconds
Started Apr 18 01:53:16 PM PDT 24
Finished Apr 18 01:53:27 PM PDT 24
Peak memory 195472 kb
Host smart-573639c3-fe3a-46f7-8c48-b447355eb185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047124029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.2047124029
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.2755073161
Short name T741
Test name
Test status
Simulation time 18381465479 ps
CPU time 284.73 seconds
Started Apr 18 01:53:16 PM PDT 24
Finished Apr 18 01:58:01 PM PDT 24
Peak memory 200872 kb
Host smart-d239280d-357c-4cbd-a3fd-8a195722551e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2755073161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.2755073161
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.2866457106
Short name T518
Test name
Test status
Simulation time 6633908449 ps
CPU time 28.25 seconds
Started Apr 18 01:53:16 PM PDT 24
Finished Apr 18 01:53:45 PM PDT 24
Peak memory 199000 kb
Host smart-19f8874b-5afd-44a0-bb8b-2be42c90f912
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2866457106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.2866457106
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.3796191193
Short name T489
Test name
Test status
Simulation time 31606973825 ps
CPU time 25.33 seconds
Started Apr 18 01:53:15 PM PDT 24
Finished Apr 18 01:53:40 PM PDT 24
Peak memory 200816 kb
Host smart-5758cb92-100d-4649-857f-4f540c5d4210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796191193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.3796191193
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.783450974
Short name T1026
Test name
Test status
Simulation time 815344097 ps
CPU time 1.91 seconds
Started Apr 18 01:53:15 PM PDT 24
Finished Apr 18 01:53:17 PM PDT 24
Peak memory 196260 kb
Host smart-fccb2f24-1a9f-4c13-94b8-21bfd310d330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783450974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.783450974
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.4140066981
Short name T703
Test name
Test status
Simulation time 898448405 ps
CPU time 2.3 seconds
Started Apr 18 01:53:16 PM PDT 24
Finished Apr 18 01:53:19 PM PDT 24
Peak memory 199556 kb
Host smart-b361dc83-ec25-4ca7-ae96-cf0968b5a0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140066981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.4140066981
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.831488025
Short name T581
Test name
Test status
Simulation time 149464150010 ps
CPU time 112.58 seconds
Started Apr 18 01:53:15 PM PDT 24
Finished Apr 18 01:55:09 PM PDT 24
Peak memory 200884 kb
Host smart-02da1619-9d0e-4a09-b584-43a5a0e5a155
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831488025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.831488025
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.2838851338
Short name T1095
Test name
Test status
Simulation time 48449687283 ps
CPU time 352.86 seconds
Started Apr 18 01:53:19 PM PDT 24
Finished Apr 18 01:59:12 PM PDT 24
Peak memory 216796 kb
Host smart-5c16fd3b-144f-4f23-ab19-09e3c0a84863
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838851338 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.2838851338
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.3629186086
Short name T307
Test name
Test status
Simulation time 963074210 ps
CPU time 2.48 seconds
Started Apr 18 01:53:16 PM PDT 24
Finished Apr 18 01:53:19 PM PDT 24
Peak memory 200532 kb
Host smart-7ee9e887-6f4b-4ae0-a95c-cda5819f9b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629186086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.3629186086
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.817736023
Short name T1041
Test name
Test status
Simulation time 16959761679 ps
CPU time 29.18 seconds
Started Apr 18 01:53:17 PM PDT 24
Finished Apr 18 01:53:47 PM PDT 24
Peak memory 200832 kb
Host smart-fc4a2fd6-0008-42a4-a818-470916ba6e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817736023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.817736023
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.2520574287
Short name T712
Test name
Test status
Simulation time 33942218 ps
CPU time 0.56 seconds
Started Apr 18 01:53:26 PM PDT 24
Finished Apr 18 01:53:27 PM PDT 24
Peak memory 196188 kb
Host smart-22fda121-263c-483a-97cf-e2c0c3a0a8b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520574287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.2520574287
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.3571534658
Short name T723
Test name
Test status
Simulation time 110861618341 ps
CPU time 227.48 seconds
Started Apr 18 01:53:18 PM PDT 24
Finished Apr 18 01:57:06 PM PDT 24
Peak memory 200800 kb
Host smart-1e7a71a7-ed86-45e7-a9c8-3dd39807a765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571534658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.3571534658
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.1247240496
Short name T1028
Test name
Test status
Simulation time 107791632255 ps
CPU time 46.92 seconds
Started Apr 18 01:53:23 PM PDT 24
Finished Apr 18 01:54:10 PM PDT 24
Peak memory 200836 kb
Host smart-8c7f3324-a1d0-4180-a840-39fc02356694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247240496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1247240496
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.3646450983
Short name T220
Test name
Test status
Simulation time 146178214549 ps
CPU time 68.58 seconds
Started Apr 18 01:53:25 PM PDT 24
Finished Apr 18 01:54:34 PM PDT 24
Peak memory 200844 kb
Host smart-56b932c5-b91f-43ee-8591-cca4b5141f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646450983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.3646450983
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.3814261579
Short name T106
Test name
Test status
Simulation time 377209095262 ps
CPU time 39.79 seconds
Started Apr 18 01:53:21 PM PDT 24
Finished Apr 18 01:54:01 PM PDT 24
Peak memory 200504 kb
Host smart-cb11fa48-2023-44bb-a8b4-72f3eb5ed021
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814261579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.3814261579
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.3006641522
Short name T383
Test name
Test status
Simulation time 36828028035 ps
CPU time 139.77 seconds
Started Apr 18 01:53:22 PM PDT 24
Finished Apr 18 01:55:42 PM PDT 24
Peak memory 200892 kb
Host smart-d1fd06a7-ea73-47c3-a77d-2e00e9f00afb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3006641522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.3006641522
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.3298258351
Short name T1098
Test name
Test status
Simulation time 4924429345 ps
CPU time 7.04 seconds
Started Apr 18 01:53:20 PM PDT 24
Finished Apr 18 01:53:28 PM PDT 24
Peak memory 200108 kb
Host smart-4b2e1cf8-e1af-4137-8dfb-d2b249b588ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298258351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.3298258351
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.3179914771
Short name T90
Test name
Test status
Simulation time 50057635848 ps
CPU time 43.03 seconds
Started Apr 18 01:53:18 PM PDT 24
Finished Apr 18 01:54:02 PM PDT 24
Peak memory 201012 kb
Host smart-36d83254-ea38-4e76-a948-e759d6cbf39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179914771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.3179914771
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.2765417729
Short name T958
Test name
Test status
Simulation time 4877925952 ps
CPU time 4 seconds
Started Apr 18 01:53:20 PM PDT 24
Finished Apr 18 01:53:24 PM PDT 24
Peak memory 198780 kb
Host smart-b6c8532f-8f71-4c50-830d-67b539f43845
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2765417729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.2765417729
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.2677792249
Short name T761
Test name
Test status
Simulation time 102373940235 ps
CPU time 37.29 seconds
Started Apr 18 01:53:20 PM PDT 24
Finished Apr 18 01:53:58 PM PDT 24
Peak memory 200748 kb
Host smart-63ac76cf-8127-48ff-8683-4230f164d7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677792249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.2677792249
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.3277678625
Short name T738
Test name
Test status
Simulation time 3853151367 ps
CPU time 6.17 seconds
Started Apr 18 01:53:25 PM PDT 24
Finished Apr 18 01:53:32 PM PDT 24
Peak memory 196908 kb
Host smart-09096f53-339d-4c0c-a328-e22c73065555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277678625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.3277678625
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.2457641184
Short name T363
Test name
Test status
Simulation time 547186867 ps
CPU time 2.66 seconds
Started Apr 18 01:53:16 PM PDT 24
Finished Apr 18 01:53:20 PM PDT 24
Peak memory 199140 kb
Host smart-2e2964bd-07ce-4e9a-a4db-d2d8859dd3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457641184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.2457641184
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.2614408404
Short name T43
Test name
Test status
Simulation time 307361653148 ps
CPU time 275.17 seconds
Started Apr 18 01:53:25 PM PDT 24
Finished Apr 18 01:58:01 PM PDT 24
Peak memory 217552 kb
Host smart-962e0a95-a98f-435c-86dc-518613cf7466
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614408404 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.2614408404
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.3639632516
Short name T1139
Test name
Test status
Simulation time 8302963749 ps
CPU time 9.74 seconds
Started Apr 18 01:53:25 PM PDT 24
Finished Apr 18 01:53:35 PM PDT 24
Peak memory 200808 kb
Host smart-a0069a19-242b-40c3-ab68-281fcc16e280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639632516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.3639632516
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.1670528883
Short name T788
Test name
Test status
Simulation time 65821548273 ps
CPU time 37.3 seconds
Started Apr 18 01:53:15 PM PDT 24
Finished Apr 18 01:53:53 PM PDT 24
Peak memory 200816 kb
Host smart-7e4fe042-d6c5-4a00-95a6-82267e03f8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670528883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.1670528883
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.1997433003
Short name T20
Test name
Test status
Simulation time 28261324 ps
CPU time 0.57 seconds
Started Apr 18 01:53:27 PM PDT 24
Finished Apr 18 01:53:28 PM PDT 24
Peak memory 196172 kb
Host smart-c1f85ed8-dfb7-4cf1-b799-c51835ebcdc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997433003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.1997433003
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.2880819078
Short name T423
Test name
Test status
Simulation time 57853262687 ps
CPU time 52.65 seconds
Started Apr 18 01:53:27 PM PDT 24
Finished Apr 18 01:54:20 PM PDT 24
Peak memory 200668 kb
Host smart-06a86a3d-08a1-4345-8bbe-ff620bcd2aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880819078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.2880819078
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.280100925
Short name T1145
Test name
Test status
Simulation time 7924907706 ps
CPU time 12.8 seconds
Started Apr 18 01:53:30 PM PDT 24
Finished Apr 18 01:53:43 PM PDT 24
Peak memory 200908 kb
Host smart-92d90d1b-ce4f-48c7-880a-999b45b9d9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280100925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.280100925
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.4025799579
Short name T540
Test name
Test status
Simulation time 107177480123 ps
CPU time 92.7 seconds
Started Apr 18 01:53:28 PM PDT 24
Finished Apr 18 01:55:01 PM PDT 24
Peak memory 200916 kb
Host smart-62896190-de42-4561-b992-936d0af2bb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025799579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.4025799579
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.2307017811
Short name T1117
Test name
Test status
Simulation time 73791471505 ps
CPU time 115.25 seconds
Started Apr 18 01:53:27 PM PDT 24
Finished Apr 18 01:55:23 PM PDT 24
Peak memory 200196 kb
Host smart-e4b684af-c1da-4133-b18a-2852d49a3bc6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307017811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.2307017811
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.2065738317
Short name T337
Test name
Test status
Simulation time 72757671188 ps
CPU time 461.54 seconds
Started Apr 18 01:53:26 PM PDT 24
Finished Apr 18 02:01:08 PM PDT 24
Peak memory 200840 kb
Host smart-1c16ff7a-8be6-44c0-b91f-1b1df51681f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2065738317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.2065738317
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.3661840018
Short name T717
Test name
Test status
Simulation time 799071758 ps
CPU time 2.21 seconds
Started Apr 18 01:53:28 PM PDT 24
Finished Apr 18 01:53:31 PM PDT 24
Peak memory 198236 kb
Host smart-6b2748e5-7e62-49c5-b1f7-804b462e4bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661840018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.3661840018
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.1496571582
Short name T559
Test name
Test status
Simulation time 219441510719 ps
CPU time 37.65 seconds
Started Apr 18 01:53:29 PM PDT 24
Finished Apr 18 01:54:07 PM PDT 24
Peak memory 199768 kb
Host smart-8301d552-d0e6-41af-9e65-71c45768cfef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496571582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.1496571582
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.1099656457
Short name T764
Test name
Test status
Simulation time 15705569480 ps
CPU time 164.52 seconds
Started Apr 18 01:53:29 PM PDT 24
Finished Apr 18 01:56:14 PM PDT 24
Peak memory 200832 kb
Host smart-e57002c8-4968-4c11-9292-f8d5a110e192
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1099656457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.1099656457
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.1449687622
Short name T469
Test name
Test status
Simulation time 5694630843 ps
CPU time 12.21 seconds
Started Apr 18 01:53:32 PM PDT 24
Finished Apr 18 01:53:44 PM PDT 24
Peak memory 199720 kb
Host smart-47402749-88ad-4a0a-8b76-1381a4849c0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1449687622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.1449687622
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.1508772936
Short name T802
Test name
Test status
Simulation time 180816226463 ps
CPU time 57.77 seconds
Started Apr 18 01:53:26 PM PDT 24
Finished Apr 18 01:54:25 PM PDT 24
Peak memory 200576 kb
Host smart-a0803f08-af93-4b0a-b6ca-221f475d64dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508772936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.1508772936
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.200058082
Short name T440
Test name
Test status
Simulation time 5289339073 ps
CPU time 4.23 seconds
Started Apr 18 01:53:28 PM PDT 24
Finished Apr 18 01:53:33 PM PDT 24
Peak memory 196880 kb
Host smart-0e1df115-9b8a-415c-a1f4-a301037059d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200058082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.200058082
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.3901130648
Short name T580
Test name
Test status
Simulation time 6071247384 ps
CPU time 10.74 seconds
Started Apr 18 01:53:26 PM PDT 24
Finished Apr 18 01:53:37 PM PDT 24
Peak memory 200816 kb
Host smart-be6d56d1-6793-496b-ab1a-ce9420337293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901130648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.3901130648
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.3068089775
Short name T246
Test name
Test status
Simulation time 259037014985 ps
CPU time 856.02 seconds
Started Apr 18 01:53:25 PM PDT 24
Finished Apr 18 02:07:41 PM PDT 24
Peak memory 225724 kb
Host smart-cb8b4e26-e428-4a98-ba90-f0d466be8984
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068089775 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.3068089775
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.2664610479
Short name T380
Test name
Test status
Simulation time 4471393427 ps
CPU time 2.02 seconds
Started Apr 18 01:53:24 PM PDT 24
Finished Apr 18 01:53:27 PM PDT 24
Peak memory 200436 kb
Host smart-810eb271-f07c-479c-b097-2d429750ad81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664610479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.2664610479
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.1490919380
Short name T1111
Test name
Test status
Simulation time 37751350386 ps
CPU time 62.35 seconds
Started Apr 18 01:53:24 PM PDT 24
Finished Apr 18 01:54:27 PM PDT 24
Peak memory 200876 kb
Host smart-ae22162a-7b38-46ab-9be9-bc8ae73cc459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490919380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.1490919380
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.3730389005
Short name T661
Test name
Test status
Simulation time 31840742 ps
CPU time 0.55 seconds
Started Apr 18 01:53:32 PM PDT 24
Finished Apr 18 01:53:33 PM PDT 24
Peak memory 195608 kb
Host smart-b9c3ecd1-dbe1-4e11-8e15-d91e2cb31558
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730389005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.3730389005
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.2869228044
Short name T772
Test name
Test status
Simulation time 39708233483 ps
CPU time 62.11 seconds
Started Apr 18 01:53:26 PM PDT 24
Finished Apr 18 01:54:29 PM PDT 24
Peak memory 200936 kb
Host smart-4d854abc-8834-4450-9600-18f25b0b9282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869228044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.2869228044
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.931405157
Short name T550
Test name
Test status
Simulation time 35375770048 ps
CPU time 56.19 seconds
Started Apr 18 01:53:25 PM PDT 24
Finished Apr 18 01:54:21 PM PDT 24
Peak memory 200872 kb
Host smart-69144cb0-57b3-44c1-8d96-763df93fcc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931405157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.931405157
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.2900107392
Short name T1105
Test name
Test status
Simulation time 44822403194 ps
CPU time 22.15 seconds
Started Apr 18 01:53:26 PM PDT 24
Finished Apr 18 01:53:49 PM PDT 24
Peak memory 200740 kb
Host smart-274bb3ad-c768-4d5d-af6f-a40768acb25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900107392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.2900107392
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.4227716753
Short name T536
Test name
Test status
Simulation time 238024262923 ps
CPU time 164.21 seconds
Started Apr 18 01:53:26 PM PDT 24
Finished Apr 18 01:56:11 PM PDT 24
Peak memory 200872 kb
Host smart-30336a66-9791-49e9-ae0d-d6e93dc85549
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227716753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.4227716753
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.399132396
Short name T773
Test name
Test status
Simulation time 102332929130 ps
CPU time 811.62 seconds
Started Apr 18 01:53:36 PM PDT 24
Finished Apr 18 02:07:08 PM PDT 24
Peak memory 200828 kb
Host smart-1d9906a7-1e75-443c-8a9d-d6e4397cc42b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=399132396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.399132396
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.1113376464
Short name T1007
Test name
Test status
Simulation time 8671694461 ps
CPU time 7.63 seconds
Started Apr 18 01:53:31 PM PDT 24
Finished Apr 18 01:53:39 PM PDT 24
Peak memory 200776 kb
Host smart-b5ba1abc-e1a7-4962-8221-84f1e09f590e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113376464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.1113376464
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.4130000403
Short name T803
Test name
Test status
Simulation time 75799917853 ps
CPU time 63.33 seconds
Started Apr 18 01:53:35 PM PDT 24
Finished Apr 18 01:54:39 PM PDT 24
Peak memory 200812 kb
Host smart-bec1b7a8-027f-4899-b781-7a2db814d13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130000403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.4130000403
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.1145486596
Short name T702
Test name
Test status
Simulation time 18830157139 ps
CPU time 70.98 seconds
Started Apr 18 01:53:31 PM PDT 24
Finished Apr 18 01:54:42 PM PDT 24
Peak memory 200924 kb
Host smart-212ba00f-b95a-4958-ac0e-13e7f5b9dc20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1145486596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.1145486596
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.239814068
Short name T567
Test name
Test status
Simulation time 3882697046 ps
CPU time 34.34 seconds
Started Apr 18 01:53:26 PM PDT 24
Finished Apr 18 01:54:01 PM PDT 24
Peak memory 199244 kb
Host smart-a980b2c9-6755-4ceb-a293-49c1581e1bef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=239814068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.239814068
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.3492638045
Short name T153
Test name
Test status
Simulation time 11096343730 ps
CPU time 23.29 seconds
Started Apr 18 01:53:36 PM PDT 24
Finished Apr 18 01:53:59 PM PDT 24
Peak memory 200760 kb
Host smart-e4f18af0-3c36-4330-9a83-9273073b5a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492638045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.3492638045
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.2513826358
Short name T437
Test name
Test status
Simulation time 3259991154 ps
CPU time 5.21 seconds
Started Apr 18 01:53:32 PM PDT 24
Finished Apr 18 01:53:38 PM PDT 24
Peak memory 196724 kb
Host smart-f631c02e-5230-438c-8264-b8d8a511a7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513826358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.2513826358
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.589916907
Short name T647
Test name
Test status
Simulation time 5837645661 ps
CPU time 10.26 seconds
Started Apr 18 01:54:01 PM PDT 24
Finished Apr 18 01:54:11 PM PDT 24
Peak memory 200132 kb
Host smart-e9b151a6-6dec-429b-8b9e-c6559674b2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589916907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.589916907
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.1635287901
Short name T674
Test name
Test status
Simulation time 145232848865 ps
CPU time 266.51 seconds
Started Apr 18 01:53:32 PM PDT 24
Finished Apr 18 01:57:59 PM PDT 24
Peak memory 216556 kb
Host smart-1086ccfa-c174-412a-a080-24eb3e140524
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635287901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.1635287901
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.454904843
Short name T941
Test name
Test status
Simulation time 65952477512 ps
CPU time 1202.18 seconds
Started Apr 18 01:53:32 PM PDT 24
Finished Apr 18 02:13:34 PM PDT 24
Peak memory 225736 kb
Host smart-0deded8d-4dc2-4cdc-8a3b-ce531091c4cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454904843 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.454904843
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.2369301503
Short name T405
Test name
Test status
Simulation time 2419621193 ps
CPU time 2.49 seconds
Started Apr 18 01:53:36 PM PDT 24
Finished Apr 18 01:53:39 PM PDT 24
Peak memory 199424 kb
Host smart-9898f983-4d6d-43da-878b-4bb448b1d5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369301503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.2369301503
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.2050766921
Short name T1068
Test name
Test status
Simulation time 41486001116 ps
CPU time 19.23 seconds
Started Apr 18 01:53:26 PM PDT 24
Finished Apr 18 01:53:46 PM PDT 24
Peak memory 200892 kb
Host smart-2b5bccac-e780-4299-acc7-0d96b3249fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050766921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.2050766921
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.2395870642
Short name T523
Test name
Test status
Simulation time 45748477 ps
CPU time 0.54 seconds
Started Apr 18 01:53:30 PM PDT 24
Finished Apr 18 01:53:31 PM PDT 24
Peak memory 196152 kb
Host smart-78cd7d91-e1d0-427e-b30d-00345adc5a8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395870642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.2395870642
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.4143489814
Short name T371
Test name
Test status
Simulation time 89661546618 ps
CPU time 229.43 seconds
Started Apr 18 01:53:30 PM PDT 24
Finished Apr 18 01:57:20 PM PDT 24
Peak memory 200832 kb
Host smart-4bbdf1d5-f744-4228-a471-5a6fec9fb261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143489814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.4143489814
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.2351764094
Short name T1171
Test name
Test status
Simulation time 164624410383 ps
CPU time 56.1 seconds
Started Apr 18 01:53:30 PM PDT 24
Finished Apr 18 01:54:26 PM PDT 24
Peak memory 200424 kb
Host smart-0f53eabf-b424-4d2f-8fb5-582246240871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351764094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.2351764094
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.1329470991
Short name T586
Test name
Test status
Simulation time 149810223827 ps
CPU time 71.26 seconds
Started Apr 18 01:53:31 PM PDT 24
Finished Apr 18 01:54:43 PM PDT 24
Peak memory 200920 kb
Host smart-9f2df495-aaa0-4346-83a5-c1e7248d2f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329470991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.1329470991
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.3905191628
Short name T690
Test name
Test status
Simulation time 38432729294 ps
CPU time 18.17 seconds
Started Apr 18 01:53:35 PM PDT 24
Finished Apr 18 01:53:54 PM PDT 24
Peak memory 200840 kb
Host smart-e0f9fe5f-6f51-4fa5-b387-6211ec7a1479
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905191628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.3905191628
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.539065895
Short name T1158
Test name
Test status
Simulation time 76928323920 ps
CPU time 637.09 seconds
Started Apr 18 01:53:32 PM PDT 24
Finished Apr 18 02:04:10 PM PDT 24
Peak memory 200880 kb
Host smart-789f33df-7fad-47a7-8007-71df186a4491
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=539065895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.539065895
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.4180830318
Short name T504
Test name
Test status
Simulation time 1201222955 ps
CPU time 1.13 seconds
Started Apr 18 01:53:29 PM PDT 24
Finished Apr 18 01:53:31 PM PDT 24
Peak memory 196860 kb
Host smart-e4b40e42-6cc9-48f6-af58-f1abd447e28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180830318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.4180830318
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.3321991106
Short name T510
Test name
Test status
Simulation time 46991150989 ps
CPU time 79.09 seconds
Started Apr 18 01:53:36 PM PDT 24
Finished Apr 18 01:54:55 PM PDT 24
Peak memory 200532 kb
Host smart-07c0dfc4-73b6-4034-a15c-8b55ee336e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321991106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.3321991106
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.2887006767
Short name T259
Test name
Test status
Simulation time 17677254572 ps
CPU time 615.58 seconds
Started Apr 18 01:53:31 PM PDT 24
Finished Apr 18 02:03:47 PM PDT 24
Peak memory 200812 kb
Host smart-1e2d09a7-5f33-44b4-a486-a7ac053482ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2887006767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.2887006767
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.1702678894
Short name T506
Test name
Test status
Simulation time 4131610548 ps
CPU time 8.66 seconds
Started Apr 18 01:53:33 PM PDT 24
Finished Apr 18 01:53:42 PM PDT 24
Peak memory 199944 kb
Host smart-847c6fa8-7ad6-4adf-8d0a-c039088f5ee5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1702678894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.1702678894
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.1846038490
Short name T826
Test name
Test status
Simulation time 7626302509 ps
CPU time 27.47 seconds
Started Apr 18 01:53:39 PM PDT 24
Finished Apr 18 01:54:07 PM PDT 24
Peak memory 200888 kb
Host smart-5828c5ed-2c07-4bcb-a41a-0bb175602482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846038490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.1846038490
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.102506485
Short name T1042
Test name
Test status
Simulation time 43097057646 ps
CPU time 9.11 seconds
Started Apr 18 01:53:41 PM PDT 24
Finished Apr 18 01:53:50 PM PDT 24
Peak memory 196668 kb
Host smart-b03d2b67-4eaf-44ae-8d32-9c2d951ca727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102506485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.102506485
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.2774566862
Short name T485
Test name
Test status
Simulation time 6275799340 ps
CPU time 9.41 seconds
Started Apr 18 01:53:32 PM PDT 24
Finished Apr 18 01:53:41 PM PDT 24
Peak memory 200764 kb
Host smart-d432fd0a-0de2-4a8b-acdc-c037a75dbba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774566862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.2774566862
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.2371307869
Short name T496
Test name
Test status
Simulation time 177959706323 ps
CPU time 277.9 seconds
Started Apr 18 01:53:32 PM PDT 24
Finished Apr 18 01:58:11 PM PDT 24
Peak memory 200840 kb
Host smart-f9b7e084-730a-4286-b1d8-1f521b6e6c5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371307869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.2371307869
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.900453091
Short name T27
Test name
Test status
Simulation time 69642939257 ps
CPU time 308.41 seconds
Started Apr 18 01:53:34 PM PDT 24
Finished Apr 18 01:58:43 PM PDT 24
Peak memory 217312 kb
Host smart-54798624-d580-49c2-98b6-cd0dd42c5fb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900453091 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.900453091
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.3676049095
Short name T591
Test name
Test status
Simulation time 4323566220 ps
CPU time 1.77 seconds
Started Apr 18 01:53:34 PM PDT 24
Finished Apr 18 01:53:36 PM PDT 24
Peak memory 200776 kb
Host smart-2e65a782-b6a8-4fb5-a697-0453129375cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676049095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.3676049095
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.560702525
Short name T525
Test name
Test status
Simulation time 38390892138 ps
CPU time 68.42 seconds
Started Apr 18 01:53:33 PM PDT 24
Finished Apr 18 01:54:42 PM PDT 24
Peak memory 200860 kb
Host smart-c001321d-4d27-4099-abb2-e04fa8566d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560702525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.560702525
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.762543967
Short name T815
Test name
Test status
Simulation time 14106122 ps
CPU time 0.58 seconds
Started Apr 18 01:53:36 PM PDT 24
Finished Apr 18 01:53:37 PM PDT 24
Peak memory 196216 kb
Host smart-a71813ce-004d-472d-a3b1-632a8f534566
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762543967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.762543967
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.2631912256
Short name T285
Test name
Test status
Simulation time 180441628344 ps
CPU time 293.14 seconds
Started Apr 18 01:53:29 PM PDT 24
Finished Apr 18 01:58:22 PM PDT 24
Peak memory 200888 kb
Host smart-16411efb-ad90-4c46-9cc6-5fcdca4ee981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631912256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2631912256
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.1449520238
Short name T899
Test name
Test status
Simulation time 52511074955 ps
CPU time 23.88 seconds
Started Apr 18 01:53:34 PM PDT 24
Finished Apr 18 01:53:58 PM PDT 24
Peak memory 200836 kb
Host smart-9bd15069-2265-4c35-a2b8-2257d3536303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449520238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1449520238
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.3925896282
Short name T196
Test name
Test status
Simulation time 118266753501 ps
CPU time 221.57 seconds
Started Apr 18 01:53:36 PM PDT 24
Finished Apr 18 01:57:17 PM PDT 24
Peak memory 200824 kb
Host smart-5078add0-ff96-444e-84ce-948604046749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925896282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.3925896282
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.927449553
Short name T874
Test name
Test status
Simulation time 84806390022 ps
CPU time 194.46 seconds
Started Apr 18 01:53:34 PM PDT 24
Finished Apr 18 01:56:49 PM PDT 24
Peak memory 200828 kb
Host smart-93e52781-7366-40c7-97de-b07219d0789f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927449553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.927449553
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.2608570611
Short name T916
Test name
Test status
Simulation time 110126001040 ps
CPU time 423.73 seconds
Started Apr 18 01:53:39 PM PDT 24
Finished Apr 18 02:00:43 PM PDT 24
Peak memory 200752 kb
Host smart-bab2d3b8-fa81-4ebe-a835-9982ddcb7762
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2608570611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.2608570611
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.952010280
Short name T464
Test name
Test status
Simulation time 2324022329 ps
CPU time 1.85 seconds
Started Apr 18 01:53:38 PM PDT 24
Finished Apr 18 01:53:40 PM PDT 24
Peak memory 198352 kb
Host smart-4effa18a-d0c7-4b7d-949c-3af3f75f2533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952010280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.952010280
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.1507009877
Short name T1102
Test name
Test status
Simulation time 24706529656 ps
CPU time 31.61 seconds
Started Apr 18 01:53:33 PM PDT 24
Finished Apr 18 01:54:05 PM PDT 24
Peak memory 199568 kb
Host smart-77eb8475-1950-43ed-b6d3-b7303314386b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507009877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.1507009877
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.1843441993
Short name T310
Test name
Test status
Simulation time 8589682704 ps
CPU time 481.08 seconds
Started Apr 18 01:53:36 PM PDT 24
Finished Apr 18 02:01:38 PM PDT 24
Peak memory 200840 kb
Host smart-e4f287cb-45c1-42ac-952a-edc2a314df21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1843441993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.1843441993
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.1101364063
Short name T338
Test name
Test status
Simulation time 5805622273 ps
CPU time 51.19 seconds
Started Apr 18 01:53:33 PM PDT 24
Finished Apr 18 01:54:25 PM PDT 24
Peak memory 200104 kb
Host smart-65d20012-41ea-4139-a35b-dcbf628b9658
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1101364063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.1101364063
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.2966358872
Short name T254
Test name
Test status
Simulation time 100735555259 ps
CPU time 75.71 seconds
Started Apr 18 01:53:41 PM PDT 24
Finished Apr 18 01:54:57 PM PDT 24
Peak memory 200856 kb
Host smart-81e8cc53-4caf-4d64-8062-ae319e42e4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966358872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.2966358872
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.2484821840
Short name T478
Test name
Test status
Simulation time 41104745733 ps
CPU time 70.5 seconds
Started Apr 18 01:53:40 PM PDT 24
Finished Apr 18 01:54:51 PM PDT 24
Peak memory 196860 kb
Host smart-5e4895a4-b016-4e7f-923d-da4cf8b67423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484821840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.2484821840
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.2223770190
Short name T1175
Test name
Test status
Simulation time 287334377 ps
CPU time 1.06 seconds
Started Apr 18 01:53:31 PM PDT 24
Finished Apr 18 01:53:32 PM PDT 24
Peak memory 200632 kb
Host smart-4481c1b2-dff1-423b-97a2-0584ee3cde0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223770190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.2223770190
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.136617768
Short name T605
Test name
Test status
Simulation time 98236119014 ps
CPU time 326.75 seconds
Started Apr 18 01:53:38 PM PDT 24
Finished Apr 18 01:59:05 PM PDT 24
Peak memory 200792 kb
Host smart-c3f956cc-4d78-4be9-8930-3167ae2a48d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136617768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.136617768
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.1111184500
Short name T609
Test name
Test status
Simulation time 112211817217 ps
CPU time 685.38 seconds
Started Apr 18 01:53:36 PM PDT 24
Finished Apr 18 02:05:02 PM PDT 24
Peak memory 225772 kb
Host smart-9cfc94b5-6359-4976-aa8b-88979ddf56da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111184500 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.1111184500
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.1528288472
Short name T748
Test name
Test status
Simulation time 6072341967 ps
CPU time 19.3 seconds
Started Apr 18 01:53:37 PM PDT 24
Finished Apr 18 01:53:57 PM PDT 24
Peak memory 200840 kb
Host smart-b312056c-ec5d-4331-8564-352194e31c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528288472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.1528288472
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.2315423925
Short name T969
Test name
Test status
Simulation time 114513295254 ps
CPU time 10.44 seconds
Started Apr 18 01:53:30 PM PDT 24
Finished Apr 18 01:53:41 PM PDT 24
Peak memory 199416 kb
Host smart-eaf42a62-86ce-4c6b-ad07-cdee16a4ef4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315423925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.2315423925
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.2904315530
Short name T392
Test name
Test status
Simulation time 12992780 ps
CPU time 0.56 seconds
Started Apr 18 01:53:42 PM PDT 24
Finished Apr 18 01:53:43 PM PDT 24
Peak memory 196208 kb
Host smart-bd0cb274-1257-49b2-8388-2ecff67bb408
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904315530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.2904315530
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.156557379
Short name T377
Test name
Test status
Simulation time 44227800228 ps
CPU time 67.25 seconds
Started Apr 18 01:53:37 PM PDT 24
Finished Apr 18 01:54:45 PM PDT 24
Peak memory 200900 kb
Host smart-7c9be3e7-1383-4a45-907e-f48bf3417470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156557379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.156557379
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.1355323096
Short name T373
Test name
Test status
Simulation time 29797172571 ps
CPU time 9.54 seconds
Started Apr 18 01:53:37 PM PDT 24
Finished Apr 18 01:53:47 PM PDT 24
Peak memory 200488 kb
Host smart-93785b11-a1e1-448d-9e66-5cb1586ea624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355323096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.1355323096
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.1101758505
Short name T422
Test name
Test status
Simulation time 83825917080 ps
CPU time 59.57 seconds
Started Apr 18 01:53:38 PM PDT 24
Finished Apr 18 01:54:38 PM PDT 24
Peak memory 200908 kb
Host smart-dd10e39f-ac0d-471b-a39c-6a1f2f7a892f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101758505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.1101758505
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.3818511715
Short name T805
Test name
Test status
Simulation time 15814258538 ps
CPU time 7.93 seconds
Started Apr 18 01:53:38 PM PDT 24
Finished Apr 18 01:53:47 PM PDT 24
Peak memory 200004 kb
Host smart-926ee51f-4785-4cb4-928f-9a9c6cd027b7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818511715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.3818511715
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.835286792
Short name T693
Test name
Test status
Simulation time 95718027141 ps
CPU time 230.27 seconds
Started Apr 18 01:53:45 PM PDT 24
Finished Apr 18 01:57:35 PM PDT 24
Peak memory 200884 kb
Host smart-c66fad5a-30da-49bd-adf1-386018a67196
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=835286792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.835286792
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.2486159584
Short name T318
Test name
Test status
Simulation time 8338337380 ps
CPU time 10.26 seconds
Started Apr 18 01:53:41 PM PDT 24
Finished Apr 18 01:53:52 PM PDT 24
Peak memory 199852 kb
Host smart-b3758028-563d-4a69-9297-e59e44cad7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486159584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.2486159584
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.1201715757
Short name T870
Test name
Test status
Simulation time 49465454370 ps
CPU time 14.5 seconds
Started Apr 18 01:53:38 PM PDT 24
Finished Apr 18 01:53:53 PM PDT 24
Peak memory 195800 kb
Host smart-6cb46ed0-0a1f-476b-bfd5-d4ce328350ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201715757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.1201715757
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.1893368217
Short name T513
Test name
Test status
Simulation time 26628833893 ps
CPU time 382.23 seconds
Started Apr 18 01:53:44 PM PDT 24
Finished Apr 18 02:00:07 PM PDT 24
Peak memory 200812 kb
Host smart-70e33184-6505-458c-9440-1e71c465b095
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1893368217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.1893368217
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.475527538
Short name T697
Test name
Test status
Simulation time 5097586380 ps
CPU time 21.55 seconds
Started Apr 18 01:53:35 PM PDT 24
Finished Apr 18 01:53:57 PM PDT 24
Peak memory 199832 kb
Host smart-8fa54c4c-caf2-42a8-a1d1-c734aa60d783
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=475527538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.475527538
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.2101830417
Short name T1076
Test name
Test status
Simulation time 58219476006 ps
CPU time 71.74 seconds
Started Apr 18 01:53:42 PM PDT 24
Finished Apr 18 01:54:54 PM PDT 24
Peak memory 200876 kb
Host smart-46d00971-3a24-47a4-abbb-fb385cf60c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101830417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.2101830417
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.299355339
Short name T313
Test name
Test status
Simulation time 1588584134 ps
CPU time 1.36 seconds
Started Apr 18 01:53:37 PM PDT 24
Finished Apr 18 01:53:39 PM PDT 24
Peak memory 196304 kb
Host smart-a930163c-20dc-475c-accc-a34798ca4eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299355339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.299355339
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.1403797299
Short name T278
Test name
Test status
Simulation time 711680400 ps
CPU time 2.59 seconds
Started Apr 18 01:53:39 PM PDT 24
Finished Apr 18 01:53:42 PM PDT 24
Peak memory 200520 kb
Host smart-e1945c33-3bd7-4249-96e8-6dee60a0d715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403797299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.1403797299
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.1082248757
Short name T944
Test name
Test status
Simulation time 160868637869 ps
CPU time 186.99 seconds
Started Apr 18 01:53:45 PM PDT 24
Finished Apr 18 01:56:53 PM PDT 24
Peak memory 209156 kb
Host smart-b87aff47-fa0c-45e4-8435-bb7bf4a792c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082248757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.1082248757
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.790135976
Short name T97
Test name
Test status
Simulation time 163917653291 ps
CPU time 633.61 seconds
Started Apr 18 01:53:42 PM PDT 24
Finished Apr 18 02:04:17 PM PDT 24
Peak memory 217568 kb
Host smart-0fda3e43-6189-47f3-a8d1-a481c43c7091
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790135976 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.790135976
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.3157578414
Short name T1131
Test name
Test status
Simulation time 2194605386 ps
CPU time 1.34 seconds
Started Apr 18 01:53:42 PM PDT 24
Finished Apr 18 01:53:44 PM PDT 24
Peak memory 199524 kb
Host smart-eb2080c1-737f-4e94-9f25-057d577cd84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157578414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.3157578414
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.812507709
Short name T1046
Test name
Test status
Simulation time 46501994849 ps
CPU time 70.01 seconds
Started Apr 18 01:53:37 PM PDT 24
Finished Apr 18 01:54:48 PM PDT 24
Peak memory 200828 kb
Host smart-c9d3d222-b1db-4d7d-a8f9-cae3b5218f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812507709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.812507709
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.4278823948
Short name T387
Test name
Test status
Simulation time 41021773 ps
CPU time 0.55 seconds
Started Apr 18 01:51:21 PM PDT 24
Finished Apr 18 01:51:22 PM PDT 24
Peak memory 195176 kb
Host smart-2d3ec969-c8bd-43fe-a8f6-cece0af87257
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278823948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.4278823948
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1335488527
Short name T817
Test name
Test status
Simulation time 95911488207 ps
CPU time 40.45 seconds
Started Apr 18 01:51:25 PM PDT 24
Finished Apr 18 01:52:07 PM PDT 24
Peak memory 200896 kb
Host smart-d110c8fa-7d16-4a71-9e04-3a02379b5dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335488527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1335488527
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.3476987132
Short name T935
Test name
Test status
Simulation time 39964630574 ps
CPU time 34.4 seconds
Started Apr 18 01:51:22 PM PDT 24
Finished Apr 18 01:51:57 PM PDT 24
Peak memory 200776 kb
Host smart-3a45b6b6-b20f-4343-9e5f-bc724a7216de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476987132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.3476987132
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.4135000783
Short name T878
Test name
Test status
Simulation time 122892499629 ps
CPU time 88.04 seconds
Started Apr 18 01:51:22 PM PDT 24
Finished Apr 18 01:52:51 PM PDT 24
Peak memory 200752 kb
Host smart-5a404d1c-242b-45e0-a560-4efb9dbea0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135000783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.4135000783
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.3753232342
Short name T303
Test name
Test status
Simulation time 170415226357 ps
CPU time 192.66 seconds
Started Apr 18 01:51:24 PM PDT 24
Finished Apr 18 01:54:37 PM PDT 24
Peak memory 200844 kb
Host smart-a9529d88-8b9c-4ec2-a4fe-f43557905a7e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753232342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.3753232342
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.1114292393
Short name T964
Test name
Test status
Simulation time 128829105169 ps
CPU time 250.03 seconds
Started Apr 18 01:51:30 PM PDT 24
Finished Apr 18 01:55:41 PM PDT 24
Peak memory 200788 kb
Host smart-69ee6cce-b0f5-4b9e-a5cd-e162d438c3bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1114292393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.1114292393
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.4205951989
Short name T1090
Test name
Test status
Simulation time 7438966945 ps
CPU time 18.34 seconds
Started Apr 18 01:51:28 PM PDT 24
Finished Apr 18 01:51:52 PM PDT 24
Peak memory 199672 kb
Host smart-b4c427a7-ee6f-4737-9676-cd05e645846e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205951989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.4205951989
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.603072314
Short name T402
Test name
Test status
Simulation time 18094112512 ps
CPU time 32.34 seconds
Started Apr 18 01:51:32 PM PDT 24
Finished Apr 18 01:52:05 PM PDT 24
Peak memory 200992 kb
Host smart-05bcb85f-3dcb-4dd6-b515-0d53f6df7025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603072314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.603072314
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.435421987
Short name T1033
Test name
Test status
Simulation time 14061465081 ps
CPU time 747.56 seconds
Started Apr 18 01:51:33 PM PDT 24
Finished Apr 18 02:04:02 PM PDT 24
Peak memory 200788 kb
Host smart-21388312-5694-4dac-810e-8d65808d1aa8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=435421987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.435421987
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.4079288989
Short name T634
Test name
Test status
Simulation time 7424126836 ps
CPU time 17.08 seconds
Started Apr 18 01:51:27 PM PDT 24
Finished Apr 18 01:51:45 PM PDT 24
Peak memory 200064 kb
Host smart-c3bd7cef-6f45-4ad3-843b-e0701aa7cb48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4079288989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.4079288989
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.1609406303
Short name T300
Test name
Test status
Simulation time 28182426076 ps
CPU time 11.52 seconds
Started Apr 18 01:51:25 PM PDT 24
Finished Apr 18 01:51:37 PM PDT 24
Peak memory 199064 kb
Host smart-ea371eb0-7eea-463c-9e06-dbf0476c5471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609406303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.1609406303
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.1712926149
Short name T684
Test name
Test status
Simulation time 672129652 ps
CPU time 1.77 seconds
Started Apr 18 01:51:30 PM PDT 24
Finished Apr 18 01:51:33 PM PDT 24
Peak memory 196584 kb
Host smart-6a156029-239b-49fa-aea1-4d5bc407e6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712926149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1712926149
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.4195589107
Short name T294
Test name
Test status
Simulation time 6209507709 ps
CPU time 9.03 seconds
Started Apr 18 01:51:27 PM PDT 24
Finished Apr 18 01:51:37 PM PDT 24
Peak memory 200708 kb
Host smart-a18a0d88-457d-419a-b076-dd4be2c454c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195589107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.4195589107
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.3064498782
Short name T1119
Test name
Test status
Simulation time 16004047819 ps
CPU time 420.94 seconds
Started Apr 18 01:51:25 PM PDT 24
Finished Apr 18 01:58:26 PM PDT 24
Peak memory 216664 kb
Host smart-02c1113d-ddcc-47b3-94c3-221771054c6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064498782 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.3064498782
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.1367230546
Short name T372
Test name
Test status
Simulation time 1530150081 ps
CPU time 3.84 seconds
Started Apr 18 01:51:28 PM PDT 24
Finished Apr 18 01:51:32 PM PDT 24
Peak memory 199904 kb
Host smart-6dee834e-3230-46ac-9a05-5479e66fdc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367230546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1367230546
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.977831540
Short name T593
Test name
Test status
Simulation time 5232834602 ps
CPU time 6.78 seconds
Started Apr 18 01:51:27 PM PDT 24
Finished Apr 18 01:51:35 PM PDT 24
Peak memory 200876 kb
Host smart-c484cfbc-012c-47df-9e51-d4a79285b64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977831540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.977831540
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.837129924
Short name T1075
Test name
Test status
Simulation time 96814080326 ps
CPU time 221.6 seconds
Started Apr 18 01:53:44 PM PDT 24
Finished Apr 18 01:57:26 PM PDT 24
Peak memory 200212 kb
Host smart-f4a7b179-3854-41cf-86cb-25ea35927c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837129924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.837129924
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.3781075959
Short name T1056
Test name
Test status
Simulation time 660112319347 ps
CPU time 1509.56 seconds
Started Apr 18 01:53:43 PM PDT 24
Finished Apr 18 02:18:53 PM PDT 24
Peak memory 228536 kb
Host smart-fc69b230-9f04-4d87-9bea-9ed215bfc91a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781075959 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.3781075959
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.916047816
Short name T177
Test name
Test status
Simulation time 18391955046 ps
CPU time 25.59 seconds
Started Apr 18 01:53:41 PM PDT 24
Finished Apr 18 01:54:07 PM PDT 24
Peak memory 200576 kb
Host smart-e20e430f-66c3-4ff1-b73a-f262d8d1a12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916047816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.916047816
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.2046073196
Short name T893
Test name
Test status
Simulation time 20518263198 ps
CPU time 229.67 seconds
Started Apr 18 01:53:43 PM PDT 24
Finished Apr 18 01:57:33 PM PDT 24
Peak memory 216704 kb
Host smart-4c51309f-6509-4b45-a6af-4b2d9df3f516
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046073196 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.2046073196
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.3835847842
Short name T114
Test name
Test status
Simulation time 19449438780 ps
CPU time 31.22 seconds
Started Apr 18 01:53:48 PM PDT 24
Finished Apr 18 01:54:20 PM PDT 24
Peak memory 200896 kb
Host smart-44d082d8-9df3-4d68-8d79-8a1d50651d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835847842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.3835847842
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.4103154655
Short name T1001
Test name
Test status
Simulation time 92705353275 ps
CPU time 1432.51 seconds
Started Apr 18 01:53:46 PM PDT 24
Finished Apr 18 02:17:39 PM PDT 24
Peak memory 225712 kb
Host smart-4189da3d-5ab5-4014-abbf-962d32299e9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103154655 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.4103154655
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.3426842609
Short name T174
Test name
Test status
Simulation time 111977608558 ps
CPU time 162.85 seconds
Started Apr 18 01:53:44 PM PDT 24
Finished Apr 18 01:56:27 PM PDT 24
Peak memory 200844 kb
Host smart-cfcb5b3d-fe1a-4b32-8f82-48cb1dba106b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426842609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.3426842609
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.2761769699
Short name T638
Test name
Test status
Simulation time 20643302120 ps
CPU time 267.09 seconds
Started Apr 18 01:53:44 PM PDT 24
Finished Apr 18 01:58:11 PM PDT 24
Peak memory 216600 kb
Host smart-6f530b45-602b-4f4b-b135-a2f46464080d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761769699 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.2761769699
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.216561540
Short name T194
Test name
Test status
Simulation time 183786154127 ps
CPU time 414.16 seconds
Started Apr 18 01:53:44 PM PDT 24
Finished Apr 18 02:00:39 PM PDT 24
Peak memory 200804 kb
Host smart-4a45e21b-da1c-4156-9734-0e4670a7fd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216561540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.216561540
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.3172167283
Short name T315
Test name
Test status
Simulation time 97771858783 ps
CPU time 517.71 seconds
Started Apr 18 01:53:43 PM PDT 24
Finished Apr 18 02:02:21 PM PDT 24
Peak memory 217476 kb
Host smart-95d54852-0bb6-4151-aa3f-7977d769db97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172167283 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.3172167283
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.1388988968
Short name T1170
Test name
Test status
Simulation time 12141262248 ps
CPU time 10.8 seconds
Started Apr 18 01:53:42 PM PDT 24
Finished Apr 18 01:53:53 PM PDT 24
Peak memory 200904 kb
Host smart-d9bc5ef2-28ae-4b3b-a56b-a31193cdb79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388988968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.1388988968
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.4209235605
Short name T997
Test name
Test status
Simulation time 46078747604 ps
CPU time 254.21 seconds
Started Apr 18 01:53:44 PM PDT 24
Finished Apr 18 01:57:58 PM PDT 24
Peak memory 217560 kb
Host smart-f362a93b-e8b9-43a0-8ae0-f220151c32ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209235605 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.4209235605
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.3384327656
Short name T985
Test name
Test status
Simulation time 46990885541 ps
CPU time 331.24 seconds
Started Apr 18 01:53:44 PM PDT 24
Finished Apr 18 01:59:15 PM PDT 24
Peak memory 200872 kb
Host smart-80ea2d19-bc11-4605-8a34-6c1f4c4ce688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384327656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.3384327656
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.2179621597
Short name T250
Test name
Test status
Simulation time 129869766528 ps
CPU time 58.24 seconds
Started Apr 18 01:53:42 PM PDT 24
Finished Apr 18 01:54:41 PM PDT 24
Peak memory 200852 kb
Host smart-f18ce4bc-bd9f-47d8-b5ba-7381ae699e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179621597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.2179621597
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.1644251253
Short name T385
Test name
Test status
Simulation time 77092150368 ps
CPU time 634.35 seconds
Started Apr 18 01:53:42 PM PDT 24
Finished Apr 18 02:04:17 PM PDT 24
Peak memory 212140 kb
Host smart-01855fea-7b9d-43a0-a377-6574081673b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644251253 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.1644251253
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.3712027692
Short name T1072
Test name
Test status
Simulation time 88490404315 ps
CPU time 33.14 seconds
Started Apr 18 01:53:50 PM PDT 24
Finished Apr 18 01:54:24 PM PDT 24
Peak memory 200836 kb
Host smart-8eac215f-1ff6-409f-bc03-8bee02313896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712027692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.3712027692
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.208150580
Short name T127
Test name
Test status
Simulation time 75613706629 ps
CPU time 220.57 seconds
Started Apr 18 01:53:44 PM PDT 24
Finished Apr 18 01:57:25 PM PDT 24
Peak memory 209024 kb
Host smart-2119d481-4816-41d1-9482-a2955c5bd5ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208150580 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.208150580
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.2053324941
Short name T1045
Test name
Test status
Simulation time 14183455273 ps
CPU time 12.25 seconds
Started Apr 18 01:54:02 PM PDT 24
Finished Apr 18 01:54:15 PM PDT 24
Peak memory 200880 kb
Host smart-a8289f4d-1673-44a7-8724-f1d7a46f15bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053324941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.2053324941
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.3229811236
Short name T39
Test name
Test status
Simulation time 13514199769 ps
CPU time 118.05 seconds
Started Apr 18 01:53:50 PM PDT 24
Finished Apr 18 01:55:49 PM PDT 24
Peak memory 217368 kb
Host smart-52aab7fb-ef8c-47f9-a5ab-b9eca46fda4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229811236 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.3229811236
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.605905634
Short name T1159
Test name
Test status
Simulation time 13459636 ps
CPU time 0.57 seconds
Started Apr 18 01:51:27 PM PDT 24
Finished Apr 18 01:51:29 PM PDT 24
Peak memory 196224 kb
Host smart-43d1dee2-1c55-4a3d-ac1b-6b650a0efe64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605905634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.605905634
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.1126146572
Short name T716
Test name
Test status
Simulation time 29478090032 ps
CPU time 25.31 seconds
Started Apr 18 01:51:31 PM PDT 24
Finished Apr 18 01:51:57 PM PDT 24
Peak memory 200840 kb
Host smart-79bb1b26-8ce9-4df3-9e4a-d69f09240728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126146572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.1126146572
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.3223220076
Short name T719
Test name
Test status
Simulation time 126943727710 ps
CPU time 50.13 seconds
Started Apr 18 01:51:30 PM PDT 24
Finished Apr 18 01:52:20 PM PDT 24
Peak memory 200700 kb
Host smart-b3de3a16-0009-4e33-acbc-aa86a05f241f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223220076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.3223220076
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.3458928879
Short name T839
Test name
Test status
Simulation time 65110456229 ps
CPU time 29.81 seconds
Started Apr 18 01:51:28 PM PDT 24
Finished Apr 18 01:51:58 PM PDT 24
Peak memory 200788 kb
Host smart-11fa7dca-8050-4ad2-8653-3cb32dc52504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458928879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.3458928879
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.3565814070
Short name T646
Test name
Test status
Simulation time 40552772324 ps
CPU time 17.87 seconds
Started Apr 18 01:51:31 PM PDT 24
Finished Apr 18 01:51:49 PM PDT 24
Peak memory 200916 kb
Host smart-975ddc39-5440-4e2f-8431-7c2b121a090b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565814070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.3565814070
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.3807970206
Short name T355
Test name
Test status
Simulation time 94073200943 ps
CPU time 606.56 seconds
Started Apr 18 01:51:28 PM PDT 24
Finished Apr 18 02:01:36 PM PDT 24
Peak memory 200792 kb
Host smart-a1ba968e-6357-4ca0-bd7f-e78bfc62bf7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3807970206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.3807970206
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.3412436259
Short name T416
Test name
Test status
Simulation time 3668372543 ps
CPU time 2.87 seconds
Started Apr 18 01:51:44 PM PDT 24
Finished Apr 18 01:51:47 PM PDT 24
Peak memory 199308 kb
Host smart-37802d83-c20e-491f-9d69-c97280a25806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412436259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.3412436259
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.1954371947
Short name T806
Test name
Test status
Simulation time 8212837325 ps
CPU time 15.96 seconds
Started Apr 18 01:51:32 PM PDT 24
Finished Apr 18 01:51:48 PM PDT 24
Peak memory 199404 kb
Host smart-33fc0094-29da-4816-88fe-1edf23936ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954371947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.1954371947
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.1776323256
Short name T450
Test name
Test status
Simulation time 7255932329 ps
CPU time 425.96 seconds
Started Apr 18 01:51:27 PM PDT 24
Finished Apr 18 01:58:34 PM PDT 24
Peak memory 200888 kb
Host smart-03bc6fe1-708b-41a8-a6bb-81e02e1d022b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1776323256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.1776323256
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.973911963
Short name T912
Test name
Test status
Simulation time 5902228593 ps
CPU time 3.68 seconds
Started Apr 18 01:51:32 PM PDT 24
Finished Apr 18 01:51:36 PM PDT 24
Peak memory 199452 kb
Host smart-d9492ed3-66e6-47c9-9b07-71a5e5e86d61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=973911963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.973911963
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.1207222441
Short name T268
Test name
Test status
Simulation time 49622032775 ps
CPU time 25.24 seconds
Started Apr 18 01:51:28 PM PDT 24
Finished Apr 18 01:51:54 PM PDT 24
Peak memory 200884 kb
Host smart-c236e295-519c-4111-ae32-e4a24e306199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207222441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.1207222441
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.3994031216
Short name T1110
Test name
Test status
Simulation time 43190434121 ps
CPU time 66.61 seconds
Started Apr 18 01:51:25 PM PDT 24
Finished Apr 18 01:52:33 PM PDT 24
Peak memory 197188 kb
Host smart-ca9dedb7-bcba-403b-83f8-9234bd2f3a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994031216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.3994031216
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.3269022485
Short name T644
Test name
Test status
Simulation time 5557773115 ps
CPU time 20.43 seconds
Started Apr 18 01:51:25 PM PDT 24
Finished Apr 18 01:51:46 PM PDT 24
Peak memory 200824 kb
Host smart-d9880366-9bee-41e2-a737-e5006f6ee82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269022485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.3269022485
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.344936578
Short name T183
Test name
Test status
Simulation time 681551341010 ps
CPU time 1306.57 seconds
Started Apr 18 01:51:26 PM PDT 24
Finished Apr 18 02:13:14 PM PDT 24
Peak memory 200824 kb
Host smart-1cb4ff16-78d8-4f89-a63b-49d8e856c826
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344936578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.344936578
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.1965256935
Short name T108
Test name
Test status
Simulation time 133019576314 ps
CPU time 1170.38 seconds
Started Apr 18 01:51:33 PM PDT 24
Finished Apr 18 02:11:04 PM PDT 24
Peak memory 225112 kb
Host smart-57c7766a-f3c1-4010-a31b-2eb53e0ec8ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965256935 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.1965256935
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.4217940761
Short name T940
Test name
Test status
Simulation time 759807620 ps
CPU time 1.59 seconds
Started Apr 18 01:51:32 PM PDT 24
Finished Apr 18 01:51:34 PM PDT 24
Peak memory 199660 kb
Host smart-a7fee82a-8535-4549-9b2f-be30cc078bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217940761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.4217940761
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.1614801312
Short name T399
Test name
Test status
Simulation time 73007717846 ps
CPU time 136.29 seconds
Started Apr 18 01:51:24 PM PDT 24
Finished Apr 18 01:53:41 PM PDT 24
Peak memory 200824 kb
Host smart-f37b7e54-4550-48e4-ad91-31d8e6d44347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614801312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.1614801312
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.1518846713
Short name T745
Test name
Test status
Simulation time 63231858057 ps
CPU time 28.45 seconds
Started Apr 18 01:53:50 PM PDT 24
Finished Apr 18 01:54:19 PM PDT 24
Peak memory 200868 kb
Host smart-fe65a446-8a8b-4dad-806a-8e29d30aad37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518846713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1518846713
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.2856994104
Short name T1089
Test name
Test status
Simulation time 70604983038 ps
CPU time 291.19 seconds
Started Apr 18 01:53:48 PM PDT 24
Finished Apr 18 01:58:39 PM PDT 24
Peak memory 217504 kb
Host smart-d9dbe756-bad7-4961-8852-eb548aa927c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856994104 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.2856994104
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.1153954558
Short name T633
Test name
Test status
Simulation time 83078342166 ps
CPU time 41.26 seconds
Started Apr 18 01:53:48 PM PDT 24
Finished Apr 18 01:54:30 PM PDT 24
Peak memory 200880 kb
Host smart-3e15f0a6-f657-4393-8f4a-285ebc56104a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153954558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.1153954558
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.418195623
Short name T18
Test name
Test status
Simulation time 41669839198 ps
CPU time 177.75 seconds
Started Apr 18 01:53:50 PM PDT 24
Finished Apr 18 01:56:48 PM PDT 24
Peak memory 212836 kb
Host smart-9333517d-967b-4848-923a-70d768ed59f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418195623 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.418195623
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.4279921556
Short name T834
Test name
Test status
Simulation time 59455410192 ps
CPU time 138.06 seconds
Started Apr 18 01:53:47 PM PDT 24
Finished Apr 18 01:56:06 PM PDT 24
Peak memory 200732 kb
Host smart-fa275bc8-d25f-4190-80e6-56c3d6ebfa98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279921556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.4279921556
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.368595620
Short name T592
Test name
Test status
Simulation time 450951132787 ps
CPU time 1076.44 seconds
Started Apr 18 01:54:03 PM PDT 24
Finished Apr 18 02:12:00 PM PDT 24
Peak memory 217540 kb
Host smart-67866d77-c9e9-492a-846e-d9823ae83920
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368595620 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.368595620
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.3411416774
Short name T393
Test name
Test status
Simulation time 80140581021 ps
CPU time 63.63 seconds
Started Apr 18 01:53:50 PM PDT 24
Finished Apr 18 01:54:54 PM PDT 24
Peak memory 200832 kb
Host smart-1534e0e8-c76a-455d-8276-a5e911ae49a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411416774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.3411416774
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.1795461243
Short name T26
Test name
Test status
Simulation time 199385693195 ps
CPU time 938.77 seconds
Started Apr 18 01:53:53 PM PDT 24
Finished Apr 18 02:09:32 PM PDT 24
Peak memory 231772 kb
Host smart-ced523c3-6f11-43fa-b480-e91f0fb3a8a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795461243 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.1795461243
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.1223632213
Short name T824
Test name
Test status
Simulation time 56403546479 ps
CPU time 113.66 seconds
Started Apr 18 01:53:48 PM PDT 24
Finished Apr 18 01:55:42 PM PDT 24
Peak memory 200896 kb
Host smart-af97adaf-f3d4-4038-ab87-c49f54ec9646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223632213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.1223632213
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.480184459
Short name T902
Test name
Test status
Simulation time 198232219652 ps
CPU time 437.88 seconds
Started Apr 18 01:53:49 PM PDT 24
Finished Apr 18 02:01:07 PM PDT 24
Peak memory 217368 kb
Host smart-8603303a-619b-4241-8c80-96fea7d93b1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480184459 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.480184459
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.1646461737
Short name T467
Test name
Test status
Simulation time 94860772508 ps
CPU time 59.37 seconds
Started Apr 18 01:53:48 PM PDT 24
Finished Apr 18 01:54:48 PM PDT 24
Peak memory 200904 kb
Host smart-237e8f90-8a2b-44be-b52f-42c6ba8e82d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646461737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.1646461737
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.2966127276
Short name T655
Test name
Test status
Simulation time 260689901813 ps
CPU time 261.58 seconds
Started Apr 18 01:53:49 PM PDT 24
Finished Apr 18 01:58:11 PM PDT 24
Peak memory 217484 kb
Host smart-fedc76e2-5382-4996-a098-68766d460ac4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966127276 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.2966127276
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.670973661
Short name T175
Test name
Test status
Simulation time 46376439146 ps
CPU time 98.34 seconds
Started Apr 18 01:54:03 PM PDT 24
Finished Apr 18 01:55:42 PM PDT 24
Peak memory 200812 kb
Host smart-22688500-f9c6-40ce-a795-ed2ac2bb55d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670973661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.670973661
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.1240286685
Short name T668
Test name
Test status
Simulation time 40658675935 ps
CPU time 848.17 seconds
Started Apr 18 01:53:52 PM PDT 24
Finished Apr 18 02:08:01 PM PDT 24
Peak memory 217228 kb
Host smart-0c77da04-5d98-451a-849c-1471ad2126be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240286685 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.1240286685
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.1671613748
Short name T396
Test name
Test status
Simulation time 16531735533 ps
CPU time 16.15 seconds
Started Apr 18 01:53:50 PM PDT 24
Finished Apr 18 01:54:06 PM PDT 24
Peak memory 200812 kb
Host smart-4746b6cf-29c7-446b-91d7-e30835d0f949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671613748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.1671613748
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.2999956123
Short name T98
Test name
Test status
Simulation time 41832034655 ps
CPU time 446.13 seconds
Started Apr 18 01:53:51 PM PDT 24
Finished Apr 18 02:01:17 PM PDT 24
Peak memory 217364 kb
Host smart-183d9318-7c32-4bbb-b5f7-88c32407ecbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999956123 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.2999956123
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.2696428228
Short name T213
Test name
Test status
Simulation time 21262449624 ps
CPU time 31.1 seconds
Started Apr 18 01:53:51 PM PDT 24
Finished Apr 18 01:54:23 PM PDT 24
Peak memory 200904 kb
Host smart-0a1fe0c6-8d90-4168-98af-a2ddbd82b24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696428228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.2696428228
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.185144157
Short name T42
Test name
Test status
Simulation time 257341027092 ps
CPU time 593.77 seconds
Started Apr 18 01:53:49 PM PDT 24
Finished Apr 18 02:03:44 PM PDT 24
Peak memory 217188 kb
Host smart-cb70fdd5-853d-4485-96ed-10c9cae17c06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185144157 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.185144157
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.3969200587
Short name T1069
Test name
Test status
Simulation time 132060011 ps
CPU time 0.55 seconds
Started Apr 18 01:51:32 PM PDT 24
Finished Apr 18 01:51:33 PM PDT 24
Peak memory 196220 kb
Host smart-cbea6727-b5c2-4e91-91e3-c628cec1d6d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969200587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.3969200587
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.3187668582
Short name T381
Test name
Test status
Simulation time 33959416767 ps
CPU time 29.57 seconds
Started Apr 18 01:51:28 PM PDT 24
Finished Apr 18 01:51:59 PM PDT 24
Peak memory 200868 kb
Host smart-bbfce135-5d24-4c7e-9bac-bebe770e60c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187668582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.3187668582
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.1658204581
Short name T676
Test name
Test status
Simulation time 15342857719 ps
CPU time 11.77 seconds
Started Apr 18 01:51:28 PM PDT 24
Finished Apr 18 01:51:41 PM PDT 24
Peak memory 199128 kb
Host smart-6dde5296-9b2a-440f-a6e1-74704481d3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658204581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.1658204581
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.2851266547
Short name T1100
Test name
Test status
Simulation time 95009845701 ps
CPU time 20.4 seconds
Started Apr 18 01:51:30 PM PDT 24
Finished Apr 18 01:51:51 PM PDT 24
Peak memory 200788 kb
Host smart-06a12818-9483-4491-831f-f072e0a3474c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851266547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2851266547
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.877203331
Short name T670
Test name
Test status
Simulation time 34480386852 ps
CPU time 87.11 seconds
Started Apr 18 01:51:30 PM PDT 24
Finished Apr 18 01:52:58 PM PDT 24
Peak memory 200664 kb
Host smart-637a423f-8111-4a37-a0f2-3b03855c8bfd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877203331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.877203331
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.1369795913
Short name T1107
Test name
Test status
Simulation time 125358784979 ps
CPU time 247.42 seconds
Started Apr 18 01:51:33 PM PDT 24
Finished Apr 18 01:55:41 PM PDT 24
Peak memory 200840 kb
Host smart-9a339028-2ff6-419f-8d9e-c75dc5d5496e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1369795913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.1369795913
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.2907818962
Short name T1143
Test name
Test status
Simulation time 2421239441 ps
CPU time 5.18 seconds
Started Apr 18 01:51:28 PM PDT 24
Finished Apr 18 01:51:34 PM PDT 24
Peak memory 199592 kb
Host smart-4369ef1f-df44-4c27-a5eb-1d4414cecdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907818962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.2907818962
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.984199283
Short name T1002
Test name
Test status
Simulation time 17859572323 ps
CPU time 35.53 seconds
Started Apr 18 01:51:27 PM PDT 24
Finished Apr 18 01:52:03 PM PDT 24
Peak memory 200680 kb
Host smart-535fbcd3-0f99-420b-ac82-0706b26224b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984199283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.984199283
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.1571851346
Short name T959
Test name
Test status
Simulation time 19907466724 ps
CPU time 1076.57 seconds
Started Apr 18 01:51:27 PM PDT 24
Finished Apr 18 02:09:25 PM PDT 24
Peak memory 200892 kb
Host smart-436dd507-6039-49ce-8857-a625b3584762
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1571851346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.1571851346
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.2337505466
Short name T1118
Test name
Test status
Simulation time 4407649755 ps
CPU time 9.54 seconds
Started Apr 18 01:51:29 PM PDT 24
Finished Apr 18 01:51:39 PM PDT 24
Peak memory 198892 kb
Host smart-294d1b37-c8db-4929-8f54-74925abd38a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2337505466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.2337505466
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.4235635806
Short name T508
Test name
Test status
Simulation time 47231856325 ps
CPU time 22.04 seconds
Started Apr 18 01:51:37 PM PDT 24
Finished Apr 18 01:51:59 PM PDT 24
Peak memory 200808 kb
Host smart-01bd5d35-1e25-45a5-84ff-bccf8065ecd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235635806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.4235635806
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.3431872352
Short name T984
Test name
Test status
Simulation time 4725847610 ps
CPU time 8.02 seconds
Started Apr 18 01:51:27 PM PDT 24
Finished Apr 18 01:51:36 PM PDT 24
Peak memory 197172 kb
Host smart-e7407017-4867-4ed2-b25a-fb4d784428dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431872352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.3431872352
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.2169692716
Short name T1065
Test name
Test status
Simulation time 562072443 ps
CPU time 1.27 seconds
Started Apr 18 01:51:26 PM PDT 24
Finished Apr 18 01:51:29 PM PDT 24
Peak memory 200116 kb
Host smart-534b0537-1de3-455b-93aa-ad2b5c57b4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169692716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2169692716
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.1739324619
Short name T945
Test name
Test status
Simulation time 1405896092 ps
CPU time 2.2 seconds
Started Apr 18 01:51:33 PM PDT 24
Finished Apr 18 01:51:36 PM PDT 24
Peak memory 199700 kb
Host smart-e022d643-4f2c-462f-9efd-007d34cc7725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739324619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.1739324619
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.2511332309
Short name T911
Test name
Test status
Simulation time 5095920681 ps
CPU time 10.41 seconds
Started Apr 18 01:51:30 PM PDT 24
Finished Apr 18 01:51:41 PM PDT 24
Peak memory 199976 kb
Host smart-5755f3dd-0ae4-49ba-800f-bae99bf9ad0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511332309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2511332309
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.2824941409
Short name T368
Test name
Test status
Simulation time 111735549649 ps
CPU time 58.46 seconds
Started Apr 18 01:54:02 PM PDT 24
Finished Apr 18 01:55:01 PM PDT 24
Peak memory 200888 kb
Host smart-4b136d72-d39f-441a-9a1a-7718fca68338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824941409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2824941409
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.2288394683
Short name T50
Test name
Test status
Simulation time 58637395935 ps
CPU time 427.07 seconds
Started Apr 18 01:53:50 PM PDT 24
Finished Apr 18 02:00:57 PM PDT 24
Peak memory 217576 kb
Host smart-76a9f868-6931-4155-abbf-2882003c9dfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288394683 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.2288394683
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.2138943871
Short name T185
Test name
Test status
Simulation time 197941469909 ps
CPU time 572.04 seconds
Started Apr 18 01:53:50 PM PDT 24
Finished Apr 18 02:03:22 PM PDT 24
Peak memory 225476 kb
Host smart-1d845cbb-2804-464b-85a9-2bd931bdc689
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138943871 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.2138943871
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.237740556
Short name T245
Test name
Test status
Simulation time 104772917933 ps
CPU time 23.65 seconds
Started Apr 18 01:53:50 PM PDT 24
Finished Apr 18 01:54:14 PM PDT 24
Peak memory 200860 kb
Host smart-3a567dcf-7848-43aa-8401-7613aef41b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237740556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.237740556
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.777861983
Short name T421
Test name
Test status
Simulation time 66917221216 ps
CPU time 247.2 seconds
Started Apr 18 01:53:48 PM PDT 24
Finished Apr 18 01:57:56 PM PDT 24
Peak memory 217524 kb
Host smart-caa4396f-1c77-41ed-adfb-d8fb692c29f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777861983 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.777861983
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.1530180850
Short name T1129
Test name
Test status
Simulation time 19338369142 ps
CPU time 32.13 seconds
Started Apr 18 01:53:50 PM PDT 24
Finished Apr 18 01:54:22 PM PDT 24
Peak memory 200640 kb
Host smart-a11851ea-5b1c-4d62-9b27-bdba4d3e6c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530180850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.1530180850
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.2597241154
Short name T316
Test name
Test status
Simulation time 10090322660 ps
CPU time 65.82 seconds
Started Apr 18 01:53:55 PM PDT 24
Finished Apr 18 01:55:02 PM PDT 24
Peak memory 209552 kb
Host smart-5c54cd04-7080-4bcc-b88f-9713f7a7a871
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597241154 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.2597241154
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.1361636963
Short name T1017
Test name
Test status
Simulation time 14691131800 ps
CPU time 24.23 seconds
Started Apr 18 01:54:01 PM PDT 24
Finished Apr 18 01:54:26 PM PDT 24
Peak memory 199768 kb
Host smart-969e9c9d-847e-41a9-af1d-9c15000f70e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361636963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.1361636963
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.2193223564
Short name T1149
Test name
Test status
Simulation time 88519903703 ps
CPU time 527.46 seconds
Started Apr 18 01:53:50 PM PDT 24
Finished Apr 18 02:02:38 PM PDT 24
Peak memory 217336 kb
Host smart-d871c54b-3cea-4269-ae46-09096f884316
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193223564 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.2193223564
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.4174442258
Short name T104
Test name
Test status
Simulation time 20037067440 ps
CPU time 21.1 seconds
Started Apr 18 01:54:03 PM PDT 24
Finished Apr 18 01:54:24 PM PDT 24
Peak memory 200860 kb
Host smart-8e75d583-b350-466b-9f88-4f5e32ecec1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174442258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.4174442258
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.4243786116
Short name T756
Test name
Test status
Simulation time 48389049137 ps
CPU time 233.03 seconds
Started Apr 18 01:54:03 PM PDT 24
Finished Apr 18 01:57:56 PM PDT 24
Peak memory 212800 kb
Host smart-08b9cd20-91fd-4dea-a5d5-a7d78d458b4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243786116 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.4243786116
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.608835095
Short name T784
Test name
Test status
Simulation time 141342278273 ps
CPU time 399.42 seconds
Started Apr 18 01:53:51 PM PDT 24
Finished Apr 18 02:00:31 PM PDT 24
Peak memory 200880 kb
Host smart-3400c970-ef35-4f88-8227-c6bded26f917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608835095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.608835095
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.1394644560
Short name T1006
Test name
Test status
Simulation time 39495134016 ps
CPU time 409.72 seconds
Started Apr 18 01:53:53 PM PDT 24
Finished Apr 18 02:00:44 PM PDT 24
Peak memory 217576 kb
Host smart-0a3999af-1fd7-43d6-a901-716d909304b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394644560 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.1394644560
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.1311820800
Short name T692
Test name
Test status
Simulation time 13213230194 ps
CPU time 33.94 seconds
Started Apr 18 01:54:03 PM PDT 24
Finished Apr 18 01:54:38 PM PDT 24
Peak memory 200824 kb
Host smart-fccef022-296d-4819-9cdf-e59a725dfbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311820800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.1311820800
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.2812027629
Short name T62
Test name
Test status
Simulation time 34780083919 ps
CPU time 336.2 seconds
Started Apr 18 01:53:50 PM PDT 24
Finished Apr 18 01:59:27 PM PDT 24
Peak memory 217368 kb
Host smart-d4659665-ad24-4d30-9c51-dde92c4650d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812027629 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.2812027629
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.3179769849
Short name T1009
Test name
Test status
Simulation time 29224339533 ps
CPU time 56.31 seconds
Started Apr 18 01:53:50 PM PDT 24
Finished Apr 18 01:54:47 PM PDT 24
Peak memory 200868 kb
Host smart-cbc17a5b-7320-4dab-8409-111153c63ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179769849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.3179769849
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.2698880923
Short name T685
Test name
Test status
Simulation time 22347254789 ps
CPU time 9.43 seconds
Started Apr 18 01:53:54 PM PDT 24
Finished Apr 18 01:54:04 PM PDT 24
Peak memory 200724 kb
Host smart-d382599f-7b4d-4b03-99e7-819cb66ac8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698880923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2698880923
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.1763890102
Short name T531
Test name
Test status
Simulation time 278506242847 ps
CPU time 913.83 seconds
Started Apr 18 01:53:54 PM PDT 24
Finished Apr 18 02:09:09 PM PDT 24
Peak memory 225764 kb
Host smart-89cff806-cf2b-4a23-9cc9-82f03a48bb9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763890102 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.1763890102
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.1168194585
Short name T570
Test name
Test status
Simulation time 10750811 ps
CPU time 0.55 seconds
Started Apr 18 01:51:33 PM PDT 24
Finished Apr 18 01:51:34 PM PDT 24
Peak memory 195128 kb
Host smart-d0e0e3c3-ff66-407b-a709-953f096ddbc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168194585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.1168194585
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.2560216366
Short name T579
Test name
Test status
Simulation time 222502730904 ps
CPU time 42.97 seconds
Started Apr 18 01:51:38 PM PDT 24
Finished Apr 18 01:52:22 PM PDT 24
Peak memory 200772 kb
Host smart-702fb62f-b50a-4ff4-b2fe-4de313c2212a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560216366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.2560216366
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.1862031723
Short name T650
Test name
Test status
Simulation time 138823680314 ps
CPU time 235.81 seconds
Started Apr 18 01:51:33 PM PDT 24
Finished Apr 18 01:55:30 PM PDT 24
Peak memory 200804 kb
Host smart-5181201e-db0b-4eba-ac5c-da8308186ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862031723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1862031723
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.2599084998
Short name T248
Test name
Test status
Simulation time 77018049869 ps
CPU time 11.8 seconds
Started Apr 18 01:51:34 PM PDT 24
Finished Apr 18 01:51:46 PM PDT 24
Peak memory 200652 kb
Host smart-365daa0d-70d1-475d-b901-f37f92e55ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599084998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.2599084998
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.660802825
Short name T95
Test name
Test status
Simulation time 32350073084 ps
CPU time 30.7 seconds
Started Apr 18 01:51:36 PM PDT 24
Finished Apr 18 01:52:07 PM PDT 24
Peak memory 200764 kb
Host smart-562e9760-ccfe-4665-9159-06294a419ad3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660802825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.660802825
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.1545466620
Short name T1088
Test name
Test status
Simulation time 116181134368 ps
CPU time 501.36 seconds
Started Apr 18 01:51:31 PM PDT 24
Finished Apr 18 01:59:53 PM PDT 24
Peak memory 200912 kb
Host smart-ed57bf39-2b92-4367-9e5b-e954d0fc602f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1545466620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.1545466620
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.613716481
Short name T778
Test name
Test status
Simulation time 8598516367 ps
CPU time 11.56 seconds
Started Apr 18 01:51:43 PM PDT 24
Finished Apr 18 01:51:55 PM PDT 24
Peak memory 200808 kb
Host smart-b70fcc8b-f7bf-487b-90da-eace3b83ef44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613716481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.613716481
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.3083177241
Short name T807
Test name
Test status
Simulation time 74477588532 ps
CPU time 138.91 seconds
Started Apr 18 01:51:52 PM PDT 24
Finished Apr 18 01:54:11 PM PDT 24
Peak memory 209228 kb
Host smart-7e057b48-cc87-441b-b2d7-31a7e208a152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083177241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.3083177241
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.937754341
Short name T829
Test name
Test status
Simulation time 12217559295 ps
CPU time 699.94 seconds
Started Apr 18 01:52:00 PM PDT 24
Finished Apr 18 02:03:40 PM PDT 24
Peak memory 200852 kb
Host smart-0479c98b-a127-4f5d-b5c6-d6df26bc2ae9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=937754341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.937754341
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.1515532199
Short name T17
Test name
Test status
Simulation time 6010865192 ps
CPU time 25.61 seconds
Started Apr 18 01:51:34 PM PDT 24
Finished Apr 18 01:52:01 PM PDT 24
Peak memory 200020 kb
Host smart-0b83a0c0-0698-4981-bcf1-7d2322b5f211
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1515532199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.1515532199
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.698009609
Short name T472
Test name
Test status
Simulation time 65218657635 ps
CPU time 29.21 seconds
Started Apr 18 01:51:34 PM PDT 24
Finished Apr 18 01:52:04 PM PDT 24
Peak memory 200796 kb
Host smart-0c3fa667-7dc5-4e5a-aa0e-1aab92f35947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698009609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.698009609
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.2823971372
Short name T406
Test name
Test status
Simulation time 4769088164 ps
CPU time 2.23 seconds
Started Apr 18 01:51:34 PM PDT 24
Finished Apr 18 01:51:37 PM PDT 24
Peak memory 196884 kb
Host smart-97bc8b8c-5cab-484d-863c-a91e653f5de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823971372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.2823971372
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.4271561682
Short name T311
Test name
Test status
Simulation time 5551598194 ps
CPU time 35.19 seconds
Started Apr 18 01:51:34 PM PDT 24
Finished Apr 18 01:52:10 PM PDT 24
Peak memory 200832 kb
Host smart-1d6ae082-d533-4a04-8616-0ed1f5179925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271561682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.4271561682
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.804813827
Short name T749
Test name
Test status
Simulation time 362505624174 ps
CPU time 2040.52 seconds
Started Apr 18 01:51:37 PM PDT 24
Finished Apr 18 02:25:38 PM PDT 24
Peak memory 209312 kb
Host smart-b3e8bcb4-7b6e-47fe-a20c-9b81d306c74f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804813827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.804813827
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.3168431864
Short name T939
Test name
Test status
Simulation time 54425776969 ps
CPU time 1163.45 seconds
Started Apr 18 01:51:34 PM PDT 24
Finished Apr 18 02:10:58 PM PDT 24
Peak memory 216768 kb
Host smart-a881d0c6-989c-44a8-b748-2f346a1f795d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168431864 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.3168431864
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.483419010
Short name T557
Test name
Test status
Simulation time 2299309748 ps
CPU time 2.66 seconds
Started Apr 18 01:51:34 PM PDT 24
Finished Apr 18 01:51:37 PM PDT 24
Peak memory 199676 kb
Host smart-5c3f6b49-832a-444f-ac3f-df54ace699ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483419010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.483419010
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.790360062
Short name T733
Test name
Test status
Simulation time 39739499111 ps
CPU time 32.87 seconds
Started Apr 18 01:51:34 PM PDT 24
Finished Apr 18 01:52:07 PM PDT 24
Peak memory 200876 kb
Host smart-5fbb3c04-9174-40e2-aae3-1975dfb77b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790360062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.790360062
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.1304698285
Short name T614
Test name
Test status
Simulation time 13178614961 ps
CPU time 9.67 seconds
Started Apr 18 01:53:52 PM PDT 24
Finished Apr 18 01:54:02 PM PDT 24
Peak memory 200660 kb
Host smart-c32a4e33-f1a3-4b26-b654-3757a7f4f469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304698285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.1304698285
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.3090178157
Short name T147
Test name
Test status
Simulation time 39669435423 ps
CPU time 722.59 seconds
Started Apr 18 01:53:54 PM PDT 24
Finished Apr 18 02:05:57 PM PDT 24
Peak memory 216760 kb
Host smart-113ff8ef-8b59-4146-a592-54dabdf1c741
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090178157 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.3090178157
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.966549578
Short name T152
Test name
Test status
Simulation time 135673675325 ps
CPU time 59.66 seconds
Started Apr 18 01:53:55 PM PDT 24
Finished Apr 18 01:54:56 PM PDT 24
Peak memory 200804 kb
Host smart-e89530c2-50b8-4d84-82fe-c0dcb427ff80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966549578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.966549578
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.2308892647
Short name T921
Test name
Test status
Simulation time 78668143473 ps
CPU time 627.04 seconds
Started Apr 18 01:53:55 PM PDT 24
Finished Apr 18 02:04:22 PM PDT 24
Peak memory 227376 kb
Host smart-edf87b3e-8b97-44da-b99d-20c48368ff1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308892647 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.2308892647
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.804306075
Short name T617
Test name
Test status
Simulation time 26275969558 ps
CPU time 69.17 seconds
Started Apr 18 01:53:53 PM PDT 24
Finished Apr 18 01:55:02 PM PDT 24
Peak memory 200772 kb
Host smart-9d50e083-31c0-4839-8cb1-e4eaa80ca79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804306075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.804306075
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.1693491845
Short name T566
Test name
Test status
Simulation time 232945251370 ps
CPU time 740.4 seconds
Started Apr 18 01:53:58 PM PDT 24
Finished Apr 18 02:06:19 PM PDT 24
Peak memory 225748 kb
Host smart-efa8e964-7579-4d74-82ca-8ec9bad67864
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693491845 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.1693491845
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.3822478219
Short name T222
Test name
Test status
Simulation time 116495958679 ps
CPU time 45.37 seconds
Started Apr 18 01:53:55 PM PDT 24
Finished Apr 18 01:54:41 PM PDT 24
Peak memory 200900 kb
Host smart-2ff5bc8c-8a68-4cc4-b4f6-d17cd7f569df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822478219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.3822478219
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.1059137834
Short name T1148
Test name
Test status
Simulation time 75130471389 ps
CPU time 185.03 seconds
Started Apr 18 01:53:54 PM PDT 24
Finished Apr 18 01:57:00 PM PDT 24
Peak memory 209352 kb
Host smart-f92dc63b-a481-4a74-9bcb-ebaf882bf751
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059137834 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.1059137834
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.3783234165
Short name T1067
Test name
Test status
Simulation time 133487832208 ps
CPU time 194.37 seconds
Started Apr 18 01:54:02 PM PDT 24
Finished Apr 18 01:57:17 PM PDT 24
Peak memory 200856 kb
Host smart-873be014-4719-42b3-9e31-26802b3e7f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783234165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.3783234165
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.2988104228
Short name T30
Test name
Test status
Simulation time 48024224882 ps
CPU time 408.7 seconds
Started Apr 18 01:53:58 PM PDT 24
Finished Apr 18 02:00:47 PM PDT 24
Peak memory 216840 kb
Host smart-68a5fb66-1713-4e03-864c-032e746c9c82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988104228 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.2988104228
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.3995693987
Short name T665
Test name
Test status
Simulation time 27487903919 ps
CPU time 24.59 seconds
Started Apr 18 01:53:55 PM PDT 24
Finished Apr 18 01:54:20 PM PDT 24
Peak memory 200836 kb
Host smart-76bcc14c-9ee5-4ca1-bf52-8d220da0bf94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995693987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.3995693987
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.1662880642
Short name T765
Test name
Test status
Simulation time 91055391216 ps
CPU time 538.37 seconds
Started Apr 18 01:54:03 PM PDT 24
Finished Apr 18 02:03:02 PM PDT 24
Peak memory 225748 kb
Host smart-ccdc219a-923c-43e5-b040-de68b49bd770
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662880642 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.1662880642
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.2375576887
Short name T203
Test name
Test status
Simulation time 80134350899 ps
CPU time 747.88 seconds
Started Apr 18 01:53:55 PM PDT 24
Finished Apr 18 02:06:23 PM PDT 24
Peak memory 225740 kb
Host smart-902e21d7-1e36-414d-bd9c-b844cff3d049
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375576887 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.2375576887
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.1808433673
Short name T562
Test name
Test status
Simulation time 41513544437 ps
CPU time 41.41 seconds
Started Apr 18 01:53:53 PM PDT 24
Finished Apr 18 01:54:35 PM PDT 24
Peak memory 200796 kb
Host smart-e45ce159-17c1-47b6-b1d9-9b070534cf51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808433673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.1808433673
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.1501249272
Short name T59
Test name
Test status
Simulation time 288366628236 ps
CPU time 1080.88 seconds
Started Apr 18 01:53:52 PM PDT 24
Finished Apr 18 02:11:54 PM PDT 24
Peak memory 227672 kb
Host smart-3af66bbe-f403-4364-a0b7-7cb0ebfe1e20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501249272 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.1501249272
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.1184057782
Short name T137
Test name
Test status
Simulation time 134872183490 ps
CPU time 106.26 seconds
Started Apr 18 01:53:57 PM PDT 24
Finished Apr 18 01:55:43 PM PDT 24
Peak memory 200832 kb
Host smart-104499b0-269a-478f-93aa-ab4eadd0826f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184057782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.1184057782
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.969022167
Short name T925
Test name
Test status
Simulation time 372606946834 ps
CPU time 1188.29 seconds
Started Apr 18 01:53:56 PM PDT 24
Finished Apr 18 02:13:45 PM PDT 24
Peak memory 217376 kb
Host smart-fb9b7184-9cd3-42c0-9ed6-c22949fefb23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969022167 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.969022167
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.3607827550
Short name T880
Test name
Test status
Simulation time 47756205778 ps
CPU time 30.94 seconds
Started Apr 18 01:53:55 PM PDT 24
Finished Apr 18 01:54:26 PM PDT 24
Peak memory 200880 kb
Host smart-f079d253-2852-4e69-b0da-ad1533343cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607827550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.3607827550
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.1863014859
Short name T13
Test name
Test status
Simulation time 13900300095 ps
CPU time 116.55 seconds
Started Apr 18 01:53:53 PM PDT 24
Finished Apr 18 01:55:50 PM PDT 24
Peak memory 217264 kb
Host smart-09cce4ce-a347-4743-8e2f-1cef376512e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863014859 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.1863014859
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.2516114820
Short name T1097
Test name
Test status
Simulation time 110596754 ps
CPU time 0.56 seconds
Started Apr 18 01:51:38 PM PDT 24
Finished Apr 18 01:51:39 PM PDT 24
Peak memory 196208 kb
Host smart-f666e16b-f5fb-4a96-871b-b166193fddf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516114820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.2516114820
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.2886946688
Short name T291
Test name
Test status
Simulation time 28660585491 ps
CPU time 53.22 seconds
Started Apr 18 01:51:36 PM PDT 24
Finished Apr 18 01:52:30 PM PDT 24
Peak memory 200796 kb
Host smart-91f886d7-efdc-45b8-a56e-03f706134a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886946688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.2886946688
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.2297793008
Short name T535
Test name
Test status
Simulation time 211655005758 ps
CPU time 312.89 seconds
Started Apr 18 01:51:34 PM PDT 24
Finished Apr 18 01:56:48 PM PDT 24
Peak memory 200700 kb
Host smart-b14a6898-177f-4cab-bce2-a615dd3be476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297793008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.2297793008
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.1900420171
Short name T881
Test name
Test status
Simulation time 34032717727 ps
CPU time 86.63 seconds
Started Apr 18 01:51:41 PM PDT 24
Finished Apr 18 01:53:08 PM PDT 24
Peak memory 200896 kb
Host smart-6bec87d5-d785-4f6f-9830-8531ae2ffb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900420171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1900420171
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.2332638211
Short name T309
Test name
Test status
Simulation time 13161771994 ps
CPU time 29.66 seconds
Started Apr 18 01:51:37 PM PDT 24
Finished Apr 18 01:52:08 PM PDT 24
Peak memory 200868 kb
Host smart-fb1bfd1a-dde1-480c-b2c4-106845311f0d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332638211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.2332638211
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.983493368
Short name T937
Test name
Test status
Simulation time 164225731223 ps
CPU time 338.17 seconds
Started Apr 18 01:51:39 PM PDT 24
Finished Apr 18 01:57:17 PM PDT 24
Peak memory 200872 kb
Host smart-ce0dcfdb-a56a-4e68-92e3-66e83fd22af9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=983493368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.983493368
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.4266729243
Short name T319
Test name
Test status
Simulation time 11704853382 ps
CPU time 11.08 seconds
Started Apr 18 01:51:56 PM PDT 24
Finished Apr 18 01:52:08 PM PDT 24
Peak memory 200240 kb
Host smart-916210a2-0849-4d2d-ad65-d0761580039b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266729243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.4266729243
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.2815456319
Short name T1004
Test name
Test status
Simulation time 39173612559 ps
CPU time 74.05 seconds
Started Apr 18 01:51:38 PM PDT 24
Finished Apr 18 01:52:52 PM PDT 24
Peak memory 200948 kb
Host smart-91329c52-e8fd-4c25-990f-e0b2ade012a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815456319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.2815456319
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.853156608
Short name T861
Test name
Test status
Simulation time 5868447306 ps
CPU time 270.48 seconds
Started Apr 18 01:51:54 PM PDT 24
Finished Apr 18 01:56:26 PM PDT 24
Peak memory 200912 kb
Host smart-338a7a40-2f82-4e38-b35e-6e3e70e79472
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=853156608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.853156608
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.1694347498
Short name T432
Test name
Test status
Simulation time 6043499145 ps
CPU time 25.69 seconds
Started Apr 18 01:51:49 PM PDT 24
Finished Apr 18 01:52:15 PM PDT 24
Peak memory 199176 kb
Host smart-8580ac6a-8314-405d-a3e2-d932ace5cea8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1694347498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.1694347498
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.3547346457
Short name T630
Test name
Test status
Simulation time 59658223936 ps
CPU time 89.02 seconds
Started Apr 18 01:51:39 PM PDT 24
Finished Apr 18 01:53:09 PM PDT 24
Peak memory 200828 kb
Host smart-707eadc1-ff03-47e9-a8ec-1f2d69ba031f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547346457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.3547346457
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.2312392992
Short name T1106
Test name
Test status
Simulation time 3669535255 ps
CPU time 6.98 seconds
Started Apr 18 01:51:37 PM PDT 24
Finished Apr 18 01:51:44 PM PDT 24
Peak memory 197188 kb
Host smart-a11e9fc7-4d38-48da-a8f6-b89a079fe0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312392992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.2312392992
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.1630203035
Short name T2
Test name
Test status
Simulation time 5325402991 ps
CPU time 16.96 seconds
Started Apr 18 01:51:31 PM PDT 24
Finished Apr 18 01:51:48 PM PDT 24
Peak memory 200552 kb
Host smart-eafd6a8d-e74c-4fc0-a1f7-7a2925c9ee17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630203035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.1630203035
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.3784539924
Short name T727
Test name
Test status
Simulation time 251341806095 ps
CPU time 254.57 seconds
Started Apr 18 01:51:39 PM PDT 24
Finished Apr 18 01:55:54 PM PDT 24
Peak memory 200872 kb
Host smart-cb8bfdcd-ff5d-4a0b-b0f0-b6b903720c54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784539924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.3784539924
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.2017766816
Short name T102
Test name
Test status
Simulation time 35684073386 ps
CPU time 502.97 seconds
Started Apr 18 01:51:38 PM PDT 24
Finished Apr 18 02:00:02 PM PDT 24
Peak memory 217412 kb
Host smart-7b90d08e-b73b-462a-ad9c-fce98f66b787
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017766816 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.2017766816
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.878141371
Short name T588
Test name
Test status
Simulation time 860369265 ps
CPU time 3.34 seconds
Started Apr 18 01:51:36 PM PDT 24
Finished Apr 18 01:51:44 PM PDT 24
Peak memory 199376 kb
Host smart-ac8a91ad-0aca-4e7d-b9c4-2629f73ac27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878141371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.878141371
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.269594512
Short name T812
Test name
Test status
Simulation time 67196318408 ps
CPU time 96.35 seconds
Started Apr 18 01:51:35 PM PDT 24
Finished Apr 18 01:53:12 PM PDT 24
Peak memory 200880 kb
Host smart-109d29a1-94bd-4115-be8a-ab44b82112a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269594512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.269594512
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.4191451883
Short name T884
Test name
Test status
Simulation time 70747706490 ps
CPU time 37.86 seconds
Started Apr 18 01:53:53 PM PDT 24
Finished Apr 18 01:54:32 PM PDT 24
Peak memory 200896 kb
Host smart-8429f705-1ff2-46e1-b55b-761c4aa2e65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191451883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.4191451883
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.3274279833
Short name T227
Test name
Test status
Simulation time 35702369585 ps
CPU time 435.81 seconds
Started Apr 18 01:53:56 PM PDT 24
Finished Apr 18 02:01:12 PM PDT 24
Peak memory 217316 kb
Host smart-74325c97-54cb-4874-a8cf-e001693dcfe1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274279833 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.3274279833
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.4241946645
Short name T766
Test name
Test status
Simulation time 28298487857 ps
CPU time 31.22 seconds
Started Apr 18 01:53:54 PM PDT 24
Finished Apr 18 01:54:25 PM PDT 24
Peak memory 200828 kb
Host smart-8080ad3c-7a8d-4686-a758-c03f58f04ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241946645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.4241946645
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.570818629
Short name T1047
Test name
Test status
Simulation time 168235837911 ps
CPU time 184.32 seconds
Started Apr 18 01:53:56 PM PDT 24
Finished Apr 18 01:57:01 PM PDT 24
Peak memory 200896 kb
Host smart-0fbe74c9-01e1-4aab-b774-ea3dcf7b1bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570818629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.570818629
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.1537684813
Short name T192
Test name
Test status
Simulation time 81236110838 ps
CPU time 1362.62 seconds
Started Apr 18 01:53:54 PM PDT 24
Finished Apr 18 02:16:37 PM PDT 24
Peak memory 225760 kb
Host smart-1c0a8cd0-e080-4420-ab4f-3c620914ed5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537684813 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.1537684813
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.2634226064
Short name T849
Test name
Test status
Simulation time 148781681960 ps
CPU time 56.38 seconds
Started Apr 18 01:53:59 PM PDT 24
Finished Apr 18 01:54:56 PM PDT 24
Peak memory 200856 kb
Host smart-24d4192c-c62d-4bb8-a2a8-d04a174495f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634226064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.2634226064
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.3175463355
Short name T45
Test name
Test status
Simulation time 228710634019 ps
CPU time 901.11 seconds
Started Apr 18 01:53:58 PM PDT 24
Finished Apr 18 02:09:00 PM PDT 24
Peak memory 217304 kb
Host smart-a370a4af-85ac-4193-a58d-7e219a3a9bbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175463355 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.3175463355
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.3143234863
Short name T972
Test name
Test status
Simulation time 67395461810 ps
CPU time 27.51 seconds
Started Apr 18 01:54:07 PM PDT 24
Finished Apr 18 01:54:35 PM PDT 24
Peak memory 200900 kb
Host smart-3910e674-42c5-4beb-84f5-49a5213ce1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143234863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.3143234863
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.891310661
Short name T1122
Test name
Test status
Simulation time 145932970672 ps
CPU time 1254.51 seconds
Started Apr 18 01:53:58 PM PDT 24
Finished Apr 18 02:14:54 PM PDT 24
Peak memory 225508 kb
Host smart-1f603ba5-1ea7-417f-8d6e-5c22a0e9f1e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891310661 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.891310661
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.626509714
Short name T602
Test name
Test status
Simulation time 79295428597 ps
CPU time 167.79 seconds
Started Apr 18 01:54:01 PM PDT 24
Finished Apr 18 01:56:49 PM PDT 24
Peak memory 200936 kb
Host smart-2d80f6ed-db9c-4ec6-bac3-b86c08525983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626509714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.626509714
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.794094234
Short name T600
Test name
Test status
Simulation time 53076405326 ps
CPU time 335.66 seconds
Started Apr 18 01:54:01 PM PDT 24
Finished Apr 18 01:59:37 PM PDT 24
Peak memory 216940 kb
Host smart-26ba7057-b22b-46ac-a652-fbe36196ee36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794094234 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.794094234
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.934139843
Short name T770
Test name
Test status
Simulation time 74944392746 ps
CPU time 31.93 seconds
Started Apr 18 01:53:59 PM PDT 24
Finished Apr 18 01:54:32 PM PDT 24
Peak memory 200888 kb
Host smart-dde29495-0836-46d0-9265-fa3b3763ea39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934139843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.934139843
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.1936014989
Short name T73
Test name
Test status
Simulation time 30109732953 ps
CPU time 368.74 seconds
Started Apr 18 01:54:01 PM PDT 24
Finished Apr 18 02:00:10 PM PDT 24
Peak memory 215416 kb
Host smart-e8281146-e9c6-4a00-9f9d-88a76fffea18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936014989 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.1936014989
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.79863250
Short name T830
Test name
Test status
Simulation time 84823606151 ps
CPU time 172.63 seconds
Started Apr 18 01:53:59 PM PDT 24
Finished Apr 18 01:56:52 PM PDT 24
Peak memory 200768 kb
Host smart-ebfadb47-6abd-4f67-8e8c-aeda1b8684c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79863250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.79863250
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.3453506372
Short name T705
Test name
Test status
Simulation time 56919458158 ps
CPU time 359.99 seconds
Started Apr 18 01:54:02 PM PDT 24
Finished Apr 18 02:00:02 PM PDT 24
Peak memory 217520 kb
Host smart-e3229d47-2e12-445f-b270-73c3a8f8d1f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453506372 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.3453506372
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.3891667291
Short name T133
Test name
Test status
Simulation time 23306896825 ps
CPU time 35.82 seconds
Started Apr 18 01:54:00 PM PDT 24
Finished Apr 18 01:54:36 PM PDT 24
Peak memory 200788 kb
Host smart-94032a27-6e8c-46e9-9768-c86e38d11da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891667291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.3891667291
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.1683061215
Short name T1071
Test name
Test status
Simulation time 174796695089 ps
CPU time 47.49 seconds
Started Apr 18 01:54:02 PM PDT 24
Finished Apr 18 01:54:50 PM PDT 24
Peak memory 200852 kb
Host smart-71a9dab0-8fc0-4062-b2a3-fe84f136d44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683061215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.1683061215
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.3749363121
Short name T1063
Test name
Test status
Simulation time 52370258773 ps
CPU time 314.3 seconds
Started Apr 18 01:53:59 PM PDT 24
Finished Apr 18 01:59:13 PM PDT 24
Peak memory 217340 kb
Host smart-c2f28fbc-3a9f-475b-a3b9-d7dea7ddf6c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749363121 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.3749363121
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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