Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	112468	1			T1	2		T2	28		T3	37
all_values[1]	112468	1			T1	2		T2	28		T3	37
all_values[2]	112468	1			T1	2		T2	28		T3	37
all_values[3]	112468	1			T1	2		T2	28		T3	37
all_values[4]	112468	1			T1	2		T2	28		T3	37
all_values[5]	112468	1			T1	2		T2	28		T3	37
all_values[6]	112468	1			T1	2		T2	28		T3	37
all_values[7]	112468	1			T1	2		T2	28		T3	37

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

452515

1

T1

16

T2

138

T3

226

auto[1]

447229

1

T2

86

T3

70

T4

100

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

839830

1

T1

13

T2

194

T3

263

auto[1]

59914

1

T1

3

T2

30

T3

33

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	30610	1			T3	4		T4	1		T6	12
all_values[0]	auto[0]	auto[1]	24548	1			T1	2		T3	22		T4	18
all_values[0]	auto[1]	auto[0]	34384	1			T2	1		T4	6		T6	2
all_values[0]	auto[1]	auto[1]	22926	1			T2	27		T3	11		T5	1
all_values[1]	auto[0]	auto[0]	54295	1			T1	2		T2	28		T3	26
all_values[1]	auto[0]	auto[1]	1686	1			T4	3		T6	15		T111	13
all_values[1]	auto[1]	auto[0]	54654	1			T3	11		T4	17		T6	99
all_values[1]	auto[1]	auto[1]	1833	1			T6	5		T13	9		T14	1
all_values[2]	auto[0]	auto[0]	54654	1			T1	1		T2	23		T3	37
all_values[2]	auto[0]	auto[1]	2916	1			T1	1		T2	3		T4	1
all_values[2]	auto[1]	auto[0]	52255	1			T2	2		T4	17		T5	1
all_values[2]	auto[1]	auto[1]	2643	1			T4	4		T5	1		T6	28
all_values[3]	auto[0]	auto[0]	56640	1			T1	2		T2	2		T3	37
all_values[3]	auto[0]	auto[1]	358	1			T4	1		T6	2		T13	5
all_values[3]	auto[1]	auto[0]	55139	1			T2	26		T4	2		T5	3
all_values[3]	auto[1]	auto[1]	331	1			T6	2		T13	2		T14	1
all_values[4]	auto[0]	auto[0]	55280	1			T1	2		T2	2		T3	26
all_values[4]	auto[0]	auto[1]	521	1			T6	16		T13	1		T14	7
all_values[4]	auto[1]	auto[0]	56129	1			T2	26		T3	11		T4	2
all_values[4]	auto[1]	auto[1]	538	1			T6	10		T13	3		T14	1
all_values[5]	auto[0]	auto[0]	57113	1			T1	2		T2	26		T3	37
all_values[5]	auto[0]	auto[1]	188	1			T13	3		T14	1		T22	4
all_values[5]	auto[1]	auto[0]	54965	1			T2	2		T4	6		T5	1
all_values[5]	auto[1]	auto[1]	202	1			T13	4		T14	1		T32	2
all_values[6]	auto[0]	auto[0]	56513	1			T1	2		T2	26		T3	26
all_values[6]	auto[0]	auto[1]	212	1			T13	2		T14	5		T22	3
all_values[6]	auto[1]	auto[0]	55535	1			T2	2		T3	11		T4	23
all_values[6]	auto[1]	auto[1]	208	1			T14	1		T22	1		T32	2
all_values[7]	auto[0]	auto[0]	56596	1			T1	2		T2	28		T3	11
all_values[7]	auto[0]	auto[1]	385	1			T5	1		T89	1		T13	2
all_values[7]	auto[1]	auto[0]	55068	1			T3	26		T4	23		T6	76
all_values[7]	auto[1]	auto[1]	419	1			T6	16		T13	4		T14	2