Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2336	1			T2	2		T3	1		T4	2
auto[BaudRate115200]	2040	1			T2	2		T4	1		T5	1
auto[BaudRate230400]	2028	1			T4	1		T5	1		T6	4
auto[BaudRate128Kbps]	2021	1			T3	1		T4	1		T5	2
auto[BaudRate256Kbps]	2181	1			T1	1		T4	1		T6	5
auto[BaudRate1Mbps]	2025	1			T1	1		T11	3		T15	3
auto[BaudRate1p5Mbps]	1352	1			T2	1		T5	1		T8	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	2134	1			T89	10		T20	6		T256	16
freqs[25]	1380	1			T1	2		T41	2		T42	9
freqs[48]	604	1			T11	6		T24	14		T39	5
freqs[50]	424	1			T15	8		T13	35		T321	7
freqs[100]	1281	1			T9	18		T105	5		T17	1

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	357	1			T89	1		T20	3		T256	4
auto[BaudRate9600]	freqs[25]	207	1			T42	3		T112	5		T115	2
auto[BaudRate9600]	freqs[48]	81	1			T11	1		T24	14		T266	1
auto[BaudRate9600]	freqs[50]	76	1			T13	3		T321	2		T325	9
auto[BaudRate9600]	freqs[100]	222	1			T9	18		T105	1		T189	2
auto[BaudRate115200]	freqs[24]	290	1			T89	1		T256	4		T48	2
auto[BaudRate115200]	freqs[25]	224	1			T41	1		T42	2		T112	3
auto[BaudRate115200]	freqs[48]	88	1			T113	1		T172	1		T35	3
auto[BaudRate115200]	freqs[50]	52	1			T15	2		T13	4		T325	9
auto[BaudRate115200]	freqs[100]	186	1			T105	2		T189	1		T22	1
auto[BaudRate230400]	freqs[24]	307	1			T256	1		T269	1		T36	8
auto[BaudRate230400]	freqs[25]	200	1			T42	1		T112	4		T144	2
auto[BaudRate230400]	freqs[48]	87	1			T11	1		T39	1		T266	1
auto[BaudRate230400]	freqs[50]	58	1			T15	1		T13	5		T325	3
auto[BaudRate230400]	freqs[100]	159	1			T17	1		T189	1		T22	4
auto[BaudRate128Kbps]	freqs[24]	319	1			T89	3		T256	3		T48	1
auto[BaudRate128Kbps]	freqs[25]	197	1			T41	1		T42	1		T112	8
auto[BaudRate128Kbps]	freqs[48]	85	1			T39	2		T266	2		T113	1
auto[BaudRate128Kbps]	freqs[50]	55	1			T15	1		T13	8		T321	1
auto[BaudRate128Kbps]	freqs[100]	150	1			T105	1		T22	5		T257	1
auto[BaudRate256Kbps]	freqs[24]	299	1			T20	3		T256	1		T268	1
auto[BaudRate256Kbps]	freqs[25]	210	1			T1	1		T42	2		T112	5
auto[BaudRate256Kbps]	freqs[48]	94	1			T39	1		T113	2		T172	4
auto[BaudRate256Kbps]	freqs[50]	70	1			T13	7		T321	1		T325	12
auto[BaudRate256Kbps]	freqs[100]	197	1			T105	1		T189	1		T22	4
auto[BaudRate1Mbps]	freqs[24]	378	1			T89	4		T256	3		T48	1
auto[BaudRate1Mbps]	freqs[25]	231	1			T1	1		T112	12		T144	1
auto[BaudRate1Mbps]	freqs[48]	83	1			T11	3		T35	1		T277	1
auto[BaudRate1Mbps]	freqs[50]	55	1			T15	3		T13	7		T321	3
auto[BaudRate1Mbps]	freqs[100]	211	1			T22	4		T326	12		T119	8
auto[BaudRate1p5Mbps]	freqs[25]	111	1			T112	4		T115	1		T327	1
auto[BaudRate1p5Mbps]	freqs[48]	86	1			T11	1		T39	1		T266	1
auto[BaudRate1p5Mbps]	freqs[50]	58	1			T15	1		T13	1		T325	9
auto[BaudRate1p5Mbps]	freqs[100]	156	1			T189	2		T22	1		T257	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded