Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.43	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	9	121	93.08

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	9	121	93.08	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	31103029	1			T2	38		T3	53243		T4	34
all_levels[1]	190256	1			T2	16		T4	2		T6	2
all_levels[2]	2540	1			T2	2		T6	1		T15	1
all_levels[3]	1079	1			T4	4		T40	7		T42	11
all_levels[4]	794	1			T4	2		T6	4		T15	1
all_levels[5]	589	1			T6	3		T11	1		T15	1
all_levels[6]	495	1			T5	1		T6	3		T7	1
all_levels[7]	357	1			T6	1		T44	1		T124	1
all_levels[8]	324	1			T89	1		T42	1		T100	1
all_levels[9]	262	1			T4	1		T5	1		T6	1
all_levels[10]	227	1			T4	3		T102	1		T125	2
all_levels[11]	203	1			T4	2		T124	1		T45	1
all_levels[12]	203	1			T15	1		T44	1		T126	1
all_levels[13]	158	1			T5	1		T6	1		T100	2
all_levels[14]	148	1			T31	1		T102	3		T46	1
all_levels[15]	117	1			T11	2		T89	1		T44	1
all_levels[16]	126	1			T4	1		T6	1		T100	1
all_levels[17]	97	1			T89	1		T40	1		T44	1
all_levels[18]	92	1			T11	1		T126	2		T22	1
all_levels[19]	96	1			T102	1		T44	1		T127	1
all_levels[20]	79	1			T105	3		T128	1		T33	1
all_levels[21]	79	1			T118	1		T129	1		T35	1
all_levels[22]	66	1			T127	1		T118	1		T130	1
all_levels[23]	69	1			T42	1		T100	1		T118	1
all_levels[24]	71	1			T11	5		T112	1		T46	1
all_levels[25]	63	1			T44	1		T34	1		T119	1
all_levels[26]	59	1			T6	1		T102	1		T112	1
all_levels[27]	47	1			T131	1		T106	1		T132	1
all_levels[28]	38	1			T89	1		T118	1		T129	1
all_levels[29]	31	1			T35	1		T133	1		T38	1
all_levels[30]	50	1			T134	1		T135	1		T130	3
all_levels[31]	28	1			T136	1		T50	1		T137	1
all_levels[32]	35	1			T112	1		T118	1		T138	1
all_levels[33]	40	1			T138	1		T34	1		T119	1
all_levels[34]	21	1			T44	1		T116	1		T57	1
all_levels[35]	25	1			T129	1		T139	1		T140	2
all_levels[36]	21	1			T129	1		T36	1		T136	1
all_levels[37]	24	1			T141	1		T142	1		T143	1
all_levels[38]	17	1			T144	2		T118	2		T145	1
all_levels[39]	27	1			T129	1		T146	2		T147	1
all_levels[40]	21	1			T115	1		T109	1		T148	1
all_levels[41]	23	1			T146	1		T149	1		T150	1
all_levels[42]	18	1			T151	1		T152	1		T153	1
all_levels[43]	21	1			T44	1		T154	1		T155	1
all_levels[44]	36	1			T44	1		T156	3		T149	1
all_levels[45]	19	1			T127	3		T145	1		T157	2
all_levels[46]	13	1			T44	1		T158	1		T159	1
all_levels[47]	14	1			T89	1		T160	1		T133	1
all_levels[48]	13	1			T132	1		T161	1		T61	1
all_levels[49]	7	1			T152	1		T161	1		T61	1
all_levels[50]	8	1			T44	1		T162	1		T61	1
all_levels[51]	9	1			T163	1		T148	1		T164	1
all_levels[52]	12	1			T44	1		T141	1		T165	3
all_levels[53]	9	1			T151	1		T166	1		T167	2
all_levels[54]	13	1			T166	1		T61	5		T62	2
all_levels[55]	12	1			T168	1		T169	3		T170	1
all_levels[56]	7	1			T132	1		T170	1		T171	1
all_levels[57]	5	1			T131	1		T137	1		T61	1
all_levels[58]	12	1			T133	1		T141	1		T166	1
all_levels[59]	6	1			T172	1		T173	1		T159	1
all_levels[60]	5	1			T174	1		T175	3		T176	1
all_levels[61]	12	1			T177	1		T174	1		T178	1
all_levels[62]	6	1			T163	2		T142	1		T179	1
all_levels[63]	15	1			T44	1		T106	1		T180	1
all_levels[64]	112	1			T4	2		T6	2		T42	2

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31297966

1

T2

51

T3

53225

T4

51

auto[1]

4544

1

T2

5

T3

18

T6

26

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	9	121	93.08	9

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[36]]	[auto[1]]	0	1	1
[all_levels[47]]	[auto[1]]	0	1	1
[all_levels[49] , all_levels[50] , all_levels[51]]	[auto[1]]	--	--	3
[all_levels[56] , all_levels[57] , all_levels[58] , all_levels[59]]	[auto[1]]	--	--	4

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	31098975	1			T2	34		T3	53225		T4	34
all_levels[0]	auto[1]	4054	1			T2	4		T3	18		T6	26
all_levels[1]	auto[0]	190162	1			T2	15		T4	2		T6	2
all_levels[1]	auto[1]	94	1			T2	1		T40	1		T131	1
all_levels[2]	auto[0]	2516	1			T2	2		T6	1		T15	1
all_levels[2]	auto[1]	24	1			T113	1		T115	1		T181	2
all_levels[3]	auto[0]	1046	1			T4	4		T40	7		T42	11
all_levels[3]	auto[1]	33	1			T104	4		T163	2		T130	2
all_levels[4]	auto[0]	779	1			T4	2		T6	4		T15	1
all_levels[4]	auto[1]	15	1			T39	1		T128	2		T182	1
all_levels[5]	auto[0]	566	1			T6	3		T11	1		T15	1
all_levels[5]	auto[1]	23	1			T39	1		T40	2		T112	1
all_levels[6]	auto[0]	474	1			T5	1		T6	3		T7	1
all_levels[6]	auto[1]	21	1			T183	3		T172	1		T62	1
all_levels[7]	auto[0]	340	1			T6	1		T44	1		T124	1
all_levels[7]	auto[1]	17	1			T146	2		T184	1		T185	1
all_levels[8]	auto[0]	312	1			T89	1		T42	1		T100	1
all_levels[8]	auto[1]	12	1			T134	2		T181	1		T186	1
all_levels[9]	auto[0]	255	1			T4	1		T5	1		T6	1
all_levels[9]	auto[1]	7	1			T173	1		T187	1		T188	1
all_levels[10]	auto[0]	213	1			T4	3		T102	1		T125	2
all_levels[10]	auto[1]	14	1			T189	1		T190	1		T165	3
all_levels[11]	auto[0]	190	1			T4	2		T124	1		T45	1
all_levels[11]	auto[1]	13	1			T191	1		T192	1		T193	1
all_levels[12]	auto[0]	188	1			T15	1		T44	1		T126	1
all_levels[12]	auto[1]	15	1			T194	2		T195	3		T196	1
all_levels[13]	auto[0]	149	1			T5	1		T6	1		T100	1
all_levels[13]	auto[1]	9	1			T100	1		T197	1		T198	1
all_levels[14]	auto[0]	142	1			T31	1		T102	3		T46	1
all_levels[14]	auto[1]	6	1			T129	1		T199	1		T143	1
all_levels[15]	auto[0]	108	1			T11	1		T89	1		T44	1
all_levels[15]	auto[1]	9	1			T11	1		T128	3		T200	1
all_levels[16]	auto[0]	115	1			T4	1		T6	1		T100	1
all_levels[16]	auto[1]	11	1			T201	1		T202	1		T203	1
all_levels[17]	auto[0]	86	1			T89	1		T40	1		T44	1
all_levels[17]	auto[1]	11	1			T144	3		T204	1		T205	4
all_levels[18]	auto[0]	88	1			T11	1		T126	2		T22	1
all_levels[18]	auto[1]	4	1			T188	2		T206	1		T207	1
all_levels[19]	auto[0]	88	1			T102	1		T44	1		T127	1
all_levels[19]	auto[1]	8	1			T33	2		T208	2		T209	1
all_levels[20]	auto[0]	73	1			T105	3		T128	1		T33	1
all_levels[20]	auto[1]	6	1			T198	1		T210	1		T196	1
all_levels[21]	auto[0]	68	1			T118	1		T129	1		T35	1
all_levels[21]	auto[1]	11	1			T197	1		T211	1		T212	1
all_levels[22]	auto[0]	62	1			T127	1		T118	1		T130	1
all_levels[22]	auto[1]	4	1			T213	1		T178	1		T214	2
all_levels[23]	auto[0]	64	1			T42	1		T100	1		T118	1
all_levels[23]	auto[1]	5	1			T215	1		T216	1		T217	1
all_levels[24]	auto[0]	63	1			T11	1		T112	1		T46	1
all_levels[24]	auto[1]	8	1			T11	4		T218	2		T219	1
all_levels[25]	auto[0]	56	1			T44	1		T34	1		T119	1
all_levels[25]	auto[1]	7	1			T164	1		T220	2		T221	1
all_levels[26]	auto[0]	50	1			T6	1		T102	1		T112	1
all_levels[26]	auto[1]	9	1			T222	1		T223	1		T224	1
all_levels[27]	auto[0]	42	1			T131	1		T106	1		T132	1
all_levels[27]	auto[1]	5	1			T61	2		T225	1		T226	1
all_levels[28]	auto[0]	36	1			T89	1		T118	1		T129	1
all_levels[28]	auto[1]	2	1			T227	1		T228	1		-	-
all_levels[29]	auto[0]	29	1			T35	1		T133	1		T38	1
all_levels[29]	auto[1]	2	1			T207	1		T229	1		-	-
all_levels[30]	auto[0]	44	1			T134	1		T135	1		T130	1
all_levels[30]	auto[1]	6	1			T130	2		T230	1		T231	3
all_levels[31]	auto[0]	26	1			T136	1		T50	1		T137	1
all_levels[31]	auto[1]	2	1			T232	1		T233	1		-	-
all_levels[32]	auto[0]	33	1			T112	1		T118	1		T138	1
all_levels[32]	auto[1]	2	1			T234	1		T235	1		-	-
all_levels[33]	auto[0]	36	1			T138	1		T34	1		T119	1
all_levels[33]	auto[1]	4	1			T236	1		T237	1		T238	1
all_levels[34]	auto[0]	18	1			T44	1		T116	1		T57	1
all_levels[34]	auto[1]	3	1			T229	3		-	-		-	-
all_levels[35]	auto[0]	24	1			T129	1		T139	1		T140	1
all_levels[35]	auto[1]	1	1			T140	1		-	-		-	-
all_levels[36]	auto[0]	21	1			T129	1		T36	1		T136	1
all_levels[37]	auto[0]	22	1			T141	1		T142	1		T143	1
all_levels[37]	auto[1]	2	1			T225	1		T239	1		-	-
all_levels[38]	auto[0]	15	1			T144	1		T118	2		T145	1
all_levels[38]	auto[1]	2	1			T144	1		T240	1		-	-
all_levels[39]	auto[0]	25	1			T129	1		T146	2		T147	1
all_levels[39]	auto[1]	2	1			T241	1		T242	1		-	-
all_levels[40]	auto[0]	16	1			T115	1		T109	1		T148	1
all_levels[40]	auto[1]	5	1			T243	2		T244	1		T245	2
all_levels[41]	auto[0]	21	1			T146	1		T149	1		T150	1
all_levels[41]	auto[1]	2	1			T246	1		T237	1		-	-
all_levels[42]	auto[0]	17	1			T151	1		T152	1		T153	1
all_levels[42]	auto[1]	1	1			T247	1		-	-		-	-
all_levels[43]	auto[0]	19	1			T44	1		T154	1		T155	1
all_levels[43]	auto[1]	2	1			T248	1		T249	1		-	-
all_levels[44]	auto[0]	26	1			T44	1		T156	1		T149	1
all_levels[44]	auto[1]	10	1			T156	2		T192	4		T223	2
all_levels[45]	auto[0]	14	1			T127	1		T145	1		T157	1
all_levels[45]	auto[1]	5	1			T127	2		T157	1		T250	1
all_levels[46]	auto[0]	11	1			T44	1		T158	1		T159	1
all_levels[46]	auto[1]	2	1			T214	1		T251	1		-	-
all_levels[47]	auto[0]	14	1			T89	1		T160	1		T133	1
all_levels[48]	auto[0]	11	1			T132	1		T161	1		T61	1
all_levels[48]	auto[1]	2	1			T252	2		-	-		-	-
all_levels[49]	auto[0]	7	1			T152	1		T161	1		T61	1
all_levels[50]	auto[0]	8	1			T44	1		T162	1		T61	1
all_levels[51]	auto[0]	9	1			T163	1		T148	1		T164	1
all_levels[52]	auto[0]	10	1			T44	1		T141	1		T165	1
all_levels[52]	auto[1]	2	1			T165	2		-	-		-	-
all_levels[53]	auto[0]	8	1			T151	1		T166	1		T167	1
all_levels[53]	auto[1]	1	1			T167	1		-	-		-	-
all_levels[54]	auto[0]	8	1			T166	1		T61	1		T62	2
all_levels[54]	auto[1]	5	1			T61	4		T253	1		-	-
all_levels[55]	auto[0]	10	1			T168	1		T169	1		T170	1
all_levels[55]	auto[1]	2	1			T169	2		-	-		-	-
all_levels[56]	auto[0]	7	1			T132	1		T170	1		T171	1
all_levels[57]	auto[0]	5	1			T131	1		T137	1		T61	1
all_levels[58]	auto[0]	12	1			T133	1		T141	1		T166	1
all_levels[59]	auto[0]	6	1			T172	1		T173	1		T159	1
all_levels[60]	auto[0]	3	1			T174	1		T175	1		T176	1
all_levels[60]	auto[1]	2	1			T175	2		-	-		-	-
all_levels[61]	auto[0]	11	1			T177	1		T174	1		T178	1
all_levels[61]	auto[1]	1	1			T254	1		-	-		-	-
all_levels[62]	auto[0]	5	1			T163	1		T142	1		T179	1
all_levels[62]	auto[1]	1	1			T163	1		-	-		-	-
all_levels[63]	auto[0]	12	1			T44	1		T106	1		T180	1
all_levels[63]	auto[1]	3	1			T255	3		-	-		-	-
all_levels[64]	auto[0]	97	1			T4	2		T6	2		T42	2
all_levels[64]	auto[1]	15	1			T112	1		T151	2		T115	1