Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	112468	1			T1	2		T2	28		T3	37
all_pins[1]	112468	1			T1	2		T2	28		T3	37
all_pins[2]	112468	1			T1	2		T2	28		T3	37
all_pins[3]	112468	1			T1	2		T2	28		T3	37
all_pins[4]	112468	1			T1	2		T2	28		T3	37
all_pins[5]	112468	1			T1	2		T2	28		T3	37
all_pins[6]	112468	1			T1	2		T2	28		T3	37
all_pins[7]	112468	1			T1	2		T2	28		T3	37

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	869766	1			T1	16		T2	197		T3	285
values[0x1]	29978	1			T2	27		T3	11		T4	4
transitions[0x0=>0x1]	28679	1			T2	27		T3	11		T4	4
transitions[0x1=>0x0]	28243	1			T2	26		T3	11		T4	4

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	89450	1			T1	2		T2	1		T3	26
all_pins[0]	values[0x1]	23018	1			T2	27		T3	11		T5	1
all_pins[0]	transitions[0x0=>0x1]	22369	1			T2	27		T3	11		T5	1
all_pins[0]	transitions[0x1=>0x0]	1182	1			T13	1		T42	25		T104	8
all_pins[1]	values[0x0]	110637	1			T1	2		T2	28		T3	37
all_pins[1]	values[0x1]	1831	1			T6	5		T13	9		T14	1
all_pins[1]	transitions[0x0=>0x1]	1727	1			T6	5		T13	9		T12	2
all_pins[1]	transitions[0x1=>0x0]	2603	1			T4	4		T5	1		T6	30
all_pins[2]	values[0x0]	109761	1			T1	2		T2	28		T3	37
all_pins[2]	values[0x1]	2707	1			T4	4		T5	1		T6	30
all_pins[2]	transitions[0x0=>0x1]	2624	1			T4	4		T5	1		T6	30
all_pins[2]	transitions[0x1=>0x0]	248	1			T6	2		T13	1		T14	1
all_pins[3]	values[0x0]	112137	1			T1	2		T2	28		T3	37
all_pins[3]	values[0x1]	331	1			T6	2		T13	2		T14	1
all_pins[3]	transitions[0x0=>0x1]	276	1			T6	2		T13	1		T14	1
all_pins[3]	transitions[0x1=>0x0]	483	1			T6	10		T13	2		T14	1
all_pins[4]	values[0x0]	111930	1			T1	2		T2	28		T3	37
all_pins[4]	values[0x1]	538	1			T6	10		T13	3		T14	1
all_pins[4]	transitions[0x0=>0x1]	453	1			T6	10		T13	1		T14	1
all_pins[4]	transitions[0x1=>0x0]	165	1			T13	2		T14	1		T32	2
all_pins[5]	values[0x0]	112218	1			T1	2		T2	28		T3	37
all_pins[5]	values[0x1]	250	1			T13	4		T14	1		T19	2
all_pins[5]	transitions[0x0=>0x1]	190	1			T13	4		T19	2		T32	2
all_pins[5]	transitions[0x1=>0x0]	824	1			T6	8		T89	1		T111	7
all_pins[6]	values[0x0]	111584	1			T1	2		T2	28		T3	37
all_pins[6]	values[0x1]	884	1			T6	8		T89	1		T111	7
all_pins[6]	transitions[0x0=>0x1]	824	1			T6	8		T89	1		T111	7
all_pins[6]	transitions[0x1=>0x0]	359	1			T6	16		T13	4		T14	2
all_pins[7]	values[0x0]	112049	1			T1	2		T2	28		T3	37
all_pins[7]	values[0x1]	419	1			T6	16		T13	4		T14	2
all_pins[7]	transitions[0x0=>0x1]	216	1			T13	1		T44	1		T17	17
all_pins[7]	transitions[0x1=>0x0]	22379	1			T2	26		T3	11		T5	1