Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	8015018	1			T2	34		T3	15		T4	44
all_levels[1]	1438834	1			T2	2		T4	2		T6	371
all_levels[2]	802469	1			T2	2		T6	3		T23	530
all_levels[3]	327389	1			T2	5		T6	10		T23	534
all_levels[4]	391521	1			T2	2		T4	2		T6	1
all_levels[5]	229614	1			T2	4		T23	536		T43	32
all_levels[6]	242577	1			T4	1		T23	536		T15	1
all_levels[7]	277758	1			T3	2		T23	557		T15	1
all_levels[8]	371254	1			T3	53224		T23	790		T15	5
all_levels[9]	273644	1			T2	4		T6	3		T11	2
all_levels[10]	392049	1			T23	790		T15	20		T43	37
all_levels[11]	393814	1			T6	7		T8	2		T23	786
all_levels[12]	533963	1			T6	5		T23	787		T15	1
all_levels[13]	297090	1			T23	768		T15	2		T43	38
all_levels[14]	217737	1			T23	789		T15	2		T43	28
all_levels[15]	216659	1			T4	1		T11	2		T23	788
all_levels[16]	358678	1			T4	1		T23	790		T43	32
all_levels[17]	256628	1			T23	791		T15	6		T43	29
all_levels[18]	282945	1			T23	790		T15	1		T43	27
all_levels[19]	215556	1			T6	3		T23	790		T43	24
all_levels[20]	399883	1			T6	5		T23	788		T15	2
all_levels[21]	218086	1			T23	790		T15	1		T43	26
all_levels[22]	207649	1			T6	1		T23	782		T43	34
all_levels[23]	303712	1			T23	772		T43	31		T13	338
all_levels[24]	186231	1			T23	749		T15	1		T43	35
all_levels[25]	320841	1			T6	1		T23	51199		T15	7
all_levels[26]	405788	1			T6	2		T23	281		T43	27
all_levels[27]	168920	1			T6	1		T23	281		T15	2
all_levels[28]	278208	1			T23	278		T43	32		T89	1
all_levels[29]	235681	1			T23	281		T43	30		T13	374
all_levels[30]	520172	1			T23	281		T43	43		T13	293
all_levels[31]	463406	1			T6	4		T23	1926		T43	863
all_levels[32]	12058353	1			T5	13		T6	1		T8	7

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31297966

1

T2

51

T3

53225

T4

51

auto[1]

4161

1

T2

2

T3

16

T5

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	8012822	1			T2	34		T4	44		T5	3
all_levels[0]	auto[1]	2196	1			T3	15		T6	21		T8	5
all_levels[1]	auto[0]	1438491	1			T2	2		T4	2		T6	371
all_levels[1]	auto[1]	343	1			T7	1		T31	1		T42	1
all_levels[2]	auto[0]	802436	1			T2	2		T6	3		T23	530
all_levels[2]	auto[1]	33	1			T129	1		T190	2		T216	1
all_levels[3]	auto[0]	327225	1			T2	5		T6	10		T23	534
all_levels[3]	auto[1]	164	1			T293	7		T118	11		T215	1
all_levels[4]	auto[0]	391493	1			T2	2		T4	2		T6	1
all_levels[4]	auto[1]	28	1			T124	1		T181	1		T195	1
all_levels[5]	auto[0]	229595	1			T2	4		T23	536		T43	32
all_levels[5]	auto[1]	19	1			T266	1		T163	3		T201	1
all_levels[6]	auto[0]	242540	1			T4	1		T23	536		T15	1
all_levels[6]	auto[1]	37	1			T112	2		T257	1		T216	1
all_levels[7]	auto[0]	277573	1			T3	1		T23	557		T15	1
all_levels[7]	auto[1]	185	1			T3	1		T183	2		T273	14
all_levels[8]	auto[0]	371235	1			T3	53224		T23	790		T15	5
all_levels[8]	auto[1]	19	1			T104	1		T284	1		T129	1
all_levels[9]	auto[0]	273613	1			T2	2		T6	3		T11	2
all_levels[9]	auto[1]	31	1			T2	2		T189	1		T113	1
all_levels[10]	auto[0]	392018	1			T23	790		T15	20		T43	37
all_levels[10]	auto[1]	31	1			T131	1		T34	1		T320	2
all_levels[11]	auto[0]	393785	1			T6	7		T8	2		T23	786
all_levels[11]	auto[1]	29	1			T112	1		T172	1		T282	1
all_levels[12]	auto[0]	533937	1			T6	5		T23	787		T15	1
all_levels[12]	auto[1]	26	1			T112	1		T194	1		T283	2
all_levels[13]	auto[0]	297067	1			T23	768		T15	2		T43	38
all_levels[13]	auto[1]	23	1			T131	2		T256	1		T108	1
all_levels[14]	auto[0]	217702	1			T23	789		T15	2		T43	28
all_levels[14]	auto[1]	35	1			T267	1		T279	1		T115	1
all_levels[15]	auto[0]	216497	1			T4	1		T11	2		T23	788
all_levels[15]	auto[1]	162	1			T14	2		T114	5		T322	1
all_levels[16]	auto[0]	358653	1			T4	1		T23	790		T43	32
all_levels[16]	auto[1]	25	1			T113	1		T184	2		T330	1
all_levels[17]	auto[0]	256611	1			T23	791		T15	5		T43	29
all_levels[17]	auto[1]	17	1			T15	1		T172	1		T62	1
all_levels[18]	auto[0]	282912	1			T23	790		T15	1		T43	27
all_levels[18]	auto[1]	33	1			T40	1		T104	1		T272	1
all_levels[19]	auto[0]	215527	1			T6	3		T23	790		T43	24
all_levels[19]	auto[1]	29	1			T128	1		T331	2		T330	3
all_levels[20]	auto[0]	399866	1			T6	5		T23	788		T15	2
all_levels[20]	auto[1]	17	1			T222	1		T201	1		T216	1
all_levels[21]	auto[0]	218074	1			T23	790		T15	1		T43	26
all_levels[21]	auto[1]	12	1			T144	2		T173	1		T332	1
all_levels[22]	auto[0]	207634	1			T6	1		T23	782		T43	34
all_levels[22]	auto[1]	15	1			T112	1		T333	2		T334	1
all_levels[23]	auto[0]	303695	1			T23	772		T43	31		T13	338
all_levels[23]	auto[1]	17	1			T134	1		T174	1		T335	1
all_levels[24]	auto[0]	186216	1			T23	749		T15	1		T43	35
all_levels[24]	auto[1]	15	1			T40	1		T276	1		T198	1
all_levels[25]	auto[0]	320830	1			T6	1		T23	51199		T15	7
all_levels[25]	auto[1]	11	1			T61	1		T336	1		T337	1
all_levels[26]	auto[0]	405777	1			T6	2		T23	281		T43	27
all_levels[26]	auto[1]	11	1			T189	1		T276	1		T129	1
all_levels[27]	auto[0]	168897	1			T6	1		T23	281		T15	2
all_levels[27]	auto[1]	23	1			T270	1		T334	1		T338	1
all_levels[28]	auto[0]	278197	1			T23	278		T43	32		T89	1
all_levels[28]	auto[1]	11	1			T321	1		T202	1		T339	1
all_levels[29]	auto[0]	235667	1			T23	281		T43	30		T13	374
all_levels[29]	auto[1]	14	1			T39	1		T284	1		T134	1
all_levels[30]	auto[0]	520158	1			T23	281		T43	43		T13	293
all_levels[30]	auto[1]	14	1			T279	4		T152	1		T203	1
all_levels[31]	auto[0]	463382	1			T6	4		T23	1926		T43	863
all_levels[31]	auto[1]	24	1			T102	1		T276	2		T282	1
all_levels[32]	auto[0]	12057841	1			T5	12		T6	1		T8	6
all_levels[32]	auto[1]	512	1			T5	1		T8	1		T23	1