Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	850	1			T13	12		T14	7		T22	7
all_values[1]	850	1			T13	12		T14	7		T22	7
all_values[2]	850	1			T13	12		T14	7		T22	7
all_values[3]	850	1			T13	12		T14	7		T22	7
all_values[4]	850	1			T13	12		T14	7		T22	7
all_values[5]	850	1			T13	12		T14	7		T22	7
all_values[6]	850	1			T13	12		T14	7		T22	7
all_values[7]	850	1			T13	12		T14	7		T22	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3708

1

T13

52

T14

27

T22

35

auto[1]

3092

1

T13

44

T14

29

T22

21

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2472

1

T13

37

T14

17

T22

20

auto[1]

4328

1

T13

59

T14

39

T22

36

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4025

1

T13

59

T14

32

T22

33

auto[1]

2775

1

T13

37

T14

24

T22

23

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	4	44	91.67	4
Automatically Generated Cross Bins	48	4	44	91.67	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	279	1			T13	4		T22	4		T32	4
all_values[0]	auto[0]	auto[1]	auto[1]	228	1			T13	3		T14	4		T22	1
all_values[0]	auto[1]	auto[0]	auto[1]	183	1			T13	3		T22	2		T32	2
all_values[0]	auto[1]	auto[1]	auto[1]	160	1			T13	2		T14	3		T32	4
all_values[1]	auto[0]	auto[0]	auto[0]	269	1			T13	3		T14	2		T22	1
all_values[1]	auto[0]	auto[1]	auto[0]	240	1			T13	5		T14	2		T22	1
all_values[1]	auto[1]	auto[0]	auto[1]	198	1			T13	2		T14	2		T22	4
all_values[1]	auto[1]	auto[1]	auto[1]	143	1			T13	2		T14	1		T22	1
all_values[2]	auto[0]	auto[0]	auto[0]	175	1			T13	2		T22	2		T32	3
all_values[2]	auto[0]	auto[0]	auto[1]	84	1			T13	1		T14	1		T32	2
all_values[2]	auto[0]	auto[1]	auto[0]	140	1			T13	3		T14	2		T22	1
all_values[2]	auto[0]	auto[1]	auto[1]	96	1			T13	2		T14	1		T22	2
all_values[2]	auto[1]	auto[0]	auto[1]	201	1			T13	3		T14	2		T32	5
all_values[2]	auto[1]	auto[1]	auto[1]	154	1			T13	1		T14	1		T22	2
all_values[3]	auto[0]	auto[0]	auto[0]	187	1			T13	2		T22	1		T32	5
all_values[3]	auto[0]	auto[0]	auto[1]	84	1			T13	3		T14	1		T22	2
all_values[3]	auto[0]	auto[1]	auto[0]	142	1			T13	1		T14	2		T22	1
all_values[3]	auto[0]	auto[1]	auto[1]	78	1			T14	2		T22	1		T34	1
all_values[3]	auto[1]	auto[0]	auto[1]	209	1			T13	4		T14	2		T22	1
all_values[3]	auto[1]	auto[1]	auto[1]	150	1			T13	2		T22	1		T32	4
all_values[4]	auto[0]	auto[0]	auto[0]	180	1			T13	4		T14	1		T22	2
all_values[4]	auto[0]	auto[0]	auto[1]	90	1			T14	1		T32	2		T34	1
all_values[4]	auto[0]	auto[1]	auto[0]	138	1			T13	2		T35	3		T36	1
all_values[4]	auto[0]	auto[1]	auto[1]	86	1			T13	2		T22	1		T34	2
all_values[4]	auto[1]	auto[0]	auto[1]	194	1			T13	3		T14	4		T22	2
all_values[4]	auto[1]	auto[1]	auto[1]	162	1			T13	1		T14	1		T22	2
all_values[5]	auto[0]	auto[0]	auto[0]	185	1			T13	4		T14	1		T22	2
all_values[5]	auto[0]	auto[0]	auto[1]	82	1			T22	1		T32	1		T36	1
all_values[5]	auto[0]	auto[1]	auto[0]	161	1			T14	3		T32	1		T34	2
all_values[5]	auto[0]	auto[1]	auto[1]	91	1			T13	3		T14	1		T32	1
all_values[5]	auto[1]	auto[0]	auto[1]	177	1			T13	3		T14	2		T22	3
all_values[5]	auto[1]	auto[1]	auto[1]	154	1			T13	2		T22	1		T32	3
all_values[6]	auto[0]	auto[0]	auto[0]	193	1			T13	4		T22	1		T32	4
all_values[6]	auto[0]	auto[0]	auto[1]	84	1			T14	2		T22	1		T32	1
all_values[6]	auto[0]	auto[1]	auto[0]	143	1			T13	5		T14	1		T22	2
all_values[6]	auto[0]	auto[1]	auto[1]	85	1			T13	1		T32	1		T34	1
all_values[6]	auto[1]	auto[0]	auto[1]	200	1			T13	2		T14	2		T22	2
all_values[6]	auto[1]	auto[1]	auto[1]	145	1			T14	2		T22	1		T32	3
all_values[7]	auto[0]	auto[0]	auto[0]	165	1			T13	1		T14	1		T22	3
all_values[7]	auto[0]	auto[0]	auto[1]	97	1			T14	2		T32	1		T34	2
all_values[7]	auto[0]	auto[1]	auto[0]	154	1			T13	1		T14	2		T22	3
all_values[7]	auto[0]	auto[1]	auto[1]	89	1			T13	3		T32	1		T34	2
all_values[7]	auto[1]	auto[0]	auto[1]	192	1			T13	4		T14	1		T22	1
all_values[7]	auto[1]	auto[1]	auto[1]	153	1			T13	3		T14	1		T32	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal