| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.27 | 99.27 | 97.95 | 100.00 | 98.80 | 100.00 | 99.61 |
| T1259 | /workspace/coverage/cover_reg_top/19.uart_intr_test.574778220 | Apr 21 01:01:10 PM PDT 24 | Apr 21 01:01:11 PM PDT 24 | 41210044 ps | ||
| T1260 | /workspace/coverage/cover_reg_top/26.uart_intr_test.1509699362 | Apr 21 01:01:17 PM PDT 24 | Apr 21 01:01:18 PM PDT 24 | 11136526 ps | ||
| T1261 | /workspace/coverage/cover_reg_top/19.uart_tl_errors.1381893802 | Apr 21 01:01:13 PM PDT 24 | Apr 21 01:01:14 PM PDT 24 | 55198398 ps | ||
| T1262 | /workspace/coverage/cover_reg_top/7.uart_tl_errors.2105956390 | Apr 21 01:01:04 PM PDT 24 | Apr 21 01:01:06 PM PDT 24 | 34559481 ps | ||
| T1263 | /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2593729103 | Apr 21 01:01:06 PM PDT 24 | Apr 21 01:01:07 PM PDT 24 | 49458379 ps | ||
| T1264 | /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.340731425 | Apr 21 01:01:12 PM PDT 24 | Apr 21 01:01:13 PM PDT 24 | 21888708 ps | ||
| T78 | /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.4190841559 | Apr 21 01:00:49 PM PDT 24 | Apr 21 01:00:50 PM PDT 24 | 15727506 ps | ||
| T1265 | /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2675427832 | Apr 21 01:00:54 PM PDT 24 | Apr 21 01:00:55 PM PDT 24 | 20381827 ps | ||
| T1266 | /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3007049934 | Apr 21 01:00:58 PM PDT 24 | Apr 21 01:01:01 PM PDT 24 | 676762554 ps | ||
| T1267 | /workspace/coverage/cover_reg_top/44.uart_intr_test.771918641 | Apr 21 01:01:17 PM PDT 24 | Apr 21 01:01:18 PM PDT 24 | 13426860 ps | ||
| T1268 | /workspace/coverage/cover_reg_top/4.uart_csr_rw.2530833079 | Apr 21 01:00:57 PM PDT 24 | Apr 21 01:00:58 PM PDT 24 | 16892730 ps | ||
| T1269 | /workspace/coverage/cover_reg_top/24.uart_intr_test.1732094075 | Apr 21 01:01:11 PM PDT 24 | Apr 21 01:01:12 PM PDT 24 | 51100638 ps | ||
| T1270 | /workspace/coverage/cover_reg_top/12.uart_intr_test.2054502337 | Apr 21 01:01:07 PM PDT 24 | Apr 21 01:01:08 PM PDT 24 | 99150040 ps | ||
| T1271 | /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.775660530 | Apr 21 01:01:00 PM PDT 24 | Apr 21 01:01:01 PM PDT 24 | 199001433 ps | ||
| T1272 | /workspace/coverage/cover_reg_top/11.uart_csr_rw.2220645922 | Apr 21 01:01:02 PM PDT 24 | Apr 21 01:01:04 PM PDT 24 | 26928755 ps | ||
| T1273 | /workspace/coverage/cover_reg_top/10.uart_intr_test.1851575564 | Apr 21 01:01:11 PM PDT 24 | Apr 21 01:01:12 PM PDT 24 | 11756476 ps | ||
| T1274 | /workspace/coverage/cover_reg_top/1.uart_intr_test.4171459822 | Apr 21 01:00:54 PM PDT 24 | Apr 21 01:00:56 PM PDT 24 | 13761383 ps | ||
| T1275 | /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.128472424 | Apr 21 01:01:07 PM PDT 24 | Apr 21 01:01:08 PM PDT 24 | 19188427 ps | ||
| T1276 | /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3771057561 | Apr 21 01:00:58 PM PDT 24 | Apr 21 01:00:59 PM PDT 24 | 20879953 ps | ||
| T1277 | /workspace/coverage/cover_reg_top/39.uart_intr_test.3132712121 | Apr 21 01:01:15 PM PDT 24 | Apr 21 01:01:16 PM PDT 24 | 139418377 ps | ||
| T1278 | /workspace/coverage/cover_reg_top/19.uart_csr_rw.3329047014 | Apr 21 01:01:10 PM PDT 24 | Apr 21 01:01:11 PM PDT 24 | 37328234 ps | ||
| T1279 | /workspace/coverage/cover_reg_top/8.uart_intr_test.2793949826 | Apr 21 01:01:01 PM PDT 24 | Apr 21 01:01:02 PM PDT 24 | 88128974 ps | ||
| T1280 | /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.2225769771 | Apr 21 01:00:55 PM PDT 24 | Apr 21 01:00:56 PM PDT 24 | 193162676 ps | ||
| T73 | /workspace/coverage/cover_reg_top/1.uart_csr_rw.2339864138 | Apr 21 01:00:52 PM PDT 24 | Apr 21 01:00:53 PM PDT 24 | 13252141 ps | ||
| T1281 | /workspace/coverage/cover_reg_top/6.uart_tl_errors.1838492403 | Apr 21 01:00:56 PM PDT 24 | Apr 21 01:00:58 PM PDT 24 | 842451884 ps | ||
| T1282 | /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1851197245 | Apr 21 01:00:53 PM PDT 24 | Apr 21 01:00:55 PM PDT 24 | 37722392 ps | ||
| T1283 | /workspace/coverage/cover_reg_top/27.uart_intr_test.2523806082 | Apr 21 01:01:12 PM PDT 24 | Apr 21 01:01:13 PM PDT 24 | 27461531 ps | ||
| T1284 | /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.467507677 | Apr 21 01:00:57 PM PDT 24 | Apr 21 01:00:58 PM PDT 24 | 16043098 ps | ||
| T1285 | /workspace/coverage/cover_reg_top/15.uart_tl_errors.3283613791 | Apr 21 01:01:11 PM PDT 24 | Apr 21 01:01:12 PM PDT 24 | 221335373 ps | ||
| T1286 | /workspace/coverage/cover_reg_top/5.uart_intr_test.3305949457 | Apr 21 01:01:03 PM PDT 24 | Apr 21 01:01:04 PM PDT 24 | 68267444 ps | ||
| T1287 | /workspace/coverage/cover_reg_top/34.uart_intr_test.1497080685 | Apr 21 01:01:17 PM PDT 24 | Apr 21 01:01:18 PM PDT 24 | 34582294 ps | ||
| T1288 | /workspace/coverage/cover_reg_top/8.uart_csr_rw.2456790028 | Apr 21 01:01:00 PM PDT 24 | Apr 21 01:01:01 PM PDT 24 | 107758674 ps | ||
| T1289 | /workspace/coverage/cover_reg_top/0.uart_intr_test.3534921024 | Apr 21 01:00:54 PM PDT 24 | Apr 21 01:00:55 PM PDT 24 | 48534974 ps | ||
| T1290 | /workspace/coverage/cover_reg_top/12.uart_tl_errors.2229253926 | Apr 21 01:01:08 PM PDT 24 | Apr 21 01:01:10 PM PDT 24 | 26256095 ps | ||
| T1291 | /workspace/coverage/cover_reg_top/14.uart_intr_test.3522269819 | Apr 21 01:01:04 PM PDT 24 | Apr 21 01:01:06 PM PDT 24 | 17277459 ps | ||
| T1292 | /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1193792826 | Apr 21 01:00:49 PM PDT 24 | Apr 21 01:00:51 PM PDT 24 | 22454724 ps | ||
| T1293 | /workspace/coverage/cover_reg_top/42.uart_intr_test.3694903082 | Apr 21 01:01:14 PM PDT 24 | Apr 21 01:01:15 PM PDT 24 | 12508026 ps | ||
| T1294 | /workspace/coverage/cover_reg_top/36.uart_intr_test.3133325121 | Apr 21 01:01:17 PM PDT 24 | Apr 21 01:01:19 PM PDT 24 | 15866702 ps | ||
| T79 | /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2428133857 | Apr 21 01:00:50 PM PDT 24 | Apr 21 01:00:51 PM PDT 24 | 120801392 ps | ||
| T1295 | /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3228842835 | Apr 21 01:00:54 PM PDT 24 | Apr 21 01:00:56 PM PDT 24 | 62971583 ps | ||
| T1296 | /workspace/coverage/cover_reg_top/22.uart_intr_test.829334351 | Apr 21 01:01:09 PM PDT 24 | Apr 21 01:01:09 PM PDT 24 | 11050942 ps | ||
| T93 | /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1128301626 | Apr 21 01:00:52 PM PDT 24 | Apr 21 01:00:53 PM PDT 24 | 56388059 ps | ||
| T1297 | /workspace/coverage/cover_reg_top/4.uart_intr_test.1419259748 | Apr 21 01:00:58 PM PDT 24 | Apr 21 01:00:59 PM PDT 24 | 57028179 ps | ||
| T94 | /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3217925651 | Apr 21 01:01:08 PM PDT 24 | Apr 21 01:01:10 PM PDT 24 | 220222498 ps | ||
| T1298 | /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1808422907 | Apr 21 01:01:10 PM PDT 24 | Apr 21 01:01:11 PM PDT 24 | 45808574 ps | ||
| T1299 | /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3853044423 | Apr 21 01:01:03 PM PDT 24 | Apr 21 01:01:04 PM PDT 24 | 25813688 ps | ||
| T95 | /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.4154003808 | Apr 21 01:01:04 PM PDT 24 | Apr 21 01:01:06 PM PDT 24 | 93921267 ps | ||
| T1300 | /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2198285556 | Apr 21 01:01:09 PM PDT 24 | Apr 21 01:01:10 PM PDT 24 | 19275927 ps | ||
| T1301 | /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1598825144 | Apr 21 01:01:02 PM PDT 24 | Apr 21 01:01:03 PM PDT 24 | 54935236 ps | ||
| T1302 | /workspace/coverage/cover_reg_top/15.uart_csr_rw.1006783125 | Apr 21 01:01:07 PM PDT 24 | Apr 21 01:01:08 PM PDT 24 | 21709970 ps | ||
| T1303 | /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3303777571 | Apr 21 01:01:09 PM PDT 24 | Apr 21 01:01:11 PM PDT 24 | 215370866 ps | ||
| T1304 | /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1062185267 | Apr 21 01:00:56 PM PDT 24 | Apr 21 01:00:57 PM PDT 24 | 15623014 ps | ||
| T1305 | /workspace/coverage/cover_reg_top/28.uart_intr_test.1319899450 | Apr 21 01:01:12 PM PDT 24 | Apr 21 01:01:13 PM PDT 24 | 44996258 ps | ||
| T1306 | /workspace/coverage/cover_reg_top/4.uart_tl_errors.2793983461 | Apr 21 01:00:53 PM PDT 24 | Apr 21 01:00:55 PM PDT 24 | 417136575 ps | ||
| T1307 | /workspace/coverage/cover_reg_top/17.uart_tl_errors.410710265 | Apr 21 01:01:08 PM PDT 24 | Apr 21 01:01:10 PM PDT 24 | 298481719 ps | ||
| T1308 | /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.488361155 | Apr 21 01:00:56 PM PDT 24 | Apr 21 01:00:57 PM PDT 24 | 167841078 ps | ||
| T74 | /workspace/coverage/cover_reg_top/16.uart_csr_rw.3520745176 | Apr 21 01:01:11 PM PDT 24 | Apr 21 01:01:12 PM PDT 24 | 17471527 ps | ||
| T1309 | /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.640571612 | Apr 21 01:01:03 PM PDT 24 | Apr 21 01:01:05 PM PDT 24 | 189707568 ps | ||
| T1310 | /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.886176646 | Apr 21 01:00:59 PM PDT 24 | Apr 21 01:01:00 PM PDT 24 | 54832112 ps | ||
| T1311 | /workspace/coverage/cover_reg_top/7.uart_csr_rw.676680051 | Apr 21 01:01:03 PM PDT 24 | Apr 21 01:01:04 PM PDT 24 | 12110366 ps | ||
| T1312 | /workspace/coverage/cover_reg_top/10.uart_tl_errors.2308831 | Apr 21 01:01:02 PM PDT 24 | Apr 21 01:01:04 PM PDT 24 | 61314276 ps | ||
| T1313 | /workspace/coverage/cover_reg_top/18.uart_csr_rw.3650861421 | Apr 21 01:01:10 PM PDT 24 | Apr 21 01:01:11 PM PDT 24 | 29584969 ps | ||
| T1314 | /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1972483902 | Apr 21 01:01:02 PM PDT 24 | Apr 21 01:01:03 PM PDT 24 | 136231064 ps | ||
| T1315 | /workspace/coverage/cover_reg_top/3.uart_intr_test.4078610392 | Apr 21 01:00:53 PM PDT 24 | Apr 21 01:00:54 PM PDT 24 | 23691695 ps | ||
| T1316 | /workspace/coverage/cover_reg_top/14.uart_tl_errors.3328581566 | Apr 21 01:01:07 PM PDT 24 | Apr 21 01:01:09 PM PDT 24 | 221072676 ps | ||
| T1317 | /workspace/coverage/cover_reg_top/33.uart_intr_test.384270988 | Apr 21 01:01:14 PM PDT 24 | Apr 21 01:01:15 PM PDT 24 | 39133066 ps | ||
| T1318 | /workspace/coverage/cover_reg_top/40.uart_intr_test.4215495584 | Apr 21 01:01:15 PM PDT 24 | Apr 21 01:01:16 PM PDT 24 | 42735051 ps | ||
| T1319 | /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.4158552277 | Apr 21 01:00:53 PM PDT 24 | Apr 21 01:00:55 PM PDT 24 | 377278444 ps | ||
| T123 | /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.2212209231 | Apr 21 01:01:10 PM PDT 24 | Apr 21 01:01:13 PM PDT 24 | 955791288 ps | ||
| T1320 | /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1973895812 | Apr 21 01:01:02 PM PDT 24 | Apr 21 01:01:04 PM PDT 24 | 74996549 ps |
| Test location | /workspace/coverage/default/3.uart_stress_all.718795192 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 372856418198 ps |
| CPU time | 249.81 seconds |
| Started | Apr 21 04:26:07 PM PDT 24 |
| Finished | Apr 21 04:30:17 PM PDT 24 |
| Peak memory | 200884 kb |
| Host | smart-47fcbfcd-dd45-476b-8067-2db654919a00 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718795192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.718795192 |
| Directory | /workspace/3.uart_stress_all/latest |
| Test location | /workspace/coverage/default/60.uart_stress_all_with_rand_reset.1214194862 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 102828321929 ps |
| CPU time | 856.58 seconds |
| Started | Apr 21 04:35:38 PM PDT 24 |
| Finished | Apr 21 04:49:55 PM PDT 24 |
| Peak memory | 225808 kb |
| Host | smart-fd588288-63db-4d23-b56b-e2ac95412c6c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214194862 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.1214194862 |
| Directory | /workspace/60.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/20.uart_stress_all.3926874497 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 305660816132 ps |
| CPU time | 232.15 seconds |
| Started | Apr 21 04:29:58 PM PDT 24 |
| Finished | Apr 21 04:33:50 PM PDT 24 |
| Peak memory | 216972 kb |
| Host | smart-aecc2d0d-74b8-42ba-9ce3-72e27600bf6d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926874497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.3926874497 |
| Directory | /workspace/20.uart_stress_all/latest |
| Test location | /workspace/coverage/default/19.uart_stress_all_with_rand_reset.1644800782 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 455475842463 ps |
| CPU time | 691.01 seconds |
| Started | Apr 21 04:29:49 PM PDT 24 |
| Finished | Apr 21 04:41:21 PM PDT 24 |
| Peak memory | 225732 kb |
| Host | smart-259b4930-de36-4cae-9b22-256eb475dcc2 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644800782 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.1644800782 |
| Directory | /workspace/19.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/12.uart_stress_all_with_rand_reset.3734806622 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 362078907385 ps |
| CPU time | 651.99 seconds |
| Started | Apr 21 04:28:16 PM PDT 24 |
| Finished | Apr 21 04:39:09 PM PDT 24 |
| Peak memory | 217364 kb |
| Host | smart-441e0b6d-db6b-462f-8116-aa7e81ae51f0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734806622 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.3734806622 |
| Directory | /workspace/12.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/34.uart_stress_all_with_rand_reset.1181319907 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 100503806454 ps |
| CPU time | 763.41 seconds |
| Started | Apr 21 04:32:35 PM PDT 24 |
| Finished | Apr 21 04:45:19 PM PDT 24 |
| Peak memory | 217212 kb |
| Host | smart-a2a6b965-9a75-47bc-ac56-1704b42771e8 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181319907 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.1181319907 |
| Directory | /workspace/34.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/75.uart_stress_all_with_rand_reset.2569095338 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 83073425643 ps |
| CPU time | 1068.38 seconds |
| Started | Apr 21 04:36:01 PM PDT 24 |
| Finished | Apr 21 04:53:50 PM PDT 24 |
| Peak memory | 217536 kb |
| Host | smart-15ce0963-c10b-42ec-9be0-7f1692f2b268 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569095338 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.2569095338 |
| Directory | /workspace/75.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.uart_sec_cm.1107044143 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 37749063 ps |
| CPU time | 0.79 seconds |
| Started | Apr 21 04:25:17 PM PDT 24 |
| Finished | Apr 21 04:25:18 PM PDT 24 |
| Peak memory | 218876 kb |
| Host | smart-c62f3b83-8413-426d-9db4-ed973ebf86e7 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107044143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.1107044143 |
| Directory | /workspace/0.uart_sec_cm/latest |
| Test location | /workspace/coverage/default/48.uart_stress_all.3553244253 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 725740760801 ps |
| CPU time | 129.43 seconds |
| Started | Apr 21 04:35:14 PM PDT 24 |
| Finished | Apr 21 04:37:24 PM PDT 24 |
| Peak memory | 200844 kb |
| Host | smart-ab68dac8-3819-437d-8b59-762c0e8be46f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553244253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.3553244253 |
| Directory | /workspace/48.uart_stress_all/latest |
| Test location | /workspace/coverage/default/93.uart_stress_all_with_rand_reset.998066015 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 134014637189 ps |
| CPU time | 369.19 seconds |
| Started | Apr 21 04:36:29 PM PDT 24 |
| Finished | Apr 21 04:42:38 PM PDT 24 |
| Peak memory | 217376 kb |
| Host | smart-683b3c68-eb16-44d7-b88c-0dcfe9bab259 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998066015 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.998066015 |
| Directory | /workspace/93.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/39.uart_stress_all.1652586517 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 280012832317 ps |
| CPU time | 585.5 seconds |
| Started | Apr 21 04:33:36 PM PDT 24 |
| Finished | Apr 21 04:43:22 PM PDT 24 |
| Peak memory | 216492 kb |
| Host | smart-3fee8137-46ff-4d63-a49a-f07b75800636 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652586517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.1652586517 |
| Directory | /workspace/39.uart_stress_all/latest |
| Test location | /workspace/coverage/default/45.uart_stress_all.1987942339 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 122116135770 ps |
| CPU time | 245.49 seconds |
| Started | Apr 21 04:34:42 PM PDT 24 |
| Finished | Apr 21 04:38:48 PM PDT 24 |
| Peak memory | 200964 kb |
| Host | smart-54b4749f-d3f4-4ec8-8115-13b1d26d7685 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987942339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.1987942339 |
| Directory | /workspace/45.uart_stress_all/latest |
| Test location | /workspace/coverage/default/99.uart_stress_all_with_rand_reset.2142192691 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 133641998497 ps |
| CPU time | 497.98 seconds |
| Started | Apr 21 04:36:39 PM PDT 24 |
| Finished | Apr 21 04:44:57 PM PDT 24 |
| Peak memory | 225692 kb |
| Host | smart-b8320e45-0e0e-4f2b-a68e-00639dfb97bf |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142192691 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.2142192691 |
| Directory | /workspace/99.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/19.uart_long_xfer_wo_dly.3604220325 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 111678356535 ps |
| CPU time | 283.36 seconds |
| Started | Apr 21 04:29:45 PM PDT 24 |
| Finished | Apr 21 04:34:29 PM PDT 24 |
| Peak memory | 200912 kb |
| Host | smart-e43e4173-a1e2-4627-8640-43d1514dd7ee |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3604220325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.3604220325 |
| Directory | /workspace/19.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/11.uart_fifo_overflow.2897768204 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 293770341433 ps |
| CPU time | 234.67 seconds |
| Started | Apr 21 04:27:50 PM PDT 24 |
| Finished | Apr 21 04:31:45 PM PDT 24 |
| Peak memory | 200844 kb |
| Host | smart-e6585f53-c42f-424f-9cc4-5d9903bcee6c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2897768204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.2897768204 |
| Directory | /workspace/11.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/15.uart_stress_all_with_rand_reset.2264050530 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 212603182074 ps |
| CPU time | 1093.18 seconds |
| Started | Apr 21 04:29:02 PM PDT 24 |
| Finished | Apr 21 04:47:15 PM PDT 24 |
| Peak memory | 228744 kb |
| Host | smart-4ae5607d-741b-4320-a921-2621e63276aa |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264050530 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.2264050530 |
| Directory | /workspace/15.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/47.uart_stress_all.765276840 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 161434818989 ps |
| CPU time | 1386.62 seconds |
| Started | Apr 21 04:35:03 PM PDT 24 |
| Finished | Apr 21 04:58:11 PM PDT 24 |
| Peak memory | 200912 kb |
| Host | smart-424541ec-7b95-4abf-9bbe-309441166713 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765276840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.765276840 |
| Directory | /workspace/47.uart_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1767118437 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 152623332 ps |
| CPU time | 1.27 seconds |
| Started | Apr 21 01:01:08 PM PDT 24 |
| Finished | Apr 21 01:01:10 PM PDT 24 |
| Peak memory | 199156 kb |
| Host | smart-a3548376-66e7-43c6-a415-de68f3417693 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767118437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.1767118437 |
| Directory | /workspace/11.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.uart_alert_test.2291163420 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 43764800 ps |
| CPU time | 0.62 seconds |
| Started | Apr 21 04:25:18 PM PDT 24 |
| Finished | Apr 21 04:25:18 PM PDT 24 |
| Peak memory | 195684 kb |
| Host | smart-45a7f284-e1f5-4340-a038-1522f4e53609 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291163420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2291163420 |
| Directory | /workspace/0.uart_alert_test/latest |
| Test location | /workspace/coverage/default/29.uart_stress_all_with_rand_reset.596032545 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 165548733094 ps |
| CPU time | 745.1 seconds |
| Started | Apr 21 04:31:37 PM PDT 24 |
| Finished | Apr 21 04:44:03 PM PDT 24 |
| Peak memory | 217356 kb |
| Host | smart-b9d6ba58-d0a4-4293-8368-3f97a7a7aa5b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596032545 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.596032545 |
| Directory | /workspace/29.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/43.uart_long_xfer_wo_dly.1653020440 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 96488010635 ps |
| CPU time | 558.87 seconds |
| Started | Apr 21 04:34:22 PM PDT 24 |
| Finished | Apr 21 04:43:41 PM PDT 24 |
| Peak memory | 200924 kb |
| Host | smart-a721eb5e-0c32-4c23-99b0-5954ac343870 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1653020440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.1653020440 |
| Directory | /workspace/43.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/10.uart_stress_all.2176679683 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 293835097535 ps |
| CPU time | 1165.59 seconds |
| Started | Apr 21 04:27:47 PM PDT 24 |
| Finished | Apr 21 04:47:13 PM PDT 24 |
| Peak memory | 200908 kb |
| Host | smart-794f418b-3748-41e0-a5da-0f1153cdcab2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176679683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.2176679683 |
| Directory | /workspace/10.uart_stress_all/latest |
| Test location | /workspace/coverage/default/24.uart_stress_all.3438483700 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 99889046566 ps |
| CPU time | 481.03 seconds |
| Started | Apr 21 04:30:42 PM PDT 24 |
| Finished | Apr 21 04:38:44 PM PDT 24 |
| Peak memory | 200840 kb |
| Host | smart-4338d4d1-2d0b-4136-989d-0464e71fc456 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438483700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.3438483700 |
| Directory | /workspace/24.uart_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_csr_rw.3488224192 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 30068822 ps |
| CPU time | 0.61 seconds |
| Started | Apr 21 01:00:49 PM PDT 24 |
| Finished | Apr 21 01:00:50 PM PDT 24 |
| Peak memory | 195440 kb |
| Host | smart-c3541209-2a16-4eec-84e7-cef38872e22d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488224192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.3488224192 |
| Directory | /workspace/0.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_csr_rw.2339864138 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 13252141 ps |
| CPU time | 0.6 seconds |
| Started | Apr 21 01:00:52 PM PDT 24 |
| Finished | Apr 21 01:00:53 PM PDT 24 |
| Peak memory | 195744 kb |
| Host | smart-6412209d-d30d-4f8b-8173-210161e5f9c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339864138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.2339864138 |
| Directory | /workspace/1.uart_csr_rw/latest |
| Test location | /workspace/coverage/default/179.uart_fifo_reset.3787383141 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 67332610263 ps |
| CPU time | 51.52 seconds |
| Started | Apr 21 04:38:04 PM PDT 24 |
| Finished | Apr 21 04:38:55 PM PDT 24 |
| Peak memory | 200908 kb |
| Host | smart-4f11213c-bdbe-4e8d-9787-b8674dcbf020 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3787383141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.3787383141 |
| Directory | /workspace/179.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/35.uart_rx_parity_err.866217404 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 19462963584 ps |
| CPU time | 35.33 seconds |
| Started | Apr 21 04:32:47 PM PDT 24 |
| Finished | Apr 21 04:33:23 PM PDT 24 |
| Peak memory | 200852 kb |
| Host | smart-cb68173b-b0b5-43bd-81b0-7295c5520959 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=866217404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.866217404 |
| Directory | /workspace/35.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/175.uart_fifo_reset.3611039339 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 196479081715 ps |
| CPU time | 220.46 seconds |
| Started | Apr 21 04:37:56 PM PDT 24 |
| Finished | Apr 21 04:41:37 PM PDT 24 |
| Peak memory | 200872 kb |
| Host | smart-941a4b77-a525-40f0-8e72-3798dc096831 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3611039339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.3611039339 |
| Directory | /workspace/175.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/41.uart_stress_all_with_rand_reset.1343076904 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 238499820168 ps |
| CPU time | 1163.54 seconds |
| Started | Apr 21 04:34:00 PM PDT 24 |
| Finished | Apr 21 04:53:24 PM PDT 24 |
| Peak memory | 217164 kb |
| Host | smart-c141d438-9d4b-497c-85ab-d3397e2cfb40 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343076904 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.1343076904 |
| Directory | /workspace/41.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/10.uart_fifo_full.71451293 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 118455742740 ps |
| CPU time | 242.15 seconds |
| Started | Apr 21 04:27:36 PM PDT 24 |
| Finished | Apr 21 04:31:38 PM PDT 24 |
| Peak memory | 200868 kb |
| Host | smart-1cb0b7fe-f7d4-4625-80b2-a1585fa3eee9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=71451293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.71451293 |
| Directory | /workspace/10.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/32.uart_stress_all_with_rand_reset.47904374 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 33330056584 ps |
| CPU time | 213.25 seconds |
| Started | Apr 21 04:32:13 PM PDT 24 |
| Finished | Apr 21 04:35:46 PM PDT 24 |
| Peak memory | 217360 kb |
| Host | smart-8f53dc48-88a1-465a-99b5-05d535324977 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47904374 -assert nopostpro c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.47904374 |
| Directory | /workspace/32.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/16.uart_perf.3629780634 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 7261537966 ps |
| CPU time | 72.08 seconds |
| Started | Apr 21 04:29:11 PM PDT 24 |
| Finished | Apr 21 04:30:23 PM PDT 24 |
| Peak memory | 200868 kb |
| Host | smart-1931e54f-f234-416b-b583-743753eab995 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3629780634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.3629780634 |
| Directory | /workspace/16.uart_perf/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1128301626 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 56388059 ps |
| CPU time | 0.95 seconds |
| Started | Apr 21 01:00:52 PM PDT 24 |
| Finished | Apr 21 01:00:53 PM PDT 24 |
| Peak memory | 198896 kb |
| Host | smart-c53b5b6f-b413-4b07-b211-a99f7fa8655e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128301626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.1128301626 |
| Directory | /workspace/2.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/default/4.uart_stress_all_with_rand_reset.2810734507 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 52372965431 ps |
| CPU time | 302.32 seconds |
| Started | Apr 21 04:26:24 PM PDT 24 |
| Finished | Apr 21 04:31:27 PM PDT 24 |
| Peak memory | 217472 kb |
| Host | smart-6bcf4aee-c417-4e8c-8729-d94173381a5c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810734507 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.2810734507 |
| Directory | /workspace/4.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/7.uart_stress_all.3217920720 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 138180448053 ps |
| CPU time | 155.78 seconds |
| Started | Apr 21 04:27:06 PM PDT 24 |
| Finished | Apr 21 04:29:42 PM PDT 24 |
| Peak memory | 200828 kb |
| Host | smart-1c73d3d4-4e3b-4465-b50b-f2b549e0ecc2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217920720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.3217920720 |
| Directory | /workspace/7.uart_stress_all/latest |
| Test location | /workspace/coverage/default/22.uart_fifo_overflow.2892116017 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 137387504691 ps |
| CPU time | 275.62 seconds |
| Started | Apr 21 04:30:12 PM PDT 24 |
| Finished | Apr 21 04:34:48 PM PDT 24 |
| Peak memory | 200836 kb |
| Host | smart-43e8c7f1-8c3f-47dd-bd2a-a8732fc16cd7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2892116017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2892116017 |
| Directory | /workspace/22.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/30.uart_fifo_reset.4028880058 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 96748420852 ps |
| CPU time | 65.53 seconds |
| Started | Apr 21 04:31:41 PM PDT 24 |
| Finished | Apr 21 04:32:47 PM PDT 24 |
| Peak memory | 200896 kb |
| Host | smart-7a24dd33-affd-4cb5-a8d2-30467de95c72 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4028880058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.4028880058 |
| Directory | /workspace/30.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/73.uart_fifo_reset.2076411848 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 15037895150 ps |
| CPU time | 30.46 seconds |
| Started | Apr 21 04:36:03 PM PDT 24 |
| Finished | Apr 21 04:36:34 PM PDT 24 |
| Peak memory | 200928 kb |
| Host | smart-22340700-8363-4046-acc3-29cb8b1b787f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2076411848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2076411848 |
| Directory | /workspace/73.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/103.uart_fifo_reset.504964792 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 52956171732 ps |
| CPU time | 158.77 seconds |
| Started | Apr 21 04:36:45 PM PDT 24 |
| Finished | Apr 21 04:39:24 PM PDT 24 |
| Peak memory | 200924 kb |
| Host | smart-3c471cfc-1e08-41a6-b65d-cff597c12112 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=504964792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.504964792 |
| Directory | /workspace/103.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/232.uart_fifo_reset.3219122734 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 64392926075 ps |
| CPU time | 31.78 seconds |
| Started | Apr 21 04:38:43 PM PDT 24 |
| Finished | Apr 21 04:39:15 PM PDT 24 |
| Peak memory | 200808 kb |
| Host | smart-d5b86185-3831-4640-ae26-20cfed8cdea1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3219122734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.3219122734 |
| Directory | /workspace/232.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/267.uart_fifo_reset.1109163451 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 217640773271 ps |
| CPU time | 132.12 seconds |
| Started | Apr 21 04:39:11 PM PDT 24 |
| Finished | Apr 21 04:41:24 PM PDT 24 |
| Peak memory | 200924 kb |
| Host | smart-d4d60b9b-da9a-481c-b301-4de668340ae6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1109163451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.1109163451 |
| Directory | /workspace/267.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/75.uart_fifo_reset.495928029 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 104423988140 ps |
| CPU time | 31.22 seconds |
| Started | Apr 21 04:36:03 PM PDT 24 |
| Finished | Apr 21 04:36:34 PM PDT 24 |
| Peak memory | 200664 kb |
| Host | smart-b5c94571-57f3-4ae6-94d5-ceb847ab23a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=495928029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.495928029 |
| Directory | /workspace/75.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/132.uart_fifo_reset.1103948844 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 24435457583 ps |
| CPU time | 15.53 seconds |
| Started | Apr 21 04:37:13 PM PDT 24 |
| Finished | Apr 21 04:37:29 PM PDT 24 |
| Peak memory | 200828 kb |
| Host | smart-266c73b2-91ca-4709-a756-9650954e4b94 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1103948844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.1103948844 |
| Directory | /workspace/132.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/154.uart_fifo_reset.1633364390 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 168576812180 ps |
| CPU time | 72.77 seconds |
| Started | Apr 21 04:37:33 PM PDT 24 |
| Finished | Apr 21 04:38:46 PM PDT 24 |
| Peak memory | 200924 kb |
| Host | smart-31e23cd2-00fd-43a0-97c3-3e4e7e0b736f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1633364390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.1633364390 |
| Directory | /workspace/154.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/258.uart_fifo_reset.608698594 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 18237605404 ps |
| CPU time | 32.84 seconds |
| Started | Apr 21 04:39:04 PM PDT 24 |
| Finished | Apr 21 04:39:38 PM PDT 24 |
| Peak memory | 200864 kb |
| Host | smart-fcacb214-3219-451e-a199-b802eddd1130 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=608698594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.608698594 |
| Directory | /workspace/258.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/287.uart_fifo_reset.2314467906 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 94446281576 ps |
| CPU time | 46.54 seconds |
| Started | Apr 21 04:39:23 PM PDT 24 |
| Finished | Apr 21 04:40:10 PM PDT 24 |
| Peak memory | 200924 kb |
| Host | smart-cf8ab9e1-40c1-4eaa-94cb-0dc7653329a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2314467906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.2314467906 |
| Directory | /workspace/287.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/109.uart_fifo_reset.2644256103 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 107063404058 ps |
| CPU time | 166.97 seconds |
| Started | Apr 21 04:36:48 PM PDT 24 |
| Finished | Apr 21 04:39:35 PM PDT 24 |
| Peak memory | 200896 kb |
| Host | smart-18187498-6fea-4019-b8a5-3bf7c09aa25b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2644256103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.2644256103 |
| Directory | /workspace/109.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/12.uart_rx_parity_err.4075040244 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 93638791849 ps |
| CPU time | 46.81 seconds |
| Started | Apr 21 04:28:19 PM PDT 24 |
| Finished | Apr 21 04:29:06 PM PDT 24 |
| Peak memory | 200856 kb |
| Host | smart-b71ea878-d767-4321-96dc-f2551c83ea32 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4075040244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.4075040244 |
| Directory | /workspace/12.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/120.uart_fifo_reset.4187452199 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 540064055 ps |
| CPU time | 1.69 seconds |
| Started | Apr 21 04:37:01 PM PDT 24 |
| Finished | Apr 21 04:37:03 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-5e555579-c58e-44d3-b04a-22c9d1afdc73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4187452199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.4187452199 |
| Directory | /workspace/120.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/121.uart_fifo_reset.1487525638 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 41168565680 ps |
| CPU time | 70.94 seconds |
| Started | Apr 21 04:36:59 PM PDT 24 |
| Finished | Apr 21 04:38:10 PM PDT 24 |
| Peak memory | 200788 kb |
| Host | smart-48b51b56-3a3b-4878-a364-0bf0e0c1b9e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1487525638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.1487525638 |
| Directory | /workspace/121.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/127.uart_fifo_reset.2988059730 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 109296748451 ps |
| CPU time | 45.09 seconds |
| Started | Apr 21 04:37:09 PM PDT 24 |
| Finished | Apr 21 04:37:55 PM PDT 24 |
| Peak memory | 200940 kb |
| Host | smart-ad8cc38a-a102-468c-aafc-ef7ef110441a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2988059730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.2988059730 |
| Directory | /workspace/127.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/189.uart_fifo_reset.2693367347 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 24700126099 ps |
| CPU time | 51.98 seconds |
| Started | Apr 21 04:38:11 PM PDT 24 |
| Finished | Apr 21 04:39:03 PM PDT 24 |
| Peak memory | 200856 kb |
| Host | smart-373271b9-f18e-492a-8564-72481491a4b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2693367347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.2693367347 |
| Directory | /workspace/189.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/2.uart_tx_ovrd.244050933 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 12369630169 ps |
| CPU time | 41.95 seconds |
| Started | Apr 21 04:25:45 PM PDT 24 |
| Finished | Apr 21 04:26:27 PM PDT 24 |
| Peak memory | 200736 kb |
| Host | smart-cb386874-efe7-4797-bf4b-bbdaef437ceb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=244050933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.244050933 |
| Directory | /workspace/2.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/212.uart_fifo_reset.2192777781 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 47881771336 ps |
| CPU time | 41.52 seconds |
| Started | Apr 21 04:38:33 PM PDT 24 |
| Finished | Apr 21 04:39:14 PM PDT 24 |
| Peak memory | 200856 kb |
| Host | smart-f5d760e8-ad57-4a47-9fed-2cd1cfeb605c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2192777781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.2192777781 |
| Directory | /workspace/212.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/257.uart_fifo_reset.2958879757 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 157852397725 ps |
| CPU time | 87.76 seconds |
| Started | Apr 21 04:39:06 PM PDT 24 |
| Finished | Apr 21 04:40:34 PM PDT 24 |
| Peak memory | 200928 kb |
| Host | smart-6e78ddc7-b31e-44e6-a239-ac027ff08cc2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2958879757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.2958879757 |
| Directory | /workspace/257.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/27.uart_fifo_reset.3450152709 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 13959489674 ps |
| CPU time | 8.87 seconds |
| Started | Apr 21 04:31:05 PM PDT 24 |
| Finished | Apr 21 04:31:14 PM PDT 24 |
| Peak memory | 200880 kb |
| Host | smart-06920f97-9daf-40bc-ae08-8ee4e623067c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3450152709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.3450152709 |
| Directory | /workspace/27.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/80.uart_fifo_reset.3123920933 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 134965929083 ps |
| CPU time | 90.37 seconds |
| Started | Apr 21 04:36:06 PM PDT 24 |
| Finished | Apr 21 04:37:37 PM PDT 24 |
| Peak memory | 200884 kb |
| Host | smart-f4363979-8d18-4b00-8592-6caf20d3e7e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3123920933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.3123920933 |
| Directory | /workspace/80.uart_fifo_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.4158552277 |
| Short name | T1319 |
| Test name | |
| Test status | |
| Simulation time | 377278444 ps |
| CPU time | 1.37 seconds |
| Started | Apr 21 01:00:53 PM PDT 24 |
| Finished | Apr 21 01:00:55 PM PDT 24 |
| Peak memory | 199416 kb |
| Host | smart-d280b1a4-5146-4e95-b52f-2adba6776e48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158552277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.4158552277 |
| Directory | /workspace/1.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/default/106.uart_fifo_reset.3896976727 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 24264443497 ps |
| CPU time | 26.15 seconds |
| Started | Apr 21 04:36:46 PM PDT 24 |
| Finished | Apr 21 04:37:12 PM PDT 24 |
| Peak memory | 200952 kb |
| Host | smart-d7193749-0316-4409-8606-096be52fcdb1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3896976727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.3896976727 |
| Directory | /workspace/106.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/108.uart_fifo_reset.1549587567 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 13581115924 ps |
| CPU time | 22.17 seconds |
| Started | Apr 21 04:36:50 PM PDT 24 |
| Finished | Apr 21 04:37:12 PM PDT 24 |
| Peak memory | 200904 kb |
| Host | smart-f25e3187-a3e3-4488-9b84-a8c29d5cafc2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1549587567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1549587567 |
| Directory | /workspace/108.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/12.uart_fifo_reset.4256566114 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 43679292301 ps |
| CPU time | 38.99 seconds |
| Started | Apr 21 04:28:09 PM PDT 24 |
| Finished | Apr 21 04:28:48 PM PDT 24 |
| Peak memory | 200896 kb |
| Host | smart-32a15f95-9c9e-40d9-aaff-13bd3b3c51a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4256566114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.4256566114 |
| Directory | /workspace/12.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/13.uart_fifo_reset.2617658020 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 65071242190 ps |
| CPU time | 29.45 seconds |
| Started | Apr 21 04:28:22 PM PDT 24 |
| Finished | Apr 21 04:28:52 PM PDT 24 |
| Peak memory | 200868 kb |
| Host | smart-7c576f7a-0f90-4806-bcd9-228819ed19d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2617658020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.2617658020 |
| Directory | /workspace/13.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/13.uart_stress_all_with_rand_reset.3124887053 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 81812063852 ps |
| CPU time | 1220.69 seconds |
| Started | Apr 21 04:28:30 PM PDT 24 |
| Finished | Apr 21 04:48:51 PM PDT 24 |
| Peak memory | 225860 kb |
| Host | smart-d7cc9de5-e73d-47c9-ba94-73d3dfad7ea6 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124887053 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.3124887053 |
| Directory | /workspace/13.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/134.uart_fifo_reset.3036896279 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 9769494674 ps |
| CPU time | 19.66 seconds |
| Started | Apr 21 04:37:14 PM PDT 24 |
| Finished | Apr 21 04:37:34 PM PDT 24 |
| Peak memory | 200860 kb |
| Host | smart-76f3bd2a-680c-4ed0-b2b1-b8fc40f2e7da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3036896279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3036896279 |
| Directory | /workspace/134.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/159.uart_fifo_reset.2889294081 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 8334274008 ps |
| CPU time | 9.89 seconds |
| Started | Apr 21 04:37:34 PM PDT 24 |
| Finished | Apr 21 04:37:44 PM PDT 24 |
| Peak memory | 200928 kb |
| Host | smart-27217b70-a71e-4d71-905f-4248256dd665 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2889294081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2889294081 |
| Directory | /workspace/159.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/16.uart_stress_all_with_rand_reset.3331663680 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 208114397489 ps |
| CPU time | 517.41 seconds |
| Started | Apr 21 04:29:09 PM PDT 24 |
| Finished | Apr 21 04:37:47 PM PDT 24 |
| Peak memory | 217332 kb |
| Host | smart-19b15eb3-3b13-4e41-bf75-9e1622443a60 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331663680 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.3331663680 |
| Directory | /workspace/16.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/160.uart_fifo_reset.3630632849 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 62388713718 ps |
| CPU time | 102.79 seconds |
| Started | Apr 21 04:37:36 PM PDT 24 |
| Finished | Apr 21 04:39:19 PM PDT 24 |
| Peak memory | 200880 kb |
| Host | smart-fa3d3fc2-5b6d-4e61-afc7-769c52bf6660 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3630632849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.3630632849 |
| Directory | /workspace/160.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/19.uart_fifo_reset.61915182 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 58598854036 ps |
| CPU time | 26.97 seconds |
| Started | Apr 21 04:29:39 PM PDT 24 |
| Finished | Apr 21 04:30:07 PM PDT 24 |
| Peak memory | 200572 kb |
| Host | smart-7c7985e3-ec26-4a0c-af53-e3102d1f787c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=61915182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.61915182 |
| Directory | /workspace/19.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/195.uart_fifo_reset.2630952407 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 161689971849 ps |
| CPU time | 37.46 seconds |
| Started | Apr 21 04:38:21 PM PDT 24 |
| Finished | Apr 21 04:38:59 PM PDT 24 |
| Peak memory | 200924 kb |
| Host | smart-dd7b506b-ea00-4aa2-bdab-79b40b284435 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2630952407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.2630952407 |
| Directory | /workspace/195.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/198.uart_fifo_reset.3119838701 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 88676946002 ps |
| CPU time | 148.03 seconds |
| Started | Apr 21 04:38:23 PM PDT 24 |
| Finished | Apr 21 04:40:51 PM PDT 24 |
| Peak memory | 200904 kb |
| Host | smart-0a79becd-eb2f-4fde-a582-6c25e10a03fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3119838701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3119838701 |
| Directory | /workspace/198.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/4.uart_stress_all.2461095256 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 430516640229 ps |
| CPU time | 1285.1 seconds |
| Started | Apr 21 04:26:24 PM PDT 24 |
| Finished | Apr 21 04:47:49 PM PDT 24 |
| Peak memory | 200820 kb |
| Host | smart-0bae0109-5763-4af7-bcb8-d9da40b80b12 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461095256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2461095256 |
| Directory | /workspace/4.uart_stress_all/latest |
| Test location | /workspace/coverage/default/6.uart_fifo_reset.2132924403 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 31892599890 ps |
| CPU time | 28.11 seconds |
| Started | Apr 21 04:26:42 PM PDT 24 |
| Finished | Apr 21 04:27:11 PM PDT 24 |
| Peak memory | 200864 kb |
| Host | smart-ed4f0a75-6acc-4e3d-8713-857cee69b18b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2132924403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.2132924403 |
| Directory | /workspace/6.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/65.uart_stress_all_with_rand_reset.2142907550 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 82820365768 ps |
| CPU time | 628.39 seconds |
| Started | Apr 21 04:35:52 PM PDT 24 |
| Finished | Apr 21 04:46:21 PM PDT 24 |
| Peak memory | 225644 kb |
| Host | smart-6662603f-2122-4495-b29b-0b9b746083dd |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142907550 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.2142907550 |
| Directory | /workspace/65.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/68.uart_fifo_reset.3739635915 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 20404662441 ps |
| CPU time | 33.17 seconds |
| Started | Apr 21 04:35:54 PM PDT 24 |
| Finished | Apr 21 04:36:28 PM PDT 24 |
| Peak memory | 200864 kb |
| Host | smart-a60906c4-93dc-4ffd-b579-aa1476e01d49 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3739635915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.3739635915 |
| Directory | /workspace/68.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/74.uart_fifo_reset.1565387122 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 41977022865 ps |
| CPU time | 33.7 seconds |
| Started | Apr 21 04:36:03 PM PDT 24 |
| Finished | Apr 21 04:36:37 PM PDT 24 |
| Peak memory | 200684 kb |
| Host | smart-60936e44-1d6f-4955-8383-b6f85ba297d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1565387122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.1565387122 |
| Directory | /workspace/74.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/85.uart_fifo_reset.446997525 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 107766123462 ps |
| CPU time | 45.22 seconds |
| Started | Apr 21 04:36:14 PM PDT 24 |
| Finished | Apr 21 04:37:00 PM PDT 24 |
| Peak memory | 200776 kb |
| Host | smart-5d787588-1ce6-4822-9539-61634316c722 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=446997525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.446997525 |
| Directory | /workspace/85.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/91.uart_fifo_reset.1412267390 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 70704238477 ps |
| CPU time | 353.14 seconds |
| Started | Apr 21 04:36:24 PM PDT 24 |
| Finished | Apr 21 04:42:17 PM PDT 24 |
| Peak memory | 200884 kb |
| Host | smart-850e0ef3-9498-49cf-a74d-d26f40b9f485 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1412267390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.1412267390 |
| Directory | /workspace/91.uart_fifo_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2657628711 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 65534958 ps |
| CPU time | 0.63 seconds |
| Started | Apr 21 01:00:47 PM PDT 24 |
| Finished | Apr 21 01:00:48 PM PDT 24 |
| Peak memory | 194792 kb |
| Host | smart-837a0858-8656-4839-9f0b-a7ed5cb23d03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657628711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.2657628711 |
| Directory | /workspace/0.uart_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2278695481 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 37804352 ps |
| CPU time | 1.41 seconds |
| Started | Apr 21 01:00:47 PM PDT 24 |
| Finished | Apr 21 01:00:49 PM PDT 24 |
| Peak memory | 197928 kb |
| Host | smart-35b55674-4a31-40f7-9348-53bcff9ebaf2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278695481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.2278695481 |
| Directory | /workspace/0.uart_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.467507677 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 16043098 ps |
| CPU time | 0.58 seconds |
| Started | Apr 21 01:00:57 PM PDT 24 |
| Finished | Apr 21 01:00:58 PM PDT 24 |
| Peak memory | 195476 kb |
| Host | smart-cb967fda-9c92-4fc6-ad6b-563f1d89928c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467507677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.467507677 |
| Directory | /workspace/0.uart_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1193792826 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 22454724 ps |
| CPU time | 0.82 seconds |
| Started | Apr 21 01:00:49 PM PDT 24 |
| Finished | Apr 21 01:00:51 PM PDT 24 |
| Peak memory | 199236 kb |
| Host | smart-f67005a2-636d-4cd2-81a4-01d548eb9f0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193792826 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.1193792826 |
| Directory | /workspace/0.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_intr_test.3534921024 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 48534974 ps |
| CPU time | 0.57 seconds |
| Started | Apr 21 01:00:54 PM PDT 24 |
| Finished | Apr 21 01:00:55 PM PDT 24 |
| Peak memory | 194392 kb |
| Host | smart-e45f2adf-ecf0-475b-8483-67707feb6786 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534921024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.3534921024 |
| Directory | /workspace/0.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.4148474784 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 124252436 ps |
| CPU time | 0.87 seconds |
| Started | Apr 21 01:00:51 PM PDT 24 |
| Finished | Apr 21 01:00:52 PM PDT 24 |
| Peak memory | 197300 kb |
| Host | smart-29ad35fa-7d46-4a28-af18-00431d84f9f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148474784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr _outstanding.4148474784 |
| Directory | /workspace/0.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_tl_errors.3984999505 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 73680351 ps |
| CPU time | 1.92 seconds |
| Started | Apr 21 01:00:49 PM PDT 24 |
| Finished | Apr 21 01:00:52 PM PDT 24 |
| Peak memory | 200072 kb |
| Host | smart-54d61199-9a2d-42ac-b7a4-1c7fdc2020ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984999505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.3984999505 |
| Directory | /workspace/0.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.175339421 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 104581225 ps |
| CPU time | 1.37 seconds |
| Started | Apr 21 01:00:49 PM PDT 24 |
| Finished | Apr 21 01:00:51 PM PDT 24 |
| Peak memory | 199452 kb |
| Host | smart-b23838a4-f88a-4a97-8ff1-8421ca269db6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175339421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.175339421 |
| Directory | /workspace/0.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2428133857 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 120801392 ps |
| CPU time | 0.75 seconds |
| Started | Apr 21 01:00:50 PM PDT 24 |
| Finished | Apr 21 01:00:51 PM PDT 24 |
| Peak memory | 196412 kb |
| Host | smart-82055c00-c30a-4725-8cc6-45305108f907 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428133857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.2428133857 |
| Directory | /workspace/1.uart_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3728037129 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 113272341 ps |
| CPU time | 1.41 seconds |
| Started | Apr 21 01:00:54 PM PDT 24 |
| Finished | Apr 21 01:00:57 PM PDT 24 |
| Peak memory | 197676 kb |
| Host | smart-4b316c21-5b2c-48dc-8d41-8f9c66696f03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728037129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3728037129 |
| Directory | /workspace/1.uart_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.325480617 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 41870885 ps |
| CPU time | 0.58 seconds |
| Started | Apr 21 01:00:51 PM PDT 24 |
| Finished | Apr 21 01:00:52 PM PDT 24 |
| Peak memory | 195384 kb |
| Host | smart-5b2d8af5-ffeb-42e6-bbcb-99814b4de205 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325480617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.325480617 |
| Directory | /workspace/1.uart_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2781288206 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 74040620 ps |
| CPU time | 0.77 seconds |
| Started | Apr 21 01:00:52 PM PDT 24 |
| Finished | Apr 21 01:00:53 PM PDT 24 |
| Peak memory | 198084 kb |
| Host | smart-1eb528fd-afa9-4fa1-8b33-7c63f692b066 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781288206 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.2781288206 |
| Directory | /workspace/1.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_intr_test.4171459822 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 13761383 ps |
| CPU time | 0.61 seconds |
| Started | Apr 21 01:00:54 PM PDT 24 |
| Finished | Apr 21 01:00:56 PM PDT 24 |
| Peak memory | 194328 kb |
| Host | smart-cc49bb63-7367-4f55-b88d-44bf986b68e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171459822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.4171459822 |
| Directory | /workspace/1.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1685518351 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 191047507 ps |
| CPU time | 0.65 seconds |
| Started | Apr 21 01:00:49 PM PDT 24 |
| Finished | Apr 21 01:00:50 PM PDT 24 |
| Peak memory | 196616 kb |
| Host | smart-bc91054c-79fc-4dc7-8712-4fc3a9efb0a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685518351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr _outstanding.1685518351 |
| Directory | /workspace/1.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_tl_errors.271967013 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 120783064 ps |
| CPU time | 2.2 seconds |
| Started | Apr 21 01:00:49 PM PDT 24 |
| Finished | Apr 21 01:00:52 PM PDT 24 |
| Peak memory | 200172 kb |
| Host | smart-d95d611d-ba61-4a56-b506-316ec3b79258 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271967013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.271967013 |
| Directory | /workspace/1.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3853044423 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 25813688 ps |
| CPU time | 0.78 seconds |
| Started | Apr 21 01:01:03 PM PDT 24 |
| Finished | Apr 21 01:01:04 PM PDT 24 |
| Peak memory | 199372 kb |
| Host | smart-17c0ff33-3eaf-46cc-9907-a7a1294b5a08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853044423 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.3853044423 |
| Directory | /workspace/10.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.uart_csr_rw.3091643978 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 15762583 ps |
| CPU time | 0.59 seconds |
| Started | Apr 21 01:01:07 PM PDT 24 |
| Finished | Apr 21 01:01:08 PM PDT 24 |
| Peak memory | 195492 kb |
| Host | smart-6393c899-0777-4474-bde0-0a0da09d750e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091643978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.3091643978 |
| Directory | /workspace/10.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.uart_intr_test.1851575564 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 11756476 ps |
| CPU time | 0.59 seconds |
| Started | Apr 21 01:01:11 PM PDT 24 |
| Finished | Apr 21 01:01:12 PM PDT 24 |
| Peak memory | 194352 kb |
| Host | smart-430b772c-2ed3-4cb6-9b7a-68e4b7a2dc77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851575564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.1851575564 |
| Directory | /workspace/10.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3960999278 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 28567067 ps |
| CPU time | 0.75 seconds |
| Started | Apr 21 01:01:05 PM PDT 24 |
| Finished | Apr 21 01:01:06 PM PDT 24 |
| Peak memory | 197544 kb |
| Host | smart-02b79e72-87a8-4e6d-b672-11c1c1f442f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960999278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs r_outstanding.3960999278 |
| Directory | /workspace/10.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.uart_tl_errors.2308831 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 61314276 ps |
| CPU time | 1.58 seconds |
| Started | Apr 21 01:01:02 PM PDT 24 |
| Finished | Apr 21 01:01:04 PM PDT 24 |
| Peak memory | 200100 kb |
| Host | smart-7c46936d-4ed3-45d7-af80-bd5a4eabdc89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.2308831 |
| Directory | /workspace/10.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.4154003808 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 93921267 ps |
| CPU time | 0.91 seconds |
| Started | Apr 21 01:01:04 PM PDT 24 |
| Finished | Apr 21 01:01:06 PM PDT 24 |
| Peak memory | 198844 kb |
| Host | smart-8ad72ad7-37c0-481a-91ce-33ac7dc1c970 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154003808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.4154003808 |
| Directory | /workspace/10.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.543800546 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 59341409 ps |
| CPU time | 0.86 seconds |
| Started | Apr 21 01:01:03 PM PDT 24 |
| Finished | Apr 21 01:01:04 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-f773dfb4-f3c8-46ed-a809-c592102998bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543800546 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.543800546 |
| Directory | /workspace/11.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.uart_csr_rw.2220645922 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 26928755 ps |
| CPU time | 0.61 seconds |
| Started | Apr 21 01:01:02 PM PDT 24 |
| Finished | Apr 21 01:01:04 PM PDT 24 |
| Peak memory | 195500 kb |
| Host | smart-e1027ba8-6af1-48c0-9852-9207db494635 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220645922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.2220645922 |
| Directory | /workspace/11.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.uart_intr_test.288045165 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 100912736 ps |
| CPU time | 0.54 seconds |
| Started | Apr 21 01:01:04 PM PDT 24 |
| Finished | Apr 21 01:01:05 PM PDT 24 |
| Peak memory | 194404 kb |
| Host | smart-4eb5f43e-551c-464e-8e8f-33b47495c270 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288045165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.288045165 |
| Directory | /workspace/11.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3461802448 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 88891976 ps |
| CPU time | 0.79 seconds |
| Started | Apr 21 01:01:04 PM PDT 24 |
| Finished | Apr 21 01:01:06 PM PDT 24 |
| Peak memory | 197148 kb |
| Host | smart-77fbba74-c2be-4864-a864-6f7059a2b040 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461802448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs r_outstanding.3461802448 |
| Directory | /workspace/11.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.uart_tl_errors.103199763 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 47039483 ps |
| CPU time | 1.6 seconds |
| Started | Apr 21 01:01:04 PM PDT 24 |
| Finished | Apr 21 01:01:06 PM PDT 24 |
| Peak memory | 200116 kb |
| Host | smart-aed2d514-3d56-4678-aa14-15ba9326fce0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103199763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.103199763 |
| Directory | /workspace/11.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1585869736 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 44374314 ps |
| CPU time | 0.74 seconds |
| Started | Apr 21 01:01:09 PM PDT 24 |
| Finished | Apr 21 01:01:10 PM PDT 24 |
| Peak memory | 199136 kb |
| Host | smart-b4a3f6a8-1749-4a73-9553-a724c90aa939 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585869736 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.1585869736 |
| Directory | /workspace/12.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.uart_csr_rw.3797933693 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 29382611 ps |
| CPU time | 0.63 seconds |
| Started | Apr 21 01:01:06 PM PDT 24 |
| Finished | Apr 21 01:01:07 PM PDT 24 |
| Peak memory | 195528 kb |
| Host | smart-d3a3b553-2791-4146-8029-b88fdd232425 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797933693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.3797933693 |
| Directory | /workspace/12.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.uart_intr_test.2054502337 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 99150040 ps |
| CPU time | 0.54 seconds |
| Started | Apr 21 01:01:07 PM PDT 24 |
| Finished | Apr 21 01:01:08 PM PDT 24 |
| Peak memory | 194392 kb |
| Host | smart-0df421b9-e3b3-40d9-91e4-f0084ec477be |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054502337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2054502337 |
| Directory | /workspace/12.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1808422907 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 45808574 ps |
| CPU time | 0.63 seconds |
| Started | Apr 21 01:01:10 PM PDT 24 |
| Finished | Apr 21 01:01:11 PM PDT 24 |
| Peak memory | 195552 kb |
| Host | smart-24f5e033-1934-40e9-88cc-38b9dc44da79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808422907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs r_outstanding.1808422907 |
| Directory | /workspace/12.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.uart_tl_errors.2229253926 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 26256095 ps |
| CPU time | 1.4 seconds |
| Started | Apr 21 01:01:08 PM PDT 24 |
| Finished | Apr 21 01:01:10 PM PDT 24 |
| Peak memory | 200160 kb |
| Host | smart-e8eed026-af14-472a-9bd4-181eed359965 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229253926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.2229253926 |
| Directory | /workspace/12.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.575581727 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 60583933 ps |
| CPU time | 0.92 seconds |
| Started | Apr 21 01:01:10 PM PDT 24 |
| Finished | Apr 21 01:01:11 PM PDT 24 |
| Peak memory | 198864 kb |
| Host | smart-d23ab239-447b-4ea9-9dbb-1fe28abbb3ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575581727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.575581727 |
| Directory | /workspace/12.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2646418920 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 28545411 ps |
| CPU time | 1.27 seconds |
| Started | Apr 21 01:01:09 PM PDT 24 |
| Finished | Apr 21 01:01:11 PM PDT 24 |
| Peak memory | 200060 kb |
| Host | smart-37da0d6b-9582-4d06-bf04-23f192a11991 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646418920 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.2646418920 |
| Directory | /workspace/13.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.uart_csr_rw.2006519975 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 48660457 ps |
| CPU time | 0.59 seconds |
| Started | Apr 21 01:01:11 PM PDT 24 |
| Finished | Apr 21 01:01:12 PM PDT 24 |
| Peak memory | 195056 kb |
| Host | smart-bcd1dabb-c59e-4d99-b2c1-072a714ac102 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006519975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.2006519975 |
| Directory | /workspace/13.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.uart_intr_test.3182032074 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 23682982 ps |
| CPU time | 0.6 seconds |
| Started | Apr 21 01:01:06 PM PDT 24 |
| Finished | Apr 21 01:01:07 PM PDT 24 |
| Peak memory | 194364 kb |
| Host | smart-2cf208a5-2ef2-444a-a1ea-230259d7f6c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182032074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.3182032074 |
| Directory | /workspace/13.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3040907042 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 52636169 ps |
| CPU time | 0.68 seconds |
| Started | Apr 21 01:01:03 PM PDT 24 |
| Finished | Apr 21 01:01:04 PM PDT 24 |
| Peak memory | 194780 kb |
| Host | smart-a11fc84e-eba1-425d-88a6-7357fc82a83a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040907042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs r_outstanding.3040907042 |
| Directory | /workspace/13.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.uart_tl_errors.3125255277 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 444350072 ps |
| CPU time | 1.98 seconds |
| Started | Apr 21 01:01:05 PM PDT 24 |
| Finished | Apr 21 01:01:07 PM PDT 24 |
| Peak memory | 200152 kb |
| Host | smart-ba3a3ca4-1de6-4ad9-a62d-3dcc30af3666 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125255277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3125255277 |
| Directory | /workspace/13.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3039724091 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 326511415 ps |
| CPU time | 1.27 seconds |
| Started | Apr 21 01:01:10 PM PDT 24 |
| Finished | Apr 21 01:01:12 PM PDT 24 |
| Peak memory | 199448 kb |
| Host | smart-aa11dec1-b60c-4da4-b3b4-c37293c1493a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039724091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3039724091 |
| Directory | /workspace/13.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2059158706 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 32398303 ps |
| CPU time | 0.91 seconds |
| Started | Apr 21 01:01:08 PM PDT 24 |
| Finished | Apr 21 01:01:10 PM PDT 24 |
| Peak memory | 199804 kb |
| Host | smart-f63f5371-344f-4a76-a32e-fc671fa0c35d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059158706 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.2059158706 |
| Directory | /workspace/14.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.uart_csr_rw.2713649552 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 13916611 ps |
| CPU time | 0.63 seconds |
| Started | Apr 21 01:01:11 PM PDT 24 |
| Finished | Apr 21 01:01:12 PM PDT 24 |
| Peak memory | 195356 kb |
| Host | smart-f6ab2689-0ad8-43d0-953a-967113e82bb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713649552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.2713649552 |
| Directory | /workspace/14.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.uart_intr_test.3522269819 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 17277459 ps |
| CPU time | 0.58 seconds |
| Started | Apr 21 01:01:04 PM PDT 24 |
| Finished | Apr 21 01:01:06 PM PDT 24 |
| Peak memory | 194428 kb |
| Host | smart-e1d11578-ef59-442d-8ef0-69d8752921b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522269819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.3522269819 |
| Directory | /workspace/14.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.128472424 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 19188427 ps |
| CPU time | 0.7 seconds |
| Started | Apr 21 01:01:07 PM PDT 24 |
| Finished | Apr 21 01:01:08 PM PDT 24 |
| Peak memory | 195672 kb |
| Host | smart-4a94bb8e-218e-49d6-acff-079d3cdbd1ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128472424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr _outstanding.128472424 |
| Directory | /workspace/14.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.uart_tl_errors.3328581566 |
| Short name | T1316 |
| Test name | |
| Test status | |
| Simulation time | 221072676 ps |
| CPU time | 2.34 seconds |
| Started | Apr 21 01:01:07 PM PDT 24 |
| Finished | Apr 21 01:01:09 PM PDT 24 |
| Peak memory | 200064 kb |
| Host | smart-911dd923-5c2c-4154-9888-9b4304f39494 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328581566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.3328581566 |
| Directory | /workspace/14.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.1537259932 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 250807896 ps |
| CPU time | 1.23 seconds |
| Started | Apr 21 01:01:08 PM PDT 24 |
| Finished | Apr 21 01:01:09 PM PDT 24 |
| Peak memory | 199356 kb |
| Host | smart-5c20c64d-f02e-478e-a5eb-addcb3715946 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537259932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.1537259932 |
| Directory | /workspace/14.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3458800168 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 32471171 ps |
| CPU time | 0.7 seconds |
| Started | Apr 21 01:01:07 PM PDT 24 |
| Finished | Apr 21 01:01:08 PM PDT 24 |
| Peak memory | 198652 kb |
| Host | smart-b2e758d0-7222-42b1-91d2-628c3a545cf4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458800168 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.3458800168 |
| Directory | /workspace/15.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.uart_csr_rw.1006783125 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 21709970 ps |
| CPU time | 0.58 seconds |
| Started | Apr 21 01:01:07 PM PDT 24 |
| Finished | Apr 21 01:01:08 PM PDT 24 |
| Peak memory | 195420 kb |
| Host | smart-59313413-20fc-45b7-982d-0a5812e49a2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006783125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1006783125 |
| Directory | /workspace/15.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.uart_intr_test.546226963 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 26507385 ps |
| CPU time | 0.59 seconds |
| Started | Apr 21 01:01:11 PM PDT 24 |
| Finished | Apr 21 01:01:12 PM PDT 24 |
| Peak memory | 194428 kb |
| Host | smart-bf5736c0-ade3-4a07-950c-651d1ad8279a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546226963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.546226963 |
| Directory | /workspace/15.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2198285556 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 19275927 ps |
| CPU time | 0.62 seconds |
| Started | Apr 21 01:01:09 PM PDT 24 |
| Finished | Apr 21 01:01:10 PM PDT 24 |
| Peak memory | 195512 kb |
| Host | smart-ec3503d4-3be2-4e2d-b9a7-1d8bda17002d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198285556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs r_outstanding.2198285556 |
| Directory | /workspace/15.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.uart_tl_errors.3283613791 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 221335373 ps |
| CPU time | 1.17 seconds |
| Started | Apr 21 01:01:11 PM PDT 24 |
| Finished | Apr 21 01:01:12 PM PDT 24 |
| Peak memory | 199608 kb |
| Host | smart-c16479bc-cddd-4ad2-8ae9-c88a3d184b37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283613791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.3283613791 |
| Directory | /workspace/15.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.761833808 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 72613152 ps |
| CPU time | 1.3 seconds |
| Started | Apr 21 01:01:07 PM PDT 24 |
| Finished | Apr 21 01:01:08 PM PDT 24 |
| Peak memory | 199396 kb |
| Host | smart-35f70281-4246-4ce4-a2c0-8e49c78580db |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761833808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.761833808 |
| Directory | /workspace/15.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2593729103 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 49458379 ps |
| CPU time | 0.64 seconds |
| Started | Apr 21 01:01:06 PM PDT 24 |
| Finished | Apr 21 01:01:07 PM PDT 24 |
| Peak memory | 197552 kb |
| Host | smart-1e4abc39-8146-4812-b9f1-6802a1c82832 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593729103 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.2593729103 |
| Directory | /workspace/16.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.uart_csr_rw.3520745176 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 17471527 ps |
| CPU time | 0.63 seconds |
| Started | Apr 21 01:01:11 PM PDT 24 |
| Finished | Apr 21 01:01:12 PM PDT 24 |
| Peak memory | 195280 kb |
| Host | smart-3cf21212-b31b-47e3-903b-7ce92ebf5a1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520745176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.3520745176 |
| Directory | /workspace/16.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.uart_intr_test.3697921665 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 28539644 ps |
| CPU time | 0.54 seconds |
| Started | Apr 21 01:01:11 PM PDT 24 |
| Finished | Apr 21 01:01:12 PM PDT 24 |
| Peak memory | 194356 kb |
| Host | smart-4ebaa3f1-eb4e-4ecd-9f6c-097ff7028537 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697921665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.3697921665 |
| Directory | /workspace/16.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3835939764 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 75063652 ps |
| CPU time | 0.73 seconds |
| Started | Apr 21 01:01:11 PM PDT 24 |
| Finished | Apr 21 01:01:13 PM PDT 24 |
| Peak memory | 197508 kb |
| Host | smart-33895b18-8244-4eb3-912f-4310bedbafb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835939764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs r_outstanding.3835939764 |
| Directory | /workspace/16.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.uart_tl_errors.2640061935 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 249063165 ps |
| CPU time | 1.39 seconds |
| Started | Apr 21 01:01:09 PM PDT 24 |
| Finished | Apr 21 01:01:10 PM PDT 24 |
| Peak memory | 199956 kb |
| Host | smart-7a450a1d-0289-42a8-acf5-ab725ff7fcfa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640061935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.2640061935 |
| Directory | /workspace/16.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3217925651 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 220222498 ps |
| CPU time | 1.41 seconds |
| Started | Apr 21 01:01:08 PM PDT 24 |
| Finished | Apr 21 01:01:10 PM PDT 24 |
| Peak memory | 199236 kb |
| Host | smart-bd63426a-eca9-4ff9-95de-6e67f05589a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217925651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3217925651 |
| Directory | /workspace/16.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1840677197 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 284691262 ps |
| CPU time | 1.03 seconds |
| Started | Apr 21 01:01:08 PM PDT 24 |
| Finished | Apr 21 01:01:09 PM PDT 24 |
| Peak memory | 200084 kb |
| Host | smart-72f887ed-ebe8-4179-84a8-34e9466f0ebb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840677197 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.1840677197 |
| Directory | /workspace/17.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.uart_csr_rw.3819115167 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 48081438 ps |
| CPU time | 0.6 seconds |
| Started | Apr 21 01:01:06 PM PDT 24 |
| Finished | Apr 21 01:01:07 PM PDT 24 |
| Peak memory | 195488 kb |
| Host | smart-85c21b9b-f2db-4438-931e-96668924d891 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819115167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3819115167 |
| Directory | /workspace/17.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.uart_intr_test.3672934131 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 35002454 ps |
| CPU time | 0.56 seconds |
| Started | Apr 21 01:01:07 PM PDT 24 |
| Finished | Apr 21 01:01:08 PM PDT 24 |
| Peak memory | 194312 kb |
| Host | smart-8215c6c5-ed84-4c5f-a864-e1cbdbca6e06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672934131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.3672934131 |
| Directory | /workspace/17.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.631128283 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 53283856 ps |
| CPU time | 0.76 seconds |
| Started | Apr 21 01:01:05 PM PDT 24 |
| Finished | Apr 21 01:01:06 PM PDT 24 |
| Peak memory | 197092 kb |
| Host | smart-78159cc4-50fb-4a20-a2c0-cf2d0a8c88c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631128283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr _outstanding.631128283 |
| Directory | /workspace/17.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.uart_tl_errors.410710265 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 298481719 ps |
| CPU time | 1.48 seconds |
| Started | Apr 21 01:01:08 PM PDT 24 |
| Finished | Apr 21 01:01:10 PM PDT 24 |
| Peak memory | 200156 kb |
| Host | smart-0b37728a-2ee4-472f-8b5a-026290f76f92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410710265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.410710265 |
| Directory | /workspace/17.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3116381038 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 74688810 ps |
| CPU time | 1.24 seconds |
| Started | Apr 21 01:01:09 PM PDT 24 |
| Finished | Apr 21 01:01:11 PM PDT 24 |
| Peak memory | 199304 kb |
| Host | smart-18729856-79c4-4cad-bd8e-ac7484a7694c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116381038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3116381038 |
| Directory | /workspace/17.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2648457581 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 31184633 ps |
| CPU time | 0.85 seconds |
| Started | Apr 21 01:01:12 PM PDT 24 |
| Finished | Apr 21 01:01:13 PM PDT 24 |
| Peak memory | 199804 kb |
| Host | smart-b40fa1c1-959c-46a4-a783-f49bcb4c7464 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648457581 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.2648457581 |
| Directory | /workspace/18.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.uart_csr_rw.3650861421 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 29584969 ps |
| CPU time | 0.67 seconds |
| Started | Apr 21 01:01:10 PM PDT 24 |
| Finished | Apr 21 01:01:11 PM PDT 24 |
| Peak memory | 195548 kb |
| Host | smart-e8d5933a-ae8b-4371-b93c-ee62a82546e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650861421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3650861421 |
| Directory | /workspace/18.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.uart_intr_test.1192604318 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 27142316 ps |
| CPU time | 0.57 seconds |
| Started | Apr 21 01:01:09 PM PDT 24 |
| Finished | Apr 21 01:01:10 PM PDT 24 |
| Peak memory | 194368 kb |
| Host | smart-a3b38569-6933-45af-a26d-2a78a168a566 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192604318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.1192604318 |
| Directory | /workspace/18.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.340731425 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 21888708 ps |
| CPU time | 0.67 seconds |
| Started | Apr 21 01:01:12 PM PDT 24 |
| Finished | Apr 21 01:01:13 PM PDT 24 |
| Peak memory | 194528 kb |
| Host | smart-e1722090-b7cb-4214-b4de-6259e24dbddc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340731425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr _outstanding.340731425 |
| Directory | /workspace/18.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.uart_tl_errors.2688247327 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 48812216 ps |
| CPU time | 1.26 seconds |
| Started | Apr 21 01:01:08 PM PDT 24 |
| Finished | Apr 21 01:01:10 PM PDT 24 |
| Peak memory | 200064 kb |
| Host | smart-0b8316f6-4bd7-4597-ba33-143380c8f929 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688247327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.2688247327 |
| Directory | /workspace/18.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.2212209231 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 955791288 ps |
| CPU time | 1.7 seconds |
| Started | Apr 21 01:01:10 PM PDT 24 |
| Finished | Apr 21 01:01:13 PM PDT 24 |
| Peak memory | 199412 kb |
| Host | smart-efed8d0c-8a21-4cbd-b8ab-7c84b3316a95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212209231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.2212209231 |
| Directory | /workspace/18.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2912973231 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 19818016 ps |
| CPU time | 0.96 seconds |
| Started | Apr 21 01:01:11 PM PDT 24 |
| Finished | Apr 21 01:01:13 PM PDT 24 |
| Peak memory | 199816 kb |
| Host | smart-3b67a52c-2fa8-410b-8e9f-af938dca08c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912973231 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.2912973231 |
| Directory | /workspace/19.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.uart_csr_rw.3329047014 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 37328234 ps |
| CPU time | 0.59 seconds |
| Started | Apr 21 01:01:10 PM PDT 24 |
| Finished | Apr 21 01:01:11 PM PDT 24 |
| Peak memory | 195468 kb |
| Host | smart-a4fe1f9b-05fe-4468-b301-34db7f880977 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329047014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.3329047014 |
| Directory | /workspace/19.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.uart_intr_test.574778220 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 41210044 ps |
| CPU time | 0.56 seconds |
| Started | Apr 21 01:01:10 PM PDT 24 |
| Finished | Apr 21 01:01:11 PM PDT 24 |
| Peak memory | 194368 kb |
| Host | smart-f32f192b-ffb1-453a-869d-b105706e6e31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574778220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.574778220 |
| Directory | /workspace/19.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2423028729 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 22697146 ps |
| CPU time | 0.72 seconds |
| Started | Apr 21 01:01:17 PM PDT 24 |
| Finished | Apr 21 01:01:19 PM PDT 24 |
| Peak memory | 194460 kb |
| Host | smart-91a56d8a-6a84-4d4e-98de-fba7858f5844 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423028729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs r_outstanding.2423028729 |
| Directory | /workspace/19.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.uart_tl_errors.1381893802 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 55198398 ps |
| CPU time | 1.37 seconds |
| Started | Apr 21 01:01:13 PM PDT 24 |
| Finished | Apr 21 01:01:14 PM PDT 24 |
| Peak memory | 200108 kb |
| Host | smart-bc3ac5f6-2eaf-4eb2-af80-7420469ade67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381893802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.1381893802 |
| Directory | /workspace/19.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3303777571 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 215370866 ps |
| CPU time | 0.91 seconds |
| Started | Apr 21 01:01:09 PM PDT 24 |
| Finished | Apr 21 01:01:11 PM PDT 24 |
| Peak memory | 199040 kb |
| Host | smart-c16c3356-8bec-469f-9372-b73a8bb73187 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303777571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.3303777571 |
| Directory | /workspace/19.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2023305791 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 111413402 ps |
| CPU time | 0.77 seconds |
| Started | Apr 21 01:00:54 PM PDT 24 |
| Finished | Apr 21 01:00:55 PM PDT 24 |
| Peak memory | 196740 kb |
| Host | smart-fda4ed89-899e-48e4-a5fe-b4f6d56b86df |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023305791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.2023305791 |
| Directory | /workspace/2.uart_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1902329220 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 136762451 ps |
| CPU time | 1.62 seconds |
| Started | Apr 21 01:00:54 PM PDT 24 |
| Finished | Apr 21 01:00:56 PM PDT 24 |
| Peak memory | 198004 kb |
| Host | smart-5c60c109-f03a-4a98-8f5a-020d234aa9e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902329220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1902329220 |
| Directory | /workspace/2.uart_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.4190841559 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 15727506 ps |
| CPU time | 0.61 seconds |
| Started | Apr 21 01:00:49 PM PDT 24 |
| Finished | Apr 21 01:00:50 PM PDT 24 |
| Peak memory | 195496 kb |
| Host | smart-d9eebd4a-3962-419b-ae19-f4aae487aa8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190841559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.4190841559 |
| Directory | /workspace/2.uart_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2675427832 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 20381827 ps |
| CPU time | 0.65 seconds |
| Started | Apr 21 01:00:54 PM PDT 24 |
| Finished | Apr 21 01:00:55 PM PDT 24 |
| Peak memory | 197780 kb |
| Host | smart-0d4476d7-4049-4431-9d82-7cc1e47ec0ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675427832 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.2675427832 |
| Directory | /workspace/2.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_csr_rw.4293985000 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 50068430 ps |
| CPU time | 0.64 seconds |
| Started | Apr 21 01:00:54 PM PDT 24 |
| Finished | Apr 21 01:00:54 PM PDT 24 |
| Peak memory | 195412 kb |
| Host | smart-0dd7b320-df84-4bce-ac72-6735bf691999 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293985000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.4293985000 |
| Directory | /workspace/2.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_intr_test.3381314615 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 21851997 ps |
| CPU time | 0.57 seconds |
| Started | Apr 21 01:00:54 PM PDT 24 |
| Finished | Apr 21 01:00:55 PM PDT 24 |
| Peak memory | 194404 kb |
| Host | smart-78c8ddc6-319c-4abd-b3e5-324b45c015a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381314615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3381314615 |
| Directory | /workspace/2.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3771057561 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 20879953 ps |
| CPU time | 0.63 seconds |
| Started | Apr 21 01:00:58 PM PDT 24 |
| Finished | Apr 21 01:00:59 PM PDT 24 |
| Peak memory | 195804 kb |
| Host | smart-be1ac4f7-da61-48ac-8d31-793a4b1565aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771057561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr _outstanding.3771057561 |
| Directory | /workspace/2.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_tl_errors.1188257148 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 33799791 ps |
| CPU time | 1.5 seconds |
| Started | Apr 21 01:00:54 PM PDT 24 |
| Finished | Apr 21 01:00:56 PM PDT 24 |
| Peak memory | 200040 kb |
| Host | smart-6b2dffd9-a2d3-4d4b-b183-f0e3e82f049a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188257148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.1188257148 |
| Directory | /workspace/2.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/20.uart_intr_test.1694551122 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 43463019 ps |
| CPU time | 0.59 seconds |
| Started | Apr 21 01:01:13 PM PDT 24 |
| Finished | Apr 21 01:01:14 PM PDT 24 |
| Peak memory | 194428 kb |
| Host | smart-135a04da-54e1-442a-9f81-33acf6206aa8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694551122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.1694551122 |
| Directory | /workspace/20.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.uart_intr_test.1842937475 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 23293114 ps |
| CPU time | 0.62 seconds |
| Started | Apr 21 01:01:17 PM PDT 24 |
| Finished | Apr 21 01:01:19 PM PDT 24 |
| Peak memory | 194436 kb |
| Host | smart-31fd137a-eca1-4deb-b376-3d6a46b9bba5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842937475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.1842937475 |
| Directory | /workspace/21.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.uart_intr_test.829334351 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 11050942 ps |
| CPU time | 0.58 seconds |
| Started | Apr 21 01:01:09 PM PDT 24 |
| Finished | Apr 21 01:01:09 PM PDT 24 |
| Peak memory | 194400 kb |
| Host | smart-415ad5dd-297b-41ab-a465-f6b3ed612dc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829334351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.829334351 |
| Directory | /workspace/22.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.uart_intr_test.1930330631 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 15417667 ps |
| CPU time | 0.6 seconds |
| Started | Apr 21 01:01:12 PM PDT 24 |
| Finished | Apr 21 01:01:13 PM PDT 24 |
| Peak memory | 194276 kb |
| Host | smart-9d6921d7-0262-47cb-a1ce-006021a991a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930330631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.1930330631 |
| Directory | /workspace/23.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.uart_intr_test.1732094075 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 51100638 ps |
| CPU time | 0.59 seconds |
| Started | Apr 21 01:01:11 PM PDT 24 |
| Finished | Apr 21 01:01:12 PM PDT 24 |
| Peak memory | 194356 kb |
| Host | smart-ffa52eac-d9e3-46ed-8040-22b2487ddba3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732094075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.1732094075 |
| Directory | /workspace/24.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.uart_intr_test.4100801746 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 12307107 ps |
| CPU time | 0.57 seconds |
| Started | Apr 21 01:01:12 PM PDT 24 |
| Finished | Apr 21 01:01:13 PM PDT 24 |
| Peak memory | 194284 kb |
| Host | smart-09df1566-9410-4928-8c59-035a9a80e692 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100801746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.4100801746 |
| Directory | /workspace/25.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.uart_intr_test.1509699362 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 11136526 ps |
| CPU time | 0.55 seconds |
| Started | Apr 21 01:01:17 PM PDT 24 |
| Finished | Apr 21 01:01:18 PM PDT 24 |
| Peak memory | 194324 kb |
| Host | smart-c886a036-894a-468e-9000-156f4b6d1b25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509699362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1509699362 |
| Directory | /workspace/26.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.uart_intr_test.2523806082 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 27461531 ps |
| CPU time | 0.57 seconds |
| Started | Apr 21 01:01:12 PM PDT 24 |
| Finished | Apr 21 01:01:13 PM PDT 24 |
| Peak memory | 194388 kb |
| Host | smart-f72601b5-ec44-44a1-88a9-ed688c33535f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523806082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.2523806082 |
| Directory | /workspace/27.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.uart_intr_test.1319899450 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 44996258 ps |
| CPU time | 0.58 seconds |
| Started | Apr 21 01:01:12 PM PDT 24 |
| Finished | Apr 21 01:01:13 PM PDT 24 |
| Peak memory | 194460 kb |
| Host | smart-cd968b7b-ef00-4621-aea2-d7e95fb84546 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319899450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.1319899450 |
| Directory | /workspace/28.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.uart_intr_test.1453033684 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 20983437 ps |
| CPU time | 0.55 seconds |
| Started | Apr 21 01:01:13 PM PDT 24 |
| Finished | Apr 21 01:01:14 PM PDT 24 |
| Peak memory | 194456 kb |
| Host | smart-9df8d4bb-1cee-4382-a9f3-996e7bb8e399 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453033684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.1453033684 |
| Directory | /workspace/29.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3541764112 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 43304619 ps |
| CPU time | 0.78 seconds |
| Started | Apr 21 01:00:58 PM PDT 24 |
| Finished | Apr 21 01:00:59 PM PDT 24 |
| Peak memory | 196652 kb |
| Host | smart-9fbfa832-d056-45e1-8ac5-546a963e8576 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541764112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.3541764112 |
| Directory | /workspace/3.uart_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3007049934 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 676762554 ps |
| CPU time | 2.43 seconds |
| Started | Apr 21 01:00:58 PM PDT 24 |
| Finished | Apr 21 01:01:01 PM PDT 24 |
| Peak memory | 198068 kb |
| Host | smart-8eed31ad-2894-4c7d-b085-db72ef408c07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007049934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.3007049934 |
| Directory | /workspace/3.uart_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1763368544 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 12946302 ps |
| CPU time | 0.58 seconds |
| Started | Apr 21 01:00:53 PM PDT 24 |
| Finished | Apr 21 01:00:53 PM PDT 24 |
| Peak memory | 195416 kb |
| Host | smart-20fbb04f-6df1-4c9f-ad95-7b358239fab7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763368544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.1763368544 |
| Directory | /workspace/3.uart_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1851197245 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 37722392 ps |
| CPU time | 1.09 seconds |
| Started | Apr 21 01:00:53 PM PDT 24 |
| Finished | Apr 21 01:00:55 PM PDT 24 |
| Peak memory | 200128 kb |
| Host | smart-c8e9c0bb-e1e2-4204-8322-47af517ee4ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851197245 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.1851197245 |
| Directory | /workspace/3.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_csr_rw.2767919085 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 16527312 ps |
| CPU time | 0.59 seconds |
| Started | Apr 21 01:00:55 PM PDT 24 |
| Finished | Apr 21 01:00:56 PM PDT 24 |
| Peak memory | 195488 kb |
| Host | smart-26fd7c39-335e-4bfc-af15-d1187238ed9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767919085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2767919085 |
| Directory | /workspace/3.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_intr_test.4078610392 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 23691695 ps |
| CPU time | 0.53 seconds |
| Started | Apr 21 01:00:53 PM PDT 24 |
| Finished | Apr 21 01:00:54 PM PDT 24 |
| Peak memory | 194384 kb |
| Host | smart-a4e81b73-7c46-48e2-bf82-4a73094ab1bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078610392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.4078610392 |
| Directory | /workspace/3.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3228842835 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 62971583 ps |
| CPU time | 0.64 seconds |
| Started | Apr 21 01:00:54 PM PDT 24 |
| Finished | Apr 21 01:00:56 PM PDT 24 |
| Peak memory | 195772 kb |
| Host | smart-9cbf4c70-150f-4832-a191-3bceb9131800 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228842835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr _outstanding.3228842835 |
| Directory | /workspace/3.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_tl_errors.3850818881 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 121679906 ps |
| CPU time | 1.67 seconds |
| Started | Apr 21 01:01:01 PM PDT 24 |
| Finished | Apr 21 01:01:03 PM PDT 24 |
| Peak memory | 200040 kb |
| Host | smart-e549c392-4a13-4162-b46d-aad6260498f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850818881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.3850818881 |
| Directory | /workspace/3.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.2225769771 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 193162676 ps |
| CPU time | 0.94 seconds |
| Started | Apr 21 01:00:55 PM PDT 24 |
| Finished | Apr 21 01:00:56 PM PDT 24 |
| Peak memory | 199004 kb |
| Host | smart-8ee9e1ff-0d05-406b-9145-a0fc35464a43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225769771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.2225769771 |
| Directory | /workspace/3.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/30.uart_intr_test.179974784 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 12129274 ps |
| CPU time | 0.56 seconds |
| Started | Apr 21 01:01:13 PM PDT 24 |
| Finished | Apr 21 01:01:14 PM PDT 24 |
| Peak memory | 194400 kb |
| Host | smart-f4b495be-2d57-44c6-a464-267ee01044cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179974784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.179974784 |
| Directory | /workspace/30.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.uart_intr_test.3479471103 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 15047502 ps |
| CPU time | 0.64 seconds |
| Started | Apr 21 01:01:24 PM PDT 24 |
| Finished | Apr 21 01:01:25 PM PDT 24 |
| Peak memory | 194348 kb |
| Host | smart-d546ee9d-b4d7-4d78-88cf-445930cfd2a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479471103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.3479471103 |
| Directory | /workspace/31.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.uart_intr_test.1537348015 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 10930869 ps |
| CPU time | 0.54 seconds |
| Started | Apr 21 01:01:17 PM PDT 24 |
| Finished | Apr 21 01:01:18 PM PDT 24 |
| Peak memory | 194356 kb |
| Host | smart-1afb4c3d-b284-4fab-9717-1c7f4ecb31fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537348015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.1537348015 |
| Directory | /workspace/32.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.uart_intr_test.384270988 |
| Short name | T1317 |
| Test name | |
| Test status | |
| Simulation time | 39133066 ps |
| CPU time | 0.62 seconds |
| Started | Apr 21 01:01:14 PM PDT 24 |
| Finished | Apr 21 01:01:15 PM PDT 24 |
| Peak memory | 194452 kb |
| Host | smart-24ec2bf4-3a78-4443-8ee3-d579b02c1d4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384270988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.384270988 |
| Directory | /workspace/33.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.uart_intr_test.1497080685 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 34582294 ps |
| CPU time | 0.55 seconds |
| Started | Apr 21 01:01:17 PM PDT 24 |
| Finished | Apr 21 01:01:18 PM PDT 24 |
| Peak memory | 194344 kb |
| Host | smart-bb3766a1-7853-4c6d-9a2d-a536cdd438b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497080685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.1497080685 |
| Directory | /workspace/34.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.uart_intr_test.789707081 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 51374904 ps |
| CPU time | 0.58 seconds |
| Started | Apr 21 01:01:22 PM PDT 24 |
| Finished | Apr 21 01:01:23 PM PDT 24 |
| Peak memory | 194368 kb |
| Host | smart-73ed495d-f897-4902-9688-e27b0fd28971 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789707081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.789707081 |
| Directory | /workspace/35.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.uart_intr_test.3133325121 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 15866702 ps |
| CPU time | 0.61 seconds |
| Started | Apr 21 01:01:17 PM PDT 24 |
| Finished | Apr 21 01:01:19 PM PDT 24 |
| Peak memory | 194064 kb |
| Host | smart-75a63f9e-68f4-43e9-9ed3-c06556451a28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133325121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.3133325121 |
| Directory | /workspace/36.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.uart_intr_test.2007225275 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 21935819 ps |
| CPU time | 0.62 seconds |
| Started | Apr 21 01:01:24 PM PDT 24 |
| Finished | Apr 21 01:01:25 PM PDT 24 |
| Peak memory | 194344 kb |
| Host | smart-5df50a4e-8096-4a66-9574-bc1d88d2c0c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007225275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.2007225275 |
| Directory | /workspace/37.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.uart_intr_test.1639032179 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 20160225 ps |
| CPU time | 0.56 seconds |
| Started | Apr 21 01:01:13 PM PDT 24 |
| Finished | Apr 21 01:01:14 PM PDT 24 |
| Peak memory | 194396 kb |
| Host | smart-c3dede56-6403-4f28-96d2-62b0f3f07a73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639032179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.1639032179 |
| Directory | /workspace/38.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.uart_intr_test.3132712121 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 139418377 ps |
| CPU time | 0.57 seconds |
| Started | Apr 21 01:01:15 PM PDT 24 |
| Finished | Apr 21 01:01:16 PM PDT 24 |
| Peak memory | 194296 kb |
| Host | smart-d127b59b-109e-4c20-8f0b-885a451ee681 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132712121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3132712121 |
| Directory | /workspace/39.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2337189694 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 39605628 ps |
| CPU time | 0.64 seconds |
| Started | Apr 21 01:00:55 PM PDT 24 |
| Finished | Apr 21 01:00:56 PM PDT 24 |
| Peak memory | 194848 kb |
| Host | smart-e52b6866-7524-4901-bb08-47666da2c95f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337189694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.2337189694 |
| Directory | /workspace/4.uart_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.2496509009 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 357903526 ps |
| CPU time | 2.5 seconds |
| Started | Apr 21 01:00:55 PM PDT 24 |
| Finished | Apr 21 01:00:58 PM PDT 24 |
| Peak memory | 198068 kb |
| Host | smart-f667c04f-92a5-4346-8f38-32b54879f8db |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496509009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.2496509009 |
| Directory | /workspace/4.uart_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1062185267 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 15623014 ps |
| CPU time | 0.59 seconds |
| Started | Apr 21 01:00:56 PM PDT 24 |
| Finished | Apr 21 01:00:57 PM PDT 24 |
| Peak memory | 195480 kb |
| Host | smart-c1058d69-0113-4bbb-aa9a-d3d599e892e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062185267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.1062185267 |
| Directory | /workspace/4.uart_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3281183005 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 53342674 ps |
| CPU time | 0.7 seconds |
| Started | Apr 21 01:00:56 PM PDT 24 |
| Finished | Apr 21 01:00:57 PM PDT 24 |
| Peak memory | 197780 kb |
| Host | smart-e0c07002-6059-48f6-9403-c080f62662aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281183005 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.3281183005 |
| Directory | /workspace/4.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_csr_rw.2530833079 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 16892730 ps |
| CPU time | 0.62 seconds |
| Started | Apr 21 01:00:57 PM PDT 24 |
| Finished | Apr 21 01:00:58 PM PDT 24 |
| Peak memory | 195724 kb |
| Host | smart-c6328e1e-3daa-46bc-ba4a-dd2fd48dcd2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530833079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.2530833079 |
| Directory | /workspace/4.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_intr_test.1419259748 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 57028179 ps |
| CPU time | 0.55 seconds |
| Started | Apr 21 01:00:58 PM PDT 24 |
| Finished | Apr 21 01:00:59 PM PDT 24 |
| Peak memory | 194432 kb |
| Host | smart-1edb9039-9081-4102-8519-0c4c7c78a042 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419259748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.1419259748 |
| Directory | /workspace/4.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.3983591407 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 26869992 ps |
| CPU time | 0.77 seconds |
| Started | Apr 21 01:00:57 PM PDT 24 |
| Finished | Apr 21 01:00:58 PM PDT 24 |
| Peak memory | 196176 kb |
| Host | smart-2ffe1eed-b453-4f36-8a33-4d7b198b69cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983591407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr _outstanding.3983591407 |
| Directory | /workspace/4.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_tl_errors.2793983461 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 417136575 ps |
| CPU time | 1.31 seconds |
| Started | Apr 21 01:00:53 PM PDT 24 |
| Finished | Apr 21 01:00:55 PM PDT 24 |
| Peak memory | 200076 kb |
| Host | smart-a1091b5a-a088-44ab-8f95-a7d48217125f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793983461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.2793983461 |
| Directory | /workspace/4.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.161090463 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 81435625 ps |
| CPU time | 0.96 seconds |
| Started | Apr 21 01:00:56 PM PDT 24 |
| Finished | Apr 21 01:00:57 PM PDT 24 |
| Peak memory | 199208 kb |
| Host | smart-3adc3af1-2621-403f-8892-17b8a1924574 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161090463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.161090463 |
| Directory | /workspace/4.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/40.uart_intr_test.4215495584 |
| Short name | T1318 |
| Test name | |
| Test status | |
| Simulation time | 42735051 ps |
| CPU time | 0.62 seconds |
| Started | Apr 21 01:01:15 PM PDT 24 |
| Finished | Apr 21 01:01:16 PM PDT 24 |
| Peak memory | 194368 kb |
| Host | smart-756e4bf3-3edc-4449-9683-b488ec6fea53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215495584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.4215495584 |
| Directory | /workspace/40.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.uart_intr_test.2263589416 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 15653532 ps |
| CPU time | 0.57 seconds |
| Started | Apr 21 01:01:19 PM PDT 24 |
| Finished | Apr 21 01:01:20 PM PDT 24 |
| Peak memory | 194360 kb |
| Host | smart-728937ba-eb17-4d01-a53d-04c5fc92f947 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263589416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.2263589416 |
| Directory | /workspace/41.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.uart_intr_test.3694903082 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 12508026 ps |
| CPU time | 0.58 seconds |
| Started | Apr 21 01:01:14 PM PDT 24 |
| Finished | Apr 21 01:01:15 PM PDT 24 |
| Peak memory | 194308 kb |
| Host | smart-9c8f0412-f746-4655-ae12-00b1aa84c0cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694903082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.3694903082 |
| Directory | /workspace/42.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.uart_intr_test.3746838118 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 84363061 ps |
| CPU time | 0.54 seconds |
| Started | Apr 21 01:01:15 PM PDT 24 |
| Finished | Apr 21 01:01:15 PM PDT 24 |
| Peak memory | 194360 kb |
| Host | smart-b09378d5-7c75-4ef0-95c7-df9f031a3e98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746838118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.3746838118 |
| Directory | /workspace/43.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.uart_intr_test.771918641 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 13426860 ps |
| CPU time | 0.56 seconds |
| Started | Apr 21 01:01:17 PM PDT 24 |
| Finished | Apr 21 01:01:18 PM PDT 24 |
| Peak memory | 194372 kb |
| Host | smart-38bdcde4-eb96-467f-b1b2-11dfed74a065 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771918641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.771918641 |
| Directory | /workspace/44.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.uart_intr_test.1698436228 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 52724740 ps |
| CPU time | 0.58 seconds |
| Started | Apr 21 01:01:19 PM PDT 24 |
| Finished | Apr 21 01:01:19 PM PDT 24 |
| Peak memory | 194320 kb |
| Host | smart-d7e299e4-6c09-4a23-a7e6-57c0a068c640 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698436228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.1698436228 |
| Directory | /workspace/45.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.uart_intr_test.319714610 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 88416369 ps |
| CPU time | 0.56 seconds |
| Started | Apr 21 01:01:17 PM PDT 24 |
| Finished | Apr 21 01:01:18 PM PDT 24 |
| Peak memory | 194380 kb |
| Host | smart-dd9845dc-7e4a-4170-a75f-063856544c60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319714610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.319714610 |
| Directory | /workspace/46.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.uart_intr_test.4012084421 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 13659376 ps |
| CPU time | 0.58 seconds |
| Started | Apr 21 01:01:16 PM PDT 24 |
| Finished | Apr 21 01:01:17 PM PDT 24 |
| Peak memory | 194316 kb |
| Host | smart-dc30fda0-74e6-4b1f-abd3-985abe99bb2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012084421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.4012084421 |
| Directory | /workspace/47.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.uart_intr_test.1828234256 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 35829350 ps |
| CPU time | 0.57 seconds |
| Started | Apr 21 01:01:20 PM PDT 24 |
| Finished | Apr 21 01:01:21 PM PDT 24 |
| Peak memory | 194372 kb |
| Host | smart-fb3a178a-1589-410e-abc5-489f010ea196 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828234256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.1828234256 |
| Directory | /workspace/48.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.uart_intr_test.1466921450 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 12454773 ps |
| CPU time | 0.61 seconds |
| Started | Apr 21 01:01:20 PM PDT 24 |
| Finished | Apr 21 01:01:20 PM PDT 24 |
| Peak memory | 194456 kb |
| Host | smart-111a2a33-6923-42cb-857e-9510a0d8f890 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466921450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.1466921450 |
| Directory | /workspace/49.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1973895812 |
| Short name | T1320 |
| Test name | |
| Test status | |
| Simulation time | 74996549 ps |
| CPU time | 1.05 seconds |
| Started | Apr 21 01:01:02 PM PDT 24 |
| Finished | Apr 21 01:01:04 PM PDT 24 |
| Peak memory | 199716 kb |
| Host | smart-8a141f43-f4dc-432f-8cc7-58638e24462d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973895812 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.1973895812 |
| Directory | /workspace/5.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.uart_csr_rw.2410596504 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 26058657 ps |
| CPU time | 0.56 seconds |
| Started | Apr 21 01:00:57 PM PDT 24 |
| Finished | Apr 21 01:00:58 PM PDT 24 |
| Peak memory | 195400 kb |
| Host | smart-eef69d9d-0141-484f-ba95-70b8c2bf106b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410596504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.2410596504 |
| Directory | /workspace/5.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.uart_intr_test.3305949457 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 68267444 ps |
| CPU time | 0.58 seconds |
| Started | Apr 21 01:01:03 PM PDT 24 |
| Finished | Apr 21 01:01:04 PM PDT 24 |
| Peak memory | 194268 kb |
| Host | smart-5b768542-888b-4b33-9b68-9440fd47c2cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305949457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3305949457 |
| Directory | /workspace/5.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.1559262821 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 106081646 ps |
| CPU time | 0.67 seconds |
| Started | Apr 21 01:00:57 PM PDT 24 |
| Finished | Apr 21 01:00:58 PM PDT 24 |
| Peak memory | 195728 kb |
| Host | smart-f1618760-380d-4055-bbf6-be42a9617d1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559262821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr _outstanding.1559262821 |
| Directory | /workspace/5.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.uart_tl_errors.1426890460 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 420238091 ps |
| CPU time | 2.48 seconds |
| Started | Apr 21 01:00:58 PM PDT 24 |
| Finished | Apr 21 01:01:01 PM PDT 24 |
| Peak memory | 200040 kb |
| Host | smart-6fc75c9c-de05-47b2-89df-dc1647a36cfe |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426890460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.1426890460 |
| Directory | /workspace/5.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.488361155 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 167841078 ps |
| CPU time | 0.96 seconds |
| Started | Apr 21 01:00:56 PM PDT 24 |
| Finished | Apr 21 01:00:57 PM PDT 24 |
| Peak memory | 198932 kb |
| Host | smart-5a8ed770-b9de-4834-8597-5f1ce1bdced5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488361155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.488361155 |
| Directory | /workspace/5.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1272516414 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 40253773 ps |
| CPU time | 0.67 seconds |
| Started | Apr 21 01:01:02 PM PDT 24 |
| Finished | Apr 21 01:01:03 PM PDT 24 |
| Peak memory | 197608 kb |
| Host | smart-d83a9a0c-3ac1-4c28-ae4b-a4317db0c147 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272516414 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.1272516414 |
| Directory | /workspace/6.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.uart_csr_rw.4198982959 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 80542724 ps |
| CPU time | 0.59 seconds |
| Started | Apr 21 01:01:00 PM PDT 24 |
| Finished | Apr 21 01:01:00 PM PDT 24 |
| Peak memory | 195468 kb |
| Host | smart-a6410470-94f2-40c0-b5fe-922d510d2938 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198982959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.4198982959 |
| Directory | /workspace/6.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.uart_intr_test.1504608669 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 49839411 ps |
| CPU time | 0.55 seconds |
| Started | Apr 21 01:01:00 PM PDT 24 |
| Finished | Apr 21 01:01:01 PM PDT 24 |
| Peak memory | 194448 kb |
| Host | smart-6656d2a5-461d-4be4-ba65-bc3ab933ae2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504608669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.1504608669 |
| Directory | /workspace/6.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.886176646 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 54832112 ps |
| CPU time | 0.72 seconds |
| Started | Apr 21 01:00:59 PM PDT 24 |
| Finished | Apr 21 01:01:00 PM PDT 24 |
| Peak memory | 197032 kb |
| Host | smart-d6ba7337-3d1f-46e8-a288-1f60b72e18cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886176646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_ outstanding.886176646 |
| Directory | /workspace/6.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.uart_tl_errors.1838492403 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 842451884 ps |
| CPU time | 1.32 seconds |
| Started | Apr 21 01:00:56 PM PDT 24 |
| Finished | Apr 21 01:00:58 PM PDT 24 |
| Peak memory | 200064 kb |
| Host | smart-4981229d-32b2-4435-b536-3faf2450b5f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838492403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1838492403 |
| Directory | /workspace/6.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.4063881941 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 50607030 ps |
| CPU time | 0.99 seconds |
| Started | Apr 21 01:01:02 PM PDT 24 |
| Finished | Apr 21 01:01:04 PM PDT 24 |
| Peak memory | 198888 kb |
| Host | smart-08471726-82b9-4665-b893-f9322b097ccc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063881941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.4063881941 |
| Directory | /workspace/6.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2765205472 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 117657161 ps |
| CPU time | 0.75 seconds |
| Started | Apr 21 01:01:04 PM PDT 24 |
| Finished | Apr 21 01:01:05 PM PDT 24 |
| Peak memory | 198416 kb |
| Host | smart-53baea5c-e614-4a4c-af7e-22568ee1cd34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765205472 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.2765205472 |
| Directory | /workspace/7.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.uart_csr_rw.676680051 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 12110366 ps |
| CPU time | 0.62 seconds |
| Started | Apr 21 01:01:03 PM PDT 24 |
| Finished | Apr 21 01:01:04 PM PDT 24 |
| Peak memory | 195604 kb |
| Host | smart-f7bf7555-4360-45d5-845f-ef8bf5bef6f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676680051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.676680051 |
| Directory | /workspace/7.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.uart_intr_test.3708431414 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 26750819 ps |
| CPU time | 0.57 seconds |
| Started | Apr 21 01:01:01 PM PDT 24 |
| Finished | Apr 21 01:01:02 PM PDT 24 |
| Peak memory | 194296 kb |
| Host | smart-373fda44-a4db-431e-8a18-cea3d23ca98e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708431414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.3708431414 |
| Directory | /workspace/7.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.3071023727 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 31263565 ps |
| CPU time | 0.67 seconds |
| Started | Apr 21 01:01:02 PM PDT 24 |
| Finished | Apr 21 01:01:03 PM PDT 24 |
| Peak memory | 196604 kb |
| Host | smart-c233cba4-451c-4936-b29e-e100390ac157 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071023727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr _outstanding.3071023727 |
| Directory | /workspace/7.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.uart_tl_errors.2105956390 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 34559481 ps |
| CPU time | 1.74 seconds |
| Started | Apr 21 01:01:04 PM PDT 24 |
| Finished | Apr 21 01:01:06 PM PDT 24 |
| Peak memory | 199980 kb |
| Host | smart-5a68e4bf-e78b-4736-8cd8-a4a81f421fa1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105956390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2105956390 |
| Directory | /workspace/7.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.775660530 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 199001433 ps |
| CPU time | 1.22 seconds |
| Started | Apr 21 01:01:00 PM PDT 24 |
| Finished | Apr 21 01:01:01 PM PDT 24 |
| Peak memory | 199248 kb |
| Host | smart-a3bd9940-96f4-4956-8ff1-f03375e3d4f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775660530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.775660530 |
| Directory | /workspace/7.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.640571612 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 189707568 ps |
| CPU time | 1.09 seconds |
| Started | Apr 21 01:01:03 PM PDT 24 |
| Finished | Apr 21 01:01:05 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-6f5cdd6b-960e-4b84-9983-bf094ced6ec9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640571612 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.640571612 |
| Directory | /workspace/8.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.uart_csr_rw.2456790028 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 107758674 ps |
| CPU time | 0.58 seconds |
| Started | Apr 21 01:01:00 PM PDT 24 |
| Finished | Apr 21 01:01:01 PM PDT 24 |
| Peak memory | 195792 kb |
| Host | smart-2cbee33f-38fc-49c3-9e46-7bbe3c37aabc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456790028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.2456790028 |
| Directory | /workspace/8.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.uart_intr_test.2793949826 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 88128974 ps |
| CPU time | 0.56 seconds |
| Started | Apr 21 01:01:01 PM PDT 24 |
| Finished | Apr 21 01:01:02 PM PDT 24 |
| Peak memory | 194372 kb |
| Host | smart-7f9251b5-f15b-44d0-bf45-ab3f4ecb9fb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793949826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.2793949826 |
| Directory | /workspace/8.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1598825144 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 54935236 ps |
| CPU time | 0.77 seconds |
| Started | Apr 21 01:01:02 PM PDT 24 |
| Finished | Apr 21 01:01:03 PM PDT 24 |
| Peak memory | 196972 kb |
| Host | smart-ef0954a8-5d1d-49e4-91e0-77197f79c48e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598825144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr _outstanding.1598825144 |
| Directory | /workspace/8.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.uart_tl_errors.2034380653 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 18628538 ps |
| CPU time | 0.94 seconds |
| Started | Apr 21 01:01:02 PM PDT 24 |
| Finished | Apr 21 01:01:04 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-41fb4415-af73-4d5c-a7be-2c418b8afa71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034380653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.2034380653 |
| Directory | /workspace/8.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1972483902 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 136231064 ps |
| CPU time | 0.97 seconds |
| Started | Apr 21 01:01:02 PM PDT 24 |
| Finished | Apr 21 01:01:03 PM PDT 24 |
| Peak memory | 198860 kb |
| Host | smart-98b6a67b-213f-4ad6-bab8-4826ac4a2563 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972483902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.1972483902 |
| Directory | /workspace/8.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1384074702 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 15094916 ps |
| CPU time | 0.69 seconds |
| Started | Apr 21 01:01:05 PM PDT 24 |
| Finished | Apr 21 01:01:06 PM PDT 24 |
| Peak memory | 197816 kb |
| Host | smart-eec04f27-2b90-4be9-adcc-afb21b9a90fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384074702 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.1384074702 |
| Directory | /workspace/9.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.uart_csr_rw.265289918 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 27556824 ps |
| CPU time | 0.62 seconds |
| Started | Apr 21 01:01:03 PM PDT 24 |
| Finished | Apr 21 01:01:04 PM PDT 24 |
| Peak memory | 195584 kb |
| Host | smart-ac2cdc55-c61e-4278-8ed6-2cffc8513b8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265289918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.265289918 |
| Directory | /workspace/9.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.uart_intr_test.4073753788 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 40830483 ps |
| CPU time | 0.56 seconds |
| Started | Apr 21 01:01:03 PM PDT 24 |
| Finished | Apr 21 01:01:04 PM PDT 24 |
| Peak memory | 194368 kb |
| Host | smart-9d21c910-1d0d-47f9-b738-212bc84151cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073753788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.4073753788 |
| Directory | /workspace/9.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2935548954 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 48099013 ps |
| CPU time | 0.7 seconds |
| Started | Apr 21 01:01:03 PM PDT 24 |
| Finished | Apr 21 01:01:04 PM PDT 24 |
| Peak memory | 195780 kb |
| Host | smart-1dc64d67-9940-4706-bc23-7842726ea096 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935548954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr _outstanding.2935548954 |
| Directory | /workspace/9.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.uart_tl_errors.2036777868 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 40399020 ps |
| CPU time | 2.02 seconds |
| Started | Apr 21 01:01:03 PM PDT 24 |
| Finished | Apr 21 01:01:06 PM PDT 24 |
| Peak memory | 200028 kb |
| Host | smart-8f5b1442-47bc-432e-a661-05337f0c8ffc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036777868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.2036777868 |
| Directory | /workspace/9.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1747724148 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 34753364 ps |
| CPU time | 0.88 seconds |
| Started | Apr 21 01:00:59 PM PDT 24 |
| Finished | Apr 21 01:01:00 PM PDT 24 |
| Peak memory | 198996 kb |
| Host | smart-1b945f8d-b870-40a0-b35b-c2c508f159c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747724148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.1747724148 |
| Directory | /workspace/9.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.uart_fifo_full.2819438340 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 128627366942 ps |
| CPU time | 62.76 seconds |
| Started | Apr 21 04:24:58 PM PDT 24 |
| Finished | Apr 21 04:26:01 PM PDT 24 |
| Peak memory | 200916 kb |
| Host | smart-b3270533-2004-4b07-9fb7-cb72231078ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2819438340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.2819438340 |
| Directory | /workspace/0.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/0.uart_fifo_overflow.2918550859 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 64855778633 ps |
| CPU time | 111.82 seconds |
| Started | Apr 21 04:24:58 PM PDT 24 |
| Finished | Apr 21 04:26:50 PM PDT 24 |
| Peak memory | 200900 kb |
| Host | smart-99cc7f3c-37f9-4916-839e-61e607e5117e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2918550859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.2918550859 |
| Directory | /workspace/0.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/0.uart_fifo_reset.3396518339 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 123666078169 ps |
| CPU time | 46.82 seconds |
| Started | Apr 21 04:25:06 PM PDT 24 |
| Finished | Apr 21 04:25:53 PM PDT 24 |
| Peak memory | 200904 kb |
| Host | smart-a268a626-d0a9-4fdc-93e1-56ba114cca93 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3396518339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.3396518339 |
| Directory | /workspace/0.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/0.uart_intr.423834061 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 31883037986 ps |
| CPU time | 31.59 seconds |
| Started | Apr 21 04:25:06 PM PDT 24 |
| Finished | Apr 21 04:25:38 PM PDT 24 |
| Peak memory | 200628 kb |
| Host | smart-ebf34a43-7a0d-4349-8c6f-63c1eeeed0a1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423834061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.423834061 |
| Directory | /workspace/0.uart_intr/latest |
| Test location | /workspace/coverage/default/0.uart_long_xfer_wo_dly.4173923893 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 90540891667 ps |
| CPU time | 506.45 seconds |
| Started | Apr 21 04:25:12 PM PDT 24 |
| Finished | Apr 21 04:33:39 PM PDT 24 |
| Peak memory | 200924 kb |
| Host | smart-bd7f404d-c1b5-4ec5-9fb1-a92a3128216a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4173923893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.4173923893 |
| Directory | /workspace/0.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/0.uart_loopback.806680923 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 7152912077 ps |
| CPU time | 4.46 seconds |
| Started | Apr 21 04:25:11 PM PDT 24 |
| Finished | Apr 21 04:25:16 PM PDT 24 |
| Peak memory | 200228 kb |
| Host | smart-c98d6fe8-76fa-462b-8a24-5983111c994c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=806680923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.806680923 |
| Directory | /workspace/0.uart_loopback/latest |
| Test location | /workspace/coverage/default/0.uart_noise_filter.3240652414 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 140531377790 ps |
| CPU time | 125.99 seconds |
| Started | Apr 21 04:25:05 PM PDT 24 |
| Finished | Apr 21 04:27:11 PM PDT 24 |
| Peak memory | 209276 kb |
| Host | smart-92a3598e-4dc3-4b6c-9c2a-68746dd9130c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3240652414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.3240652414 |
| Directory | /workspace/0.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/0.uart_perf.2355774084 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 25641195385 ps |
| CPU time | 685.53 seconds |
| Started | Apr 21 04:25:11 PM PDT 24 |
| Finished | Apr 21 04:36:37 PM PDT 24 |
| Peak memory | 200924 kb |
| Host | smart-b79417f0-4f86-4c2f-a16b-e5fedffa398d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2355774084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.2355774084 |
| Directory | /workspace/0.uart_perf/latest |
| Test location | /workspace/coverage/default/0.uart_rx_oversample.265792307 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 5569101333 ps |
| CPU time | 51.61 seconds |
| Started | Apr 21 04:25:04 PM PDT 24 |
| Finished | Apr 21 04:25:56 PM PDT 24 |
| Peak memory | 200232 kb |
| Host | smart-1fd9c517-b0a8-4ea8-abc2-1c893f7d9dd8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=265792307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.265792307 |
| Directory | /workspace/0.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/0.uart_rx_parity_err.974255031 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 31822068000 ps |
| CPU time | 26.22 seconds |
| Started | Apr 21 04:25:08 PM PDT 24 |
| Finished | Apr 21 04:25:34 PM PDT 24 |
| Peak memory | 200868 kb |
| Host | smart-a1882510-85da-4098-9135-be26bccbd5b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=974255031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.974255031 |
| Directory | /workspace/0.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/0.uart_rx_start_bit_filter.3570154262 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 1932550806 ps |
| CPU time | 1.38 seconds |
| Started | Apr 21 04:25:08 PM PDT 24 |
| Finished | Apr 21 04:25:10 PM PDT 24 |
| Peak memory | 196304 kb |
| Host | smart-82930ef9-a8fd-40ea-856b-e48775045c31 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3570154262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.3570154262 |
| Directory | /workspace/0.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/0.uart_smoke.1619433922 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 275964322 ps |
| CPU time | 1.46 seconds |
| Started | Apr 21 04:25:02 PM PDT 24 |
| Finished | Apr 21 04:25:04 PM PDT 24 |
| Peak memory | 200052 kb |
| Host | smart-cb4d1932-4b01-4c06-b924-20e65eb6b2c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1619433922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.1619433922 |
| Directory | /workspace/0.uart_smoke/latest |
| Test location | /workspace/coverage/default/0.uart_stress_all.2480752000 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 88941669697 ps |
| CPU time | 308.81 seconds |
| Started | Apr 21 04:25:15 PM PDT 24 |
| Finished | Apr 21 04:30:24 PM PDT 24 |
| Peak memory | 200872 kb |
| Host | smart-183448d7-a507-43b3-99e3-2a0e973288b1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480752000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.2480752000 |
| Directory | /workspace/0.uart_stress_all/latest |
| Test location | /workspace/coverage/default/0.uart_stress_all_with_rand_reset.2675041741 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 436466695310 ps |
| CPU time | 649.52 seconds |
| Started | Apr 21 04:25:15 PM PDT 24 |
| Finished | Apr 21 04:36:05 PM PDT 24 |
| Peak memory | 229756 kb |
| Host | smart-65e23f84-f9a6-449a-8999-1b686655dbc7 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675041741 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.2675041741 |
| Directory | /workspace/0.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.uart_tx_ovrd.1740691519 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 6760006623 ps |
| CPU time | 15.61 seconds |
| Started | Apr 21 04:25:10 PM PDT 24 |
| Finished | Apr 21 04:25:26 PM PDT 24 |
| Peak memory | 200856 kb |
| Host | smart-b2d8e273-6c07-4afc-9e23-dd99a11a0ba3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1740691519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.1740691519 |
| Directory | /workspace/0.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/0.uart_tx_rx.216807538 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 39299369867 ps |
| CPU time | 60.43 seconds |
| Started | Apr 21 04:25:02 PM PDT 24 |
| Finished | Apr 21 04:26:02 PM PDT 24 |
| Peak memory | 200904 kb |
| Host | smart-aa069ca4-24f0-404d-b5d8-175dd80bd28a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=216807538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.216807538 |
| Directory | /workspace/0.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/1.uart_alert_test.907428320 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 13685784 ps |
| CPU time | 0.58 seconds |
| Started | Apr 21 04:25:35 PM PDT 24 |
| Finished | Apr 21 04:25:35 PM PDT 24 |
| Peak memory | 196244 kb |
| Host | smart-2b7ff26a-f8b9-43b6-ba57-c404032df006 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907428320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.907428320 |
| Directory | /workspace/1.uart_alert_test/latest |
| Test location | /workspace/coverage/default/1.uart_fifo_full.1811190865 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 125536081494 ps |
| CPU time | 145.03 seconds |
| Started | Apr 21 04:25:22 PM PDT 24 |
| Finished | Apr 21 04:27:47 PM PDT 24 |
| Peak memory | 200896 kb |
| Host | smart-500de7b0-1423-4d80-a97b-85496199e166 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1811190865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.1811190865 |
| Directory | /workspace/1.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/1.uart_fifo_overflow.2351293794 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 13436718068 ps |
| CPU time | 25.84 seconds |
| Started | Apr 21 04:25:21 PM PDT 24 |
| Finished | Apr 21 04:25:47 PM PDT 24 |
| Peak memory | 200912 kb |
| Host | smart-d8e7fb43-07d1-49c1-ab57-0395062b6999 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2351293794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.2351293794 |
| Directory | /workspace/1.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/1.uart_fifo_reset.3416770539 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 27570551733 ps |
| CPU time | 34.67 seconds |
| Started | Apr 21 04:25:25 PM PDT 24 |
| Finished | Apr 21 04:26:00 PM PDT 24 |
| Peak memory | 200904 kb |
| Host | smart-03af2386-fd94-4bb8-84c1-50f2402b08c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3416770539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.3416770539 |
| Directory | /workspace/1.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/1.uart_intr.1020119459 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 12386808048 ps |
| CPU time | 5.86 seconds |
| Started | Apr 21 04:25:25 PM PDT 24 |
| Finished | Apr 21 04:25:31 PM PDT 24 |
| Peak memory | 200300 kb |
| Host | smart-0abba76b-106b-4ecd-9626-c0ad84909b6e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020119459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.1020119459 |
| Directory | /workspace/1.uart_intr/latest |
| Test location | /workspace/coverage/default/1.uart_long_xfer_wo_dly.1944336848 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 131381238015 ps |
| CPU time | 871.77 seconds |
| Started | Apr 21 04:25:32 PM PDT 24 |
| Finished | Apr 21 04:40:04 PM PDT 24 |
| Peak memory | 200888 kb |
| Host | smart-e844b543-69ff-4104-9117-a7c5c9c9903d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1944336848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.1944336848 |
| Directory | /workspace/1.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/1.uart_loopback.3861818959 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 10972636771 ps |
| CPU time | 6.9 seconds |
| Started | Apr 21 04:25:30 PM PDT 24 |
| Finished | Apr 21 04:25:37 PM PDT 24 |
| Peak memory | 200760 kb |
| Host | smart-b40a1c82-02e0-41b2-b1f4-20b6892ff740 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3861818959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.3861818959 |
| Directory | /workspace/1.uart_loopback/latest |
| Test location | /workspace/coverage/default/1.uart_noise_filter.2094221684 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 140168462973 ps |
| CPU time | 277.33 seconds |
| Started | Apr 21 04:25:26 PM PDT 24 |
| Finished | Apr 21 04:30:03 PM PDT 24 |
| Peak memory | 200816 kb |
| Host | smart-d31bd3b1-f3cf-41d9-9dec-610628c800ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2094221684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.2094221684 |
| Directory | /workspace/1.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/1.uart_perf.2019027432 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 30212721184 ps |
| CPU time | 231.01 seconds |
| Started | Apr 21 04:25:29 PM PDT 24 |
| Finished | Apr 21 04:29:20 PM PDT 24 |
| Peak memory | 200892 kb |
| Host | smart-6d9455a7-05fd-494a-831e-b415a49eb9cd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2019027432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.2019027432 |
| Directory | /workspace/1.uart_perf/latest |
| Test location | /workspace/coverage/default/1.uart_rx_oversample.3226887756 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 2843696050 ps |
| CPU time | 14.6 seconds |
| Started | Apr 21 04:25:24 PM PDT 24 |
| Finished | Apr 21 04:25:39 PM PDT 24 |
| Peak memory | 199020 kb |
| Host | smart-1cb90b48-6275-49dd-8327-8679e84e11ca |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3226887756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.3226887756 |
| Directory | /workspace/1.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/1.uart_rx_parity_err.1809237438 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 307512033479 ps |
| CPU time | 614.5 seconds |
| Started | Apr 21 04:25:26 PM PDT 24 |
| Finished | Apr 21 04:35:41 PM PDT 24 |
| Peak memory | 200948 kb |
| Host | smart-7df3577c-fca8-432d-8590-bc6b26734479 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1809237438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.1809237438 |
| Directory | /workspace/1.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/1.uart_rx_start_bit_filter.3502126117 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 1297017125 ps |
| CPU time | 1.89 seconds |
| Started | Apr 21 04:25:27 PM PDT 24 |
| Finished | Apr 21 04:25:30 PM PDT 24 |
| Peak memory | 196316 kb |
| Host | smart-bd413041-428c-4391-8af5-fed2aea6f8c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3502126117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.3502126117 |
| Directory | /workspace/1.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/1.uart_sec_cm.2158980811 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 282698532 ps |
| CPU time | 0.85 seconds |
| Started | Apr 21 04:25:34 PM PDT 24 |
| Finished | Apr 21 04:25:35 PM PDT 24 |
| Peak memory | 218908 kb |
| Host | smart-eacf4382-3210-4838-8e6c-a94224bdf08e |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158980811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.2158980811 |
| Directory | /workspace/1.uart_sec_cm/latest |
| Test location | /workspace/coverage/default/1.uart_smoke.3260039423 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 532264479 ps |
| CPU time | 1.23 seconds |
| Started | Apr 21 04:25:19 PM PDT 24 |
| Finished | Apr 21 04:25:20 PM PDT 24 |
| Peak memory | 199136 kb |
| Host | smart-f263631f-58be-4b9b-8496-67d34d739378 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3260039423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.3260039423 |
| Directory | /workspace/1.uart_smoke/latest |
| Test location | /workspace/coverage/default/1.uart_stress_all.314691045 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 257377727112 ps |
| CPU time | 451.27 seconds |
| Started | Apr 21 04:25:31 PM PDT 24 |
| Finished | Apr 21 04:33:03 PM PDT 24 |
| Peak memory | 200892 kb |
| Host | smart-8bae49e1-ca9d-4546-a98a-9834b5347057 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314691045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.314691045 |
| Directory | /workspace/1.uart_stress_all/latest |
| Test location | /workspace/coverage/default/1.uart_stress_all_with_rand_reset.1018836397 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 66093934037 ps |
| CPU time | 411.84 seconds |
| Started | Apr 21 04:25:33 PM PDT 24 |
| Finished | Apr 21 04:32:25 PM PDT 24 |
| Peak memory | 217364 kb |
| Host | smart-553545fd-a932-422e-99eb-27303d70bfa8 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018836397 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.1018836397 |
| Directory | /workspace/1.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.uart_tx_ovrd.2292291588 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 2192438739 ps |
| CPU time | 2 seconds |
| Started | Apr 21 04:25:27 PM PDT 24 |
| Finished | Apr 21 04:25:29 PM PDT 24 |
| Peak memory | 199256 kb |
| Host | smart-ba49ba9d-557f-4dea-a090-5c4fec34e402 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2292291588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.2292291588 |
| Directory | /workspace/1.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/1.uart_tx_rx.1746951974 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 279490969401 ps |
| CPU time | 60.08 seconds |
| Started | Apr 21 04:25:19 PM PDT 24 |
| Finished | Apr 21 04:26:20 PM PDT 24 |
| Peak memory | 200804 kb |
| Host | smart-6839cc64-fafd-4e8f-a45e-b9b5eb247afb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1746951974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.1746951974 |
| Directory | /workspace/1.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/10.uart_alert_test.1496119795 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 26981118 ps |
| CPU time | 0.58 seconds |
| Started | Apr 21 04:27:47 PM PDT 24 |
| Finished | Apr 21 04:27:48 PM PDT 24 |
| Peak memory | 196248 kb |
| Host | smart-54af3b19-2013-497c-9197-2bb75c37d444 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496119795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.1496119795 |
| Directory | /workspace/10.uart_alert_test/latest |
| Test location | /workspace/coverage/default/10.uart_fifo_overflow.2410683612 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 10807617264 ps |
| CPU time | 16.37 seconds |
| Started | Apr 21 04:27:37 PM PDT 24 |
| Finished | Apr 21 04:27:54 PM PDT 24 |
| Peak memory | 200712 kb |
| Host | smart-5c83a964-0ef0-4e6e-95e3-e796b3e4ca87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2410683612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.2410683612 |
| Directory | /workspace/10.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/10.uart_fifo_reset.3926177041 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 50107693700 ps |
| CPU time | 74.54 seconds |
| Started | Apr 21 04:27:41 PM PDT 24 |
| Finished | Apr 21 04:28:56 PM PDT 24 |
| Peak memory | 200920 kb |
| Host | smart-28b7d624-485a-4233-a3f9-3122767699eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3926177041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.3926177041 |
| Directory | /workspace/10.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/10.uart_intr.524687576 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 30253033415 ps |
| CPU time | 23.9 seconds |
| Started | Apr 21 04:27:41 PM PDT 24 |
| Finished | Apr 21 04:28:05 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-a48bfa03-3b0d-457b-a3bb-0ba89d96ea89 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524687576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.524687576 |
| Directory | /workspace/10.uart_intr/latest |
| Test location | /workspace/coverage/default/10.uart_long_xfer_wo_dly.3401874178 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 109649329735 ps |
| CPU time | 753.79 seconds |
| Started | Apr 21 04:27:45 PM PDT 24 |
| Finished | Apr 21 04:40:19 PM PDT 24 |
| Peak memory | 200860 kb |
| Host | smart-343184a8-114c-4955-9f8a-d7e9f48c5470 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3401874178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.3401874178 |
| Directory | /workspace/10.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/10.uart_loopback.1285725525 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 831952145 ps |
| CPU time | 1.15 seconds |
| Started | Apr 21 04:27:44 PM PDT 24 |
| Finished | Apr 21 04:27:45 PM PDT 24 |
| Peak memory | 198160 kb |
| Host | smart-4ab9b8cc-92cd-4868-8bb1-455d32403aed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1285725525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.1285725525 |
| Directory | /workspace/10.uart_loopback/latest |
| Test location | /workspace/coverage/default/10.uart_noise_filter.2225259949 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 28262954698 ps |
| CPU time | 44.06 seconds |
| Started | Apr 21 04:27:41 PM PDT 24 |
| Finished | Apr 21 04:28:25 PM PDT 24 |
| Peak memory | 201056 kb |
| Host | smart-ff22839e-91da-49ac-8334-4d00fcf1c020 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2225259949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.2225259949 |
| Directory | /workspace/10.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/10.uart_perf.1456986819 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 21093622815 ps |
| CPU time | 1161.84 seconds |
| Started | Apr 21 04:27:44 PM PDT 24 |
| Finished | Apr 21 04:47:06 PM PDT 24 |
| Peak memory | 200896 kb |
| Host | smart-ec8b4c11-2572-4292-876f-697f73392c56 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1456986819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.1456986819 |
| Directory | /workspace/10.uart_perf/latest |
| Test location | /workspace/coverage/default/10.uart_rx_oversample.3314016031 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 2318548740 ps |
| CPU time | 14.37 seconds |
| Started | Apr 21 04:27:40 PM PDT 24 |
| Finished | Apr 21 04:27:55 PM PDT 24 |
| Peak memory | 199236 kb |
| Host | smart-b5b2c612-4844-4f7a-bd18-7c24e2a43583 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3314016031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.3314016031 |
| Directory | /workspace/10.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/10.uart_rx_parity_err.1967692325 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 274604878529 ps |
| CPU time | 68.59 seconds |
| Started | Apr 21 04:27:41 PM PDT 24 |
| Finished | Apr 21 04:28:50 PM PDT 24 |
| Peak memory | 200856 kb |
| Host | smart-fd15edca-d8fb-4384-94ab-e3b6a938375a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1967692325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.1967692325 |
| Directory | /workspace/10.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/10.uart_rx_start_bit_filter.164156439 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 2731294007 ps |
| CPU time | 1.35 seconds |
| Started | Apr 21 04:27:40 PM PDT 24 |
| Finished | Apr 21 04:27:42 PM PDT 24 |
| Peak memory | 196628 kb |
| Host | smart-cf598e8a-2186-4b71-a418-c350a1bb3695 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=164156439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.164156439 |
| Directory | /workspace/10.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/10.uart_smoke.932662228 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 5302860974 ps |
| CPU time | 15.91 seconds |
| Started | Apr 21 04:27:35 PM PDT 24 |
| Finished | Apr 21 04:27:51 PM PDT 24 |
| Peak memory | 200660 kb |
| Host | smart-0e153fbf-b7b7-45be-a2ce-aed75e32638a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=932662228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.932662228 |
| Directory | /workspace/10.uart_smoke/latest |
| Test location | /workspace/coverage/default/10.uart_stress_all_with_rand_reset.3439196970 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 95513796253 ps |
| CPU time | 631.02 seconds |
| Started | Apr 21 04:27:45 PM PDT 24 |
| Finished | Apr 21 04:38:16 PM PDT 24 |
| Peak memory | 227376 kb |
| Host | smart-20946498-ac0c-4774-baa0-a7d05481e2e0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439196970 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.3439196970 |
| Directory | /workspace/10.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/10.uart_tx_ovrd.3128606148 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 1522993913 ps |
| CPU time | 1.86 seconds |
| Started | Apr 21 04:27:44 PM PDT 24 |
| Finished | Apr 21 04:27:46 PM PDT 24 |
| Peak memory | 199700 kb |
| Host | smart-4da3bf77-badc-4ed6-b0fa-f1e7c04027ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3128606148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.3128606148 |
| Directory | /workspace/10.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/10.uart_tx_rx.2198153424 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 27934999337 ps |
| CPU time | 52.36 seconds |
| Started | Apr 21 04:27:37 PM PDT 24 |
| Finished | Apr 21 04:28:29 PM PDT 24 |
| Peak memory | 200888 kb |
| Host | smart-cad2313a-ea0e-4e62-a4b2-51fe9a7ef1f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2198153424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.2198153424 |
| Directory | /workspace/10.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/100.uart_fifo_reset.2318124590 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 177372503090 ps |
| CPU time | 272.01 seconds |
| Started | Apr 21 04:36:39 PM PDT 24 |
| Finished | Apr 21 04:41:11 PM PDT 24 |
| Peak memory | 200824 kb |
| Host | smart-f4ca6968-ee01-4183-b23d-22c318495f50 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2318124590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.2318124590 |
| Directory | /workspace/100.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/101.uart_fifo_reset.3227828118 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 82221234318 ps |
| CPU time | 122.02 seconds |
| Started | Apr 21 04:36:39 PM PDT 24 |
| Finished | Apr 21 04:38:41 PM PDT 24 |
| Peak memory | 200876 kb |
| Host | smart-3a927b3c-084e-45f9-a034-10d7516b082d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3227828118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3227828118 |
| Directory | /workspace/101.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/102.uart_fifo_reset.1178301909 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 198691859730 ps |
| CPU time | 272.18 seconds |
| Started | Apr 21 04:36:44 PM PDT 24 |
| Finished | Apr 21 04:41:17 PM PDT 24 |
| Peak memory | 200852 kb |
| Host | smart-2e5714bb-bdd5-4d73-8ca3-06c32f786135 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1178301909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.1178301909 |
| Directory | /workspace/102.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/104.uart_fifo_reset.4072480155 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 83777412928 ps |
| CPU time | 145.7 seconds |
| Started | Apr 21 04:36:45 PM PDT 24 |
| Finished | Apr 21 04:39:11 PM PDT 24 |
| Peak memory | 200940 kb |
| Host | smart-1638d082-9ba0-4b01-9a7a-59974486b446 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4072480155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.4072480155 |
| Directory | /workspace/104.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/105.uart_fifo_reset.99589698 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 50459792412 ps |
| CPU time | 243.29 seconds |
| Started | Apr 21 04:36:44 PM PDT 24 |
| Finished | Apr 21 04:40:47 PM PDT 24 |
| Peak memory | 200912 kb |
| Host | smart-6f833ef2-1414-4a57-bfd8-3dba9e9e55c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=99589698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.99589698 |
| Directory | /workspace/105.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/107.uart_fifo_reset.361766270 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 38089565175 ps |
| CPU time | 66.28 seconds |
| Started | Apr 21 04:36:44 PM PDT 24 |
| Finished | Apr 21 04:37:51 PM PDT 24 |
| Peak memory | 200940 kb |
| Host | smart-86c1cb26-83ba-4851-8270-2562c9769832 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=361766270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.361766270 |
| Directory | /workspace/107.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/11.uart_alert_test.2004266763 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 25096021 ps |
| CPU time | 0.59 seconds |
| Started | Apr 21 04:28:07 PM PDT 24 |
| Finished | Apr 21 04:28:08 PM PDT 24 |
| Peak memory | 196200 kb |
| Host | smart-16d8e102-1538-4ed5-9160-4744349550bf |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004266763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.2004266763 |
| Directory | /workspace/11.uart_alert_test/latest |
| Test location | /workspace/coverage/default/11.uart_fifo_full.3657923731 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 86281882800 ps |
| CPU time | 26.84 seconds |
| Started | Apr 21 04:27:49 PM PDT 24 |
| Finished | Apr 21 04:28:16 PM PDT 24 |
| Peak memory | 200788 kb |
| Host | smart-fb0c2a98-d2ca-4eff-b6f4-153d41f2c668 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3657923731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.3657923731 |
| Directory | /workspace/11.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/11.uart_fifo_reset.3908729803 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 83772967929 ps |
| CPU time | 38.08 seconds |
| Started | Apr 21 04:27:51 PM PDT 24 |
| Finished | Apr 21 04:28:30 PM PDT 24 |
| Peak memory | 200856 kb |
| Host | smart-6061b567-313e-4a21-85d3-d5bef5543cef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3908729803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.3908729803 |
| Directory | /workspace/11.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/11.uart_intr.2330070442 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 43439574868 ps |
| CPU time | 16.03 seconds |
| Started | Apr 21 04:27:55 PM PDT 24 |
| Finished | Apr 21 04:28:11 PM PDT 24 |
| Peak memory | 200896 kb |
| Host | smart-bb784058-5594-4c8d-b850-8113e32839ed |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330070442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.2330070442 |
| Directory | /workspace/11.uart_intr/latest |
| Test location | /workspace/coverage/default/11.uart_long_xfer_wo_dly.267320403 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 216292658726 ps |
| CPU time | 194.51 seconds |
| Started | Apr 21 04:28:04 PM PDT 24 |
| Finished | Apr 21 04:31:19 PM PDT 24 |
| Peak memory | 200868 kb |
| Host | smart-baee6f13-6112-42e0-8acb-4605a7efa1ab |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=267320403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.267320403 |
| Directory | /workspace/11.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/11.uart_loopback.3839984716 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 8627608175 ps |
| CPU time | 16.18 seconds |
| Started | Apr 21 04:28:05 PM PDT 24 |
| Finished | Apr 21 04:28:22 PM PDT 24 |
| Peak memory | 200748 kb |
| Host | smart-0346d0ed-f37c-4807-9ade-b00c8688d345 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3839984716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.3839984716 |
| Directory | /workspace/11.uart_loopback/latest |
| Test location | /workspace/coverage/default/11.uart_noise_filter.2789140952 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 8627370302 ps |
| CPU time | 7.4 seconds |
| Started | Apr 21 04:27:56 PM PDT 24 |
| Finished | Apr 21 04:28:04 PM PDT 24 |
| Peak memory | 200864 kb |
| Host | smart-31615b3a-4948-4378-b6f4-9d931bae74ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2789140952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.2789140952 |
| Directory | /workspace/11.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/11.uart_perf.922863397 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 5705598533 ps |
| CPU time | 86.17 seconds |
| Started | Apr 21 04:28:05 PM PDT 24 |
| Finished | Apr 21 04:29:31 PM PDT 24 |
| Peak memory | 200840 kb |
| Host | smart-b8ea9d3d-d066-44b5-b5ce-264ed9e52f4f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=922863397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.922863397 |
| Directory | /workspace/11.uart_perf/latest |
| Test location | /workspace/coverage/default/11.uart_rx_oversample.2187751504 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 6189413038 ps |
| CPU time | 63.88 seconds |
| Started | Apr 21 04:27:51 PM PDT 24 |
| Finished | Apr 21 04:28:55 PM PDT 24 |
| Peak memory | 200036 kb |
| Host | smart-1985acc0-4511-4318-b9f3-7fd123089513 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2187751504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.2187751504 |
| Directory | /workspace/11.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/11.uart_rx_parity_err.3906142245 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 87677802111 ps |
| CPU time | 132.55 seconds |
| Started | Apr 21 04:28:04 PM PDT 24 |
| Finished | Apr 21 04:30:17 PM PDT 24 |
| Peak memory | 200820 kb |
| Host | smart-60de6f98-28b2-4af7-98f9-1af561ecbf37 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3906142245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.3906142245 |
| Directory | /workspace/11.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/11.uart_rx_start_bit_filter.1093156532 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 3184030948 ps |
| CPU time | 6.53 seconds |
| Started | Apr 21 04:28:10 PM PDT 24 |
| Finished | Apr 21 04:28:17 PM PDT 24 |
| Peak memory | 196744 kb |
| Host | smart-a7e96b11-afe7-4518-8c02-e4fd438d5bac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1093156532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.1093156532 |
| Directory | /workspace/11.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/11.uart_smoke.3824350542 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 120782424 ps |
| CPU time | 1.16 seconds |
| Started | Apr 21 04:27:48 PM PDT 24 |
| Finished | Apr 21 04:27:49 PM PDT 24 |
| Peak memory | 199100 kb |
| Host | smart-0bd03e65-fc85-4c13-8008-842e478d6699 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3824350542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.3824350542 |
| Directory | /workspace/11.uart_smoke/latest |
| Test location | /workspace/coverage/default/11.uart_stress_all.4204684446 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 383459808830 ps |
| CPU time | 758.95 seconds |
| Started | Apr 21 04:28:08 PM PDT 24 |
| Finished | Apr 21 04:40:47 PM PDT 24 |
| Peak memory | 209224 kb |
| Host | smart-3a13299b-964c-44eb-a62e-f8d05d850fb3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204684446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.4204684446 |
| Directory | /workspace/11.uart_stress_all/latest |
| Test location | /workspace/coverage/default/11.uart_stress_all_with_rand_reset.1606825644 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 182773821736 ps |
| CPU time | 763.33 seconds |
| Started | Apr 21 04:28:03 PM PDT 24 |
| Finished | Apr 21 04:40:47 PM PDT 24 |
| Peak memory | 214644 kb |
| Host | smart-f7f0cb03-d679-4bd7-a39a-caa08175e253 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606825644 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.1606825644 |
| Directory | /workspace/11.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/11.uart_tx_ovrd.640522377 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 971382481 ps |
| CPU time | 2.22 seconds |
| Started | Apr 21 04:28:03 PM PDT 24 |
| Finished | Apr 21 04:28:06 PM PDT 24 |
| Peak memory | 200536 kb |
| Host | smart-eece43b8-78b7-49c1-b490-1d621bc470b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=640522377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.640522377 |
| Directory | /workspace/11.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/11.uart_tx_rx.3564389211 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 20990290309 ps |
| CPU time | 9.96 seconds |
| Started | Apr 21 04:27:48 PM PDT 24 |
| Finished | Apr 21 04:27:58 PM PDT 24 |
| Peak memory | 200936 kb |
| Host | smart-b8317aa4-91df-4d23-a4ef-5a1704e6cd43 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3564389211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.3564389211 |
| Directory | /workspace/11.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/110.uart_fifo_reset.1206430300 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 110210383296 ps |
| CPU time | 44.64 seconds |
| Started | Apr 21 04:36:49 PM PDT 24 |
| Finished | Apr 21 04:37:34 PM PDT 24 |
| Peak memory | 200948 kb |
| Host | smart-63b4c20e-9968-4283-b66c-e26b29231ebb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1206430300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1206430300 |
| Directory | /workspace/110.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/111.uart_fifo_reset.3889568649 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11958951218 ps |
| CPU time | 25.99 seconds |
| Started | Apr 21 04:36:50 PM PDT 24 |
| Finished | Apr 21 04:37:16 PM PDT 24 |
| Peak memory | 200812 kb |
| Host | smart-a192e6d1-46b1-4722-86cb-5697deacee83 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3889568649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.3889568649 |
| Directory | /workspace/111.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/112.uart_fifo_reset.2617151373 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 51685937161 ps |
| CPU time | 94.27 seconds |
| Started | Apr 21 04:36:50 PM PDT 24 |
| Finished | Apr 21 04:38:25 PM PDT 24 |
| Peak memory | 200828 kb |
| Host | smart-e909ccf9-fb62-4f2e-a875-9d76efad2181 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2617151373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.2617151373 |
| Directory | /workspace/112.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/113.uart_fifo_reset.108173292 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 31447638840 ps |
| CPU time | 40.72 seconds |
| Started | Apr 21 04:36:50 PM PDT 24 |
| Finished | Apr 21 04:37:31 PM PDT 24 |
| Peak memory | 200812 kb |
| Host | smart-c4212e11-f3a5-4cbf-b880-c3f1050693c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=108173292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.108173292 |
| Directory | /workspace/113.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/114.uart_fifo_reset.1410288241 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 9837242329 ps |
| CPU time | 17.46 seconds |
| Started | Apr 21 04:36:54 PM PDT 24 |
| Finished | Apr 21 04:37:12 PM PDT 24 |
| Peak memory | 200916 kb |
| Host | smart-5c922002-af15-46d7-9ec0-4ec9c1d1780a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1410288241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.1410288241 |
| Directory | /workspace/114.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/115.uart_fifo_reset.3688172802 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 181203822343 ps |
| CPU time | 372.1 seconds |
| Started | Apr 21 04:36:58 PM PDT 24 |
| Finished | Apr 21 04:43:10 PM PDT 24 |
| Peak memory | 200868 kb |
| Host | smart-8dc12385-bb31-4f0e-9ddb-d0f9bc5ffe65 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3688172802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.3688172802 |
| Directory | /workspace/115.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/116.uart_fifo_reset.2759203726 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 65108009390 ps |
| CPU time | 15.92 seconds |
| Started | Apr 21 04:36:57 PM PDT 24 |
| Finished | Apr 21 04:37:13 PM PDT 24 |
| Peak memory | 200876 kb |
| Host | smart-a68710bf-5e94-4219-9bcd-1e34acd66ea1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2759203726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.2759203726 |
| Directory | /workspace/116.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/117.uart_fifo_reset.4062571042 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 56288802461 ps |
| CPU time | 33.03 seconds |
| Started | Apr 21 04:36:55 PM PDT 24 |
| Finished | Apr 21 04:37:28 PM PDT 24 |
| Peak memory | 200940 kb |
| Host | smart-b73ee2bf-8348-4955-84dd-e77c183186aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4062571042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.4062571042 |
| Directory | /workspace/117.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/118.uart_fifo_reset.733912711 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 31913942912 ps |
| CPU time | 52.92 seconds |
| Started | Apr 21 04:36:56 PM PDT 24 |
| Finished | Apr 21 04:37:49 PM PDT 24 |
| Peak memory | 200876 kb |
| Host | smart-62d6f045-4ea0-45fc-b183-fcc52e55f0a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=733912711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.733912711 |
| Directory | /workspace/118.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/119.uart_fifo_reset.4171195309 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 200295825371 ps |
| CPU time | 105.44 seconds |
| Started | Apr 21 04:36:58 PM PDT 24 |
| Finished | Apr 21 04:38:44 PM PDT 24 |
| Peak memory | 200924 kb |
| Host | smart-5b921708-9cc4-4bb7-8ffc-13814f74759d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4171195309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.4171195309 |
| Directory | /workspace/119.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/12.uart_alert_test.793772129 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 27189033 ps |
| CPU time | 0.56 seconds |
| Started | Apr 21 04:28:21 PM PDT 24 |
| Finished | Apr 21 04:28:22 PM PDT 24 |
| Peak memory | 195164 kb |
| Host | smart-6ad41345-f486-4202-9f79-5b8b6b15c072 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793772129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.793772129 |
| Directory | /workspace/12.uart_alert_test/latest |
| Test location | /workspace/coverage/default/12.uart_fifo_full.2627823593 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 129259338140 ps |
| CPU time | 218.9 seconds |
| Started | Apr 21 04:28:09 PM PDT 24 |
| Finished | Apr 21 04:31:48 PM PDT 24 |
| Peak memory | 200864 kb |
| Host | smart-0182748c-8858-4d1e-9895-2709f30fcb00 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2627823593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2627823593 |
| Directory | /workspace/12.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/12.uart_fifo_overflow.2800174904 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 10991976752 ps |
| CPU time | 17.89 seconds |
| Started | Apr 21 04:28:09 PM PDT 24 |
| Finished | Apr 21 04:28:27 PM PDT 24 |
| Peak memory | 200812 kb |
| Host | smart-d29c1c4c-8300-4d58-af4a-49c79386587b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2800174904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2800174904 |
| Directory | /workspace/12.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/12.uart_intr.2344537176 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 66064109096 ps |
| CPU time | 106.39 seconds |
| Started | Apr 21 04:28:11 PM PDT 24 |
| Finished | Apr 21 04:29:58 PM PDT 24 |
| Peak memory | 200860 kb |
| Host | smart-c2943289-cbba-48fd-9396-f057bb515566 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344537176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.2344537176 |
| Directory | /workspace/12.uart_intr/latest |
| Test location | /workspace/coverage/default/12.uart_long_xfer_wo_dly.707987327 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 194980419058 ps |
| CPU time | 446.02 seconds |
| Started | Apr 21 04:28:18 PM PDT 24 |
| Finished | Apr 21 04:35:45 PM PDT 24 |
| Peak memory | 200920 kb |
| Host | smart-5bf2f1d5-5ff2-4c1d-a6b3-5f794006a443 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=707987327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.707987327 |
| Directory | /workspace/12.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/12.uart_loopback.4121219169 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 3519677173 ps |
| CPU time | 7.29 seconds |
| Started | Apr 21 04:28:19 PM PDT 24 |
| Finished | Apr 21 04:28:27 PM PDT 24 |
| Peak memory | 200596 kb |
| Host | smart-9b8c0981-99a1-43bc-8006-ccbbbfc433aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4121219169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.4121219169 |
| Directory | /workspace/12.uart_loopback/latest |
| Test location | /workspace/coverage/default/12.uart_noise_filter.909796179 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 253078421553 ps |
| CPU time | 92.04 seconds |
| Started | Apr 21 04:28:15 PM PDT 24 |
| Finished | Apr 21 04:29:47 PM PDT 24 |
| Peak memory | 201104 kb |
| Host | smart-c0051b26-5337-4238-827b-76c4a80ec5c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=909796179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.909796179 |
| Directory | /workspace/12.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/12.uart_perf.2378528506 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 8252650040 ps |
| CPU time | 130.38 seconds |
| Started | Apr 21 04:28:17 PM PDT 24 |
| Finished | Apr 21 04:30:28 PM PDT 24 |
| Peak memory | 200916 kb |
| Host | smart-81e41e7d-21d7-4f4a-bd3c-02a30076c481 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2378528506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.2378528506 |
| Directory | /workspace/12.uart_perf/latest |
| Test location | /workspace/coverage/default/12.uart_rx_oversample.2950785530 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 4356480893 ps |
| CPU time | 8.93 seconds |
| Started | Apr 21 04:28:11 PM PDT 24 |
| Finished | Apr 21 04:28:21 PM PDT 24 |
| Peak memory | 198728 kb |
| Host | smart-a14c4887-842a-4650-9e3d-83798595f96d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2950785530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.2950785530 |
| Directory | /workspace/12.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/12.uart_rx_start_bit_filter.2721213882 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 2981569626 ps |
| CPU time | 5.36 seconds |
| Started | Apr 21 04:28:14 PM PDT 24 |
| Finished | Apr 21 04:28:20 PM PDT 24 |
| Peak memory | 197384 kb |
| Host | smart-473317de-b6bd-45cf-b011-cc77f1311350 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2721213882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.2721213882 |
| Directory | /workspace/12.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/12.uart_smoke.2457945576 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 5724223445 ps |
| CPU time | 15.82 seconds |
| Started | Apr 21 04:28:07 PM PDT 24 |
| Finished | Apr 21 04:28:23 PM PDT 24 |
| Peak memory | 200700 kb |
| Host | smart-1492008d-d1dc-40e6-883b-cf20af045e36 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2457945576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.2457945576 |
| Directory | /workspace/12.uart_smoke/latest |
| Test location | /workspace/coverage/default/12.uart_stress_all.1898747678 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 36824563491 ps |
| CPU time | 907.34 seconds |
| Started | Apr 21 04:28:17 PM PDT 24 |
| Finished | Apr 21 04:43:24 PM PDT 24 |
| Peak memory | 200856 kb |
| Host | smart-0f1812a1-08e1-4048-bdac-811428819813 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898747678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.1898747678 |
| Directory | /workspace/12.uart_stress_all/latest |
| Test location | /workspace/coverage/default/12.uart_tx_ovrd.569109450 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 7115808370 ps |
| CPU time | 20.49 seconds |
| Started | Apr 21 04:28:16 PM PDT 24 |
| Finished | Apr 21 04:28:37 PM PDT 24 |
| Peak memory | 200640 kb |
| Host | smart-d32a9127-11dd-43fa-90ee-3789bb99f1cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=569109450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.569109450 |
| Directory | /workspace/12.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/12.uart_tx_rx.2760406599 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 85588124180 ps |
| CPU time | 22.32 seconds |
| Started | Apr 21 04:28:07 PM PDT 24 |
| Finished | Apr 21 04:28:30 PM PDT 24 |
| Peak memory | 200840 kb |
| Host | smart-22781304-3e2d-4268-9916-3db478046b05 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2760406599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.2760406599 |
| Directory | /workspace/12.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/122.uart_fifo_reset.3396685093 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 33268831696 ps |
| CPU time | 15.44 seconds |
| Started | Apr 21 04:37:02 PM PDT 24 |
| Finished | Apr 21 04:37:18 PM PDT 24 |
| Peak memory | 200400 kb |
| Host | smart-2f819b8a-485d-4369-a438-4c83a4019f74 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3396685093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.3396685093 |
| Directory | /workspace/122.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/123.uart_fifo_reset.1838009483 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 38330504259 ps |
| CPU time | 32.21 seconds |
| Started | Apr 21 04:37:05 PM PDT 24 |
| Finished | Apr 21 04:37:37 PM PDT 24 |
| Peak memory | 201020 kb |
| Host | smart-f97d29b0-6acd-48c6-9f45-5d86d3e5001f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1838009483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1838009483 |
| Directory | /workspace/123.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/124.uart_fifo_reset.2283069010 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 119703224197 ps |
| CPU time | 63.9 seconds |
| Started | Apr 21 04:37:04 PM PDT 24 |
| Finished | Apr 21 04:38:08 PM PDT 24 |
| Peak memory | 200828 kb |
| Host | smart-f64e61a1-e252-467c-945b-b2de1baf90ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2283069010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.2283069010 |
| Directory | /workspace/124.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/125.uart_fifo_reset.701169516 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 35025936270 ps |
| CPU time | 16.51 seconds |
| Started | Apr 21 04:37:04 PM PDT 24 |
| Finished | Apr 21 04:37:21 PM PDT 24 |
| Peak memory | 200904 kb |
| Host | smart-b1b63088-b757-4119-b337-e371fbfa6e4a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=701169516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.701169516 |
| Directory | /workspace/125.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/126.uart_fifo_reset.1296570442 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 100912035901 ps |
| CPU time | 155.11 seconds |
| Started | Apr 21 04:37:09 PM PDT 24 |
| Finished | Apr 21 04:39:45 PM PDT 24 |
| Peak memory | 200892 kb |
| Host | smart-f7fb2ee6-23c8-45c4-9a33-e024f4da4f25 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1296570442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.1296570442 |
| Directory | /workspace/126.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/128.uart_fifo_reset.2453800654 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 4501154541 ps |
| CPU time | 7.24 seconds |
| Started | Apr 21 04:37:08 PM PDT 24 |
| Finished | Apr 21 04:37:16 PM PDT 24 |
| Peak memory | 199172 kb |
| Host | smart-93ce0d23-13c1-48be-8133-e4472db8cf7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2453800654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.2453800654 |
| Directory | /workspace/128.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/129.uart_fifo_reset.2029663998 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 144931878546 ps |
| CPU time | 80.25 seconds |
| Started | Apr 21 04:37:08 PM PDT 24 |
| Finished | Apr 21 04:38:28 PM PDT 24 |
| Peak memory | 200864 kb |
| Host | smart-8861ef2c-5a27-43b9-a1b4-4239133a6477 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2029663998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2029663998 |
| Directory | /workspace/129.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/13.uart_alert_test.1408005315 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 15157706 ps |
| CPU time | 0.59 seconds |
| Started | Apr 21 04:28:33 PM PDT 24 |
| Finished | Apr 21 04:28:34 PM PDT 24 |
| Peak memory | 196240 kb |
| Host | smart-7655e5ed-c967-4572-947f-3c662451d7f2 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408005315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.1408005315 |
| Directory | /workspace/13.uart_alert_test/latest |
| Test location | /workspace/coverage/default/13.uart_fifo_full.633054459 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 167971310525 ps |
| CPU time | 64.87 seconds |
| Started | Apr 21 04:28:19 PM PDT 24 |
| Finished | Apr 21 04:29:24 PM PDT 24 |
| Peak memory | 200872 kb |
| Host | smart-b751cf83-bdd1-4d94-956e-eacfa697dce3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=633054459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.633054459 |
| Directory | /workspace/13.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/13.uart_fifo_overflow.2456213423 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 161134013820 ps |
| CPU time | 117.98 seconds |
| Started | Apr 21 04:28:20 PM PDT 24 |
| Finished | Apr 21 04:30:18 PM PDT 24 |
| Peak memory | 200904 kb |
| Host | smart-f2056e8f-144f-4b2f-be60-8082a05b136f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2456213423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2456213423 |
| Directory | /workspace/13.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/13.uart_intr.545758250 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 16464018671 ps |
| CPU time | 3.16 seconds |
| Started | Apr 21 04:28:25 PM PDT 24 |
| Finished | Apr 21 04:28:29 PM PDT 24 |
| Peak memory | 200360 kb |
| Host | smart-62208e5b-92f1-429d-a664-123c98a2ab37 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545758250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.545758250 |
| Directory | /workspace/13.uart_intr/latest |
| Test location | /workspace/coverage/default/13.uart_long_xfer_wo_dly.1421727812 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 83082079439 ps |
| CPU time | 881.95 seconds |
| Started | Apr 21 04:28:30 PM PDT 24 |
| Finished | Apr 21 04:43:13 PM PDT 24 |
| Peak memory | 200912 kb |
| Host | smart-1750d580-38ce-4022-9282-6ed8f24fc291 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1421727812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.1421727812 |
| Directory | /workspace/13.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/13.uart_loopback.727586493 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 6221118223 ps |
| CPU time | 15.22 seconds |
| Started | Apr 21 04:28:30 PM PDT 24 |
| Finished | Apr 21 04:28:46 PM PDT 24 |
| Peak memory | 200176 kb |
| Host | smart-068de9c2-45d2-458a-bdd3-812b5f2f89ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=727586493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.727586493 |
| Directory | /workspace/13.uart_loopback/latest |
| Test location | /workspace/coverage/default/13.uart_noise_filter.2309416182 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 54042892820 ps |
| CPU time | 19.45 seconds |
| Started | Apr 21 04:28:25 PM PDT 24 |
| Finished | Apr 21 04:28:45 PM PDT 24 |
| Peak memory | 199020 kb |
| Host | smart-7b37e6e9-2b7d-4f6e-abd9-bb827407e0f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2309416182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.2309416182 |
| Directory | /workspace/13.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/13.uart_perf.1756701133 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 18323846543 ps |
| CPU time | 563 seconds |
| Started | Apr 21 04:28:32 PM PDT 24 |
| Finished | Apr 21 04:37:55 PM PDT 24 |
| Peak memory | 200924 kb |
| Host | smart-f7790f29-8e77-494e-8a4d-63daccecadfc |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1756701133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.1756701133 |
| Directory | /workspace/13.uart_perf/latest |
| Test location | /workspace/coverage/default/13.uart_rx_oversample.3831562162 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 3293202828 ps |
| CPU time | 27.44 seconds |
| Started | Apr 21 04:28:21 PM PDT 24 |
| Finished | Apr 21 04:28:49 PM PDT 24 |
| Peak memory | 198876 kb |
| Host | smart-42c7e85d-266b-4010-8acb-93f43c69e447 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3831562162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.3831562162 |
| Directory | /workspace/13.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/13.uart_rx_parity_err.1833592248 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 7739078103 ps |
| CPU time | 13.14 seconds |
| Started | Apr 21 04:28:28 PM PDT 24 |
| Finished | Apr 21 04:28:41 PM PDT 24 |
| Peak memory | 200252 kb |
| Host | smart-14140162-284d-4393-bbd2-997a1780bc19 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1833592248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.1833592248 |
| Directory | /workspace/13.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/13.uart_rx_start_bit_filter.29607518 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 46178870742 ps |
| CPU time | 40.26 seconds |
| Started | Apr 21 04:28:28 PM PDT 24 |
| Finished | Apr 21 04:29:09 PM PDT 24 |
| Peak memory | 197232 kb |
| Host | smart-ee6f77c8-de49-4b77-b5f1-1ae01cff5d69 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=29607518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.29607518 |
| Directory | /workspace/13.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/13.uart_smoke.3456906467 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 278874034 ps |
| CPU time | 1.28 seconds |
| Started | Apr 21 04:28:20 PM PDT 24 |
| Finished | Apr 21 04:28:22 PM PDT 24 |
| Peak memory | 199188 kb |
| Host | smart-42df25de-788c-4b4f-80ac-56482d6cdcd2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3456906467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.3456906467 |
| Directory | /workspace/13.uart_smoke/latest |
| Test location | /workspace/coverage/default/13.uart_stress_all.3456272829 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 126635809296 ps |
| CPU time | 510.24 seconds |
| Started | Apr 21 04:28:35 PM PDT 24 |
| Finished | Apr 21 04:37:05 PM PDT 24 |
| Peak memory | 209196 kb |
| Host | smart-8d1523c5-55ea-4f05-aa6e-863432b2ea79 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456272829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.3456272829 |
| Directory | /workspace/13.uart_stress_all/latest |
| Test location | /workspace/coverage/default/13.uart_tx_ovrd.3807348523 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 4333261425 ps |
| CPU time | 1.76 seconds |
| Started | Apr 21 04:28:31 PM PDT 24 |
| Finished | Apr 21 04:28:33 PM PDT 24 |
| Peak memory | 200056 kb |
| Host | smart-93e4796c-b07d-4fe2-bf66-aebb5fdd48bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3807348523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.3807348523 |
| Directory | /workspace/13.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/13.uart_tx_rx.4200341764 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 30974014073 ps |
| CPU time | 21.1 seconds |
| Started | Apr 21 04:28:19 PM PDT 24 |
| Finished | Apr 21 04:28:40 PM PDT 24 |
| Peak memory | 200676 kb |
| Host | smart-0a4bc60a-cc7b-4d1e-854f-8093ac148b74 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4200341764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.4200341764 |
| Directory | /workspace/13.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/130.uart_fifo_reset.2652961450 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 33790248754 ps |
| CPU time | 16.3 seconds |
| Started | Apr 21 04:37:09 PM PDT 24 |
| Finished | Apr 21 04:37:26 PM PDT 24 |
| Peak memory | 200828 kb |
| Host | smart-59642cd1-24be-4a4c-95f9-8faa426d22e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2652961450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2652961450 |
| Directory | /workspace/130.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/131.uart_fifo_reset.2402240129 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 147352609537 ps |
| CPU time | 14.42 seconds |
| Started | Apr 21 04:37:09 PM PDT 24 |
| Finished | Apr 21 04:37:24 PM PDT 24 |
| Peak memory | 200852 kb |
| Host | smart-6aabebf2-7ef4-44df-affa-c6d9d7dc452d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2402240129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.2402240129 |
| Directory | /workspace/131.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/133.uart_fifo_reset.4107157418 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 24500767941 ps |
| CPU time | 38.91 seconds |
| Started | Apr 21 04:37:13 PM PDT 24 |
| Finished | Apr 21 04:37:52 PM PDT 24 |
| Peak memory | 200880 kb |
| Host | smart-04a5a634-4c49-473f-828b-4bb781f3372f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4107157418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.4107157418 |
| Directory | /workspace/133.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/135.uart_fifo_reset.4070863967 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 157658554536 ps |
| CPU time | 116.49 seconds |
| Started | Apr 21 04:37:15 PM PDT 24 |
| Finished | Apr 21 04:39:12 PM PDT 24 |
| Peak memory | 200868 kb |
| Host | smart-097a9108-e338-4f0c-8f1b-0563bb1a38e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4070863967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.4070863967 |
| Directory | /workspace/135.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/136.uart_fifo_reset.1357955887 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 22608127556 ps |
| CPU time | 36.98 seconds |
| Started | Apr 21 04:37:15 PM PDT 24 |
| Finished | Apr 21 04:37:52 PM PDT 24 |
| Peak memory | 200700 kb |
| Host | smart-3a1ec7a6-0556-4b32-b123-c3e96e3dfd57 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1357955887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.1357955887 |
| Directory | /workspace/136.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/137.uart_fifo_reset.3799215842 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 225816935160 ps |
| CPU time | 423.34 seconds |
| Started | Apr 21 04:37:18 PM PDT 24 |
| Finished | Apr 21 04:44:21 PM PDT 24 |
| Peak memory | 200840 kb |
| Host | smart-2f76f011-17f8-42ac-a4a4-42c2aa5b8c5f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3799215842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.3799215842 |
| Directory | /workspace/137.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/138.uart_fifo_reset.1704440812 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 64449638183 ps |
| CPU time | 78.33 seconds |
| Started | Apr 21 04:37:21 PM PDT 24 |
| Finished | Apr 21 04:38:40 PM PDT 24 |
| Peak memory | 200828 kb |
| Host | smart-e3731921-5819-4f34-b1a5-1e8d5bacba88 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1704440812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.1704440812 |
| Directory | /workspace/138.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/139.uart_fifo_reset.3857738095 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 97981995149 ps |
| CPU time | 84.27 seconds |
| Started | Apr 21 04:37:20 PM PDT 24 |
| Finished | Apr 21 04:38:45 PM PDT 24 |
| Peak memory | 200932 kb |
| Host | smart-115ea335-cf91-4b2c-85dd-8e439c294397 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3857738095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.3857738095 |
| Directory | /workspace/139.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/14.uart_alert_test.594149349 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 34498681 ps |
| CPU time | 0.55 seconds |
| Started | Apr 21 04:28:46 PM PDT 24 |
| Finished | Apr 21 04:28:47 PM PDT 24 |
| Peak memory | 195712 kb |
| Host | smart-c43b889b-196e-466d-9649-f2b8dc02787f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594149349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.594149349 |
| Directory | /workspace/14.uart_alert_test/latest |
| Test location | /workspace/coverage/default/14.uart_fifo_full.3227503372 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 136158579549 ps |
| CPU time | 412.85 seconds |
| Started | Apr 21 04:28:36 PM PDT 24 |
| Finished | Apr 21 04:35:29 PM PDT 24 |
| Peak memory | 200856 kb |
| Host | smart-d03d3a65-4d1e-4e7f-a4fb-c0c62baa05ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3227503372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.3227503372 |
| Directory | /workspace/14.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/14.uart_fifo_overflow.3777968312 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 56748494172 ps |
| CPU time | 99.71 seconds |
| Started | Apr 21 04:28:36 PM PDT 24 |
| Finished | Apr 21 04:30:16 PM PDT 24 |
| Peak memory | 200904 kb |
| Host | smart-02ec837e-e311-4996-8f10-b33a61c1a9b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3777968312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.3777968312 |
| Directory | /workspace/14.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/14.uart_fifo_reset.1263436565 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 102996985979 ps |
| CPU time | 88.22 seconds |
| Started | Apr 21 04:28:37 PM PDT 24 |
| Finished | Apr 21 04:30:06 PM PDT 24 |
| Peak memory | 200860 kb |
| Host | smart-082a8e09-03f1-440d-a6ee-7da0421a0440 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1263436565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.1263436565 |
| Directory | /workspace/14.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/14.uart_intr.176122735 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 38632974676 ps |
| CPU time | 47.52 seconds |
| Started | Apr 21 04:28:39 PM PDT 24 |
| Finished | Apr 21 04:29:27 PM PDT 24 |
| Peak memory | 200928 kb |
| Host | smart-0b17824b-c04f-46d8-a551-9c5a12597f58 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176122735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.176122735 |
| Directory | /workspace/14.uart_intr/latest |
| Test location | /workspace/coverage/default/14.uart_long_xfer_wo_dly.1838729842 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 108712424109 ps |
| CPU time | 659.03 seconds |
| Started | Apr 21 04:28:46 PM PDT 24 |
| Finished | Apr 21 04:39:46 PM PDT 24 |
| Peak memory | 200936 kb |
| Host | smart-0b57e324-f0d6-413c-88d4-0f3ea7b9d959 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1838729842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.1838729842 |
| Directory | /workspace/14.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/14.uart_loopback.2588229000 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 835954886 ps |
| CPU time | 3.15 seconds |
| Started | Apr 21 04:28:45 PM PDT 24 |
| Finished | Apr 21 04:28:49 PM PDT 24 |
| Peak memory | 199396 kb |
| Host | smart-fc01f159-6165-4334-879c-20b92e321d70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2588229000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.2588229000 |
| Directory | /workspace/14.uart_loopback/latest |
| Test location | /workspace/coverage/default/14.uart_noise_filter.2326066770 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 163434567358 ps |
| CPU time | 93.12 seconds |
| Started | Apr 21 04:28:47 PM PDT 24 |
| Finished | Apr 21 04:30:21 PM PDT 24 |
| Peak memory | 200856 kb |
| Host | smart-e16b678b-2fc1-48e0-abd1-443d9b190a44 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2326066770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.2326066770 |
| Directory | /workspace/14.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/14.uart_perf.1932626875 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 13056520616 ps |
| CPU time | 537.02 seconds |
| Started | Apr 21 04:28:46 PM PDT 24 |
| Finished | Apr 21 04:37:44 PM PDT 24 |
| Peak memory | 200936 kb |
| Host | smart-37a7e5db-1679-46b1-9fcf-d28cf5bc8a05 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1932626875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.1932626875 |
| Directory | /workspace/14.uart_perf/latest |
| Test location | /workspace/coverage/default/14.uart_rx_oversample.3555584676 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 5796306405 ps |
| CPU time | 27.03 seconds |
| Started | Apr 21 04:28:35 PM PDT 24 |
| Finished | Apr 21 04:29:03 PM PDT 24 |
| Peak memory | 198944 kb |
| Host | smart-b0642c1c-19b1-473e-95ed-bf3b67a2294f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3555584676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.3555584676 |
| Directory | /workspace/14.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/14.uart_rx_parity_err.2152963891 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 33787771792 ps |
| CPU time | 26.35 seconds |
| Started | Apr 21 04:28:42 PM PDT 24 |
| Finished | Apr 21 04:29:08 PM PDT 24 |
| Peak memory | 200840 kb |
| Host | smart-59853a3a-337e-4eac-ae68-14118220b2eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2152963891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.2152963891 |
| Directory | /workspace/14.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/14.uart_rx_start_bit_filter.1070683072 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 3221548555 ps |
| CPU time | 2.17 seconds |
| Started | Apr 21 04:28:37 PM PDT 24 |
| Finished | Apr 21 04:28:40 PM PDT 24 |
| Peak memory | 196724 kb |
| Host | smart-f149b869-eae8-4ca1-862f-be226ff6f478 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1070683072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.1070683072 |
| Directory | /workspace/14.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/14.uart_smoke.1398861453 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 524141217 ps |
| CPU time | 1.28 seconds |
| Started | Apr 21 04:28:32 PM PDT 24 |
| Finished | Apr 21 04:28:34 PM PDT 24 |
| Peak memory | 200020 kb |
| Host | smart-4a3f4d27-acff-44ae-83bc-32ecef84d81e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1398861453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.1398861453 |
| Directory | /workspace/14.uart_smoke/latest |
| Test location | /workspace/coverage/default/14.uart_stress_all.3237171664 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 1020000357204 ps |
| CPU time | 212.38 seconds |
| Started | Apr 21 04:28:46 PM PDT 24 |
| Finished | Apr 21 04:32:19 PM PDT 24 |
| Peak memory | 200916 kb |
| Host | smart-10d02415-3e9f-4f29-ad9f-a680719824ed |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237171664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.3237171664 |
| Directory | /workspace/14.uart_stress_all/latest |
| Test location | /workspace/coverage/default/14.uart_stress_all_with_rand_reset.3717134852 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 27047352649 ps |
| CPU time | 280.67 seconds |
| Started | Apr 21 04:28:46 PM PDT 24 |
| Finished | Apr 21 04:33:27 PM PDT 24 |
| Peak memory | 217548 kb |
| Host | smart-72531505-9132-4389-887e-1cd56432d87c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717134852 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.3717134852 |
| Directory | /workspace/14.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/14.uart_tx_ovrd.3398338533 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 1426008409 ps |
| CPU time | 1.55 seconds |
| Started | Apr 21 04:28:45 PM PDT 24 |
| Finished | Apr 21 04:28:46 PM PDT 24 |
| Peak memory | 199404 kb |
| Host | smart-fa375325-8536-461e-b2d8-a952a36bfd8a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3398338533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.3398338533 |
| Directory | /workspace/14.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/14.uart_tx_rx.1495405352 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 45441695051 ps |
| CPU time | 52.6 seconds |
| Started | Apr 21 04:28:37 PM PDT 24 |
| Finished | Apr 21 04:29:30 PM PDT 24 |
| Peak memory | 200880 kb |
| Host | smart-32e6d545-6430-4400-8b6f-8b3cd32de505 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1495405352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.1495405352 |
| Directory | /workspace/14.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/140.uart_fifo_reset.3908831551 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 26445814312 ps |
| CPU time | 29.1 seconds |
| Started | Apr 21 04:37:22 PM PDT 24 |
| Finished | Apr 21 04:37:51 PM PDT 24 |
| Peak memory | 200792 kb |
| Host | smart-d3c1d180-970a-423e-843b-09fe8cebc863 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3908831551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.3908831551 |
| Directory | /workspace/140.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/141.uart_fifo_reset.296624669 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 38513703988 ps |
| CPU time | 67.1 seconds |
| Started | Apr 21 04:37:21 PM PDT 24 |
| Finished | Apr 21 04:38:28 PM PDT 24 |
| Peak memory | 200804 kb |
| Host | smart-f12304ad-4409-4ca4-a8a3-a3019b154a6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=296624669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.296624669 |
| Directory | /workspace/141.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/142.uart_fifo_reset.594268973 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 121997210624 ps |
| CPU time | 179.14 seconds |
| Started | Apr 21 04:37:21 PM PDT 24 |
| Finished | Apr 21 04:40:21 PM PDT 24 |
| Peak memory | 200960 kb |
| Host | smart-7ea07ddc-0f98-4364-84bc-4bdd51aebdcf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=594268973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.594268973 |
| Directory | /workspace/142.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/143.uart_fifo_reset.3457998238 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 42451397943 ps |
| CPU time | 69.08 seconds |
| Started | Apr 21 04:37:25 PM PDT 24 |
| Finished | Apr 21 04:38:35 PM PDT 24 |
| Peak memory | 200864 kb |
| Host | smart-d439ac97-09e2-4e2f-9ab5-1419bc837890 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3457998238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3457998238 |
| Directory | /workspace/143.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/144.uart_fifo_reset.2003779394 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 54847559536 ps |
| CPU time | 59.92 seconds |
| Started | Apr 21 04:37:24 PM PDT 24 |
| Finished | Apr 21 04:38:24 PM PDT 24 |
| Peak memory | 200928 kb |
| Host | smart-0e188282-51e4-4045-9328-10633db3c919 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2003779394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.2003779394 |
| Directory | /workspace/144.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/145.uart_fifo_reset.3590375821 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 61610850978 ps |
| CPU time | 126.87 seconds |
| Started | Apr 21 04:37:23 PM PDT 24 |
| Finished | Apr 21 04:39:30 PM PDT 24 |
| Peak memory | 200828 kb |
| Host | smart-0efbff96-947c-43ed-a560-10504f12fe06 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3590375821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.3590375821 |
| Directory | /workspace/145.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/146.uart_fifo_reset.3163870493 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 13977109285 ps |
| CPU time | 34.02 seconds |
| Started | Apr 21 04:37:26 PM PDT 24 |
| Finished | Apr 21 04:38:00 PM PDT 24 |
| Peak memory | 200904 kb |
| Host | smart-969fc74a-2465-4003-b942-6d7b3c8f2b9d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3163870493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.3163870493 |
| Directory | /workspace/146.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/147.uart_fifo_reset.2357711143 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 23305496866 ps |
| CPU time | 9.17 seconds |
| Started | Apr 21 04:37:27 PM PDT 24 |
| Finished | Apr 21 04:37:37 PM PDT 24 |
| Peak memory | 200864 kb |
| Host | smart-1a0a0e36-3361-4e39-bae0-6b4e4e3d187b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2357711143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.2357711143 |
| Directory | /workspace/147.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/148.uart_fifo_reset.1052745534 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 58124798570 ps |
| CPU time | 37.02 seconds |
| Started | Apr 21 04:37:27 PM PDT 24 |
| Finished | Apr 21 04:38:04 PM PDT 24 |
| Peak memory | 200888 kb |
| Host | smart-6032ca8c-58f8-4ebe-b0dd-427e93f44128 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1052745534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.1052745534 |
| Directory | /workspace/148.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/149.uart_fifo_reset.322452363 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 159405593214 ps |
| CPU time | 40.8 seconds |
| Started | Apr 21 04:37:29 PM PDT 24 |
| Finished | Apr 21 04:38:10 PM PDT 24 |
| Peak memory | 200732 kb |
| Host | smart-2c65c33d-2832-40bd-9744-86803d26872e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=322452363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.322452363 |
| Directory | /workspace/149.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/15.uart_alert_test.481727793 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 41560653 ps |
| CPU time | 0.58 seconds |
| Started | Apr 21 04:29:01 PM PDT 24 |
| Finished | Apr 21 04:29:02 PM PDT 24 |
| Peak memory | 196208 kb |
| Host | smart-1a59b0fb-fa2a-4e45-9758-e1c6d04a665d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481727793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.481727793 |
| Directory | /workspace/15.uart_alert_test/latest |
| Test location | /workspace/coverage/default/15.uart_fifo_full.1021180212 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 41943373437 ps |
| CPU time | 39.09 seconds |
| Started | Apr 21 04:28:52 PM PDT 24 |
| Finished | Apr 21 04:29:32 PM PDT 24 |
| Peak memory | 200796 kb |
| Host | smart-2a768524-d7b5-4404-8f55-e658452cbc8b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1021180212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.1021180212 |
| Directory | /workspace/15.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/15.uart_fifo_overflow.2113109919 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 24445285767 ps |
| CPU time | 22.75 seconds |
| Started | Apr 21 04:28:53 PM PDT 24 |
| Finished | Apr 21 04:29:16 PM PDT 24 |
| Peak memory | 200872 kb |
| Host | smart-db4042fc-88fc-4c7b-b654-83132e4896cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2113109919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.2113109919 |
| Directory | /workspace/15.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/15.uart_fifo_reset.3784601040 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 135071572841 ps |
| CPU time | 87.78 seconds |
| Started | Apr 21 04:28:53 PM PDT 24 |
| Finished | Apr 21 04:30:21 PM PDT 24 |
| Peak memory | 200868 kb |
| Host | smart-2971a4eb-baf5-4598-bae9-82299afd4c8a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3784601040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.3784601040 |
| Directory | /workspace/15.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/15.uart_intr.2260594843 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 29733595660 ps |
| CPU time | 17.93 seconds |
| Started | Apr 21 04:28:52 PM PDT 24 |
| Finished | Apr 21 04:29:11 PM PDT 24 |
| Peak memory | 200696 kb |
| Host | smart-8c05ba2e-26bf-4b76-8a7c-04982aaa6eaa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260594843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.2260594843 |
| Directory | /workspace/15.uart_intr/latest |
| Test location | /workspace/coverage/default/15.uart_long_xfer_wo_dly.3821455619 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 122623934780 ps |
| CPU time | 1102.92 seconds |
| Started | Apr 21 04:28:57 PM PDT 24 |
| Finished | Apr 21 04:47:20 PM PDT 24 |
| Peak memory | 200916 kb |
| Host | smart-b5ebd2a9-e352-4b7f-b15d-8920fcfd8c17 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3821455619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.3821455619 |
| Directory | /workspace/15.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/15.uart_loopback.3795929275 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 3047470483 ps |
| CPU time | 2.47 seconds |
| Started | Apr 21 04:28:56 PM PDT 24 |
| Finished | Apr 21 04:28:59 PM PDT 24 |
| Peak memory | 199580 kb |
| Host | smart-9666fd3c-705c-43d4-93c1-133144da171a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3795929275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.3795929275 |
| Directory | /workspace/15.uart_loopback/latest |
| Test location | /workspace/coverage/default/15.uart_noise_filter.3611177858 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 41886175007 ps |
| CPU time | 67.98 seconds |
| Started | Apr 21 04:28:56 PM PDT 24 |
| Finished | Apr 21 04:30:04 PM PDT 24 |
| Peak memory | 200956 kb |
| Host | smart-90ddcbb1-cd29-4954-8d7e-e7fbddcd3386 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3611177858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.3611177858 |
| Directory | /workspace/15.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/15.uart_perf.4246669077 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 6877026299 ps |
| CPU time | 72.9 seconds |
| Started | Apr 21 04:28:57 PM PDT 24 |
| Finished | Apr 21 04:30:10 PM PDT 24 |
| Peak memory | 200920 kb |
| Host | smart-1b32eac6-2e11-4267-a337-0debef953ac8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4246669077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.4246669077 |
| Directory | /workspace/15.uart_perf/latest |
| Test location | /workspace/coverage/default/15.uart_rx_oversample.210901739 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 1679383110 ps |
| CPU time | 4.7 seconds |
| Started | Apr 21 04:28:52 PM PDT 24 |
| Finished | Apr 21 04:28:57 PM PDT 24 |
| Peak memory | 198876 kb |
| Host | smart-b1676067-6ed8-4055-9679-5f3693dc711d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=210901739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.210901739 |
| Directory | /workspace/15.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/15.uart_rx_parity_err.4189500512 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 22012858243 ps |
| CPU time | 12.77 seconds |
| Started | Apr 21 04:28:56 PM PDT 24 |
| Finished | Apr 21 04:29:08 PM PDT 24 |
| Peak memory | 200772 kb |
| Host | smart-ef502dc5-341a-48e6-86a2-52b9c1389131 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4189500512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.4189500512 |
| Directory | /workspace/15.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/15.uart_rx_start_bit_filter.2266019357 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 571477356 ps |
| CPU time | 1.67 seconds |
| Started | Apr 21 04:28:55 PM PDT 24 |
| Finished | Apr 21 04:28:56 PM PDT 24 |
| Peak memory | 196264 kb |
| Host | smart-aac9233c-97c6-4a69-a31f-179e53796a3a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2266019357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.2266019357 |
| Directory | /workspace/15.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/15.uart_smoke.1658745130 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 899926297 ps |
| CPU time | 2.45 seconds |
| Started | Apr 21 04:28:49 PM PDT 24 |
| Finished | Apr 21 04:28:52 PM PDT 24 |
| Peak memory | 200764 kb |
| Host | smart-6e9dac34-c354-4cf6-ab01-71096d80d586 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1658745130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.1658745130 |
| Directory | /workspace/15.uart_smoke/latest |
| Test location | /workspace/coverage/default/15.uart_stress_all.2582784873 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 72882905286 ps |
| CPU time | 336.57 seconds |
| Started | Apr 21 04:29:01 PM PDT 24 |
| Finished | Apr 21 04:34:38 PM PDT 24 |
| Peak memory | 209412 kb |
| Host | smart-b7cf3310-54cb-402d-b9fa-65346f9c8e3b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582784873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.2582784873 |
| Directory | /workspace/15.uart_stress_all/latest |
| Test location | /workspace/coverage/default/15.uart_tx_ovrd.1598049887 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 1646394601 ps |
| CPU time | 3.03 seconds |
| Started | Apr 21 04:28:53 PM PDT 24 |
| Finished | Apr 21 04:28:57 PM PDT 24 |
| Peak memory | 200140 kb |
| Host | smart-34bbaa09-9677-42c0-9461-35ff13714475 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1598049887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.1598049887 |
| Directory | /workspace/15.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/15.uart_tx_rx.792581925 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 70938522734 ps |
| CPU time | 55.6 seconds |
| Started | Apr 21 04:28:51 PM PDT 24 |
| Finished | Apr 21 04:29:47 PM PDT 24 |
| Peak memory | 200872 kb |
| Host | smart-4f5b81ba-aa57-44fc-9cf4-b7c286d1b1e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=792581925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.792581925 |
| Directory | /workspace/15.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/150.uart_fifo_reset.1316281987 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 161188412572 ps |
| CPU time | 23.03 seconds |
| Started | Apr 21 04:37:29 PM PDT 24 |
| Finished | Apr 21 04:37:52 PM PDT 24 |
| Peak memory | 200860 kb |
| Host | smart-594720f8-76c9-4001-9b00-fc0d86b9d7e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1316281987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.1316281987 |
| Directory | /workspace/150.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/151.uart_fifo_reset.3702457785 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 27386108732 ps |
| CPU time | 40.43 seconds |
| Started | Apr 21 04:37:30 PM PDT 24 |
| Finished | Apr 21 04:38:11 PM PDT 24 |
| Peak memory | 200828 kb |
| Host | smart-18549319-9a87-4c9c-80da-6288639e3c9f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3702457785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.3702457785 |
| Directory | /workspace/151.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/152.uart_fifo_reset.4087311758 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 174739679191 ps |
| CPU time | 91.63 seconds |
| Started | Apr 21 04:37:31 PM PDT 24 |
| Finished | Apr 21 04:39:02 PM PDT 24 |
| Peak memory | 200860 kb |
| Host | smart-c1f90d6d-c288-4c41-8e59-22e49151dbcc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4087311758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.4087311758 |
| Directory | /workspace/152.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/153.uart_fifo_reset.2041190779 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 309246039107 ps |
| CPU time | 70.81 seconds |
| Started | Apr 21 04:37:31 PM PDT 24 |
| Finished | Apr 21 04:38:42 PM PDT 24 |
| Peak memory | 200916 kb |
| Host | smart-2ac54039-0cf0-45a1-a769-51ab3d79a03b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2041190779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.2041190779 |
| Directory | /workspace/153.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/155.uart_fifo_reset.3260347363 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 56541865789 ps |
| CPU time | 135.23 seconds |
| Started | Apr 21 04:37:34 PM PDT 24 |
| Finished | Apr 21 04:39:50 PM PDT 24 |
| Peak memory | 200872 kb |
| Host | smart-43342346-5650-4cb8-aa5f-eb1ea2e54f7d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3260347363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.3260347363 |
| Directory | /workspace/155.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/156.uart_fifo_reset.2301399842 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 175692034903 ps |
| CPU time | 52.88 seconds |
| Started | Apr 21 04:37:36 PM PDT 24 |
| Finished | Apr 21 04:38:29 PM PDT 24 |
| Peak memory | 200904 kb |
| Host | smart-83015746-6ac5-4a3b-afd9-153ae430d5fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2301399842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.2301399842 |
| Directory | /workspace/156.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/157.uart_fifo_reset.1694138261 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 63932789632 ps |
| CPU time | 32.39 seconds |
| Started | Apr 21 04:37:35 PM PDT 24 |
| Finished | Apr 21 04:38:08 PM PDT 24 |
| Peak memory | 200832 kb |
| Host | smart-3953f6ac-aef5-430e-9681-afb586444946 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1694138261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.1694138261 |
| Directory | /workspace/157.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/158.uart_fifo_reset.2423858033 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 27718240397 ps |
| CPU time | 23.91 seconds |
| Started | Apr 21 04:37:36 PM PDT 24 |
| Finished | Apr 21 04:38:00 PM PDT 24 |
| Peak memory | 200924 kb |
| Host | smart-72ca2d37-e062-42b4-8c44-2b65892db9a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2423858033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.2423858033 |
| Directory | /workspace/158.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/16.uart_alert_test.3007632804 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 37124738 ps |
| CPU time | 0.59 seconds |
| Started | Apr 21 04:29:15 PM PDT 24 |
| Finished | Apr 21 04:29:15 PM PDT 24 |
| Peak memory | 196232 kb |
| Host | smart-4317e5af-5276-4185-8f48-393cc87ad7d5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007632804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.3007632804 |
| Directory | /workspace/16.uart_alert_test/latest |
| Test location | /workspace/coverage/default/16.uart_fifo_full.4146384339 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 65835793743 ps |
| CPU time | 54.14 seconds |
| Started | Apr 21 04:29:02 PM PDT 24 |
| Finished | Apr 21 04:29:57 PM PDT 24 |
| Peak memory | 200892 kb |
| Host | smart-12d4bfdd-0352-4c04-85c9-29c4f54b6836 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4146384339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.4146384339 |
| Directory | /workspace/16.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/16.uart_fifo_overflow.3949664470 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 70572231247 ps |
| CPU time | 31.06 seconds |
| Started | Apr 21 04:29:04 PM PDT 24 |
| Finished | Apr 21 04:29:35 PM PDT 24 |
| Peak memory | 200668 kb |
| Host | smart-04c07738-9091-404e-b06d-453014df1414 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3949664470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.3949664470 |
| Directory | /workspace/16.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/16.uart_fifo_reset.1321113448 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 107703703285 ps |
| CPU time | 29.72 seconds |
| Started | Apr 21 04:29:02 PM PDT 24 |
| Finished | Apr 21 04:29:32 PM PDT 24 |
| Peak memory | 200832 kb |
| Host | smart-d83c698f-0256-4b3f-896d-0884b7db6e7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1321113448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.1321113448 |
| Directory | /workspace/16.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/16.uart_intr.3962511197 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 417571790186 ps |
| CPU time | 313.7 seconds |
| Started | Apr 21 04:29:05 PM PDT 24 |
| Finished | Apr 21 04:34:19 PM PDT 24 |
| Peak memory | 200820 kb |
| Host | smart-af142337-4fd5-4d6f-87e8-3108f09918d1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962511197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.3962511197 |
| Directory | /workspace/16.uart_intr/latest |
| Test location | /workspace/coverage/default/16.uart_long_xfer_wo_dly.2667239802 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 46790029758 ps |
| CPU time | 470.5 seconds |
| Started | Apr 21 04:29:11 PM PDT 24 |
| Finished | Apr 21 04:37:01 PM PDT 24 |
| Peak memory | 200896 kb |
| Host | smart-3d2036d4-651f-40f9-a71b-b27a902530a1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2667239802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.2667239802 |
| Directory | /workspace/16.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/16.uart_loopback.3221778999 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 7197983263 ps |
| CPU time | 15.21 seconds |
| Started | Apr 21 04:29:08 PM PDT 24 |
| Finished | Apr 21 04:29:24 PM PDT 24 |
| Peak memory | 199504 kb |
| Host | smart-9606c53e-7151-40ff-8ffb-2d5859328700 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3221778999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.3221778999 |
| Directory | /workspace/16.uart_loopback/latest |
| Test location | /workspace/coverage/default/16.uart_noise_filter.3645936626 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 101132758846 ps |
| CPU time | 90.37 seconds |
| Started | Apr 21 04:29:05 PM PDT 24 |
| Finished | Apr 21 04:30:35 PM PDT 24 |
| Peak memory | 201008 kb |
| Host | smart-59355e3c-dfd2-440c-ae90-31188ad89320 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3645936626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.3645936626 |
| Directory | /workspace/16.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/16.uart_rx_oversample.1523341804 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 1829926210 ps |
| CPU time | 2.69 seconds |
| Started | Apr 21 04:29:06 PM PDT 24 |
| Finished | Apr 21 04:29:09 PM PDT 24 |
| Peak memory | 198676 kb |
| Host | smart-6a07877a-0588-4f3f-8f44-19601372c3a4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1523341804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.1523341804 |
| Directory | /workspace/16.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/16.uart_rx_parity_err.2401757024 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 6783869581 ps |
| CPU time | 12.66 seconds |
| Started | Apr 21 04:29:08 PM PDT 24 |
| Finished | Apr 21 04:29:21 PM PDT 24 |
| Peak memory | 200196 kb |
| Host | smart-53e442d5-be26-486b-9ff3-a8c19a546526 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2401757024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.2401757024 |
| Directory | /workspace/16.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/16.uart_rx_start_bit_filter.718192738 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 37431927807 ps |
| CPU time | 11.84 seconds |
| Started | Apr 21 04:29:09 PM PDT 24 |
| Finished | Apr 21 04:29:21 PM PDT 24 |
| Peak memory | 196736 kb |
| Host | smart-cc9b478e-81a6-4b1f-bed7-d65d1d037353 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=718192738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.718192738 |
| Directory | /workspace/16.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/16.uart_smoke.2285083131 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 5903800711 ps |
| CPU time | 40.28 seconds |
| Started | Apr 21 04:29:01 PM PDT 24 |
| Finished | Apr 21 04:29:42 PM PDT 24 |
| Peak memory | 200332 kb |
| Host | smart-032fca47-3025-493c-8ea2-66aaf1a6ca2d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2285083131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.2285083131 |
| Directory | /workspace/16.uart_smoke/latest |
| Test location | /workspace/coverage/default/16.uart_stress_all.3910957227 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 369024956382 ps |
| CPU time | 320.86 seconds |
| Started | Apr 21 04:29:11 PM PDT 24 |
| Finished | Apr 21 04:34:32 PM PDT 24 |
| Peak memory | 200840 kb |
| Host | smart-6b9c75bb-4ff1-4b92-aed6-12172d2e4b4b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910957227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.3910957227 |
| Directory | /workspace/16.uart_stress_all/latest |
| Test location | /workspace/coverage/default/16.uart_tx_ovrd.2299763732 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 7219183393 ps |
| CPU time | 9.58 seconds |
| Started | Apr 21 04:29:09 PM PDT 24 |
| Finished | Apr 21 04:29:18 PM PDT 24 |
| Peak memory | 200840 kb |
| Host | smart-abf356d8-30c3-4760-8727-1784720784f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2299763732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.2299763732 |
| Directory | /workspace/16.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/16.uart_tx_rx.1025183255 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 15313526479 ps |
| CPU time | 6.35 seconds |
| Started | Apr 21 04:29:02 PM PDT 24 |
| Finished | Apr 21 04:29:08 PM PDT 24 |
| Peak memory | 199592 kb |
| Host | smart-66903416-0095-4001-ad10-50a383acc786 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1025183255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.1025183255 |
| Directory | /workspace/16.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/161.uart_fifo_reset.1808312525 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 265969562450 ps |
| CPU time | 81.46 seconds |
| Started | Apr 21 04:37:44 PM PDT 24 |
| Finished | Apr 21 04:39:06 PM PDT 24 |
| Peak memory | 200964 kb |
| Host | smart-3588e569-e6fd-4e88-a176-d0f4e9432819 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1808312525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.1808312525 |
| Directory | /workspace/161.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/162.uart_fifo_reset.3546131223 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 20109853375 ps |
| CPU time | 31.38 seconds |
| Started | Apr 21 04:37:42 PM PDT 24 |
| Finished | Apr 21 04:38:14 PM PDT 24 |
| Peak memory | 200808 kb |
| Host | smart-3d33af32-b8fe-46ad-b34b-25c05b2cbaa9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3546131223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.3546131223 |
| Directory | /workspace/162.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/163.uart_fifo_reset.3600574842 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 110464338386 ps |
| CPU time | 185.72 seconds |
| Started | Apr 21 04:37:44 PM PDT 24 |
| Finished | Apr 21 04:40:50 PM PDT 24 |
| Peak memory | 200916 kb |
| Host | smart-166871a0-0583-4cab-adb9-4450537e9ce7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3600574842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.3600574842 |
| Directory | /workspace/163.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/164.uart_fifo_reset.2585137940 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 41575184141 ps |
| CPU time | 15.35 seconds |
| Started | Apr 21 04:37:44 PM PDT 24 |
| Finished | Apr 21 04:37:59 PM PDT 24 |
| Peak memory | 200824 kb |
| Host | smart-12c82025-8f78-42c8-af22-3244b59f5f89 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2585137940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.2585137940 |
| Directory | /workspace/164.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/165.uart_fifo_reset.3997031603 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 9315653844 ps |
| CPU time | 17.28 seconds |
| Started | Apr 21 04:37:45 PM PDT 24 |
| Finished | Apr 21 04:38:02 PM PDT 24 |
| Peak memory | 200732 kb |
| Host | smart-8a435926-e3ba-438b-a637-9989a26ee698 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3997031603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3997031603 |
| Directory | /workspace/165.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/166.uart_fifo_reset.1409998342 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 90875190200 ps |
| CPU time | 145.48 seconds |
| Started | Apr 21 04:37:46 PM PDT 24 |
| Finished | Apr 21 04:40:11 PM PDT 24 |
| Peak memory | 200836 kb |
| Host | smart-2e308470-7b2b-492b-aedf-8702cfa90385 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1409998342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1409998342 |
| Directory | /workspace/166.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/167.uart_fifo_reset.1977091951 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 27985764780 ps |
| CPU time | 22.84 seconds |
| Started | Apr 21 04:37:46 PM PDT 24 |
| Finished | Apr 21 04:38:09 PM PDT 24 |
| Peak memory | 200916 kb |
| Host | smart-aecf572b-28a8-4152-8051-529fd44738f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1977091951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.1977091951 |
| Directory | /workspace/167.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/168.uart_fifo_reset.1053707795 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 13292089509 ps |
| CPU time | 23.32 seconds |
| Started | Apr 21 04:37:48 PM PDT 24 |
| Finished | Apr 21 04:38:11 PM PDT 24 |
| Peak memory | 200936 kb |
| Host | smart-7d12fe12-1af1-4f1a-9efb-3fcc6efe18f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1053707795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1053707795 |
| Directory | /workspace/168.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/169.uart_fifo_reset.1439811592 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 14403617512 ps |
| CPU time | 26.03 seconds |
| Started | Apr 21 04:37:51 PM PDT 24 |
| Finished | Apr 21 04:38:18 PM PDT 24 |
| Peak memory | 200944 kb |
| Host | smart-7c487a41-a4fe-4ce0-8b02-46abf99a756f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1439811592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.1439811592 |
| Directory | /workspace/169.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/17.uart_alert_test.3629669297 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 20037977 ps |
| CPU time | 0.55 seconds |
| Started | Apr 21 04:29:24 PM PDT 24 |
| Finished | Apr 21 04:29:25 PM PDT 24 |
| Peak memory | 195660 kb |
| Host | smart-027e1a13-eb4b-4624-8668-83e3a73a2c6a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629669297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.3629669297 |
| Directory | /workspace/17.uart_alert_test/latest |
| Test location | /workspace/coverage/default/17.uart_fifo_full.3046700200 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 40950902169 ps |
| CPU time | 34.05 seconds |
| Started | Apr 21 04:29:16 PM PDT 24 |
| Finished | Apr 21 04:29:50 PM PDT 24 |
| Peak memory | 200860 kb |
| Host | smart-28e5ee2a-9061-47d7-9f20-6f4bba9bff82 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3046700200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.3046700200 |
| Directory | /workspace/17.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/17.uart_fifo_overflow.648347344 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 47630887688 ps |
| CPU time | 49.82 seconds |
| Started | Apr 21 04:29:17 PM PDT 24 |
| Finished | Apr 21 04:30:07 PM PDT 24 |
| Peak memory | 200864 kb |
| Host | smart-75acd7b0-d32a-4659-9e9e-9ac309d55cec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=648347344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.648347344 |
| Directory | /workspace/17.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/17.uart_fifo_reset.804447613 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 111859206613 ps |
| CPU time | 35.53 seconds |
| Started | Apr 21 04:29:19 PM PDT 24 |
| Finished | Apr 21 04:29:55 PM PDT 24 |
| Peak memory | 200608 kb |
| Host | smart-7af13fc5-454a-492d-b062-e293c5235da8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=804447613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.804447613 |
| Directory | /workspace/17.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/17.uart_intr.1325625901 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 48969387558 ps |
| CPU time | 52.66 seconds |
| Started | Apr 21 04:29:19 PM PDT 24 |
| Finished | Apr 21 04:30:12 PM PDT 24 |
| Peak memory | 200824 kb |
| Host | smart-0f2cd82d-4255-4e4f-80dc-081bd68fc771 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325625901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.1325625901 |
| Directory | /workspace/17.uart_intr/latest |
| Test location | /workspace/coverage/default/17.uart_long_xfer_wo_dly.1328319099 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 108114746656 ps |
| CPU time | 707.69 seconds |
| Started | Apr 21 04:29:26 PM PDT 24 |
| Finished | Apr 21 04:41:14 PM PDT 24 |
| Peak memory | 200884 kb |
| Host | smart-8b2a01e4-25eb-4d90-8daf-e2a56cd80575 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1328319099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.1328319099 |
| Directory | /workspace/17.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/17.uart_loopback.895228681 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 7446513426 ps |
| CPU time | 8.34 seconds |
| Started | Apr 21 04:29:25 PM PDT 24 |
| Finished | Apr 21 04:29:33 PM PDT 24 |
| Peak memory | 200340 kb |
| Host | smart-edfee199-4bef-4ad5-860f-bf44becb3337 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=895228681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.895228681 |
| Directory | /workspace/17.uart_loopback/latest |
| Test location | /workspace/coverage/default/17.uart_noise_filter.1427228884 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 73017008867 ps |
| CPU time | 124.63 seconds |
| Started | Apr 21 04:29:21 PM PDT 24 |
| Finished | Apr 21 04:31:25 PM PDT 24 |
| Peak memory | 200736 kb |
| Host | smart-baf463fc-341c-4080-9ed2-1d98548e4799 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1427228884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.1427228884 |
| Directory | /workspace/17.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/17.uart_perf.3757585350 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 14686775200 ps |
| CPU time | 214.41 seconds |
| Started | Apr 21 04:29:24 PM PDT 24 |
| Finished | Apr 21 04:32:58 PM PDT 24 |
| Peak memory | 200888 kb |
| Host | smart-859f55fb-27cd-446e-b5ee-0d8199d49593 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3757585350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.3757585350 |
| Directory | /workspace/17.uart_perf/latest |
| Test location | /workspace/coverage/default/17.uart_rx_oversample.2604814236 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 6460732170 ps |
| CPU time | 11.44 seconds |
| Started | Apr 21 04:29:17 PM PDT 24 |
| Finished | Apr 21 04:29:28 PM PDT 24 |
| Peak memory | 198992 kb |
| Host | smart-bfd8dc60-7a6f-45d6-acae-7c947330930f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2604814236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.2604814236 |
| Directory | /workspace/17.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/17.uart_rx_parity_err.1794581792 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 115172361083 ps |
| CPU time | 162.02 seconds |
| Started | Apr 21 04:29:21 PM PDT 24 |
| Finished | Apr 21 04:32:03 PM PDT 24 |
| Peak memory | 200796 kb |
| Host | smart-d0541945-8817-4ac0-8541-94864225378e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1794581792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.1794581792 |
| Directory | /workspace/17.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/17.uart_rx_start_bit_filter.316468122 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 4514484374 ps |
| CPU time | 3.89 seconds |
| Started | Apr 21 04:29:20 PM PDT 24 |
| Finished | Apr 21 04:29:24 PM PDT 24 |
| Peak memory | 196896 kb |
| Host | smart-ef1e5948-f68f-4b67-8bbe-a94c2707014f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=316468122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.316468122 |
| Directory | /workspace/17.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/17.uart_smoke.1629545653 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 294608146 ps |
| CPU time | 1.51 seconds |
| Started | Apr 21 04:29:15 PM PDT 24 |
| Finished | Apr 21 04:29:17 PM PDT 24 |
| Peak memory | 199060 kb |
| Host | smart-84fd5fb9-4e5f-4b57-84bd-63f0085379e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1629545653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.1629545653 |
| Directory | /workspace/17.uart_smoke/latest |
| Test location | /workspace/coverage/default/17.uart_stress_all.2089603647 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 246200276122 ps |
| CPU time | 58.98 seconds |
| Started | Apr 21 04:29:26 PM PDT 24 |
| Finished | Apr 21 04:30:25 PM PDT 24 |
| Peak memory | 200920 kb |
| Host | smart-aab60ed0-3f9c-41de-82e1-52af9cd2a5bc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089603647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.2089603647 |
| Directory | /workspace/17.uart_stress_all/latest |
| Test location | /workspace/coverage/default/17.uart_stress_all_with_rand_reset.2684518578 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 55258406612 ps |
| CPU time | 1002.85 seconds |
| Started | Apr 21 04:29:26 PM PDT 24 |
| Finished | Apr 21 04:46:09 PM PDT 24 |
| Peak memory | 217244 kb |
| Host | smart-27b04367-f7de-4e92-96d2-7036c28641dc |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684518578 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.2684518578 |
| Directory | /workspace/17.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/17.uart_tx_ovrd.1937414617 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 7402250059 ps |
| CPU time | 8.67 seconds |
| Started | Apr 21 04:29:21 PM PDT 24 |
| Finished | Apr 21 04:29:30 PM PDT 24 |
| Peak memory | 200364 kb |
| Host | smart-631e970c-9d3f-4dcb-99ea-ee9c599545cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1937414617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1937414617 |
| Directory | /workspace/17.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/17.uart_tx_rx.1651805472 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 95064662780 ps |
| CPU time | 168.87 seconds |
| Started | Apr 21 04:29:15 PM PDT 24 |
| Finished | Apr 21 04:32:04 PM PDT 24 |
| Peak memory | 200820 kb |
| Host | smart-5e72c9e3-5f2a-473f-a982-ee042c1437e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1651805472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.1651805472 |
| Directory | /workspace/17.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/170.uart_fifo_reset.3073165482 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 15145217747 ps |
| CPU time | 11.4 seconds |
| Started | Apr 21 04:37:51 PM PDT 24 |
| Finished | Apr 21 04:38:02 PM PDT 24 |
| Peak memory | 200792 kb |
| Host | smart-bb4a1e3e-9a66-492f-b1b5-346aacfea190 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3073165482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.3073165482 |
| Directory | /workspace/170.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/171.uart_fifo_reset.1345564711 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 49147585095 ps |
| CPU time | 22.82 seconds |
| Started | Apr 21 04:37:52 PM PDT 24 |
| Finished | Apr 21 04:38:15 PM PDT 24 |
| Peak memory | 200800 kb |
| Host | smart-6e8b06fa-8bb6-4058-8c4c-33a7dd882151 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1345564711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.1345564711 |
| Directory | /workspace/171.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/172.uart_fifo_reset.1962622780 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 61714021998 ps |
| CPU time | 24.77 seconds |
| Started | Apr 21 04:37:56 PM PDT 24 |
| Finished | Apr 21 04:38:21 PM PDT 24 |
| Peak memory | 200928 kb |
| Host | smart-d1a41700-2306-4887-8add-7e93111b4779 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1962622780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.1962622780 |
| Directory | /workspace/172.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/173.uart_fifo_reset.3644702143 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 254087866934 ps |
| CPU time | 107.01 seconds |
| Started | Apr 21 04:37:54 PM PDT 24 |
| Finished | Apr 21 04:39:42 PM PDT 24 |
| Peak memory | 200888 kb |
| Host | smart-f852f63f-af19-4ee9-bf74-65cf80b1ef11 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3644702143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.3644702143 |
| Directory | /workspace/173.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/174.uart_fifo_reset.3791826335 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 142087150215 ps |
| CPU time | 34.99 seconds |
| Started | Apr 21 04:37:55 PM PDT 24 |
| Finished | Apr 21 04:38:30 PM PDT 24 |
| Peak memory | 200920 kb |
| Host | smart-ee8439a2-5fc1-4288-bc4a-7b8e68bddb3c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3791826335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.3791826335 |
| Directory | /workspace/174.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/176.uart_fifo_reset.1448737741 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 101071170296 ps |
| CPU time | 46.14 seconds |
| Started | Apr 21 04:37:56 PM PDT 24 |
| Finished | Apr 21 04:38:43 PM PDT 24 |
| Peak memory | 200656 kb |
| Host | smart-45b1beea-0455-4045-969a-bbf158230b8d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1448737741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.1448737741 |
| Directory | /workspace/176.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/177.uart_fifo_reset.725544951 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 22483655044 ps |
| CPU time | 29.16 seconds |
| Started | Apr 21 04:38:04 PM PDT 24 |
| Finished | Apr 21 04:38:34 PM PDT 24 |
| Peak memory | 200960 kb |
| Host | smart-7bf56918-aa44-4e9b-95cf-846acaa173f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=725544951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.725544951 |
| Directory | /workspace/177.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/178.uart_fifo_reset.1286052836 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 20168795579 ps |
| CPU time | 38.06 seconds |
| Started | Apr 21 04:38:06 PM PDT 24 |
| Finished | Apr 21 04:38:44 PM PDT 24 |
| Peak memory | 200928 kb |
| Host | smart-f8a7770b-297f-4774-80da-c75d21160a87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1286052836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.1286052836 |
| Directory | /workspace/178.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/18.uart_alert_test.1625102275 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 69231126 ps |
| CPU time | 0.54 seconds |
| Started | Apr 21 04:29:36 PM PDT 24 |
| Finished | Apr 21 04:29:37 PM PDT 24 |
| Peak memory | 195172 kb |
| Host | smart-d84cbf2b-bede-42cb-a9dc-cdd8679f5381 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625102275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.1625102275 |
| Directory | /workspace/18.uart_alert_test/latest |
| Test location | /workspace/coverage/default/18.uart_fifo_full.3172115133 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 109663992529 ps |
| CPU time | 173.38 seconds |
| Started | Apr 21 04:29:30 PM PDT 24 |
| Finished | Apr 21 04:32:24 PM PDT 24 |
| Peak memory | 200928 kb |
| Host | smart-e25dfaad-4259-4b29-a487-4bf0d86f95b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3172115133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3172115133 |
| Directory | /workspace/18.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/18.uart_fifo_overflow.1545999040 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 25804874816 ps |
| CPU time | 23.37 seconds |
| Started | Apr 21 04:29:27 PM PDT 24 |
| Finished | Apr 21 04:29:51 PM PDT 24 |
| Peak memory | 200808 kb |
| Host | smart-e5671a6d-f782-427f-8305-e49a10a1c4aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1545999040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.1545999040 |
| Directory | /workspace/18.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/18.uart_fifo_reset.1605877989 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 103151710375 ps |
| CPU time | 71.99 seconds |
| Started | Apr 21 04:29:30 PM PDT 24 |
| Finished | Apr 21 04:30:42 PM PDT 24 |
| Peak memory | 200892 kb |
| Host | smart-66ef3687-5305-4476-9f0d-ef0fd6ea42d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1605877989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.1605877989 |
| Directory | /workspace/18.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/18.uart_intr.89956429 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 6222352311 ps |
| CPU time | 3.07 seconds |
| Started | Apr 21 04:29:34 PM PDT 24 |
| Finished | Apr 21 04:29:37 PM PDT 24 |
| Peak memory | 197776 kb |
| Host | smart-09f3d079-35bf-4e9b-8106-00c7bb767647 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89956429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.89956429 |
| Directory | /workspace/18.uart_intr/latest |
| Test location | /workspace/coverage/default/18.uart_long_xfer_wo_dly.941240337 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 41168184821 ps |
| CPU time | 218.91 seconds |
| Started | Apr 21 04:29:33 PM PDT 24 |
| Finished | Apr 21 04:33:12 PM PDT 24 |
| Peak memory | 200940 kb |
| Host | smart-cd11651a-66d7-4800-bbbe-e8e4e0e8e2ea |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=941240337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.941240337 |
| Directory | /workspace/18.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/18.uart_loopback.2475499263 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 12210349696 ps |
| CPU time | 13.98 seconds |
| Started | Apr 21 04:29:32 PM PDT 24 |
| Finished | Apr 21 04:29:46 PM PDT 24 |
| Peak memory | 200780 kb |
| Host | smart-480c5ad8-c504-40f2-b12b-3025a64f7e50 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2475499263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2475499263 |
| Directory | /workspace/18.uart_loopback/latest |
| Test location | /workspace/coverage/default/18.uart_noise_filter.3139870113 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 36899553489 ps |
| CPU time | 64.18 seconds |
| Started | Apr 21 04:29:31 PM PDT 24 |
| Finished | Apr 21 04:30:36 PM PDT 24 |
| Peak memory | 209176 kb |
| Host | smart-0d7c285a-3554-410c-bbb4-1ebeb8a85c78 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3139870113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.3139870113 |
| Directory | /workspace/18.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/18.uart_perf.251502276 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 19054020769 ps |
| CPU time | 1060.98 seconds |
| Started | Apr 21 04:29:33 PM PDT 24 |
| Finished | Apr 21 04:47:14 PM PDT 24 |
| Peak memory | 200908 kb |
| Host | smart-5c0e3816-b82a-4bdd-9ed9-036873920e95 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=251502276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.251502276 |
| Directory | /workspace/18.uart_perf/latest |
| Test location | /workspace/coverage/default/18.uart_rx_oversample.3653576470 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 4163112695 ps |
| CPU time | 7.99 seconds |
| Started | Apr 21 04:29:28 PM PDT 24 |
| Finished | Apr 21 04:29:36 PM PDT 24 |
| Peak memory | 199240 kb |
| Host | smart-b214d589-28a7-4bed-86d3-e1b5e94db937 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3653576470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.3653576470 |
| Directory | /workspace/18.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/18.uart_rx_parity_err.3615823772 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 20713691150 ps |
| CPU time | 19.39 seconds |
| Started | Apr 21 04:29:31 PM PDT 24 |
| Finished | Apr 21 04:29:50 PM PDT 24 |
| Peak memory | 200960 kb |
| Host | smart-00138eae-ac28-414a-ac60-bb58b194fb93 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3615823772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.3615823772 |
| Directory | /workspace/18.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/18.uart_rx_start_bit_filter.602510676 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 3553010499 ps |
| CPU time | 6.1 seconds |
| Started | Apr 21 04:29:31 PM PDT 24 |
| Finished | Apr 21 04:29:37 PM PDT 24 |
| Peak memory | 196904 kb |
| Host | smart-04db3ef0-3d02-4abd-ab9d-cf31d7118ad4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=602510676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.602510676 |
| Directory | /workspace/18.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/18.uart_smoke.2551412197 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 807684796 ps |
| CPU time | 1.14 seconds |
| Started | Apr 21 04:29:27 PM PDT 24 |
| Finished | Apr 21 04:29:28 PM PDT 24 |
| Peak memory | 199520 kb |
| Host | smart-a1f95544-2503-4b91-a032-0c22b612cc45 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2551412197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2551412197 |
| Directory | /workspace/18.uart_smoke/latest |
| Test location | /workspace/coverage/default/18.uart_stress_all.2470489771 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 267247671344 ps |
| CPU time | 122.81 seconds |
| Started | Apr 21 04:29:37 PM PDT 24 |
| Finished | Apr 21 04:31:40 PM PDT 24 |
| Peak memory | 200912 kb |
| Host | smart-0b042843-b217-4af7-9b1c-065360c3953f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470489771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.2470489771 |
| Directory | /workspace/18.uart_stress_all/latest |
| Test location | /workspace/coverage/default/18.uart_stress_all_with_rand_reset.3057661428 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 47966099823 ps |
| CPU time | 112.78 seconds |
| Started | Apr 21 04:29:36 PM PDT 24 |
| Finished | Apr 21 04:31:29 PM PDT 24 |
| Peak memory | 217516 kb |
| Host | smart-82f45471-7615-45b6-a864-a57dfce2bb25 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057661428 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.3057661428 |
| Directory | /workspace/18.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/18.uart_tx_ovrd.3864950741 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 1212248412 ps |
| CPU time | 2.27 seconds |
| Started | Apr 21 04:29:33 PM PDT 24 |
| Finished | Apr 21 04:29:36 PM PDT 24 |
| Peak memory | 199184 kb |
| Host | smart-81048e14-b163-472d-af1c-3285a02fa918 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3864950741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.3864950741 |
| Directory | /workspace/18.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/18.uart_tx_rx.3759409707 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 27902768537 ps |
| CPU time | 12.28 seconds |
| Started | Apr 21 04:29:28 PM PDT 24 |
| Finished | Apr 21 04:29:40 PM PDT 24 |
| Peak memory | 200932 kb |
| Host | smart-9737ebf6-2638-4758-8106-4de8a1f9b8d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3759409707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.3759409707 |
| Directory | /workspace/18.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/180.uart_fifo_reset.3970139091 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 33794856948 ps |
| CPU time | 15.15 seconds |
| Started | Apr 21 04:38:06 PM PDT 24 |
| Finished | Apr 21 04:38:22 PM PDT 24 |
| Peak memory | 200456 kb |
| Host | smart-7163b56c-bdc1-4886-92de-ca23b220a196 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3970139091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.3970139091 |
| Directory | /workspace/180.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/181.uart_fifo_reset.779022715 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 32364832100 ps |
| CPU time | 13.47 seconds |
| Started | Apr 21 04:38:05 PM PDT 24 |
| Finished | Apr 21 04:38:19 PM PDT 24 |
| Peak memory | 200872 kb |
| Host | smart-7d20f702-45dc-405e-983d-ad32a0dd6e3a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=779022715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.779022715 |
| Directory | /workspace/181.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/182.uart_fifo_reset.1563127846 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 40753915224 ps |
| CPU time | 75.55 seconds |
| Started | Apr 21 04:38:05 PM PDT 24 |
| Finished | Apr 21 04:39:20 PM PDT 24 |
| Peak memory | 200884 kb |
| Host | smart-5e894ce4-85b7-406c-b4d9-170df14c9f43 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1563127846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1563127846 |
| Directory | /workspace/182.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/183.uart_fifo_reset.1647131926 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 85536776322 ps |
| CPU time | 239.69 seconds |
| Started | Apr 21 04:38:07 PM PDT 24 |
| Finished | Apr 21 04:42:07 PM PDT 24 |
| Peak memory | 200832 kb |
| Host | smart-c36379e2-abb1-4a99-9006-e27404219cc6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1647131926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.1647131926 |
| Directory | /workspace/183.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/184.uart_fifo_reset.2777943061 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 7547239359 ps |
| CPU time | 20.93 seconds |
| Started | Apr 21 04:38:06 PM PDT 24 |
| Finished | Apr 21 04:38:28 PM PDT 24 |
| Peak memory | 200868 kb |
| Host | smart-1bc4de49-a402-478e-b763-7274e4156bf5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2777943061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.2777943061 |
| Directory | /workspace/184.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/185.uart_fifo_reset.610653572 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 47147347237 ps |
| CPU time | 23.99 seconds |
| Started | Apr 21 04:38:09 PM PDT 24 |
| Finished | Apr 21 04:38:33 PM PDT 24 |
| Peak memory | 200860 kb |
| Host | smart-a397ffe8-bd1e-4d19-a4ff-3470305b579b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=610653572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.610653572 |
| Directory | /workspace/185.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/186.uart_fifo_reset.1611723721 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 146109553118 ps |
| CPU time | 70.18 seconds |
| Started | Apr 21 04:38:10 PM PDT 24 |
| Finished | Apr 21 04:39:20 PM PDT 24 |
| Peak memory | 200880 kb |
| Host | smart-fa1d5c65-87f2-4611-9faf-9c731c1ee07b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1611723721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.1611723721 |
| Directory | /workspace/186.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/187.uart_fifo_reset.2967110629 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 123590678208 ps |
| CPU time | 177.46 seconds |
| Started | Apr 21 04:38:08 PM PDT 24 |
| Finished | Apr 21 04:41:06 PM PDT 24 |
| Peak memory | 200916 kb |
| Host | smart-7574b2fe-3681-42af-9fdc-b01f4a37c9af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2967110629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.2967110629 |
| Directory | /workspace/187.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/188.uart_fifo_reset.3036298007 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 122062706686 ps |
| CPU time | 23.21 seconds |
| Started | Apr 21 04:38:11 PM PDT 24 |
| Finished | Apr 21 04:38:35 PM PDT 24 |
| Peak memory | 200936 kb |
| Host | smart-98638297-4a53-4162-ae31-79b27801e062 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3036298007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3036298007 |
| Directory | /workspace/188.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/19.uart_alert_test.322647828 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 13235775 ps |
| CPU time | 0.56 seconds |
| Started | Apr 21 04:29:49 PM PDT 24 |
| Finished | Apr 21 04:29:49 PM PDT 24 |
| Peak memory | 195180 kb |
| Host | smart-c229d310-8b4f-4faf-9803-691b63e589c8 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322647828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.322647828 |
| Directory | /workspace/19.uart_alert_test/latest |
| Test location | /workspace/coverage/default/19.uart_fifo_full.66521530 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 331500183299 ps |
| CPU time | 34.62 seconds |
| Started | Apr 21 04:29:38 PM PDT 24 |
| Finished | Apr 21 04:30:14 PM PDT 24 |
| Peak memory | 200896 kb |
| Host | smart-95c20672-6498-4049-b5cc-b6fa9664272a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=66521530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.66521530 |
| Directory | /workspace/19.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/19.uart_fifo_overflow.3876181627 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 63488850932 ps |
| CPU time | 15.43 seconds |
| Started | Apr 21 04:29:47 PM PDT 24 |
| Finished | Apr 21 04:30:02 PM PDT 24 |
| Peak memory | 200288 kb |
| Host | smart-6c15cd05-d69b-4842-81e5-7d6cd2b7ee07 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3876181627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.3876181627 |
| Directory | /workspace/19.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/19.uart_intr.1282228566 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 33281017233 ps |
| CPU time | 23.2 seconds |
| Started | Apr 21 04:29:39 PM PDT 24 |
| Finished | Apr 21 04:30:03 PM PDT 24 |
| Peak memory | 200816 kb |
| Host | smart-5ff2b4ee-e056-445d-8449-419ce3367435 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282228566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.1282228566 |
| Directory | /workspace/19.uart_intr/latest |
| Test location | /workspace/coverage/default/19.uart_loopback.1608969573 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 503484312 ps |
| CPU time | 1.37 seconds |
| Started | Apr 21 04:29:46 PM PDT 24 |
| Finished | Apr 21 04:29:48 PM PDT 24 |
| Peak memory | 198232 kb |
| Host | smart-2e20cea9-8851-446c-862d-dab05e1d70a6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1608969573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.1608969573 |
| Directory | /workspace/19.uart_loopback/latest |
| Test location | /workspace/coverage/default/19.uart_noise_filter.715152127 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 146063050329 ps |
| CPU time | 55.45 seconds |
| Started | Apr 21 04:29:47 PM PDT 24 |
| Finished | Apr 21 04:30:43 PM PDT 24 |
| Peak memory | 199164 kb |
| Host | smart-0f5dd561-278f-4247-975c-47e8615f0a11 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=715152127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.715152127 |
| Directory | /workspace/19.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/19.uart_perf.1196349135 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 15654423806 ps |
| CPU time | 338.22 seconds |
| Started | Apr 21 04:29:47 PM PDT 24 |
| Finished | Apr 21 04:35:25 PM PDT 24 |
| Peak memory | 200888 kb |
| Host | smart-83fd97b1-8ba3-451c-a5e9-20b1b31d7eb2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1196349135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.1196349135 |
| Directory | /workspace/19.uart_perf/latest |
| Test location | /workspace/coverage/default/19.uart_rx_oversample.1097834160 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 3814578407 ps |
| CPU time | 23.97 seconds |
| Started | Apr 21 04:29:47 PM PDT 24 |
| Finished | Apr 21 04:30:11 PM PDT 24 |
| Peak memory | 199744 kb |
| Host | smart-ea0a6ad2-1e0b-423e-bfb2-d566f8c4e1fe |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1097834160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.1097834160 |
| Directory | /workspace/19.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/19.uart_rx_parity_err.829941283 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 85568835787 ps |
| CPU time | 25.37 seconds |
| Started | Apr 21 04:29:48 PM PDT 24 |
| Finished | Apr 21 04:30:13 PM PDT 24 |
| Peak memory | 200836 kb |
| Host | smart-6cef896d-6f86-4e40-a198-fc14c8be121f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=829941283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.829941283 |
| Directory | /workspace/19.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/19.uart_rx_start_bit_filter.2559980119 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 48213933728 ps |
| CPU time | 25.26 seconds |
| Started | Apr 21 04:29:41 PM PDT 24 |
| Finished | Apr 21 04:30:06 PM PDT 24 |
| Peak memory | 196644 kb |
| Host | smart-a2a851f8-143c-44c9-9da8-2d9c0c8c2b97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2559980119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.2559980119 |
| Directory | /workspace/19.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/19.uart_smoke.1673951338 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 5694018970 ps |
| CPU time | 8.9 seconds |
| Started | Apr 21 04:29:48 PM PDT 24 |
| Finished | Apr 21 04:29:57 PM PDT 24 |
| Peak memory | 200772 kb |
| Host | smart-883d68ab-59ac-408a-b35a-15e63c306cf6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1673951338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.1673951338 |
| Directory | /workspace/19.uart_smoke/latest |
| Test location | /workspace/coverage/default/19.uart_stress_all.1917403809 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 148145419244 ps |
| CPU time | 176.02 seconds |
| Started | Apr 21 04:29:49 PM PDT 24 |
| Finished | Apr 21 04:32:45 PM PDT 24 |
| Peak memory | 209352 kb |
| Host | smart-5f72d6ef-3882-4098-8c4d-b918736ddb72 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917403809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.1917403809 |
| Directory | /workspace/19.uart_stress_all/latest |
| Test location | /workspace/coverage/default/19.uart_tx_ovrd.893314535 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 751175949 ps |
| CPU time | 1.64 seconds |
| Started | Apr 21 04:29:47 PM PDT 24 |
| Finished | Apr 21 04:29:49 PM PDT 24 |
| Peak memory | 199592 kb |
| Host | smart-26be572c-0bd2-4960-8186-8f8154f4c656 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=893314535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.893314535 |
| Directory | /workspace/19.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/19.uart_tx_rx.2661310117 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 80230130899 ps |
| CPU time | 83.2 seconds |
| Started | Apr 21 04:29:48 PM PDT 24 |
| Finished | Apr 21 04:31:11 PM PDT 24 |
| Peak memory | 200888 kb |
| Host | smart-185681b2-d58d-4f69-96a7-8293305bb439 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2661310117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.2661310117 |
| Directory | /workspace/19.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/190.uart_fifo_reset.2544743249 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 78834535759 ps |
| CPU time | 123.58 seconds |
| Started | Apr 21 04:38:15 PM PDT 24 |
| Finished | Apr 21 04:40:19 PM PDT 24 |
| Peak memory | 200912 kb |
| Host | smart-418966ed-69b6-4225-9cb7-ee448bd785c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2544743249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.2544743249 |
| Directory | /workspace/190.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/191.uart_fifo_reset.3590535399 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 95405893492 ps |
| CPU time | 20.94 seconds |
| Started | Apr 21 04:38:15 PM PDT 24 |
| Finished | Apr 21 04:38:37 PM PDT 24 |
| Peak memory | 200828 kb |
| Host | smart-efd72dfe-1046-4499-b4ea-5fde6bb98cdb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3590535399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.3590535399 |
| Directory | /workspace/191.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/192.uart_fifo_reset.3373797040 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 76103936267 ps |
| CPU time | 131.4 seconds |
| Started | Apr 21 04:38:18 PM PDT 24 |
| Finished | Apr 21 04:40:29 PM PDT 24 |
| Peak memory | 200836 kb |
| Host | smart-4f80ac11-9fc6-4884-8a72-21467cf7339a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3373797040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.3373797040 |
| Directory | /workspace/192.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/193.uart_fifo_reset.3048481425 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 145004195132 ps |
| CPU time | 53.36 seconds |
| Started | Apr 21 04:38:17 PM PDT 24 |
| Finished | Apr 21 04:39:11 PM PDT 24 |
| Peak memory | 200828 kb |
| Host | smart-3c6ff09f-09d5-437e-bd05-a07a05502caa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3048481425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3048481425 |
| Directory | /workspace/193.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/194.uart_fifo_reset.2331268136 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 163128840641 ps |
| CPU time | 45.8 seconds |
| Started | Apr 21 04:38:20 PM PDT 24 |
| Finished | Apr 21 04:39:06 PM PDT 24 |
| Peak memory | 200928 kb |
| Host | smart-c2631c7a-1865-4629-856b-e34d98baf391 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2331268136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.2331268136 |
| Directory | /workspace/194.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/196.uart_fifo_reset.844415208 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 166813668333 ps |
| CPU time | 78.67 seconds |
| Started | Apr 21 04:38:20 PM PDT 24 |
| Finished | Apr 21 04:39:39 PM PDT 24 |
| Peak memory | 200704 kb |
| Host | smart-7ae5cdb1-3467-4e6d-b594-49d7842bbfc7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=844415208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.844415208 |
| Directory | /workspace/196.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/197.uart_fifo_reset.693570306 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 341098315610 ps |
| CPU time | 137 seconds |
| Started | Apr 21 04:38:23 PM PDT 24 |
| Finished | Apr 21 04:40:40 PM PDT 24 |
| Peak memory | 200936 kb |
| Host | smart-c8e2db57-945b-4795-a012-fb469dc0a424 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=693570306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.693570306 |
| Directory | /workspace/197.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/199.uart_fifo_reset.3655126120 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 99156264095 ps |
| CPU time | 15.11 seconds |
| Started | Apr 21 04:38:23 PM PDT 24 |
| Finished | Apr 21 04:38:38 PM PDT 24 |
| Peak memory | 200708 kb |
| Host | smart-3e5ea494-18db-4284-b661-5b4293bd4195 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3655126120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.3655126120 |
| Directory | /workspace/199.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/2.uart_alert_test.88034519 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 21686264 ps |
| CPU time | 0.56 seconds |
| Started | Apr 21 04:25:52 PM PDT 24 |
| Finished | Apr 21 04:25:53 PM PDT 24 |
| Peak memory | 196224 kb |
| Host | smart-54753b16-b962-444e-b34f-14532d535557 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88034519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.88034519 |
| Directory | /workspace/2.uart_alert_test/latest |
| Test location | /workspace/coverage/default/2.uart_fifo_full.2359552281 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 36848807561 ps |
| CPU time | 17.09 seconds |
| Started | Apr 21 04:25:37 PM PDT 24 |
| Finished | Apr 21 04:25:54 PM PDT 24 |
| Peak memory | 200852 kb |
| Host | smart-ce209e21-5c39-45e1-8696-8d5829614335 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2359552281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.2359552281 |
| Directory | /workspace/2.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/2.uart_fifo_overflow.3103128591 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 17254596251 ps |
| CPU time | 14.08 seconds |
| Started | Apr 21 04:25:38 PM PDT 24 |
| Finished | Apr 21 04:25:52 PM PDT 24 |
| Peak memory | 200804 kb |
| Host | smart-7e5395e3-061a-4cb3-8c72-2e367fcd34b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3103128591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3103128591 |
| Directory | /workspace/2.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/2.uart_fifo_reset.4082980016 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 144383216654 ps |
| CPU time | 233.66 seconds |
| Started | Apr 21 04:25:41 PM PDT 24 |
| Finished | Apr 21 04:29:35 PM PDT 24 |
| Peak memory | 200820 kb |
| Host | smart-de60edac-8041-4ef5-9e5f-61cb632c3edb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4082980016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.4082980016 |
| Directory | /workspace/2.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/2.uart_intr.4124800451 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 106166336511 ps |
| CPU time | 201.72 seconds |
| Started | Apr 21 04:25:41 PM PDT 24 |
| Finished | Apr 21 04:29:03 PM PDT 24 |
| Peak memory | 200796 kb |
| Host | smart-a56a8d74-5e46-4610-bb88-b200a05eabf9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124800451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.4124800451 |
| Directory | /workspace/2.uart_intr/latest |
| Test location | /workspace/coverage/default/2.uart_long_xfer_wo_dly.4196506393 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 75776045276 ps |
| CPU time | 261.97 seconds |
| Started | Apr 21 04:25:49 PM PDT 24 |
| Finished | Apr 21 04:30:11 PM PDT 24 |
| Peak memory | 200860 kb |
| Host | smart-1abb2a81-95b3-4c3b-8c8f-1d103c401086 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4196506393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.4196506393 |
| Directory | /workspace/2.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/2.uart_loopback.724573866 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 1539933175 ps |
| CPU time | 3.66 seconds |
| Started | Apr 21 04:25:46 PM PDT 24 |
| Finished | Apr 21 04:25:50 PM PDT 24 |
| Peak memory | 199324 kb |
| Host | smart-19fe5afa-a7a1-4f0a-925f-5677e7d07c3a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=724573866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.724573866 |
| Directory | /workspace/2.uart_loopback/latest |
| Test location | /workspace/coverage/default/2.uart_noise_filter.3843116941 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 143897293653 ps |
| CPU time | 59.5 seconds |
| Started | Apr 21 04:25:44 PM PDT 24 |
| Finished | Apr 21 04:26:44 PM PDT 24 |
| Peak memory | 200752 kb |
| Host | smart-3cf62c94-d564-416f-b9c1-9b7a47e1636a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3843116941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.3843116941 |
| Directory | /workspace/2.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/2.uart_perf.2458080275 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 10973366464 ps |
| CPU time | 219.35 seconds |
| Started | Apr 21 04:25:48 PM PDT 24 |
| Finished | Apr 21 04:29:27 PM PDT 24 |
| Peak memory | 200840 kb |
| Host | smart-0f65ea4a-3fdb-4cf7-9321-79b68dc51018 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2458080275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.2458080275 |
| Directory | /workspace/2.uart_perf/latest |
| Test location | /workspace/coverage/default/2.uart_rx_oversample.4061463482 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 5320454422 ps |
| CPU time | 13.64 seconds |
| Started | Apr 21 04:25:41 PM PDT 24 |
| Finished | Apr 21 04:25:55 PM PDT 24 |
| Peak memory | 200188 kb |
| Host | smart-1f3cf88f-2823-4919-85d3-05988f7c871c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4061463482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.4061463482 |
| Directory | /workspace/2.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/2.uart_rx_parity_err.3255948096 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 23241325494 ps |
| CPU time | 41.75 seconds |
| Started | Apr 21 04:25:43 PM PDT 24 |
| Finished | Apr 21 04:26:25 PM PDT 24 |
| Peak memory | 200844 kb |
| Host | smart-b990d1b1-fdc9-455f-8d3e-12cd78903eaa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3255948096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.3255948096 |
| Directory | /workspace/2.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/2.uart_rx_start_bit_filter.3334326410 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 1752339103 ps |
| CPU time | 2.01 seconds |
| Started | Apr 21 04:25:44 PM PDT 24 |
| Finished | Apr 21 04:25:46 PM PDT 24 |
| Peak memory | 196556 kb |
| Host | smart-62d3c87a-d042-49e2-bdc0-a42e98184dd9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3334326410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.3334326410 |
| Directory | /workspace/2.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/2.uart_sec_cm.4158310736 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 33530370 ps |
| CPU time | 0.77 seconds |
| Started | Apr 21 04:25:51 PM PDT 24 |
| Finished | Apr 21 04:25:52 PM PDT 24 |
| Peak memory | 218668 kb |
| Host | smart-2e0b49e9-3080-4b88-9a76-99921f311615 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158310736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.4158310736 |
| Directory | /workspace/2.uart_sec_cm/latest |
| Test location | /workspace/coverage/default/2.uart_smoke.3910521957 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 515329822 ps |
| CPU time | 1.74 seconds |
| Started | Apr 21 04:25:35 PM PDT 24 |
| Finished | Apr 21 04:25:37 PM PDT 24 |
| Peak memory | 199692 kb |
| Host | smart-f1012333-2bb1-4107-b8e6-8ce6e12164ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3910521957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.3910521957 |
| Directory | /workspace/2.uart_smoke/latest |
| Test location | /workspace/coverage/default/2.uart_stress_all.1077145716 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 280404017101 ps |
| CPU time | 312.08 seconds |
| Started | Apr 21 04:25:50 PM PDT 24 |
| Finished | Apr 21 04:31:02 PM PDT 24 |
| Peak memory | 200900 kb |
| Host | smart-05ad31db-2421-4759-b424-b474b623f3ac |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077145716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.1077145716 |
| Directory | /workspace/2.uart_stress_all/latest |
| Test location | /workspace/coverage/default/2.uart_stress_all_with_rand_reset.1005326106 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 129372076161 ps |
| CPU time | 817.38 seconds |
| Started | Apr 21 04:25:50 PM PDT 24 |
| Finished | Apr 21 04:39:28 PM PDT 24 |
| Peak memory | 217352 kb |
| Host | smart-3ebd43c8-0fcc-4a94-a55a-b585fc873c06 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005326106 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.1005326106 |
| Directory | /workspace/2.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.uart_tx_rx.3433674716 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 28639593917 ps |
| CPU time | 11.98 seconds |
| Started | Apr 21 04:25:37 PM PDT 24 |
| Finished | Apr 21 04:25:49 PM PDT 24 |
| Peak memory | 200844 kb |
| Host | smart-2a6b8b17-95be-466b-9a99-cde1d15424cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3433674716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3433674716 |
| Directory | /workspace/2.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/20.uart_alert_test.4643760 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 13459456 ps |
| CPU time | 0.59 seconds |
| Started | Apr 21 04:29:58 PM PDT 24 |
| Finished | Apr 21 04:29:59 PM PDT 24 |
| Peak memory | 196228 kb |
| Host | smart-8d04aadd-95c1-4c8c-8b0e-1325aa86af1a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4643760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.4643760 |
| Directory | /workspace/20.uart_alert_test/latest |
| Test location | /workspace/coverage/default/20.uart_fifo_full.1452468985 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 74117123879 ps |
| CPU time | 16.18 seconds |
| Started | Apr 21 04:29:52 PM PDT 24 |
| Finished | Apr 21 04:30:08 PM PDT 24 |
| Peak memory | 200668 kb |
| Host | smart-7932fd7e-2ffe-440d-99f5-d06971578b66 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1452468985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.1452468985 |
| Directory | /workspace/20.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/20.uart_fifo_overflow.508090297 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 20943338972 ps |
| CPU time | 42.07 seconds |
| Started | Apr 21 04:29:53 PM PDT 24 |
| Finished | Apr 21 04:30:36 PM PDT 24 |
| Peak memory | 200840 kb |
| Host | smart-8d150837-57ad-4219-aadd-a8e77361939d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=508090297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.508090297 |
| Directory | /workspace/20.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/20.uart_fifo_reset.329900000 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 83874417312 ps |
| CPU time | 131.22 seconds |
| Started | Apr 21 04:29:54 PM PDT 24 |
| Finished | Apr 21 04:32:05 PM PDT 24 |
| Peak memory | 200872 kb |
| Host | smart-acb58f2b-1961-490d-821c-7fdf5bc3289f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=329900000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.329900000 |
| Directory | /workspace/20.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/20.uart_intr.3700050060 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 46974847815 ps |
| CPU time | 81.05 seconds |
| Started | Apr 21 04:29:58 PM PDT 24 |
| Finished | Apr 21 04:31:19 PM PDT 24 |
| Peak memory | 200428 kb |
| Host | smart-886b465c-e3a1-457b-b90b-4c0cdba2f6f0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700050060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.3700050060 |
| Directory | /workspace/20.uart_intr/latest |
| Test location | /workspace/coverage/default/20.uart_long_xfer_wo_dly.998126709 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 139955367838 ps |
| CPU time | 529.64 seconds |
| Started | Apr 21 04:29:56 PM PDT 24 |
| Finished | Apr 21 04:38:46 PM PDT 24 |
| Peak memory | 200920 kb |
| Host | smart-3e2c7df9-29ec-426c-8668-87700ed901c9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=998126709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.998126709 |
| Directory | /workspace/20.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/20.uart_loopback.2082481017 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 543156481 ps |
| CPU time | 1.09 seconds |
| Started | Apr 21 04:29:55 PM PDT 24 |
| Finished | Apr 21 04:29:57 PM PDT 24 |
| Peak memory | 196916 kb |
| Host | smart-32ab417b-7beb-4993-8660-462d240f695b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2082481017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2082481017 |
| Directory | /workspace/20.uart_loopback/latest |
| Test location | /workspace/coverage/default/20.uart_noise_filter.3249365519 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 50811528753 ps |
| CPU time | 24.06 seconds |
| Started | Apr 21 04:29:56 PM PDT 24 |
| Finished | Apr 21 04:30:20 PM PDT 24 |
| Peak memory | 200052 kb |
| Host | smart-7a999b83-db0a-411b-87e0-26cd86447f63 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3249365519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.3249365519 |
| Directory | /workspace/20.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/20.uart_perf.3221738685 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 12318905971 ps |
| CPU time | 376.72 seconds |
| Started | Apr 21 04:29:56 PM PDT 24 |
| Finished | Apr 21 04:36:13 PM PDT 24 |
| Peak memory | 200880 kb |
| Host | smart-d7d5e4f6-afff-483c-8784-00330fc23f68 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3221738685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.3221738685 |
| Directory | /workspace/20.uart_perf/latest |
| Test location | /workspace/coverage/default/20.uart_rx_oversample.2684386186 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 2739687187 ps |
| CPU time | 2.44 seconds |
| Started | Apr 21 04:29:53 PM PDT 24 |
| Finished | Apr 21 04:29:56 PM PDT 24 |
| Peak memory | 198928 kb |
| Host | smart-641c6f64-fb8d-49ab-a696-f32cf4dc8e9f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2684386186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2684386186 |
| Directory | /workspace/20.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/20.uart_rx_parity_err.182918856 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 24295307866 ps |
| CPU time | 34.3 seconds |
| Started | Apr 21 04:29:57 PM PDT 24 |
| Finished | Apr 21 04:30:32 PM PDT 24 |
| Peak memory | 200432 kb |
| Host | smart-fc51def8-52b9-4e52-bf51-fc0234cc3710 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=182918856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.182918856 |
| Directory | /workspace/20.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/20.uart_rx_start_bit_filter.1785728007 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 3028916783 ps |
| CPU time | 6.21 seconds |
| Started | Apr 21 04:29:55 PM PDT 24 |
| Finished | Apr 21 04:30:01 PM PDT 24 |
| Peak memory | 196604 kb |
| Host | smart-b6c2f528-4ea7-4de5-9bba-5dffeae7aaa1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1785728007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.1785728007 |
| Directory | /workspace/20.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/20.uart_smoke.1945245016 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 6095890338 ps |
| CPU time | 13.83 seconds |
| Started | Apr 21 04:29:53 PM PDT 24 |
| Finished | Apr 21 04:30:07 PM PDT 24 |
| Peak memory | 200732 kb |
| Host | smart-5b252019-e05c-444a-a408-531384590045 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1945245016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.1945245016 |
| Directory | /workspace/20.uart_smoke/latest |
| Test location | /workspace/coverage/default/20.uart_stress_all_with_rand_reset.865317705 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 14540409194 ps |
| CPU time | 71.48 seconds |
| Started | Apr 21 04:29:58 PM PDT 24 |
| Finished | Apr 21 04:31:10 PM PDT 24 |
| Peak memory | 217328 kb |
| Host | smart-1dcb4411-ed69-4271-bb9c-b5d2bef875c1 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865317705 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.865317705 |
| Directory | /workspace/20.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/20.uart_tx_ovrd.948512530 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 746858571 ps |
| CPU time | 4.42 seconds |
| Started | Apr 21 04:29:58 PM PDT 24 |
| Finished | Apr 21 04:30:02 PM PDT 24 |
| Peak memory | 200172 kb |
| Host | smart-2b217322-42e7-4831-a34e-465d35e3f044 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=948512530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.948512530 |
| Directory | /workspace/20.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/20.uart_tx_rx.516134295 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 111344826595 ps |
| CPU time | 61.57 seconds |
| Started | Apr 21 04:29:54 PM PDT 24 |
| Finished | Apr 21 04:30:56 PM PDT 24 |
| Peak memory | 200896 kb |
| Host | smart-8bebecc8-f7f8-4ea6-891d-12c2190c0f18 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=516134295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.516134295 |
| Directory | /workspace/20.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/200.uart_fifo_reset.3584135566 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 180244742021 ps |
| CPU time | 112.48 seconds |
| Started | Apr 21 04:38:26 PM PDT 24 |
| Finished | Apr 21 04:40:19 PM PDT 24 |
| Peak memory | 200828 kb |
| Host | smart-f93970bc-6172-4ba1-884a-69da8cf822b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3584135566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.3584135566 |
| Directory | /workspace/200.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/201.uart_fifo_reset.2755514569 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 59868222730 ps |
| CPU time | 58.98 seconds |
| Started | Apr 21 04:38:23 PM PDT 24 |
| Finished | Apr 21 04:39:22 PM PDT 24 |
| Peak memory | 200920 kb |
| Host | smart-66b184b8-4915-4ed6-bcfd-7cf4c80e9615 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2755514569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.2755514569 |
| Directory | /workspace/201.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/202.uart_fifo_reset.2360214108 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 48634098676 ps |
| CPU time | 84.51 seconds |
| Started | Apr 21 04:38:25 PM PDT 24 |
| Finished | Apr 21 04:39:50 PM PDT 24 |
| Peak memory | 201020 kb |
| Host | smart-03b30a83-80db-4367-96bf-ca6aaa13f9fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2360214108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.2360214108 |
| Directory | /workspace/202.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/203.uart_fifo_reset.3210925594 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 129980691079 ps |
| CPU time | 17.39 seconds |
| Started | Apr 21 04:38:27 PM PDT 24 |
| Finished | Apr 21 04:38:44 PM PDT 24 |
| Peak memory | 200892 kb |
| Host | smart-bcea59b5-493f-4754-94d8-7cae4be1dab0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3210925594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.3210925594 |
| Directory | /workspace/203.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/204.uart_fifo_reset.2265350994 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 25986888814 ps |
| CPU time | 10.79 seconds |
| Started | Apr 21 04:38:27 PM PDT 24 |
| Finished | Apr 21 04:38:38 PM PDT 24 |
| Peak memory | 200824 kb |
| Host | smart-010b8c1b-93ef-40bb-b5fb-c55eeae01e0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2265350994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.2265350994 |
| Directory | /workspace/204.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/205.uart_fifo_reset.440108736 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 108508556855 ps |
| CPU time | 10.79 seconds |
| Started | Apr 21 04:38:27 PM PDT 24 |
| Finished | Apr 21 04:38:38 PM PDT 24 |
| Peak memory | 200632 kb |
| Host | smart-972fee0d-b96f-4cbf-be66-b33b6ff90a3b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=440108736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.440108736 |
| Directory | /workspace/205.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/206.uart_fifo_reset.1121280264 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 137781436801 ps |
| CPU time | 103.95 seconds |
| Started | Apr 21 04:38:25 PM PDT 24 |
| Finished | Apr 21 04:40:10 PM PDT 24 |
| Peak memory | 201020 kb |
| Host | smart-f6edf9c3-0957-4acd-90f0-43ff7013fb29 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1121280264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.1121280264 |
| Directory | /workspace/206.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/207.uart_fifo_reset.2860132791 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 36161030634 ps |
| CPU time | 59.91 seconds |
| Started | Apr 21 04:38:28 PM PDT 24 |
| Finished | Apr 21 04:39:28 PM PDT 24 |
| Peak memory | 200832 kb |
| Host | smart-1f9c5b2b-c013-4064-bb18-23b85ff6b04a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2860132791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2860132791 |
| Directory | /workspace/207.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/208.uart_fifo_reset.212147949 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 3879546787 ps |
| CPU time | 7.83 seconds |
| Started | Apr 21 04:38:32 PM PDT 24 |
| Finished | Apr 21 04:38:40 PM PDT 24 |
| Peak memory | 200708 kb |
| Host | smart-dc9144a6-48cb-4e4c-9264-a652ea63dc9d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=212147949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.212147949 |
| Directory | /workspace/208.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/209.uart_fifo_reset.2791957012 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 127586739974 ps |
| CPU time | 96.38 seconds |
| Started | Apr 21 04:38:30 PM PDT 24 |
| Finished | Apr 21 04:40:07 PM PDT 24 |
| Peak memory | 200860 kb |
| Host | smart-d3bc359e-ca65-4060-b8e0-0affa81c0438 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2791957012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2791957012 |
| Directory | /workspace/209.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/21.uart_alert_test.66373477 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 13274449 ps |
| CPU time | 0.59 seconds |
| Started | Apr 21 04:30:06 PM PDT 24 |
| Finished | Apr 21 04:30:07 PM PDT 24 |
| Peak memory | 196216 kb |
| Host | smart-9a14627e-8d22-422a-acb8-94ed6a3fe477 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66373477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.66373477 |
| Directory | /workspace/21.uart_alert_test/latest |
| Test location | /workspace/coverage/default/21.uart_fifo_full.3102930507 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 220223169034 ps |
| CPU time | 760.13 seconds |
| Started | Apr 21 04:30:00 PM PDT 24 |
| Finished | Apr 21 04:42:41 PM PDT 24 |
| Peak memory | 200880 kb |
| Host | smart-618302fc-caac-4ee2-a6b7-908a5ad84961 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3102930507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.3102930507 |
| Directory | /workspace/21.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/21.uart_fifo_overflow.389735666 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 42783632076 ps |
| CPU time | 35.12 seconds |
| Started | Apr 21 04:30:00 PM PDT 24 |
| Finished | Apr 21 04:30:35 PM PDT 24 |
| Peak memory | 200872 kb |
| Host | smart-497380e0-5f84-491a-91bf-ca0aacd23450 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=389735666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.389735666 |
| Directory | /workspace/21.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/21.uart_fifo_reset.4191513743 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 13329515160 ps |
| CPU time | 2.83 seconds |
| Started | Apr 21 04:29:58 PM PDT 24 |
| Finished | Apr 21 04:30:02 PM PDT 24 |
| Peak memory | 198356 kb |
| Host | smart-153aeb85-5075-4470-9727-004fc8941a0b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4191513743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.4191513743 |
| Directory | /workspace/21.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/21.uart_intr.2519655035 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 247678579089 ps |
| CPU time | 344.55 seconds |
| Started | Apr 21 04:30:04 PM PDT 24 |
| Finished | Apr 21 04:35:49 PM PDT 24 |
| Peak memory | 200868 kb |
| Host | smart-e34acc38-d765-4c8b-87b2-ee3ac583e7ea |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519655035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2519655035 |
| Directory | /workspace/21.uart_intr/latest |
| Test location | /workspace/coverage/default/21.uart_long_xfer_wo_dly.2051383195 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 82022387282 ps |
| CPU time | 375.39 seconds |
| Started | Apr 21 04:30:06 PM PDT 24 |
| Finished | Apr 21 04:36:22 PM PDT 24 |
| Peak memory | 200856 kb |
| Host | smart-949b7890-74df-4de9-b9e5-3d059a5aa50f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2051383195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.2051383195 |
| Directory | /workspace/21.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/21.uart_loopback.2315172219 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 2608575233 ps |
| CPU time | 2.99 seconds |
| Started | Apr 21 04:30:09 PM PDT 24 |
| Finished | Apr 21 04:30:12 PM PDT 24 |
| Peak memory | 199996 kb |
| Host | smart-75e6959c-363b-4da3-adca-04a8a34483b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2315172219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2315172219 |
| Directory | /workspace/21.uart_loopback/latest |
| Test location | /workspace/coverage/default/21.uart_noise_filter.1487349386 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 52850223308 ps |
| CPU time | 14.41 seconds |
| Started | Apr 21 04:30:04 PM PDT 24 |
| Finished | Apr 21 04:30:18 PM PDT 24 |
| Peak memory | 195604 kb |
| Host | smart-08f12069-5849-402c-bda7-8fc0f1a25c95 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1487349386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.1487349386 |
| Directory | /workspace/21.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/21.uart_perf.1515747023 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 18992300959 ps |
| CPU time | 80.25 seconds |
| Started | Apr 21 04:30:10 PM PDT 24 |
| Finished | Apr 21 04:31:30 PM PDT 24 |
| Peak memory | 200936 kb |
| Host | smart-1740655b-689a-48de-8195-87c7e9d9f090 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1515747023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.1515747023 |
| Directory | /workspace/21.uart_perf/latest |
| Test location | /workspace/coverage/default/21.uart_rx_oversample.4005959955 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 7255169758 ps |
| CPU time | 65.48 seconds |
| Started | Apr 21 04:30:00 PM PDT 24 |
| Finished | Apr 21 04:31:05 PM PDT 24 |
| Peak memory | 200032 kb |
| Host | smart-db31f309-f658-40de-b331-c6f414fbb149 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4005959955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.4005959955 |
| Directory | /workspace/21.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/21.uart_rx_parity_err.3153513496 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 23855265463 ps |
| CPU time | 7.72 seconds |
| Started | Apr 21 04:30:12 PM PDT 24 |
| Finished | Apr 21 04:30:20 PM PDT 24 |
| Peak memory | 200828 kb |
| Host | smart-c05ecb46-ea49-4ff6-9eed-c0ed4368edd1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3153513496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.3153513496 |
| Directory | /workspace/21.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/21.uart_rx_start_bit_filter.3255496102 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 3159691205 ps |
| CPU time | 1.72 seconds |
| Started | Apr 21 04:30:02 PM PDT 24 |
| Finished | Apr 21 04:30:05 PM PDT 24 |
| Peak memory | 196948 kb |
| Host | smart-ad84ab31-d681-4a1e-a6e0-0e24acd39e5e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3255496102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.3255496102 |
| Directory | /workspace/21.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/21.uart_smoke.3863449586 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 116063996 ps |
| CPU time | 0.92 seconds |
| Started | Apr 21 04:29:58 PM PDT 24 |
| Finished | Apr 21 04:29:59 PM PDT 24 |
| Peak memory | 199368 kb |
| Host | smart-3ce84f07-36b3-4f81-9fb7-c55bd8750040 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3863449586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.3863449586 |
| Directory | /workspace/21.uart_smoke/latest |
| Test location | /workspace/coverage/default/21.uart_stress_all.586356705 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 190156866988 ps |
| CPU time | 655.28 seconds |
| Started | Apr 21 04:30:10 PM PDT 24 |
| Finished | Apr 21 04:41:05 PM PDT 24 |
| Peak memory | 200912 kb |
| Host | smart-1269e907-b1b5-405d-9b56-b91c89868766 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586356705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.586356705 |
| Directory | /workspace/21.uart_stress_all/latest |
| Test location | /workspace/coverage/default/21.uart_stress_all_with_rand_reset.4144044979 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 53295411343 ps |
| CPU time | 644.22 seconds |
| Started | Apr 21 04:30:07 PM PDT 24 |
| Finished | Apr 21 04:40:52 PM PDT 24 |
| Peak memory | 225656 kb |
| Host | smart-c70f75a1-5f40-4e2f-9b7f-b348273bd129 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144044979 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.4144044979 |
| Directory | /workspace/21.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/21.uart_tx_ovrd.3640604201 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 723520409 ps |
| CPU time | 3.07 seconds |
| Started | Apr 21 04:30:08 PM PDT 24 |
| Finished | Apr 21 04:30:12 PM PDT 24 |
| Peak memory | 200404 kb |
| Host | smart-8cf09ec6-5260-477a-9a9e-7f0205a161dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3640604201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.3640604201 |
| Directory | /workspace/21.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/21.uart_tx_rx.1814755597 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 185271333280 ps |
| CPU time | 57.03 seconds |
| Started | Apr 21 04:30:00 PM PDT 24 |
| Finished | Apr 21 04:30:57 PM PDT 24 |
| Peak memory | 200768 kb |
| Host | smart-c8c8fde6-8ecb-4330-a6dd-eb8084c9f9e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1814755597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.1814755597 |
| Directory | /workspace/21.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/210.uart_fifo_reset.418654198 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 121218816227 ps |
| CPU time | 102.05 seconds |
| Started | Apr 21 04:38:32 PM PDT 24 |
| Finished | Apr 21 04:40:14 PM PDT 24 |
| Peak memory | 200888 kb |
| Host | smart-17203bc4-7deb-4a65-9045-3bcb312987f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=418654198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.418654198 |
| Directory | /workspace/210.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/211.uart_fifo_reset.1291066062 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 103925798643 ps |
| CPU time | 48.7 seconds |
| Started | Apr 21 04:38:31 PM PDT 24 |
| Finished | Apr 21 04:39:20 PM PDT 24 |
| Peak memory | 200832 kb |
| Host | smart-60af6b4d-ea74-464b-a6ca-e28a218511c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1291066062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.1291066062 |
| Directory | /workspace/211.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/213.uart_fifo_reset.4183334629 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 117190242008 ps |
| CPU time | 370.47 seconds |
| Started | Apr 21 04:38:33 PM PDT 24 |
| Finished | Apr 21 04:44:43 PM PDT 24 |
| Peak memory | 200876 kb |
| Host | smart-4f24b999-4374-4fb8-ae61-ac03d69e795f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4183334629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.4183334629 |
| Directory | /workspace/213.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/214.uart_fifo_reset.3794653670 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 17174268103 ps |
| CPU time | 8.35 seconds |
| Started | Apr 21 04:38:33 PM PDT 24 |
| Finished | Apr 21 04:38:41 PM PDT 24 |
| Peak memory | 200652 kb |
| Host | smart-976890e3-564a-4fbe-8bfd-89a3986f3d5f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3794653670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.3794653670 |
| Directory | /workspace/214.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/215.uart_fifo_reset.1727007029 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 43329333179 ps |
| CPU time | 60.6 seconds |
| Started | Apr 21 04:38:37 PM PDT 24 |
| Finished | Apr 21 04:39:37 PM PDT 24 |
| Peak memory | 200888 kb |
| Host | smart-ec593695-2072-4f28-9f3d-f9213b8db7d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1727007029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.1727007029 |
| Directory | /workspace/215.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/216.uart_fifo_reset.4094665581 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 37725153019 ps |
| CPU time | 53.21 seconds |
| Started | Apr 21 04:38:36 PM PDT 24 |
| Finished | Apr 21 04:39:29 PM PDT 24 |
| Peak memory | 200900 kb |
| Host | smart-825b0021-9604-4681-a35a-9728963ca198 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4094665581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.4094665581 |
| Directory | /workspace/216.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/217.uart_fifo_reset.892812794 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 28374964808 ps |
| CPU time | 13.18 seconds |
| Started | Apr 21 04:38:36 PM PDT 24 |
| Finished | Apr 21 04:38:49 PM PDT 24 |
| Peak memory | 200820 kb |
| Host | smart-510101fa-3ddb-4d93-bf4f-17ef216ce037 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=892812794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.892812794 |
| Directory | /workspace/217.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/218.uart_fifo_reset.4265849210 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 16426410112 ps |
| CPU time | 23.91 seconds |
| Started | Apr 21 04:38:37 PM PDT 24 |
| Finished | Apr 21 04:39:01 PM PDT 24 |
| Peak memory | 200476 kb |
| Host | smart-26d7ddbf-79c1-441c-a17a-8019af95a663 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4265849210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.4265849210 |
| Directory | /workspace/218.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/219.uart_fifo_reset.2720631978 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 27391572141 ps |
| CPU time | 31.14 seconds |
| Started | Apr 21 04:38:36 PM PDT 24 |
| Finished | Apr 21 04:39:07 PM PDT 24 |
| Peak memory | 200936 kb |
| Host | smart-e1511924-743e-406c-8402-91ead7d1ff47 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2720631978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.2720631978 |
| Directory | /workspace/219.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/22.uart_alert_test.4281547723 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 10629970 ps |
| CPU time | 0.55 seconds |
| Started | Apr 21 04:30:20 PM PDT 24 |
| Finished | Apr 21 04:30:20 PM PDT 24 |
| Peak memory | 196224 kb |
| Host | smart-bd2a6bb9-f1fc-498a-a23a-0f5b0e996a52 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281547723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.4281547723 |
| Directory | /workspace/22.uart_alert_test/latest |
| Test location | /workspace/coverage/default/22.uart_fifo_full.3046901904 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 110460577459 ps |
| CPU time | 189.07 seconds |
| Started | Apr 21 04:30:11 PM PDT 24 |
| Finished | Apr 21 04:33:20 PM PDT 24 |
| Peak memory | 200932 kb |
| Host | smart-5f787822-2371-4a1f-97bd-e8f0a0aaf3a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3046901904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.3046901904 |
| Directory | /workspace/22.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/22.uart_fifo_reset.1442468255 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 70784878792 ps |
| CPU time | 55.58 seconds |
| Started | Apr 21 04:30:10 PM PDT 24 |
| Finished | Apr 21 04:31:06 PM PDT 24 |
| Peak memory | 200680 kb |
| Host | smart-4c644268-118a-480a-9004-d4b6318b6a53 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1442468255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.1442468255 |
| Directory | /workspace/22.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/22.uart_intr.3674403383 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 53298082375 ps |
| CPU time | 101.25 seconds |
| Started | Apr 21 04:30:12 PM PDT 24 |
| Finished | Apr 21 04:31:53 PM PDT 24 |
| Peak memory | 200708 kb |
| Host | smart-333b9f87-624e-4dbc-8471-240fc619dbef |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674403383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.3674403383 |
| Directory | /workspace/22.uart_intr/latest |
| Test location | /workspace/coverage/default/22.uart_long_xfer_wo_dly.936756743 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 80912466062 ps |
| CPU time | 106.91 seconds |
| Started | Apr 21 04:30:17 PM PDT 24 |
| Finished | Apr 21 04:32:04 PM PDT 24 |
| Peak memory | 200856 kb |
| Host | smart-20f93eae-d886-4849-9480-03c503ab3f80 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=936756743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.936756743 |
| Directory | /workspace/22.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/22.uart_loopback.1918445600 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 2937639849 ps |
| CPU time | 2.03 seconds |
| Started | Apr 21 04:30:18 PM PDT 24 |
| Finished | Apr 21 04:30:20 PM PDT 24 |
| Peak memory | 196628 kb |
| Host | smart-47dc3492-1744-44cb-86c2-c3e7dde95bcb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1918445600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1918445600 |
| Directory | /workspace/22.uart_loopback/latest |
| Test location | /workspace/coverage/default/22.uart_noise_filter.1692972323 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 8827803957 ps |
| CPU time | 16.02 seconds |
| Started | Apr 21 04:30:12 PM PDT 24 |
| Finished | Apr 21 04:30:28 PM PDT 24 |
| Peak memory | 197648 kb |
| Host | smart-bdb7b238-5a84-40ca-9165-d931f9aa058a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1692972323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.1692972323 |
| Directory | /workspace/22.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/22.uart_perf.3573472120 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 13380175993 ps |
| CPU time | 164.29 seconds |
| Started | Apr 21 04:30:17 PM PDT 24 |
| Finished | Apr 21 04:33:01 PM PDT 24 |
| Peak memory | 200936 kb |
| Host | smart-e9f9b4be-f9d9-409b-94d7-43233daa22d9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3573472120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.3573472120 |
| Directory | /workspace/22.uart_perf/latest |
| Test location | /workspace/coverage/default/22.uart_rx_oversample.1238655378 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 6233893795 ps |
| CPU time | 59.6 seconds |
| Started | Apr 21 04:30:13 PM PDT 24 |
| Finished | Apr 21 04:31:13 PM PDT 24 |
| Peak memory | 200052 kb |
| Host | smart-cf3ec777-5751-467e-89c3-0a84c929b71b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1238655378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.1238655378 |
| Directory | /workspace/22.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/22.uart_rx_parity_err.2360263276 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 120320926831 ps |
| CPU time | 92.13 seconds |
| Started | Apr 21 04:30:13 PM PDT 24 |
| Finished | Apr 21 04:31:46 PM PDT 24 |
| Peak memory | 200560 kb |
| Host | smart-b8fbee3c-1a84-4f6b-834b-ebc2f8b9f140 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2360263276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.2360263276 |
| Directory | /workspace/22.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/22.uart_rx_start_bit_filter.72102681 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 4029902810 ps |
| CPU time | 4.26 seconds |
| Started | Apr 21 04:30:13 PM PDT 24 |
| Finished | Apr 21 04:30:17 PM PDT 24 |
| Peak memory | 197192 kb |
| Host | smart-f94b4f75-15a9-466b-ae87-bf18dfd8af5c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=72102681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.72102681 |
| Directory | /workspace/22.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/22.uart_smoke.444211680 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 542103942 ps |
| CPU time | 1.76 seconds |
| Started | Apr 21 04:30:11 PM PDT 24 |
| Finished | Apr 21 04:30:13 PM PDT 24 |
| Peak memory | 199608 kb |
| Host | smart-ac0666df-4ba1-4029-a6d8-263d75c7a6a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=444211680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.444211680 |
| Directory | /workspace/22.uart_smoke/latest |
| Test location | /workspace/coverage/default/22.uart_stress_all.1030383758 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 620579556631 ps |
| CPU time | 292.64 seconds |
| Started | Apr 21 04:30:20 PM PDT 24 |
| Finished | Apr 21 04:35:12 PM PDT 24 |
| Peak memory | 209324 kb |
| Host | smart-c8015334-af8f-4ba2-b996-ec25aca44451 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030383758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.1030383758 |
| Directory | /workspace/22.uart_stress_all/latest |
| Test location | /workspace/coverage/default/22.uart_stress_all_with_rand_reset.2935634378 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 41430517099 ps |
| CPU time | 612.23 seconds |
| Started | Apr 21 04:30:19 PM PDT 24 |
| Finished | Apr 21 04:40:31 PM PDT 24 |
| Peak memory | 217492 kb |
| Host | smart-ad44c275-5a62-4721-bacf-a1554a76bf24 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935634378 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.2935634378 |
| Directory | /workspace/22.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/22.uart_tx_ovrd.2090121936 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 1610725613 ps |
| CPU time | 2.52 seconds |
| Started | Apr 21 04:30:17 PM PDT 24 |
| Finished | Apr 21 04:30:19 PM PDT 24 |
| Peak memory | 199440 kb |
| Host | smart-58e6b7c2-5154-4d98-8fd2-09088b73bc2a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2090121936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.2090121936 |
| Directory | /workspace/22.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/22.uart_tx_rx.2710028019 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 25149401424 ps |
| CPU time | 22.06 seconds |
| Started | Apr 21 04:30:12 PM PDT 24 |
| Finished | Apr 21 04:30:34 PM PDT 24 |
| Peak memory | 200712 kb |
| Host | smart-b7b025a9-8c42-4876-b314-82bf973fe48a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2710028019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.2710028019 |
| Directory | /workspace/22.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/220.uart_fifo_reset.32329425 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 42265948169 ps |
| CPU time | 15.16 seconds |
| Started | Apr 21 04:38:37 PM PDT 24 |
| Finished | Apr 21 04:38:53 PM PDT 24 |
| Peak memory | 200800 kb |
| Host | smart-fbb2dcf0-986c-4d67-8506-3a30df32d202 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=32329425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.32329425 |
| Directory | /workspace/220.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/221.uart_fifo_reset.3614276185 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 12323780117 ps |
| CPU time | 22.44 seconds |
| Started | Apr 21 04:38:39 PM PDT 24 |
| Finished | Apr 21 04:39:01 PM PDT 24 |
| Peak memory | 200924 kb |
| Host | smart-62775f78-58cd-495b-89ad-02d60e7bc3b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3614276185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.3614276185 |
| Directory | /workspace/221.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/222.uart_fifo_reset.1717028254 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 11157555413 ps |
| CPU time | 11.05 seconds |
| Started | Apr 21 04:38:39 PM PDT 24 |
| Finished | Apr 21 04:38:51 PM PDT 24 |
| Peak memory | 200872 kb |
| Host | smart-80904dfe-73a1-4671-aa62-a3469f559f24 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1717028254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.1717028254 |
| Directory | /workspace/222.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/223.uart_fifo_reset.687151283 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 19427136066 ps |
| CPU time | 24.12 seconds |
| Started | Apr 21 04:38:38 PM PDT 24 |
| Finished | Apr 21 04:39:02 PM PDT 24 |
| Peak memory | 200928 kb |
| Host | smart-8b60b554-eac3-44c5-a8fc-d17c42f96a7f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=687151283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.687151283 |
| Directory | /workspace/223.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/224.uart_fifo_reset.840499814 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 265439436793 ps |
| CPU time | 699.96 seconds |
| Started | Apr 21 04:38:39 PM PDT 24 |
| Finished | Apr 21 04:50:19 PM PDT 24 |
| Peak memory | 200828 kb |
| Host | smart-f6e92150-df4d-4c1c-bc15-b9eeacce6aa9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=840499814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.840499814 |
| Directory | /workspace/224.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/225.uart_fifo_reset.908178555 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 49424791516 ps |
| CPU time | 30.57 seconds |
| Started | Apr 21 04:38:42 PM PDT 24 |
| Finished | Apr 21 04:39:12 PM PDT 24 |
| Peak memory | 200816 kb |
| Host | smart-7be6b830-82b1-48b5-9ac2-a80080431520 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=908178555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.908178555 |
| Directory | /workspace/225.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/226.uart_fifo_reset.4284857486 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 142346647926 ps |
| CPU time | 103.67 seconds |
| Started | Apr 21 04:38:41 PM PDT 24 |
| Finished | Apr 21 04:40:25 PM PDT 24 |
| Peak memory | 200900 kb |
| Host | smart-ef123f65-298f-4c6f-ac8c-595e00504715 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4284857486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.4284857486 |
| Directory | /workspace/226.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/227.uart_fifo_reset.1324981916 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 15751994452 ps |
| CPU time | 24.18 seconds |
| Started | Apr 21 04:38:42 PM PDT 24 |
| Finished | Apr 21 04:39:07 PM PDT 24 |
| Peak memory | 200736 kb |
| Host | smart-d72b408a-d119-44a0-9c6c-0fd9b8aa7626 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1324981916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.1324981916 |
| Directory | /workspace/227.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/228.uart_fifo_reset.4084594155 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 83736135499 ps |
| CPU time | 34.93 seconds |
| Started | Apr 21 04:38:41 PM PDT 24 |
| Finished | Apr 21 04:39:16 PM PDT 24 |
| Peak memory | 200904 kb |
| Host | smart-7e1612dd-030b-4377-8377-b85d2e1cfa92 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4084594155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.4084594155 |
| Directory | /workspace/228.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/229.uart_fifo_reset.1762980680 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 153440995926 ps |
| CPU time | 238.57 seconds |
| Started | Apr 21 04:38:43 PM PDT 24 |
| Finished | Apr 21 04:42:42 PM PDT 24 |
| Peak memory | 200868 kb |
| Host | smart-aa5bc68e-54e7-409e-9ceb-9a2df68fe4bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1762980680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1762980680 |
| Directory | /workspace/229.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/23.uart_alert_test.1234517349 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 17983913 ps |
| CPU time | 0.56 seconds |
| Started | Apr 21 04:30:32 PM PDT 24 |
| Finished | Apr 21 04:30:33 PM PDT 24 |
| Peak memory | 196200 kb |
| Host | smart-12a8647e-c66a-402e-a63f-25e68abf32c9 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234517349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.1234517349 |
| Directory | /workspace/23.uart_alert_test/latest |
| Test location | /workspace/coverage/default/23.uart_fifo_full.845445471 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 62974532064 ps |
| CPU time | 150.91 seconds |
| Started | Apr 21 04:30:22 PM PDT 24 |
| Finished | Apr 21 04:32:53 PM PDT 24 |
| Peak memory | 201028 kb |
| Host | smart-aed83654-7469-47d6-9f1a-bee97ebc063e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=845445471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.845445471 |
| Directory | /workspace/23.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/23.uart_fifo_overflow.3811737291 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 59454382001 ps |
| CPU time | 64.23 seconds |
| Started | Apr 21 04:30:24 PM PDT 24 |
| Finished | Apr 21 04:31:29 PM PDT 24 |
| Peak memory | 200708 kb |
| Host | smart-7b00d82f-f313-466e-9391-624937de66b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3811737291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.3811737291 |
| Directory | /workspace/23.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/23.uart_fifo_reset.1381859476 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 101032624448 ps |
| CPU time | 100.49 seconds |
| Started | Apr 21 04:30:26 PM PDT 24 |
| Finished | Apr 21 04:32:06 PM PDT 24 |
| Peak memory | 200924 kb |
| Host | smart-348768db-e8e9-4418-af9f-2860ff53cbb1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1381859476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.1381859476 |
| Directory | /workspace/23.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/23.uart_intr.3736858534 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 320240583590 ps |
| CPU time | 311.67 seconds |
| Started | Apr 21 04:30:29 PM PDT 24 |
| Finished | Apr 21 04:35:41 PM PDT 24 |
| Peak memory | 199064 kb |
| Host | smart-42c4dea5-33e5-4aba-b1e8-2e876b8edd88 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736858534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.3736858534 |
| Directory | /workspace/23.uart_intr/latest |
| Test location | /workspace/coverage/default/23.uart_long_xfer_wo_dly.1158083518 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 84295101921 ps |
| CPU time | 370.82 seconds |
| Started | Apr 21 04:30:30 PM PDT 24 |
| Finished | Apr 21 04:36:41 PM PDT 24 |
| Peak memory | 200928 kb |
| Host | smart-768b3d81-466b-405b-84e4-fe31ffe42c2f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1158083518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1158083518 |
| Directory | /workspace/23.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/23.uart_loopback.2536275854 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 7138804451 ps |
| CPU time | 14.57 seconds |
| Started | Apr 21 04:30:30 PM PDT 24 |
| Finished | Apr 21 04:30:45 PM PDT 24 |
| Peak memory | 198584 kb |
| Host | smart-bc9ae18f-533e-4bf6-b6ed-a9f9a901a552 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2536275854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.2536275854 |
| Directory | /workspace/23.uart_loopback/latest |
| Test location | /workspace/coverage/default/23.uart_noise_filter.1431030842 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 101019310649 ps |
| CPU time | 41.56 seconds |
| Started | Apr 21 04:30:29 PM PDT 24 |
| Finished | Apr 21 04:31:10 PM PDT 24 |
| Peak memory | 201084 kb |
| Host | smart-0596788e-2063-404c-a977-b6e88081f6af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1431030842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.1431030842 |
| Directory | /workspace/23.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/23.uart_perf.1964235267 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 15020233571 ps |
| CPU time | 590.13 seconds |
| Started | Apr 21 04:30:30 PM PDT 24 |
| Finished | Apr 21 04:40:20 PM PDT 24 |
| Peak memory | 200880 kb |
| Host | smart-9da2fef2-0e9f-45e1-8808-f41b40846b89 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1964235267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.1964235267 |
| Directory | /workspace/23.uart_perf/latest |
| Test location | /workspace/coverage/default/23.uart_rx_oversample.3813980695 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 6607468274 ps |
| CPU time | 4.47 seconds |
| Started | Apr 21 04:30:25 PM PDT 24 |
| Finished | Apr 21 04:30:29 PM PDT 24 |
| Peak memory | 200036 kb |
| Host | smart-3d3c9e8d-0da7-4ac7-9498-fce5685954c9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3813980695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.3813980695 |
| Directory | /workspace/23.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/23.uart_rx_parity_err.1116446680 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 64044966955 ps |
| CPU time | 24.59 seconds |
| Started | Apr 21 04:30:29 PM PDT 24 |
| Finished | Apr 21 04:30:54 PM PDT 24 |
| Peak memory | 200856 kb |
| Host | smart-b93ce56e-92cc-4654-aa93-5fae98c892ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1116446680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.1116446680 |
| Directory | /workspace/23.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/23.uart_rx_start_bit_filter.394908053 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 5384450187 ps |
| CPU time | 9.38 seconds |
| Started | Apr 21 04:30:27 PM PDT 24 |
| Finished | Apr 21 04:30:36 PM PDT 24 |
| Peak memory | 196920 kb |
| Host | smart-b69a0950-d41c-4988-8e47-14c5de7d33be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=394908053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.394908053 |
| Directory | /workspace/23.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/23.uart_smoke.1503234481 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 647262249 ps |
| CPU time | 3.22 seconds |
| Started | Apr 21 04:30:19 PM PDT 24 |
| Finished | Apr 21 04:30:22 PM PDT 24 |
| Peak memory | 200720 kb |
| Host | smart-36f04781-5073-428e-aeb0-ee85026afc07 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1503234481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.1503234481 |
| Directory | /workspace/23.uart_smoke/latest |
| Test location | /workspace/coverage/default/23.uart_stress_all.1850163952 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 60313558871 ps |
| CPU time | 103.15 seconds |
| Started | Apr 21 04:30:32 PM PDT 24 |
| Finished | Apr 21 04:32:15 PM PDT 24 |
| Peak memory | 200900 kb |
| Host | smart-9f1608a9-8bcc-4a52-8cc3-4259bb56f328 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850163952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.1850163952 |
| Directory | /workspace/23.uart_stress_all/latest |
| Test location | /workspace/coverage/default/23.uart_stress_all_with_rand_reset.3430352488 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 117573038224 ps |
| CPU time | 1072.96 seconds |
| Started | Apr 21 04:30:32 PM PDT 24 |
| Finished | Apr 21 04:48:25 PM PDT 24 |
| Peak memory | 225544 kb |
| Host | smart-76b4e17b-4742-4a49-a575-3fa6048c9136 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430352488 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.3430352488 |
| Directory | /workspace/23.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/23.uart_tx_ovrd.3322827891 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 762789842 ps |
| CPU time | 1.66 seconds |
| Started | Apr 21 04:30:33 PM PDT 24 |
| Finished | Apr 21 04:30:35 PM PDT 24 |
| Peak memory | 199988 kb |
| Host | smart-c59edc00-12b2-428d-aa79-a15fee8df394 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3322827891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.3322827891 |
| Directory | /workspace/23.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/23.uart_tx_rx.785970533 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 54149189495 ps |
| CPU time | 30.24 seconds |
| Started | Apr 21 04:30:23 PM PDT 24 |
| Finished | Apr 21 04:30:53 PM PDT 24 |
| Peak memory | 200928 kb |
| Host | smart-666aa051-2111-45e2-9110-5f4fd4fb87d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=785970533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.785970533 |
| Directory | /workspace/23.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/230.uart_fifo_reset.570907442 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 28161875821 ps |
| CPU time | 24.25 seconds |
| Started | Apr 21 04:38:40 PM PDT 24 |
| Finished | Apr 21 04:39:05 PM PDT 24 |
| Peak memory | 200932 kb |
| Host | smart-d847cbdd-c987-4a83-b3bb-b9a3e098d37e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=570907442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.570907442 |
| Directory | /workspace/230.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/231.uart_fifo_reset.1562658184 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 254834022125 ps |
| CPU time | 110.92 seconds |
| Started | Apr 21 04:38:44 PM PDT 24 |
| Finished | Apr 21 04:40:35 PM PDT 24 |
| Peak memory | 200920 kb |
| Host | smart-0a269df7-fb7a-45f3-9ef2-178e1a67c172 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1562658184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1562658184 |
| Directory | /workspace/231.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/233.uart_fifo_reset.3735068735 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 80978371834 ps |
| CPU time | 70.16 seconds |
| Started | Apr 21 04:38:43 PM PDT 24 |
| Finished | Apr 21 04:39:53 PM PDT 24 |
| Peak memory | 200832 kb |
| Host | smart-1149670c-ffda-48cf-8f16-80b3c10c2029 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3735068735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.3735068735 |
| Directory | /workspace/233.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/234.uart_fifo_reset.787851519 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 62403921854 ps |
| CPU time | 44.72 seconds |
| Started | Apr 21 04:38:46 PM PDT 24 |
| Finished | Apr 21 04:39:31 PM PDT 24 |
| Peak memory | 200868 kb |
| Host | smart-9476f698-cc2b-4859-9185-d38c2a723996 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=787851519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.787851519 |
| Directory | /workspace/234.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/235.uart_fifo_reset.2893282671 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 86658586573 ps |
| CPU time | 27.33 seconds |
| Started | Apr 21 04:38:45 PM PDT 24 |
| Finished | Apr 21 04:39:13 PM PDT 24 |
| Peak memory | 200896 kb |
| Host | smart-6d9fb6c5-c984-4e17-8050-4f0d05819892 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2893282671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.2893282671 |
| Directory | /workspace/235.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/236.uart_fifo_reset.3368671326 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 52579468180 ps |
| CPU time | 21.52 seconds |
| Started | Apr 21 04:38:46 PM PDT 24 |
| Finished | Apr 21 04:39:07 PM PDT 24 |
| Peak memory | 200828 kb |
| Host | smart-796e76d4-a422-44ab-b92f-d70acfadfdc7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3368671326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.3368671326 |
| Directory | /workspace/236.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/237.uart_fifo_reset.582652402 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 142651139104 ps |
| CPU time | 121.39 seconds |
| Started | Apr 21 04:38:45 PM PDT 24 |
| Finished | Apr 21 04:40:47 PM PDT 24 |
| Peak memory | 200932 kb |
| Host | smart-e23cbdb3-c3a6-4509-b893-9e2d550a9500 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=582652402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.582652402 |
| Directory | /workspace/237.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/238.uart_fifo_reset.553357155 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 33496682763 ps |
| CPU time | 13.53 seconds |
| Started | Apr 21 04:38:47 PM PDT 24 |
| Finished | Apr 21 04:39:00 PM PDT 24 |
| Peak memory | 200900 kb |
| Host | smart-7d440440-0a3f-4efb-bf68-da9d1a41d297 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=553357155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.553357155 |
| Directory | /workspace/238.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/239.uart_fifo_reset.196701978 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 124234105902 ps |
| CPU time | 84.03 seconds |
| Started | Apr 21 04:38:49 PM PDT 24 |
| Finished | Apr 21 04:40:13 PM PDT 24 |
| Peak memory | 200828 kb |
| Host | smart-605a2e36-1f3c-48de-a447-1e157ac28888 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=196701978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.196701978 |
| Directory | /workspace/239.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/24.uart_alert_test.2501968833 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 15044378 ps |
| CPU time | 0.58 seconds |
| Started | Apr 21 04:30:44 PM PDT 24 |
| Finished | Apr 21 04:30:45 PM PDT 24 |
| Peak memory | 196232 kb |
| Host | smart-18f97be0-be58-478e-be7c-caecbfbe687a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501968833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.2501968833 |
| Directory | /workspace/24.uart_alert_test/latest |
| Test location | /workspace/coverage/default/24.uart_fifo_full.1141421122 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 10551767651 ps |
| CPU time | 15.77 seconds |
| Started | Apr 21 04:30:35 PM PDT 24 |
| Finished | Apr 21 04:30:51 PM PDT 24 |
| Peak memory | 200356 kb |
| Host | smart-9a216b72-55a1-4135-a63f-7086139c9047 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1141421122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.1141421122 |
| Directory | /workspace/24.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/24.uart_fifo_overflow.3541906926 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 17107551063 ps |
| CPU time | 30.59 seconds |
| Started | Apr 21 04:30:36 PM PDT 24 |
| Finished | Apr 21 04:31:07 PM PDT 24 |
| Peak memory | 200888 kb |
| Host | smart-c36d73a4-5d28-493c-9aaf-53e277881493 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3541906926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3541906926 |
| Directory | /workspace/24.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/24.uart_fifo_reset.2353608638 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 174138970450 ps |
| CPU time | 330.38 seconds |
| Started | Apr 21 04:30:35 PM PDT 24 |
| Finished | Apr 21 04:36:06 PM PDT 24 |
| Peak memory | 200800 kb |
| Host | smart-5b364e92-ffe5-4ac8-8e9f-2fde84718736 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2353608638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.2353608638 |
| Directory | /workspace/24.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/24.uart_intr.2514742286 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 64273907826 ps |
| CPU time | 36.53 seconds |
| Started | Apr 21 04:30:37 PM PDT 24 |
| Finished | Apr 21 04:31:14 PM PDT 24 |
| Peak memory | 200860 kb |
| Host | smart-59148ecc-91ed-49c7-868d-ad8512542b6f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514742286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.2514742286 |
| Directory | /workspace/24.uart_intr/latest |
| Test location | /workspace/coverage/default/24.uart_long_xfer_wo_dly.1051806276 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 109725958519 ps |
| CPU time | 579.78 seconds |
| Started | Apr 21 04:30:42 PM PDT 24 |
| Finished | Apr 21 04:40:23 PM PDT 24 |
| Peak memory | 200824 kb |
| Host | smart-1cf9cd34-5d38-4a7c-9f91-05783c3e6e4d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1051806276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1051806276 |
| Directory | /workspace/24.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/24.uart_loopback.888447799 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 1029897799 ps |
| CPU time | 1.56 seconds |
| Started | Apr 21 04:30:38 PM PDT 24 |
| Finished | Apr 21 04:30:40 PM PDT 24 |
| Peak memory | 196804 kb |
| Host | smart-05a51456-60d0-4c96-9c03-a53b123b113e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=888447799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.888447799 |
| Directory | /workspace/24.uart_loopback/latest |
| Test location | /workspace/coverage/default/24.uart_noise_filter.2801282093 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 19581048473 ps |
| CPU time | 18.81 seconds |
| Started | Apr 21 04:30:37 PM PDT 24 |
| Finished | Apr 21 04:30:56 PM PDT 24 |
| Peak memory | 200092 kb |
| Host | smart-d2cb9382-8886-443b-9725-e46974949ad6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2801282093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.2801282093 |
| Directory | /workspace/24.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/24.uart_perf.142799021 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 10982041894 ps |
| CPU time | 615.53 seconds |
| Started | Apr 21 04:30:38 PM PDT 24 |
| Finished | Apr 21 04:40:54 PM PDT 24 |
| Peak memory | 200920 kb |
| Host | smart-b349a9c4-288d-4caf-b119-0ba4f46b29bb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=142799021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.142799021 |
| Directory | /workspace/24.uart_perf/latest |
| Test location | /workspace/coverage/default/24.uart_rx_oversample.364290612 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 1599046047 ps |
| CPU time | 1.99 seconds |
| Started | Apr 21 04:30:38 PM PDT 24 |
| Finished | Apr 21 04:30:40 PM PDT 24 |
| Peak memory | 198868 kb |
| Host | smart-a9412b1c-eca7-4e25-9395-eed78beeaae7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=364290612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.364290612 |
| Directory | /workspace/24.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/24.uart_rx_parity_err.1568910167 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 153708622056 ps |
| CPU time | 215.2 seconds |
| Started | Apr 21 04:30:39 PM PDT 24 |
| Finished | Apr 21 04:34:14 PM PDT 24 |
| Peak memory | 200692 kb |
| Host | smart-ceb2b88b-61a5-432f-921d-f78131cdf6b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1568910167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1568910167 |
| Directory | /workspace/24.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/24.uart_rx_start_bit_filter.3689854704 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 5177873411 ps |
| CPU time | 1.18 seconds |
| Started | Apr 21 04:30:39 PM PDT 24 |
| Finished | Apr 21 04:30:40 PM PDT 24 |
| Peak memory | 197224 kb |
| Host | smart-256cf553-654f-4d99-b370-7d8ecd5f685d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3689854704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.3689854704 |
| Directory | /workspace/24.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/24.uart_smoke.3920584038 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 6183445856 ps |
| CPU time | 6.17 seconds |
| Started | Apr 21 04:30:33 PM PDT 24 |
| Finished | Apr 21 04:30:39 PM PDT 24 |
| Peak memory | 200604 kb |
| Host | smart-f3635761-3164-4edd-b7ce-ba4ec736380c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3920584038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.3920584038 |
| Directory | /workspace/24.uart_smoke/latest |
| Test location | /workspace/coverage/default/24.uart_stress_all_with_rand_reset.4178830057 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 273630797043 ps |
| CPU time | 837.22 seconds |
| Started | Apr 21 04:30:44 PM PDT 24 |
| Finished | Apr 21 04:44:41 PM PDT 24 |
| Peak memory | 214408 kb |
| Host | smart-c57553b2-d6c4-4689-9ef1-a48007e583c7 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178830057 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.4178830057 |
| Directory | /workspace/24.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/24.uart_tx_ovrd.2963377944 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 6645227201 ps |
| CPU time | 19.78 seconds |
| Started | Apr 21 04:30:39 PM PDT 24 |
| Finished | Apr 21 04:30:59 PM PDT 24 |
| Peak memory | 200852 kb |
| Host | smart-727ccef0-205e-4537-a74d-31e0680ec363 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2963377944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.2963377944 |
| Directory | /workspace/24.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/24.uart_tx_rx.3903573254 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 63272535989 ps |
| CPU time | 165.78 seconds |
| Started | Apr 21 04:30:33 PM PDT 24 |
| Finished | Apr 21 04:33:19 PM PDT 24 |
| Peak memory | 200916 kb |
| Host | smart-64089ff5-fe67-4419-aa45-da5f63e267f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3903573254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.3903573254 |
| Directory | /workspace/24.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/240.uart_fifo_reset.85928845 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 8124398927 ps |
| CPU time | 13.35 seconds |
| Started | Apr 21 04:38:48 PM PDT 24 |
| Finished | Apr 21 04:39:02 PM PDT 24 |
| Peak memory | 200880 kb |
| Host | smart-dd01398e-a706-42ea-98e4-162bb49fe5b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=85928845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.85928845 |
| Directory | /workspace/240.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/241.uart_fifo_reset.1118754222 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 19765213770 ps |
| CPU time | 29.59 seconds |
| Started | Apr 21 04:38:47 PM PDT 24 |
| Finished | Apr 21 04:39:16 PM PDT 24 |
| Peak memory | 200612 kb |
| Host | smart-be932948-ee1f-4bfa-8c0f-7395d2f95dfc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1118754222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.1118754222 |
| Directory | /workspace/241.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/242.uart_fifo_reset.3642527556 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 150440493049 ps |
| CPU time | 68.51 seconds |
| Started | Apr 21 04:38:48 PM PDT 24 |
| Finished | Apr 21 04:39:57 PM PDT 24 |
| Peak memory | 200892 kb |
| Host | smart-b783c9f4-4a1d-439a-ba09-7baee59743cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3642527556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.3642527556 |
| Directory | /workspace/242.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/243.uart_fifo_reset.1781236179 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 77468103415 ps |
| CPU time | 63.48 seconds |
| Started | Apr 21 04:38:50 PM PDT 24 |
| Finished | Apr 21 04:39:54 PM PDT 24 |
| Peak memory | 200880 kb |
| Host | smart-dd35e619-56e6-486c-ba42-da3424421ff1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1781236179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.1781236179 |
| Directory | /workspace/243.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/244.uart_fifo_reset.3744871277 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 95420646446 ps |
| CPU time | 124.9 seconds |
| Started | Apr 21 04:38:53 PM PDT 24 |
| Finished | Apr 21 04:40:58 PM PDT 24 |
| Peak memory | 200856 kb |
| Host | smart-0b3908fc-9358-45fb-929d-5b57c549740b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3744871277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.3744871277 |
| Directory | /workspace/244.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/245.uart_fifo_reset.2960226636 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 46324691449 ps |
| CPU time | 19.5 seconds |
| Started | Apr 21 04:38:56 PM PDT 24 |
| Finished | Apr 21 04:39:15 PM PDT 24 |
| Peak memory | 200940 kb |
| Host | smart-2608ad23-7592-4639-8d7d-3f66955e487a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2960226636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.2960226636 |
| Directory | /workspace/245.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/246.uart_fifo_reset.1026864360 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 24956136889 ps |
| CPU time | 28.18 seconds |
| Started | Apr 21 04:39:00 PM PDT 24 |
| Finished | Apr 21 04:39:28 PM PDT 24 |
| Peak memory | 200824 kb |
| Host | smart-3739acfe-c502-468f-a921-0976f4cb6927 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1026864360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.1026864360 |
| Directory | /workspace/246.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/247.uart_fifo_reset.1565350657 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 24991208666 ps |
| CPU time | 17.34 seconds |
| Started | Apr 21 04:39:00 PM PDT 24 |
| Finished | Apr 21 04:39:17 PM PDT 24 |
| Peak memory | 200936 kb |
| Host | smart-20746a0e-df11-472b-bf08-38fcfbe2a067 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1565350657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.1565350657 |
| Directory | /workspace/247.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/248.uart_fifo_reset.1028124164 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 21531990317 ps |
| CPU time | 36.51 seconds |
| Started | Apr 21 04:38:58 PM PDT 24 |
| Finished | Apr 21 04:39:35 PM PDT 24 |
| Peak memory | 200736 kb |
| Host | smart-77bc66ff-5f51-47f7-824d-0870ef9f36d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1028124164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.1028124164 |
| Directory | /workspace/248.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/249.uart_fifo_reset.3160083745 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 61155203309 ps |
| CPU time | 48.21 seconds |
| Started | Apr 21 04:38:59 PM PDT 24 |
| Finished | Apr 21 04:39:47 PM PDT 24 |
| Peak memory | 200892 kb |
| Host | smart-96a5f5cc-8c6a-494f-a122-0630af9a48ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3160083745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.3160083745 |
| Directory | /workspace/249.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/25.uart_alert_test.794481979 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 56233974 ps |
| CPU time | 0.58 seconds |
| Started | Apr 21 04:30:51 PM PDT 24 |
| Finished | Apr 21 04:30:52 PM PDT 24 |
| Peak memory | 196256 kb |
| Host | smart-02cdbd78-a3b7-418c-b41a-a5ce42ea92a5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794481979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.794481979 |
| Directory | /workspace/25.uart_alert_test/latest |
| Test location | /workspace/coverage/default/25.uart_fifo_full.1544158672 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 40575664412 ps |
| CPU time | 68.98 seconds |
| Started | Apr 21 04:30:42 PM PDT 24 |
| Finished | Apr 21 04:31:51 PM PDT 24 |
| Peak memory | 200836 kb |
| Host | smart-0b5974b8-5704-4cd2-be6f-7ad198b52d48 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1544158672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.1544158672 |
| Directory | /workspace/25.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/25.uart_fifo_overflow.3698001839 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 98083474835 ps |
| CPU time | 147.29 seconds |
| Started | Apr 21 04:30:43 PM PDT 24 |
| Finished | Apr 21 04:33:11 PM PDT 24 |
| Peak memory | 200812 kb |
| Host | smart-95af615c-2c62-41da-8be4-fac04caf038e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3698001839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.3698001839 |
| Directory | /workspace/25.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/25.uart_fifo_reset.588291645 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 9255057257 ps |
| CPU time | 17.41 seconds |
| Started | Apr 21 04:30:43 PM PDT 24 |
| Finished | Apr 21 04:31:01 PM PDT 24 |
| Peak memory | 200928 kb |
| Host | smart-f0f9b774-3af8-495b-908c-712bb029fad5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=588291645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.588291645 |
| Directory | /workspace/25.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/25.uart_intr.3846682991 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 13979999307 ps |
| CPU time | 12.25 seconds |
| Started | Apr 21 04:30:45 PM PDT 24 |
| Finished | Apr 21 04:30:57 PM PDT 24 |
| Peak memory | 199904 kb |
| Host | smart-288247a1-c243-4567-958e-6fe36cdacd2d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846682991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.3846682991 |
| Directory | /workspace/25.uart_intr/latest |
| Test location | /workspace/coverage/default/25.uart_long_xfer_wo_dly.3913687469 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 67366572342 ps |
| CPU time | 442.65 seconds |
| Started | Apr 21 04:30:51 PM PDT 24 |
| Finished | Apr 21 04:38:14 PM PDT 24 |
| Peak memory | 200912 kb |
| Host | smart-08c0c984-fc85-423d-b48c-f20fcac3edf4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3913687469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.3913687469 |
| Directory | /workspace/25.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/25.uart_loopback.1560756766 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 852551182 ps |
| CPU time | 1.27 seconds |
| Started | Apr 21 04:30:48 PM PDT 24 |
| Finished | Apr 21 04:30:49 PM PDT 24 |
| Peak memory | 196332 kb |
| Host | smart-409312d5-79e5-4c5d-8bc2-b2d94675c31f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1560756766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.1560756766 |
| Directory | /workspace/25.uart_loopback/latest |
| Test location | /workspace/coverage/default/25.uart_noise_filter.71593739 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 310384716410 ps |
| CPU time | 133.76 seconds |
| Started | Apr 21 04:30:46 PM PDT 24 |
| Finished | Apr 21 04:33:00 PM PDT 24 |
| Peak memory | 201340 kb |
| Host | smart-29717a66-5581-4492-a06e-887d71408bb1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=71593739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.71593739 |
| Directory | /workspace/25.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/25.uart_perf.823773178 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 24876518857 ps |
| CPU time | 1115.07 seconds |
| Started | Apr 21 04:30:48 PM PDT 24 |
| Finished | Apr 21 04:49:24 PM PDT 24 |
| Peak memory | 200980 kb |
| Host | smart-4f54ac34-ab17-4b5f-b289-be1259e0fcfd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=823773178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.823773178 |
| Directory | /workspace/25.uart_perf/latest |
| Test location | /workspace/coverage/default/25.uart_rx_oversample.2488369511 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 5808478083 ps |
| CPU time | 51.62 seconds |
| Started | Apr 21 04:30:46 PM PDT 24 |
| Finished | Apr 21 04:31:38 PM PDT 24 |
| Peak memory | 200084 kb |
| Host | smart-c3f5ab58-2b3f-4aee-a2d0-b49e6a082aed |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2488369511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.2488369511 |
| Directory | /workspace/25.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/25.uart_rx_parity_err.1336928675 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 42783656044 ps |
| CPU time | 71.41 seconds |
| Started | Apr 21 04:30:51 PM PDT 24 |
| Finished | Apr 21 04:32:02 PM PDT 24 |
| Peak memory | 200916 kb |
| Host | smart-31e61761-4425-4cec-8c18-edfa3872b919 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1336928675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.1336928675 |
| Directory | /workspace/25.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/25.uart_rx_start_bit_filter.354082385 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 3499597421 ps |
| CPU time | 1.94 seconds |
| Started | Apr 21 04:30:46 PM PDT 24 |
| Finished | Apr 21 04:30:49 PM PDT 24 |
| Peak memory | 196952 kb |
| Host | smart-2666af21-e802-4c64-92a5-410db79c955f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=354082385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.354082385 |
| Directory | /workspace/25.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/25.uart_smoke.4173052906 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 5557504586 ps |
| CPU time | 9.4 seconds |
| Started | Apr 21 04:30:43 PM PDT 24 |
| Finished | Apr 21 04:30:53 PM PDT 24 |
| Peak memory | 200144 kb |
| Host | smart-956bb327-f738-4ccb-bef8-a680a8ef559a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4173052906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.4173052906 |
| Directory | /workspace/25.uart_smoke/latest |
| Test location | /workspace/coverage/default/25.uart_stress_all.2435147151 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 237429029428 ps |
| CPU time | 647.5 seconds |
| Started | Apr 21 04:30:52 PM PDT 24 |
| Finished | Apr 21 04:41:40 PM PDT 24 |
| Peak memory | 200932 kb |
| Host | smart-dcab169c-04eb-487b-8aed-8cb10a8a1266 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435147151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.2435147151 |
| Directory | /workspace/25.uart_stress_all/latest |
| Test location | /workspace/coverage/default/25.uart_stress_all_with_rand_reset.3361086901 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 110208390794 ps |
| CPU time | 341.56 seconds |
| Started | Apr 21 04:30:50 PM PDT 24 |
| Finished | Apr 21 04:36:32 PM PDT 24 |
| Peak memory | 211764 kb |
| Host | smart-fe1aba2f-0d64-4f1d-950a-39d7f9f7af46 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361086901 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.3361086901 |
| Directory | /workspace/25.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/25.uart_tx_ovrd.3848385397 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 7563172534 ps |
| CPU time | 5.71 seconds |
| Started | Apr 21 04:30:48 PM PDT 24 |
| Finished | Apr 21 04:30:53 PM PDT 24 |
| Peak memory | 200888 kb |
| Host | smart-b9978b63-579e-44b4-924c-553d4d41b8a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3848385397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.3848385397 |
| Directory | /workspace/25.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/25.uart_tx_rx.448257597 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 131709149314 ps |
| CPU time | 217.57 seconds |
| Started | Apr 21 04:30:45 PM PDT 24 |
| Finished | Apr 21 04:34:23 PM PDT 24 |
| Peak memory | 200880 kb |
| Host | smart-6e4f3eab-b65e-4208-8a90-be7c3c771727 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=448257597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.448257597 |
| Directory | /workspace/25.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/250.uart_fifo_reset.3951004942 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 33788899991 ps |
| CPU time | 29.28 seconds |
| Started | Apr 21 04:38:59 PM PDT 24 |
| Finished | Apr 21 04:39:28 PM PDT 24 |
| Peak memory | 200940 kb |
| Host | smart-655b649f-96a5-4140-acdc-14fc8a0f87ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3951004942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.3951004942 |
| Directory | /workspace/250.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/251.uart_fifo_reset.339988747 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 18020505987 ps |
| CPU time | 16.03 seconds |
| Started | Apr 21 04:38:58 PM PDT 24 |
| Finished | Apr 21 04:39:14 PM PDT 24 |
| Peak memory | 200880 kb |
| Host | smart-c7e3d14c-7a30-448b-aca1-13d650f0aa82 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=339988747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.339988747 |
| Directory | /workspace/251.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/252.uart_fifo_reset.2000790532 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 128396094705 ps |
| CPU time | 75.65 seconds |
| Started | Apr 21 04:38:59 PM PDT 24 |
| Finished | Apr 21 04:40:15 PM PDT 24 |
| Peak memory | 200904 kb |
| Host | smart-371ea3bd-4877-44a6-a5f6-66519aab0eb6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2000790532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.2000790532 |
| Directory | /workspace/252.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/253.uart_fifo_reset.3272684428 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 63506296580 ps |
| CPU time | 174.6 seconds |
| Started | Apr 21 04:39:04 PM PDT 24 |
| Finished | Apr 21 04:41:59 PM PDT 24 |
| Peak memory | 200920 kb |
| Host | smart-83e91dcc-33e2-4339-923b-d2381db04c8a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3272684428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.3272684428 |
| Directory | /workspace/253.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/254.uart_fifo_reset.2432873914 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 22256919577 ps |
| CPU time | 32.84 seconds |
| Started | Apr 21 04:39:03 PM PDT 24 |
| Finished | Apr 21 04:39:36 PM PDT 24 |
| Peak memory | 200876 kb |
| Host | smart-baf77925-fcb6-48e9-a717-78cc63ad5d4f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2432873914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.2432873914 |
| Directory | /workspace/254.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/255.uart_fifo_reset.4235703187 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 20673740631 ps |
| CPU time | 41.83 seconds |
| Started | Apr 21 04:39:04 PM PDT 24 |
| Finished | Apr 21 04:39:46 PM PDT 24 |
| Peak memory | 200904 kb |
| Host | smart-d91f0a45-b18d-4223-81fc-4bd421934859 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4235703187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.4235703187 |
| Directory | /workspace/255.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/256.uart_fifo_reset.3864716801 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 33597352602 ps |
| CPU time | 11.48 seconds |
| Started | Apr 21 04:39:07 PM PDT 24 |
| Finished | Apr 21 04:39:19 PM PDT 24 |
| Peak memory | 200704 kb |
| Host | smart-2c3a64ba-c0ff-4be1-8deb-f3d109b03bd4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3864716801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.3864716801 |
| Directory | /workspace/256.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/259.uart_fifo_reset.2393074885 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 37043054155 ps |
| CPU time | 33.72 seconds |
| Started | Apr 21 04:39:06 PM PDT 24 |
| Finished | Apr 21 04:39:39 PM PDT 24 |
| Peak memory | 200936 kb |
| Host | smart-2e487302-31b6-48a5-b3ea-44cdb5ad0415 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2393074885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.2393074885 |
| Directory | /workspace/259.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/26.uart_alert_test.389237920 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 41711840 ps |
| CPU time | 0.58 seconds |
| Started | Apr 21 04:31:02 PM PDT 24 |
| Finished | Apr 21 04:31:03 PM PDT 24 |
| Peak memory | 196240 kb |
| Host | smart-ecb7943b-ecf8-47fa-9b36-811febefae67 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389237920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.389237920 |
| Directory | /workspace/26.uart_alert_test/latest |
| Test location | /workspace/coverage/default/26.uart_fifo_full.1000692257 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 85412539576 ps |
| CPU time | 162.13 seconds |
| Started | Apr 21 04:30:53 PM PDT 24 |
| Finished | Apr 21 04:33:35 PM PDT 24 |
| Peak memory | 200824 kb |
| Host | smart-6472ae91-46af-475f-b67d-86e559ab1a89 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1000692257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1000692257 |
| Directory | /workspace/26.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/26.uart_fifo_overflow.2987900144 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 21427104710 ps |
| CPU time | 28.29 seconds |
| Started | Apr 21 04:30:54 PM PDT 24 |
| Finished | Apr 21 04:31:22 PM PDT 24 |
| Peak memory | 200892 kb |
| Host | smart-0c470487-906c-4e13-b9c5-9c7baab8e096 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2987900144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.2987900144 |
| Directory | /workspace/26.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/26.uart_fifo_reset.2622469180 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 259945020235 ps |
| CPU time | 480.85 seconds |
| Started | Apr 21 04:30:53 PM PDT 24 |
| Finished | Apr 21 04:38:55 PM PDT 24 |
| Peak memory | 200912 kb |
| Host | smart-5e12cf2d-9960-43a9-84e1-bc7d22bace18 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2622469180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.2622469180 |
| Directory | /workspace/26.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/26.uart_intr.2627208623 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 35445166648 ps |
| CPU time | 29.4 seconds |
| Started | Apr 21 04:30:53 PM PDT 24 |
| Finished | Apr 21 04:31:23 PM PDT 24 |
| Peak memory | 199520 kb |
| Host | smart-fa318a14-aab1-4ec4-8d4b-9e12822250cc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627208623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.2627208623 |
| Directory | /workspace/26.uart_intr/latest |
| Test location | /workspace/coverage/default/26.uart_long_xfer_wo_dly.3531870196 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 67653623349 ps |
| CPU time | 541.37 seconds |
| Started | Apr 21 04:31:00 PM PDT 24 |
| Finished | Apr 21 04:40:01 PM PDT 24 |
| Peak memory | 200868 kb |
| Host | smart-373cc8ac-364b-4dc0-b06b-5578b2d24c1e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3531870196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.3531870196 |
| Directory | /workspace/26.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/26.uart_loopback.3541971229 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 2276421899 ps |
| CPU time | 1.12 seconds |
| Started | Apr 21 04:30:59 PM PDT 24 |
| Finished | Apr 21 04:31:01 PM PDT 24 |
| Peak memory | 196368 kb |
| Host | smart-6b06eae7-4a73-452f-b248-c36caff14054 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3541971229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.3541971229 |
| Directory | /workspace/26.uart_loopback/latest |
| Test location | /workspace/coverage/default/26.uart_noise_filter.157799523 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 71555332492 ps |
| CPU time | 29.87 seconds |
| Started | Apr 21 04:30:53 PM PDT 24 |
| Finished | Apr 21 04:31:23 PM PDT 24 |
| Peak memory | 199412 kb |
| Host | smart-3339d7d3-1a3f-4a49-a0f3-57caed7ceb61 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=157799523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.157799523 |
| Directory | /workspace/26.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/26.uart_perf.405267922 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 11618103865 ps |
| CPU time | 179.66 seconds |
| Started | Apr 21 04:30:59 PM PDT 24 |
| Finished | Apr 21 04:33:59 PM PDT 24 |
| Peak memory | 200864 kb |
| Host | smart-12f2f132-fe67-4c56-9937-65b8651da506 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=405267922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.405267922 |
| Directory | /workspace/26.uart_perf/latest |
| Test location | /workspace/coverage/default/26.uart_rx_oversample.2734949318 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 4635611181 ps |
| CPU time | 21.82 seconds |
| Started | Apr 21 04:30:53 PM PDT 24 |
| Finished | Apr 21 04:31:15 PM PDT 24 |
| Peak memory | 199816 kb |
| Host | smart-1a34d299-4310-4c79-84d0-c54bf81ede91 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2734949318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.2734949318 |
| Directory | /workspace/26.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/26.uart_rx_parity_err.2582419592 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 12587056112 ps |
| CPU time | 9.19 seconds |
| Started | Apr 21 04:30:56 PM PDT 24 |
| Finished | Apr 21 04:31:06 PM PDT 24 |
| Peak memory | 199552 kb |
| Host | smart-7a079c91-3cee-4964-84a5-cbfedd97a149 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2582419592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.2582419592 |
| Directory | /workspace/26.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/26.uart_rx_start_bit_filter.2144754044 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 4948440539 ps |
| CPU time | 8.96 seconds |
| Started | Apr 21 04:30:56 PM PDT 24 |
| Finished | Apr 21 04:31:05 PM PDT 24 |
| Peak memory | 196960 kb |
| Host | smart-6ba93b36-3de8-40f9-9b7f-dfbe09f00970 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2144754044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.2144754044 |
| Directory | /workspace/26.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/26.uart_smoke.1582639956 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 694371128 ps |
| CPU time | 3.1 seconds |
| Started | Apr 21 04:30:50 PM PDT 24 |
| Finished | Apr 21 04:30:54 PM PDT 24 |
| Peak memory | 199704 kb |
| Host | smart-d79eac43-4bdd-4504-84c3-b258207232d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1582639956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.1582639956 |
| Directory | /workspace/26.uart_smoke/latest |
| Test location | /workspace/coverage/default/26.uart_stress_all.1153904524 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 365548866721 ps |
| CPU time | 230.78 seconds |
| Started | Apr 21 04:31:02 PM PDT 24 |
| Finished | Apr 21 04:34:53 PM PDT 24 |
| Peak memory | 200848 kb |
| Host | smart-dc6e54e2-1f10-47d8-b3b3-18e9e90e1ebb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153904524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.1153904524 |
| Directory | /workspace/26.uart_stress_all/latest |
| Test location | /workspace/coverage/default/26.uart_stress_all_with_rand_reset.3596547629 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 50245851849 ps |
| CPU time | 426.83 seconds |
| Started | Apr 21 04:31:01 PM PDT 24 |
| Finished | Apr 21 04:38:08 PM PDT 24 |
| Peak memory | 214576 kb |
| Host | smart-57bbe7fb-17da-42ae-ab48-941cded67ddb |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596547629 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.3596547629 |
| Directory | /workspace/26.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/26.uart_tx_ovrd.2233527544 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 10220663750 ps |
| CPU time | 10.5 seconds |
| Started | Apr 21 04:30:57 PM PDT 24 |
| Finished | Apr 21 04:31:07 PM PDT 24 |
| Peak memory | 200652 kb |
| Host | smart-f8e14f98-8bad-40b9-9bee-a9d0e280ff0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2233527544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2233527544 |
| Directory | /workspace/26.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/26.uart_tx_rx.2489422062 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 3107717842 ps |
| CPU time | 6.02 seconds |
| Started | Apr 21 04:30:53 PM PDT 24 |
| Finished | Apr 21 04:30:59 PM PDT 24 |
| Peak memory | 200832 kb |
| Host | smart-eb836dcc-1a78-412f-9117-3bdfb5ea3fcb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2489422062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.2489422062 |
| Directory | /workspace/26.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/260.uart_fifo_reset.4230135428 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 21893929793 ps |
| CPU time | 32.51 seconds |
| Started | Apr 21 04:39:07 PM PDT 24 |
| Finished | Apr 21 04:39:40 PM PDT 24 |
| Peak memory | 201084 kb |
| Host | smart-986d15b2-9c22-4484-9701-bd011af62422 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4230135428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.4230135428 |
| Directory | /workspace/260.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/261.uart_fifo_reset.771974230 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 219655614460 ps |
| CPU time | 150.75 seconds |
| Started | Apr 21 04:39:10 PM PDT 24 |
| Finished | Apr 21 04:41:41 PM PDT 24 |
| Peak memory | 200924 kb |
| Host | smart-ab9a9f78-12e1-4318-b6b4-7e3c40f5e184 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=771974230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.771974230 |
| Directory | /workspace/261.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/262.uart_fifo_reset.1583899602 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 11449618968 ps |
| CPU time | 17.57 seconds |
| Started | Apr 21 04:39:09 PM PDT 24 |
| Finished | Apr 21 04:39:27 PM PDT 24 |
| Peak memory | 200440 kb |
| Host | smart-18238948-85d0-43af-adbb-d4ea792eb9a6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1583899602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.1583899602 |
| Directory | /workspace/262.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/263.uart_fifo_reset.2340986947 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 63418813900 ps |
| CPU time | 51.13 seconds |
| Started | Apr 21 04:39:10 PM PDT 24 |
| Finished | Apr 21 04:40:02 PM PDT 24 |
| Peak memory | 200864 kb |
| Host | smart-7750e162-a338-42df-86df-98bfb7100968 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2340986947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.2340986947 |
| Directory | /workspace/263.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/264.uart_fifo_reset.3849859506 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 10321755601 ps |
| CPU time | 17.31 seconds |
| Started | Apr 21 04:39:07 PM PDT 24 |
| Finished | Apr 21 04:39:25 PM PDT 24 |
| Peak memory | 200128 kb |
| Host | smart-209c24d9-de95-4f95-a60d-af0269b96259 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3849859506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.3849859506 |
| Directory | /workspace/264.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/265.uart_fifo_reset.28795163 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 121415095737 ps |
| CPU time | 56.25 seconds |
| Started | Apr 21 04:39:08 PM PDT 24 |
| Finished | Apr 21 04:40:04 PM PDT 24 |
| Peak memory | 200928 kb |
| Host | smart-4cf947ec-58d5-4991-af09-68d587372215 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=28795163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.28795163 |
| Directory | /workspace/265.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/266.uart_fifo_reset.2572105921 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 166912026810 ps |
| CPU time | 66.88 seconds |
| Started | Apr 21 04:39:09 PM PDT 24 |
| Finished | Apr 21 04:40:16 PM PDT 24 |
| Peak memory | 200828 kb |
| Host | smart-58f25a54-e9be-4eee-a23a-40b5ebf72815 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2572105921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.2572105921 |
| Directory | /workspace/266.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/268.uart_fifo_reset.4073877980 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 50098307942 ps |
| CPU time | 66.4 seconds |
| Started | Apr 21 04:39:11 PM PDT 24 |
| Finished | Apr 21 04:40:18 PM PDT 24 |
| Peak memory | 200912 kb |
| Host | smart-86d52f5e-c68f-42ec-abe8-b5f1714dccd7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4073877980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.4073877980 |
| Directory | /workspace/268.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/269.uart_fifo_reset.2468562805 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 80760045340 ps |
| CPU time | 40.4 seconds |
| Started | Apr 21 04:39:14 PM PDT 24 |
| Finished | Apr 21 04:39:54 PM PDT 24 |
| Peak memory | 200936 kb |
| Host | smart-61cac362-fba5-4397-97ca-537cb20b5178 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2468562805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2468562805 |
| Directory | /workspace/269.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/27.uart_alert_test.3706960277 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 21005317 ps |
| CPU time | 0.57 seconds |
| Started | Apr 21 04:31:13 PM PDT 24 |
| Finished | Apr 21 04:31:14 PM PDT 24 |
| Peak memory | 196236 kb |
| Host | smart-e0bba8f9-7fda-4c28-9160-d29f1859a2f5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706960277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.3706960277 |
| Directory | /workspace/27.uart_alert_test/latest |
| Test location | /workspace/coverage/default/27.uart_fifo_full.2878573436 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 159159317507 ps |
| CPU time | 121.25 seconds |
| Started | Apr 21 04:31:11 PM PDT 24 |
| Finished | Apr 21 04:33:12 PM PDT 24 |
| Peak memory | 200876 kb |
| Host | smart-9da84f0a-e8dc-4cad-b2de-c7c389e1940b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2878573436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.2878573436 |
| Directory | /workspace/27.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/27.uart_fifo_overflow.3707455420 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 162393422935 ps |
| CPU time | 40.09 seconds |
| Started | Apr 21 04:31:05 PM PDT 24 |
| Finished | Apr 21 04:31:45 PM PDT 24 |
| Peak memory | 200820 kb |
| Host | smart-9538488a-9eaa-4ce0-b38a-6178b01972a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3707455420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.3707455420 |
| Directory | /workspace/27.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/27.uart_intr.505638754 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 25514195845 ps |
| CPU time | 12.34 seconds |
| Started | Apr 21 04:31:05 PM PDT 24 |
| Finished | Apr 21 04:31:18 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-d2ad3e99-f3aa-4f8e-ab53-81951224279d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505638754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.505638754 |
| Directory | /workspace/27.uart_intr/latest |
| Test location | /workspace/coverage/default/27.uart_long_xfer_wo_dly.2123987425 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 192261506536 ps |
| CPU time | 250.82 seconds |
| Started | Apr 21 04:31:11 PM PDT 24 |
| Finished | Apr 21 04:35:22 PM PDT 24 |
| Peak memory | 200888 kb |
| Host | smart-8a0d7ff1-4209-4f14-95c8-24129f8ba42e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2123987425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2123987425 |
| Directory | /workspace/27.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/27.uart_loopback.707665288 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 3720569915 ps |
| CPU time | 7.25 seconds |
| Started | Apr 21 04:31:06 PM PDT 24 |
| Finished | Apr 21 04:31:13 PM PDT 24 |
| Peak memory | 199248 kb |
| Host | smart-401ed79e-494b-4273-bb1f-a4194a2d69cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=707665288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.707665288 |
| Directory | /workspace/27.uart_loopback/latest |
| Test location | /workspace/coverage/default/27.uart_noise_filter.3936785436 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 272200803122 ps |
| CPU time | 130.91 seconds |
| Started | Apr 21 04:31:07 PM PDT 24 |
| Finished | Apr 21 04:33:18 PM PDT 24 |
| Peak memory | 200792 kb |
| Host | smart-420e7238-1741-408e-8e6b-f501e4947d8b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3936785436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.3936785436 |
| Directory | /workspace/27.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/27.uart_perf.160425857 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 13236880962 ps |
| CPU time | 808.77 seconds |
| Started | Apr 21 04:31:10 PM PDT 24 |
| Finished | Apr 21 04:44:39 PM PDT 24 |
| Peak memory | 200884 kb |
| Host | smart-28076758-f7be-4a1a-a1dc-c9fa390115dd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=160425857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.160425857 |
| Directory | /workspace/27.uart_perf/latest |
| Test location | /workspace/coverage/default/27.uart_rx_oversample.3276571027 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 6008920835 ps |
| CPU time | 49.81 seconds |
| Started | Apr 21 04:31:04 PM PDT 24 |
| Finished | Apr 21 04:31:54 PM PDT 24 |
| Peak memory | 198960 kb |
| Host | smart-8aa3ddd9-7fce-43ad-9a5c-44d544f8902a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3276571027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.3276571027 |
| Directory | /workspace/27.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/27.uart_rx_parity_err.3125119970 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 135605018423 ps |
| CPU time | 114.26 seconds |
| Started | Apr 21 04:31:06 PM PDT 24 |
| Finished | Apr 21 04:33:01 PM PDT 24 |
| Peak memory | 200844 kb |
| Host | smart-2c3995b5-1551-4fad-be8a-2a325c791a5a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3125119970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.3125119970 |
| Directory | /workspace/27.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/27.uart_rx_start_bit_filter.1575731473 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 4998518429 ps |
| CPU time | 1.23 seconds |
| Started | Apr 21 04:31:06 PM PDT 24 |
| Finished | Apr 21 04:31:08 PM PDT 24 |
| Peak memory | 196932 kb |
| Host | smart-94a33891-97b8-4adb-a3f3-667dc04a545e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1575731473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.1575731473 |
| Directory | /workspace/27.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/27.uart_smoke.517987922 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 848688263 ps |
| CPU time | 1.24 seconds |
| Started | Apr 21 04:31:02 PM PDT 24 |
| Finished | Apr 21 04:31:03 PM PDT 24 |
| Peak memory | 199560 kb |
| Host | smart-a6c077b9-bae8-4cba-ad14-4272fe37319c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=517987922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.517987922 |
| Directory | /workspace/27.uart_smoke/latest |
| Test location | /workspace/coverage/default/27.uart_stress_all.2484896092 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 297768313397 ps |
| CPU time | 167.44 seconds |
| Started | Apr 21 04:31:08 PM PDT 24 |
| Finished | Apr 21 04:33:56 PM PDT 24 |
| Peak memory | 200872 kb |
| Host | smart-87a9aaa6-4b38-4be2-a7d2-36a7094cbae0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484896092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.2484896092 |
| Directory | /workspace/27.uart_stress_all/latest |
| Test location | /workspace/coverage/default/27.uart_stress_all_with_rand_reset.1331317090 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 116750574242 ps |
| CPU time | 942.06 seconds |
| Started | Apr 21 04:31:09 PM PDT 24 |
| Finished | Apr 21 04:46:51 PM PDT 24 |
| Peak memory | 232436 kb |
| Host | smart-629fc9c9-b9d9-4834-8769-79ab58d36361 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331317090 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.1331317090 |
| Directory | /workspace/27.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/27.uart_tx_ovrd.3717316092 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 730738544 ps |
| CPU time | 1.34 seconds |
| Started | Apr 21 04:31:10 PM PDT 24 |
| Finished | Apr 21 04:31:12 PM PDT 24 |
| Peak memory | 197952 kb |
| Host | smart-5c70d9cd-5c67-4eeb-a748-d42b848f3cbd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3717316092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.3717316092 |
| Directory | /workspace/27.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/27.uart_tx_rx.3192987568 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 15229849045 ps |
| CPU time | 28.35 seconds |
| Started | Apr 21 04:31:05 PM PDT 24 |
| Finished | Apr 21 04:31:33 PM PDT 24 |
| Peak memory | 200904 kb |
| Host | smart-7459818d-0e20-4a2a-ba93-ed20626b132f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3192987568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.3192987568 |
| Directory | /workspace/27.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/270.uart_fifo_reset.1767864690 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 63617582140 ps |
| CPU time | 33.81 seconds |
| Started | Apr 21 04:39:12 PM PDT 24 |
| Finished | Apr 21 04:39:46 PM PDT 24 |
| Peak memory | 200888 kb |
| Host | smart-6ef0effe-407e-49cc-9e88-0988e5d23c68 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1767864690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.1767864690 |
| Directory | /workspace/270.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/271.uart_fifo_reset.3551944505 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 117177200209 ps |
| CPU time | 240.73 seconds |
| Started | Apr 21 04:39:10 PM PDT 24 |
| Finished | Apr 21 04:43:11 PM PDT 24 |
| Peak memory | 200888 kb |
| Host | smart-6f475fd3-b52b-4afc-baae-fa3fb98784a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3551944505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.3551944505 |
| Directory | /workspace/271.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/272.uart_fifo_reset.2949002372 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 20769391069 ps |
| CPU time | 32.02 seconds |
| Started | Apr 21 04:39:12 PM PDT 24 |
| Finished | Apr 21 04:39:44 PM PDT 24 |
| Peak memory | 200940 kb |
| Host | smart-268b1ca6-0adf-4e99-9763-5c8e61a81131 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2949002372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.2949002372 |
| Directory | /workspace/272.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/273.uart_fifo_reset.38341152 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 82394811115 ps |
| CPU time | 41.23 seconds |
| Started | Apr 21 04:39:15 PM PDT 24 |
| Finished | Apr 21 04:39:56 PM PDT 24 |
| Peak memory | 200916 kb |
| Host | smart-273c1d89-d4e2-4b7c-9c85-a5e25e28b6b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=38341152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.38341152 |
| Directory | /workspace/273.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/274.uart_fifo_reset.3724492626 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 79441002906 ps |
| CPU time | 118.98 seconds |
| Started | Apr 21 04:39:14 PM PDT 24 |
| Finished | Apr 21 04:41:13 PM PDT 24 |
| Peak memory | 200932 kb |
| Host | smart-9fff628c-b83e-4a5d-a778-468cfdc9633d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3724492626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.3724492626 |
| Directory | /workspace/274.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/275.uart_fifo_reset.3684912964 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 80054319593 ps |
| CPU time | 16.82 seconds |
| Started | Apr 21 04:39:15 PM PDT 24 |
| Finished | Apr 21 04:39:32 PM PDT 24 |
| Peak memory | 200672 kb |
| Host | smart-86869087-0be1-49d1-be91-14a2317092a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3684912964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.3684912964 |
| Directory | /workspace/275.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/276.uart_fifo_reset.888800491 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 75652832369 ps |
| CPU time | 52.1 seconds |
| Started | Apr 21 04:39:16 PM PDT 24 |
| Finished | Apr 21 04:40:08 PM PDT 24 |
| Peak memory | 200884 kb |
| Host | smart-9dcb63d8-37de-4cce-8428-30d52a926998 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=888800491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.888800491 |
| Directory | /workspace/276.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/277.uart_fifo_reset.4157916365 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 29782238327 ps |
| CPU time | 25.27 seconds |
| Started | Apr 21 04:39:14 PM PDT 24 |
| Finished | Apr 21 04:39:40 PM PDT 24 |
| Peak memory | 200872 kb |
| Host | smart-9b614f01-602b-4669-8b6b-456af8aab9c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4157916365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.4157916365 |
| Directory | /workspace/277.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/278.uart_fifo_reset.821563317 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 117143267780 ps |
| CPU time | 184.31 seconds |
| Started | Apr 21 04:39:13 PM PDT 24 |
| Finished | Apr 21 04:42:18 PM PDT 24 |
| Peak memory | 200860 kb |
| Host | smart-e595d36b-7c62-45dd-b633-4558ce8d5f02 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=821563317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.821563317 |
| Directory | /workspace/278.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/279.uart_fifo_reset.386610067 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 11966628603 ps |
| CPU time | 11.32 seconds |
| Started | Apr 21 04:39:16 PM PDT 24 |
| Finished | Apr 21 04:39:28 PM PDT 24 |
| Peak memory | 200556 kb |
| Host | smart-98179907-fc05-44fd-b3b3-4e9a14d82059 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=386610067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.386610067 |
| Directory | /workspace/279.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/28.uart_alert_test.1507959046 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 40476366 ps |
| CPU time | 0.59 seconds |
| Started | Apr 21 04:31:25 PM PDT 24 |
| Finished | Apr 21 04:31:26 PM PDT 24 |
| Peak memory | 196232 kb |
| Host | smart-137332d8-ea69-4399-bfe8-2f7a33499ecc |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507959046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.1507959046 |
| Directory | /workspace/28.uart_alert_test/latest |
| Test location | /workspace/coverage/default/28.uart_fifo_full.645223039 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 41352119554 ps |
| CPU time | 32.81 seconds |
| Started | Apr 21 04:31:15 PM PDT 24 |
| Finished | Apr 21 04:31:48 PM PDT 24 |
| Peak memory | 200952 kb |
| Host | smart-73be50ba-a7a2-4381-ba07-26ea4154509c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=645223039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.645223039 |
| Directory | /workspace/28.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/28.uart_fifo_overflow.882510659 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 93217285827 ps |
| CPU time | 34.57 seconds |
| Started | Apr 21 04:31:15 PM PDT 24 |
| Finished | Apr 21 04:31:49 PM PDT 24 |
| Peak memory | 200872 kb |
| Host | smart-e4854685-29e6-4aac-9b1a-27c9a9b4c3b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=882510659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.882510659 |
| Directory | /workspace/28.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/28.uart_fifo_reset.2023584663 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 213548812107 ps |
| CPU time | 94.04 seconds |
| Started | Apr 21 04:31:16 PM PDT 24 |
| Finished | Apr 21 04:32:50 PM PDT 24 |
| Peak memory | 200920 kb |
| Host | smart-602fd946-5c6c-461f-8d70-803a7b95ff37 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2023584663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.2023584663 |
| Directory | /workspace/28.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/28.uart_intr.3903167599 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 52175880914 ps |
| CPU time | 87.65 seconds |
| Started | Apr 21 04:31:21 PM PDT 24 |
| Finished | Apr 21 04:32:49 PM PDT 24 |
| Peak memory | 200824 kb |
| Host | smart-234b5fe7-79b1-43bf-bed9-24cda7cc3129 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903167599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.3903167599 |
| Directory | /workspace/28.uart_intr/latest |
| Test location | /workspace/coverage/default/28.uart_long_xfer_wo_dly.2369005834 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 125902664229 ps |
| CPU time | 1587.8 seconds |
| Started | Apr 21 04:31:24 PM PDT 24 |
| Finished | Apr 21 04:57:52 PM PDT 24 |
| Peak memory | 200904 kb |
| Host | smart-c9e7ff18-1d1f-4038-8e88-dd8375ee623f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2369005834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2369005834 |
| Directory | /workspace/28.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/28.uart_loopback.1055483163 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 2322326805 ps |
| CPU time | 4.5 seconds |
| Started | Apr 21 04:31:23 PM PDT 24 |
| Finished | Apr 21 04:31:28 PM PDT 24 |
| Peak memory | 198356 kb |
| Host | smart-bd99771d-67dd-49e8-8450-9dce24493285 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1055483163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.1055483163 |
| Directory | /workspace/28.uart_loopback/latest |
| Test location | /workspace/coverage/default/28.uart_noise_filter.1775952384 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 95682796543 ps |
| CPU time | 47.87 seconds |
| Started | Apr 21 04:31:23 PM PDT 24 |
| Finished | Apr 21 04:32:11 PM PDT 24 |
| Peak memory | 201048 kb |
| Host | smart-460aa996-a608-48b4-9d89-3a6998c87ba4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1775952384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.1775952384 |
| Directory | /workspace/28.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/28.uart_perf.462368522 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 7589360806 ps |
| CPU time | 105.05 seconds |
| Started | Apr 21 04:31:22 PM PDT 24 |
| Finished | Apr 21 04:33:08 PM PDT 24 |
| Peak memory | 200908 kb |
| Host | smart-c7bca53d-4fbf-4b91-bcef-6ac257fb2b38 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=462368522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.462368522 |
| Directory | /workspace/28.uart_perf/latest |
| Test location | /workspace/coverage/default/28.uart_rx_oversample.3847116065 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 4035023891 ps |
| CPU time | 9.23 seconds |
| Started | Apr 21 04:31:18 PM PDT 24 |
| Finished | Apr 21 04:31:27 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-dc20af7c-5713-4cee-9922-cbb4fbe70cd7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3847116065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.3847116065 |
| Directory | /workspace/28.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/28.uart_rx_parity_err.2252074867 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 96650766128 ps |
| CPU time | 253.17 seconds |
| Started | Apr 21 04:31:23 PM PDT 24 |
| Finished | Apr 21 04:35:37 PM PDT 24 |
| Peak memory | 200888 kb |
| Host | smart-52a746f0-05c3-4240-8c7f-fe419942258d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2252074867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.2252074867 |
| Directory | /workspace/28.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/28.uart_rx_start_bit_filter.4162521039 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 5608691113 ps |
| CPU time | 10.22 seconds |
| Started | Apr 21 04:31:26 PM PDT 24 |
| Finished | Apr 21 04:31:37 PM PDT 24 |
| Peak memory | 196888 kb |
| Host | smart-799c9489-0c3e-4d8a-85f7-5d3f1efc4134 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4162521039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.4162521039 |
| Directory | /workspace/28.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/28.uart_smoke.179459568 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 681145810 ps |
| CPU time | 2.18 seconds |
| Started | Apr 21 04:31:12 PM PDT 24 |
| Finished | Apr 21 04:31:15 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-b8006441-9ea5-4bb1-9fe0-6207b7b22b7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=179459568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.179459568 |
| Directory | /workspace/28.uart_smoke/latest |
| Test location | /workspace/coverage/default/28.uart_stress_all.1437199187 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 116700544220 ps |
| CPU time | 95.71 seconds |
| Started | Apr 21 04:31:27 PM PDT 24 |
| Finished | Apr 21 04:33:03 PM PDT 24 |
| Peak memory | 200824 kb |
| Host | smart-bd2dea4a-d50b-4f51-af98-c546b12fc917 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437199187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.1437199187 |
| Directory | /workspace/28.uart_stress_all/latest |
| Test location | /workspace/coverage/default/28.uart_stress_all_with_rand_reset.3808106167 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 354658291845 ps |
| CPU time | 1153.03 seconds |
| Started | Apr 21 04:31:24 PM PDT 24 |
| Finished | Apr 21 04:50:37 PM PDT 24 |
| Peak memory | 227152 kb |
| Host | smart-89251ffd-1f5b-4e30-a996-1f0d6dba3633 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808106167 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.3808106167 |
| Directory | /workspace/28.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/28.uart_tx_ovrd.4017559176 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 747231239 ps |
| CPU time | 2.2 seconds |
| Started | Apr 21 04:31:24 PM PDT 24 |
| Finished | Apr 21 04:31:26 PM PDT 24 |
| Peak memory | 199720 kb |
| Host | smart-41678e0e-e0d6-4ac1-be64-a2fef06832dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4017559176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.4017559176 |
| Directory | /workspace/28.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/28.uart_tx_rx.1579380338 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 98290655608 ps |
| CPU time | 46.18 seconds |
| Started | Apr 21 04:31:15 PM PDT 24 |
| Finished | Apr 21 04:32:01 PM PDT 24 |
| Peak memory | 200916 kb |
| Host | smart-c82d2d03-bfd5-49b4-afc1-3b61fd08a91b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1579380338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.1579380338 |
| Directory | /workspace/28.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/280.uart_fifo_reset.16477021 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 47525265063 ps |
| CPU time | 20.93 seconds |
| Started | Apr 21 04:39:18 PM PDT 24 |
| Finished | Apr 21 04:39:40 PM PDT 24 |
| Peak memory | 200844 kb |
| Host | smart-a32a5222-2d3f-43b7-b53b-3186afd93a10 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=16477021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.16477021 |
| Directory | /workspace/280.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/281.uart_fifo_reset.411941175 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 107631717145 ps |
| CPU time | 177.89 seconds |
| Started | Apr 21 04:39:17 PM PDT 24 |
| Finished | Apr 21 04:42:15 PM PDT 24 |
| Peak memory | 200892 kb |
| Host | smart-371af9d8-28ee-4c89-9800-0b58d0654568 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=411941175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.411941175 |
| Directory | /workspace/281.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/282.uart_fifo_reset.3582113462 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 22910839575 ps |
| CPU time | 42.94 seconds |
| Started | Apr 21 04:39:17 PM PDT 24 |
| Finished | Apr 21 04:40:00 PM PDT 24 |
| Peak memory | 200824 kb |
| Host | smart-f4145e22-a5e5-403f-b10b-a434e7022883 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3582113462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.3582113462 |
| Directory | /workspace/282.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/283.uart_fifo_reset.2920166523 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 152873270430 ps |
| CPU time | 38.75 seconds |
| Started | Apr 21 04:39:19 PM PDT 24 |
| Finished | Apr 21 04:39:58 PM PDT 24 |
| Peak memory | 200924 kb |
| Host | smart-999e9172-1617-4a6f-8879-3c50fcde5d6c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2920166523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.2920166523 |
| Directory | /workspace/283.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/284.uart_fifo_reset.966123796 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 66638697928 ps |
| CPU time | 109.61 seconds |
| Started | Apr 21 04:39:21 PM PDT 24 |
| Finished | Apr 21 04:41:10 PM PDT 24 |
| Peak memory | 200904 kb |
| Host | smart-4a01da08-893f-46e9-a883-74a1efc95eb8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=966123796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.966123796 |
| Directory | /workspace/284.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/285.uart_fifo_reset.487885976 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 126858399685 ps |
| CPU time | 102.5 seconds |
| Started | Apr 21 04:39:19 PM PDT 24 |
| Finished | Apr 21 04:41:02 PM PDT 24 |
| Peak memory | 200860 kb |
| Host | smart-aecec6f0-164a-4ee3-b006-f4bceb7c8f24 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=487885976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.487885976 |
| Directory | /workspace/285.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/286.uart_fifo_reset.2999633829 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 54077599264 ps |
| CPU time | 232.04 seconds |
| Started | Apr 21 04:39:23 PM PDT 24 |
| Finished | Apr 21 04:43:15 PM PDT 24 |
| Peak memory | 200848 kb |
| Host | smart-a1d9a146-cbe4-4ebc-95bc-bd0889b32a43 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2999633829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.2999633829 |
| Directory | /workspace/286.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/288.uart_fifo_reset.3123717533 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 11408285485 ps |
| CPU time | 10.05 seconds |
| Started | Apr 21 04:39:25 PM PDT 24 |
| Finished | Apr 21 04:39:35 PM PDT 24 |
| Peak memory | 200600 kb |
| Host | smart-292622c0-876a-4e83-beff-12ec009de909 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3123717533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.3123717533 |
| Directory | /workspace/288.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/289.uart_fifo_reset.2223777120 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 17442005698 ps |
| CPU time | 15.5 seconds |
| Started | Apr 21 04:39:25 PM PDT 24 |
| Finished | Apr 21 04:39:40 PM PDT 24 |
| Peak memory | 200932 kb |
| Host | smart-6a881a3e-8cd2-4d34-8d0a-b8180cefe23e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2223777120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.2223777120 |
| Directory | /workspace/289.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/29.uart_alert_test.2503125330 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 43990799 ps |
| CPU time | 0.56 seconds |
| Started | Apr 21 04:31:41 PM PDT 24 |
| Finished | Apr 21 04:31:42 PM PDT 24 |
| Peak memory | 196244 kb |
| Host | smart-2decb0be-88ac-448c-852f-6208516ede10 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503125330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2503125330 |
| Directory | /workspace/29.uart_alert_test/latest |
| Test location | /workspace/coverage/default/29.uart_fifo_full.2488510331 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 73192486031 ps |
| CPU time | 31.98 seconds |
| Started | Apr 21 04:31:26 PM PDT 24 |
| Finished | Apr 21 04:31:58 PM PDT 24 |
| Peak memory | 200964 kb |
| Host | smart-577ddd94-8ddf-443f-84db-73e0e2de07cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2488510331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.2488510331 |
| Directory | /workspace/29.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/29.uart_fifo_overflow.3359353981 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 20107547957 ps |
| CPU time | 32.55 seconds |
| Started | Apr 21 04:31:31 PM PDT 24 |
| Finished | Apr 21 04:32:03 PM PDT 24 |
| Peak memory | 200836 kb |
| Host | smart-2222c3c9-89d6-49a9-af23-e9cefb0023c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3359353981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3359353981 |
| Directory | /workspace/29.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/29.uart_fifo_reset.1307316911 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 128987248826 ps |
| CPU time | 60.9 seconds |
| Started | Apr 21 04:31:31 PM PDT 24 |
| Finished | Apr 21 04:32:32 PM PDT 24 |
| Peak memory | 200908 kb |
| Host | smart-95bf7a19-b21b-4460-99dc-e1ca7a594be4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1307316911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.1307316911 |
| Directory | /workspace/29.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/29.uart_intr.736946342 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 14270401805 ps |
| CPU time | 23.92 seconds |
| Started | Apr 21 04:31:29 PM PDT 24 |
| Finished | Apr 21 04:31:53 PM PDT 24 |
| Peak memory | 199512 kb |
| Host | smart-3b99b047-d179-40ac-93ca-9292ea3f081e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736946342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.736946342 |
| Directory | /workspace/29.uart_intr/latest |
| Test location | /workspace/coverage/default/29.uart_long_xfer_wo_dly.2292125865 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 126794794218 ps |
| CPU time | 816.27 seconds |
| Started | Apr 21 04:31:33 PM PDT 24 |
| Finished | Apr 21 04:45:09 PM PDT 24 |
| Peak memory | 200912 kb |
| Host | smart-7dad29e0-ba92-40e1-98a5-3a744c25712d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2292125865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2292125865 |
| Directory | /workspace/29.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/29.uart_loopback.1541387044 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 5267914886 ps |
| CPU time | 19.24 seconds |
| Started | Apr 21 04:31:35 PM PDT 24 |
| Finished | Apr 21 04:31:54 PM PDT 24 |
| Peak memory | 199700 kb |
| Host | smart-213214ce-8872-4cc2-b443-33a0da87e5d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1541387044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.1541387044 |
| Directory | /workspace/29.uart_loopback/latest |
| Test location | /workspace/coverage/default/29.uart_noise_filter.1158886659 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 19769665769 ps |
| CPU time | 16.81 seconds |
| Started | Apr 21 04:31:31 PM PDT 24 |
| Finished | Apr 21 04:31:48 PM PDT 24 |
| Peak memory | 195508 kb |
| Host | smart-1ab127ec-42e6-43a1-b489-72e62174975a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1158886659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.1158886659 |
| Directory | /workspace/29.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/29.uart_perf.1905665780 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 25408587591 ps |
| CPU time | 424.32 seconds |
| Started | Apr 21 04:31:34 PM PDT 24 |
| Finished | Apr 21 04:38:39 PM PDT 24 |
| Peak memory | 200920 kb |
| Host | smart-abb0029d-576a-475f-b9a6-4741c789ff4c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1905665780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.1905665780 |
| Directory | /workspace/29.uart_perf/latest |
| Test location | /workspace/coverage/default/29.uart_rx_oversample.97193624 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 2029297135 ps |
| CPU time | 3.21 seconds |
| Started | Apr 21 04:31:30 PM PDT 24 |
| Finished | Apr 21 04:31:33 PM PDT 24 |
| Peak memory | 198872 kb |
| Host | smart-799364f0-1cd6-42e4-930b-cf95f48766fe |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=97193624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.97193624 |
| Directory | /workspace/29.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/29.uart_rx_parity_err.1267992820 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 8290318412 ps |
| CPU time | 16.59 seconds |
| Started | Apr 21 04:31:31 PM PDT 24 |
| Finished | Apr 21 04:31:48 PM PDT 24 |
| Peak memory | 200808 kb |
| Host | smart-76658311-dd27-47aa-8928-a0b8b402dc3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1267992820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1267992820 |
| Directory | /workspace/29.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/29.uart_rx_start_bit_filter.3997605359 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 589724359 ps |
| CPU time | 1.56 seconds |
| Started | Apr 21 04:31:32 PM PDT 24 |
| Finished | Apr 21 04:31:34 PM PDT 24 |
| Peak memory | 196276 kb |
| Host | smart-79965f34-0db5-4f3e-a7c8-2d835c10f88d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3997605359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.3997605359 |
| Directory | /workspace/29.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/29.uart_smoke.2288633745 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 673631615 ps |
| CPU time | 1.68 seconds |
| Started | Apr 21 04:31:27 PM PDT 24 |
| Finished | Apr 21 04:31:29 PM PDT 24 |
| Peak memory | 199188 kb |
| Host | smart-465fe132-0e2d-47c9-9a48-47460f4a9a6a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2288633745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.2288633745 |
| Directory | /workspace/29.uart_smoke/latest |
| Test location | /workspace/coverage/default/29.uart_stress_all.1639852736 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 328246531662 ps |
| CPU time | 2008.22 seconds |
| Started | Apr 21 04:31:37 PM PDT 24 |
| Finished | Apr 21 05:05:06 PM PDT 24 |
| Peak memory | 200824 kb |
| Host | smart-28e8d7f8-f10c-4177-b2e5-672c107b574f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639852736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.1639852736 |
| Directory | /workspace/29.uart_stress_all/latest |
| Test location | /workspace/coverage/default/29.uart_tx_ovrd.2299799149 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 665772429 ps |
| CPU time | 1.59 seconds |
| Started | Apr 21 04:31:34 PM PDT 24 |
| Finished | Apr 21 04:31:36 PM PDT 24 |
| Peak memory | 198300 kb |
| Host | smart-215c23cb-c915-45f8-808c-9f02697574fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2299799149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.2299799149 |
| Directory | /workspace/29.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/29.uart_tx_rx.1837585303 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 22209342857 ps |
| CPU time | 13.72 seconds |
| Started | Apr 21 04:31:24 PM PDT 24 |
| Finished | Apr 21 04:31:38 PM PDT 24 |
| Peak memory | 197536 kb |
| Host | smart-20460236-723e-448b-b557-6dc0ae366f44 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1837585303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.1837585303 |
| Directory | /workspace/29.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/290.uart_fifo_reset.2229754696 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 8918680786 ps |
| CPU time | 17.97 seconds |
| Started | Apr 21 04:39:26 PM PDT 24 |
| Finished | Apr 21 04:39:44 PM PDT 24 |
| Peak memory | 200796 kb |
| Host | smart-a50dff76-c34a-40b8-a595-a0845e0300a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2229754696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.2229754696 |
| Directory | /workspace/290.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/291.uart_fifo_reset.3689700756 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 40925144837 ps |
| CPU time | 17.46 seconds |
| Started | Apr 21 04:39:27 PM PDT 24 |
| Finished | Apr 21 04:39:44 PM PDT 24 |
| Peak memory | 200172 kb |
| Host | smart-ad8d1280-5d61-4c05-b9e0-37da04347fba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3689700756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.3689700756 |
| Directory | /workspace/291.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/292.uart_fifo_reset.3900056270 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 239624589526 ps |
| CPU time | 89.68 seconds |
| Started | Apr 21 04:39:27 PM PDT 24 |
| Finished | Apr 21 04:40:57 PM PDT 24 |
| Peak memory | 200796 kb |
| Host | smart-e57ba555-7613-45a0-8670-c90b39d26eaf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3900056270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.3900056270 |
| Directory | /workspace/292.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/293.uart_fifo_reset.2469535939 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 23781185049 ps |
| CPU time | 34.97 seconds |
| Started | Apr 21 04:39:26 PM PDT 24 |
| Finished | Apr 21 04:40:01 PM PDT 24 |
| Peak memory | 200812 kb |
| Host | smart-1eb5b485-6955-4314-ae66-69a0db121b6c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2469535939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.2469535939 |
| Directory | /workspace/293.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/294.uart_fifo_reset.3886528308 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 18417881576 ps |
| CPU time | 31.81 seconds |
| Started | Apr 21 04:39:29 PM PDT 24 |
| Finished | Apr 21 04:40:01 PM PDT 24 |
| Peak memory | 200888 kb |
| Host | smart-e4a72d54-ae21-4af3-9db5-86af167160e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3886528308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.3886528308 |
| Directory | /workspace/294.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/295.uart_fifo_reset.478205000 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 19342804544 ps |
| CPU time | 20.87 seconds |
| Started | Apr 21 04:39:30 PM PDT 24 |
| Finished | Apr 21 04:39:51 PM PDT 24 |
| Peak memory | 200952 kb |
| Host | smart-c531837c-9393-4e02-9d2c-6175143cd2fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=478205000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.478205000 |
| Directory | /workspace/295.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/296.uart_fifo_reset.3720917642 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 256137240251 ps |
| CPU time | 28.2 seconds |
| Started | Apr 21 04:39:29 PM PDT 24 |
| Finished | Apr 21 04:39:58 PM PDT 24 |
| Peak memory | 200880 kb |
| Host | smart-7589a51f-a016-47b7-b628-248f2f813509 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3720917642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.3720917642 |
| Directory | /workspace/296.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/297.uart_fifo_reset.1277076177 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 92780994631 ps |
| CPU time | 44.26 seconds |
| Started | Apr 21 04:39:33 PM PDT 24 |
| Finished | Apr 21 04:40:17 PM PDT 24 |
| Peak memory | 200832 kb |
| Host | smart-5cfba826-6d1d-4077-92d7-10357f4e17eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1277076177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.1277076177 |
| Directory | /workspace/297.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/298.uart_fifo_reset.3473468164 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 35887161776 ps |
| CPU time | 29.67 seconds |
| Started | Apr 21 04:39:34 PM PDT 24 |
| Finished | Apr 21 04:40:04 PM PDT 24 |
| Peak memory | 200896 kb |
| Host | smart-376288f9-14e9-4270-a8f1-83b39171782e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3473468164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.3473468164 |
| Directory | /workspace/298.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/299.uart_fifo_reset.1196800162 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 26338385167 ps |
| CPU time | 25.66 seconds |
| Started | Apr 21 04:39:31 PM PDT 24 |
| Finished | Apr 21 04:39:57 PM PDT 24 |
| Peak memory | 200932 kb |
| Host | smart-ff79ef81-415b-480d-8847-37bf24544820 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1196800162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.1196800162 |
| Directory | /workspace/299.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/3.uart_alert_test.3074297158 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 16881654 ps |
| CPU time | 0.58 seconds |
| Started | Apr 21 04:26:13 PM PDT 24 |
| Finished | Apr 21 04:26:14 PM PDT 24 |
| Peak memory | 196236 kb |
| Host | smart-139fb616-cc28-49b8-b6bd-b071c3b79703 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074297158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.3074297158 |
| Directory | /workspace/3.uart_alert_test/latest |
| Test location | /workspace/coverage/default/3.uart_fifo_full.283699031 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 83567562678 ps |
| CPU time | 33.05 seconds |
| Started | Apr 21 04:25:57 PM PDT 24 |
| Finished | Apr 21 04:26:30 PM PDT 24 |
| Peak memory | 200832 kb |
| Host | smart-cd5412eb-e122-42ab-9cd7-7a2e6bf6d466 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=283699031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.283699031 |
| Directory | /workspace/3.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/3.uart_fifo_overflow.80223471 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 217423463614 ps |
| CPU time | 39.64 seconds |
| Started | Apr 21 04:25:56 PM PDT 24 |
| Finished | Apr 21 04:26:36 PM PDT 24 |
| Peak memory | 200856 kb |
| Host | smart-8348ba70-63df-4016-bdb8-e1381d745509 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=80223471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.80223471 |
| Directory | /workspace/3.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/3.uart_fifo_reset.1608169837 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 94613632402 ps |
| CPU time | 110.6 seconds |
| Started | Apr 21 04:25:58 PM PDT 24 |
| Finished | Apr 21 04:27:49 PM PDT 24 |
| Peak memory | 200864 kb |
| Host | smart-83b6f555-1552-47f8-9de1-aa435470302d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1608169837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.1608169837 |
| Directory | /workspace/3.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/3.uart_intr.767219033 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 530333634662 ps |
| CPU time | 207.77 seconds |
| Started | Apr 21 04:25:56 PM PDT 24 |
| Finished | Apr 21 04:29:24 PM PDT 24 |
| Peak memory | 200252 kb |
| Host | smart-de1417c2-666f-41d5-a639-674a1c4b506b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767219033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.767219033 |
| Directory | /workspace/3.uart_intr/latest |
| Test location | /workspace/coverage/default/3.uart_long_xfer_wo_dly.184417374 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 122609600341 ps |
| CPU time | 380.74 seconds |
| Started | Apr 21 04:26:04 PM PDT 24 |
| Finished | Apr 21 04:32:25 PM PDT 24 |
| Peak memory | 200824 kb |
| Host | smart-231ead42-5c48-40b1-9346-6c9394044d65 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=184417374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.184417374 |
| Directory | /workspace/3.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/3.uart_loopback.4016862534 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 8754989337 ps |
| CPU time | 5.19 seconds |
| Started | Apr 21 04:26:06 PM PDT 24 |
| Finished | Apr 21 04:26:12 PM PDT 24 |
| Peak memory | 199620 kb |
| Host | smart-6a8444ae-4d3d-436a-83b6-70dc4b80c446 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4016862534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.4016862534 |
| Directory | /workspace/3.uart_loopback/latest |
| Test location | /workspace/coverage/default/3.uart_noise_filter.2065548936 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 141215916103 ps |
| CPU time | 61.59 seconds |
| Started | Apr 21 04:25:59 PM PDT 24 |
| Finished | Apr 21 04:27:01 PM PDT 24 |
| Peak memory | 209192 kb |
| Host | smart-08610eba-6642-4f92-b755-2fa8b2998da4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2065548936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.2065548936 |
| Directory | /workspace/3.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/3.uart_perf.4000324019 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 12906700607 ps |
| CPU time | 197.76 seconds |
| Started | Apr 21 04:26:04 PM PDT 24 |
| Finished | Apr 21 04:29:22 PM PDT 24 |
| Peak memory | 200892 kb |
| Host | smart-17bbcc01-1ff3-4507-9ade-63daacabe111 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4000324019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.4000324019 |
| Directory | /workspace/3.uart_perf/latest |
| Test location | /workspace/coverage/default/3.uart_rx_oversample.2494729446 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 5876505481 ps |
| CPU time | 48.37 seconds |
| Started | Apr 21 04:25:56 PM PDT 24 |
| Finished | Apr 21 04:26:45 PM PDT 24 |
| Peak memory | 199516 kb |
| Host | smart-9781c399-0611-4cd4-aece-8c743e319f82 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2494729446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.2494729446 |
| Directory | /workspace/3.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/3.uart_rx_parity_err.3776604225 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 104344921071 ps |
| CPU time | 403.67 seconds |
| Started | Apr 21 04:26:02 PM PDT 24 |
| Finished | Apr 21 04:32:46 PM PDT 24 |
| Peak memory | 200848 kb |
| Host | smart-cd693570-09a3-4e3b-91c4-a95798f62c33 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3776604225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.3776604225 |
| Directory | /workspace/3.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/3.uart_rx_start_bit_filter.1631363167 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 2337079725 ps |
| CPU time | 4.67 seconds |
| Started | Apr 21 04:26:01 PM PDT 24 |
| Finished | Apr 21 04:26:06 PM PDT 24 |
| Peak memory | 196608 kb |
| Host | smart-1b91d777-5ea2-476d-abc4-3f58acb00a6d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1631363167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.1631363167 |
| Directory | /workspace/3.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/3.uart_sec_cm.3409145863 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 110268277 ps |
| CPU time | 0.8 seconds |
| Started | Apr 21 04:26:07 PM PDT 24 |
| Finished | Apr 21 04:26:08 PM PDT 24 |
| Peak memory | 219020 kb |
| Host | smart-e3bba29b-9718-457b-84b7-ece080bf4570 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409145863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3409145863 |
| Directory | /workspace/3.uart_sec_cm/latest |
| Test location | /workspace/coverage/default/3.uart_smoke.2614732608 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 287934494 ps |
| CPU time | 1.59 seconds |
| Started | Apr 21 04:25:57 PM PDT 24 |
| Finished | Apr 21 04:25:59 PM PDT 24 |
| Peak memory | 200768 kb |
| Host | smart-47e2402a-86e8-453e-a804-a3a44fd9c7f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2614732608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.2614732608 |
| Directory | /workspace/3.uart_smoke/latest |
| Test location | /workspace/coverage/default/3.uart_stress_all_with_rand_reset.4037557057 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 16676867392 ps |
| CPU time | 450.89 seconds |
| Started | Apr 21 04:26:14 PM PDT 24 |
| Finished | Apr 21 04:33:45 PM PDT 24 |
| Peak memory | 217312 kb |
| Host | smart-d608ee15-8156-454a-ae67-aa9fa484d413 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037557057 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.4037557057 |
| Directory | /workspace/3.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/3.uart_tx_ovrd.2377710593 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 1221955223 ps |
| CPU time | 4.54 seconds |
| Started | Apr 21 04:26:01 PM PDT 24 |
| Finished | Apr 21 04:26:06 PM PDT 24 |
| Peak memory | 200428 kb |
| Host | smart-11a62580-716d-4cb8-84d2-58f5b494f71e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2377710593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2377710593 |
| Directory | /workspace/3.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/3.uart_tx_rx.3085575918 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 5946020388 ps |
| CPU time | 11.98 seconds |
| Started | Apr 21 04:25:57 PM PDT 24 |
| Finished | Apr 21 04:26:09 PM PDT 24 |
| Peak memory | 200820 kb |
| Host | smart-10208301-7f5d-42cf-a812-bf111d5a7a9e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3085575918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.3085575918 |
| Directory | /workspace/3.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/30.uart_alert_test.2598100754 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 44772993 ps |
| CPU time | 0.55 seconds |
| Started | Apr 21 04:31:50 PM PDT 24 |
| Finished | Apr 21 04:31:51 PM PDT 24 |
| Peak memory | 196204 kb |
| Host | smart-aa1a5609-5326-4431-8b84-8f4f46d30ac6 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598100754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.2598100754 |
| Directory | /workspace/30.uart_alert_test/latest |
| Test location | /workspace/coverage/default/30.uart_fifo_full.1112271634 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 160363438255 ps |
| CPU time | 204.92 seconds |
| Started | Apr 21 04:31:42 PM PDT 24 |
| Finished | Apr 21 04:35:07 PM PDT 24 |
| Peak memory | 200908 kb |
| Host | smart-a7fe6eec-0326-4a5e-889a-98a28ac9f18b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1112271634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.1112271634 |
| Directory | /workspace/30.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/30.uart_fifo_overflow.4220523871 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 19825285425 ps |
| CPU time | 56.02 seconds |
| Started | Apr 21 04:31:39 PM PDT 24 |
| Finished | Apr 21 04:32:36 PM PDT 24 |
| Peak memory | 200920 kb |
| Host | smart-c0e61a77-9ff6-43c9-a030-1824eed34131 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4220523871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.4220523871 |
| Directory | /workspace/30.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/30.uart_intr.1505189210 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 146943982169 ps |
| CPU time | 15.34 seconds |
| Started | Apr 21 04:31:43 PM PDT 24 |
| Finished | Apr 21 04:31:59 PM PDT 24 |
| Peak memory | 200884 kb |
| Host | smart-1b86da27-f792-42bb-bad5-e5da5b228da7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505189210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.1505189210 |
| Directory | /workspace/30.uart_intr/latest |
| Test location | /workspace/coverage/default/30.uart_long_xfer_wo_dly.1049710757 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 98340384912 ps |
| CPU time | 546.81 seconds |
| Started | Apr 21 04:31:45 PM PDT 24 |
| Finished | Apr 21 04:40:52 PM PDT 24 |
| Peak memory | 200836 kb |
| Host | smart-d1278c18-d943-429a-8697-e6ab00e3d86e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1049710757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1049710757 |
| Directory | /workspace/30.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/30.uart_loopback.669971528 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 10505636872 ps |
| CPU time | 35.29 seconds |
| Started | Apr 21 04:31:43 PM PDT 24 |
| Finished | Apr 21 04:32:19 PM PDT 24 |
| Peak memory | 200580 kb |
| Host | smart-74d59d39-42e1-46dc-b99b-5d8a9377b948 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=669971528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.669971528 |
| Directory | /workspace/30.uart_loopback/latest |
| Test location | /workspace/coverage/default/30.uart_noise_filter.3869292094 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 10566256339 ps |
| CPU time | 18.9 seconds |
| Started | Apr 21 04:31:42 PM PDT 24 |
| Finished | Apr 21 04:32:01 PM PDT 24 |
| Peak memory | 199016 kb |
| Host | smart-2ea89743-46a1-4109-a43e-f32d8b76ba87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3869292094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.3869292094 |
| Directory | /workspace/30.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/30.uart_perf.147327931 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 21746739824 ps |
| CPU time | 359.08 seconds |
| Started | Apr 21 04:31:46 PM PDT 24 |
| Finished | Apr 21 04:37:46 PM PDT 24 |
| Peak memory | 200948 kb |
| Host | smart-fc0ac35f-0ce3-4a7d-9329-6dfcd31cdb45 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=147327931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.147327931 |
| Directory | /workspace/30.uart_perf/latest |
| Test location | /workspace/coverage/default/30.uart_rx_oversample.2832121199 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 2226448964 ps |
| CPU time | 18.37 seconds |
| Started | Apr 21 04:31:41 PM PDT 24 |
| Finished | Apr 21 04:32:00 PM PDT 24 |
| Peak memory | 200020 kb |
| Host | smart-87998027-7cb9-47aa-8347-005f250d6050 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2832121199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.2832121199 |
| Directory | /workspace/30.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/30.uart_rx_parity_err.772535636 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 25099520609 ps |
| CPU time | 11.33 seconds |
| Started | Apr 21 04:31:45 PM PDT 24 |
| Finished | Apr 21 04:31:57 PM PDT 24 |
| Peak memory | 200676 kb |
| Host | smart-f2de9b1d-d4fc-4f08-b398-680830cc3eb0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=772535636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.772535636 |
| Directory | /workspace/30.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/30.uart_rx_start_bit_filter.2219626650 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 1437666890 ps |
| CPU time | 2.01 seconds |
| Started | Apr 21 04:31:46 PM PDT 24 |
| Finished | Apr 21 04:31:48 PM PDT 24 |
| Peak memory | 196268 kb |
| Host | smart-0ec12cd6-bbf1-46e5-bd38-a056feb8aa2d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2219626650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.2219626650 |
| Directory | /workspace/30.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/30.uart_smoke.3866041999 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 454358712 ps |
| CPU time | 1.94 seconds |
| Started | Apr 21 04:31:37 PM PDT 24 |
| Finished | Apr 21 04:31:40 PM PDT 24 |
| Peak memory | 200504 kb |
| Host | smart-ada37252-29f7-4097-92d0-a1fb29e90475 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3866041999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3866041999 |
| Directory | /workspace/30.uart_smoke/latest |
| Test location | /workspace/coverage/default/30.uart_stress_all.3336451969 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 420882703397 ps |
| CPU time | 119.35 seconds |
| Started | Apr 21 04:32:02 PM PDT 24 |
| Finished | Apr 21 04:34:02 PM PDT 24 |
| Peak memory | 200920 kb |
| Host | smart-5fcf5068-6fdd-4ef2-8579-a9ef916b73b9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336451969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.3336451969 |
| Directory | /workspace/30.uart_stress_all/latest |
| Test location | /workspace/coverage/default/30.uart_stress_all_with_rand_reset.3788580849 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 66616760110 ps |
| CPU time | 795.41 seconds |
| Started | Apr 21 04:31:44 PM PDT 24 |
| Finished | Apr 21 04:45:00 PM PDT 24 |
| Peak memory | 217340 kb |
| Host | smart-3f71e11f-a47d-4afe-85fb-b591f5553934 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788580849 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.3788580849 |
| Directory | /workspace/30.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/30.uart_tx_ovrd.214283851 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 1260941242 ps |
| CPU time | 2.78 seconds |
| Started | Apr 21 04:31:47 PM PDT 24 |
| Finished | Apr 21 04:31:50 PM PDT 24 |
| Peak memory | 200680 kb |
| Host | smart-2b9ab29e-84af-48e2-a988-d376c146ec2a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=214283851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.214283851 |
| Directory | /workspace/30.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/30.uart_tx_rx.3384139845 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 80129046643 ps |
| CPU time | 195.61 seconds |
| Started | Apr 21 04:31:37 PM PDT 24 |
| Finished | Apr 21 04:34:53 PM PDT 24 |
| Peak memory | 200824 kb |
| Host | smart-8690e4fb-9776-4391-b964-e9ad4ab53889 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3384139845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.3384139845 |
| Directory | /workspace/30.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/31.uart_alert_test.3282270968 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 71825010 ps |
| CPU time | 0.57 seconds |
| Started | Apr 21 04:32:00 PM PDT 24 |
| Finished | Apr 21 04:32:01 PM PDT 24 |
| Peak memory | 196248 kb |
| Host | smart-927472e5-ea36-4b52-a4a5-902f6dddbb21 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282270968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.3282270968 |
| Directory | /workspace/31.uart_alert_test/latest |
| Test location | /workspace/coverage/default/31.uart_fifo_full.3474296591 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 65856708766 ps |
| CPU time | 38.85 seconds |
| Started | Apr 21 04:31:53 PM PDT 24 |
| Finished | Apr 21 04:32:32 PM PDT 24 |
| Peak memory | 200832 kb |
| Host | smart-70b00e79-64dd-4a00-acc3-3b2742eed66b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3474296591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.3474296591 |
| Directory | /workspace/31.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/31.uart_fifo_overflow.2022967319 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 23385605450 ps |
| CPU time | 41.03 seconds |
| Started | Apr 21 04:31:53 PM PDT 24 |
| Finished | Apr 21 04:32:34 PM PDT 24 |
| Peak memory | 200800 kb |
| Host | smart-84f45d13-6350-49ab-99ee-e9d791641518 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2022967319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.2022967319 |
| Directory | /workspace/31.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/31.uart_fifo_reset.2573296870 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 20928082527 ps |
| CPU time | 24.66 seconds |
| Started | Apr 21 04:31:54 PM PDT 24 |
| Finished | Apr 21 04:32:19 PM PDT 24 |
| Peak memory | 200924 kb |
| Host | smart-4de4e257-611d-4c0d-ac47-07ef7f4dc5b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2573296870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.2573296870 |
| Directory | /workspace/31.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/31.uart_intr.3664375971 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 48714915241 ps |
| CPU time | 84.36 seconds |
| Started | Apr 21 04:31:58 PM PDT 24 |
| Finished | Apr 21 04:33:23 PM PDT 24 |
| Peak memory | 200936 kb |
| Host | smart-cd4727e6-cd59-47e8-9a56-1c4f584c1e5e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664375971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.3664375971 |
| Directory | /workspace/31.uart_intr/latest |
| Test location | /workspace/coverage/default/31.uart_long_xfer_wo_dly.2464723434 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 113841371842 ps |
| CPU time | 1191.31 seconds |
| Started | Apr 21 04:31:59 PM PDT 24 |
| Finished | Apr 21 04:51:51 PM PDT 24 |
| Peak memory | 200940 kb |
| Host | smart-a2359fc4-4d40-4253-91a0-d98081731c32 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2464723434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.2464723434 |
| Directory | /workspace/31.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/31.uart_loopback.3481254652 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 5925227767 ps |
| CPU time | 3.36 seconds |
| Started | Apr 21 04:32:02 PM PDT 24 |
| Finished | Apr 21 04:32:05 PM PDT 24 |
| Peak memory | 200880 kb |
| Host | smart-7427d2e7-fbab-4a91-993d-97e03be77344 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3481254652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.3481254652 |
| Directory | /workspace/31.uart_loopback/latest |
| Test location | /workspace/coverage/default/31.uart_noise_filter.1178612194 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 31643330200 ps |
| CPU time | 29.49 seconds |
| Started | Apr 21 04:31:57 PM PDT 24 |
| Finished | Apr 21 04:32:26 PM PDT 24 |
| Peak memory | 200828 kb |
| Host | smart-7dfca490-e6d8-4f6c-8e46-c07c9570fd43 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1178612194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.1178612194 |
| Directory | /workspace/31.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/31.uart_perf.3798721910 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 2950653533 ps |
| CPU time | 37.92 seconds |
| Started | Apr 21 04:32:02 PM PDT 24 |
| Finished | Apr 21 04:32:40 PM PDT 24 |
| Peak memory | 200908 kb |
| Host | smart-ce54dd5b-aa26-4c3e-a421-5235050f460c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3798721910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.3798721910 |
| Directory | /workspace/31.uart_perf/latest |
| Test location | /workspace/coverage/default/31.uart_rx_oversample.2418785748 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 1197499316 ps |
| CPU time | 0.91 seconds |
| Started | Apr 21 04:31:58 PM PDT 24 |
| Finished | Apr 21 04:31:59 PM PDT 24 |
| Peak memory | 196520 kb |
| Host | smart-d26b8f39-7618-4a88-ba63-db3851549d81 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2418785748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.2418785748 |
| Directory | /workspace/31.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/31.uart_rx_parity_err.3726318480 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 341102690439 ps |
| CPU time | 68.12 seconds |
| Started | Apr 21 04:31:56 PM PDT 24 |
| Finished | Apr 21 04:33:04 PM PDT 24 |
| Peak memory | 200836 kb |
| Host | smart-4ddabdbf-b767-4015-8a44-655ea644b429 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3726318480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.3726318480 |
| Directory | /workspace/31.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/31.uart_rx_start_bit_filter.3765277127 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 3927570615 ps |
| CPU time | 2.11 seconds |
| Started | Apr 21 04:32:01 PM PDT 24 |
| Finished | Apr 21 04:32:04 PM PDT 24 |
| Peak memory | 197196 kb |
| Host | smart-0ab21e99-9fcb-433e-a3e8-d4f1b3103ef6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3765277127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.3765277127 |
| Directory | /workspace/31.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/31.uart_smoke.2215255516 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 667830244 ps |
| CPU time | 2.14 seconds |
| Started | Apr 21 04:31:51 PM PDT 24 |
| Finished | Apr 21 04:31:53 PM PDT 24 |
| Peak memory | 199108 kb |
| Host | smart-a03995ad-19b6-48fa-bccf-4dd251fb9008 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2215255516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.2215255516 |
| Directory | /workspace/31.uart_smoke/latest |
| Test location | /workspace/coverage/default/31.uart_stress_all.1511672088 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 37082884968 ps |
| CPU time | 33.22 seconds |
| Started | Apr 21 04:31:58 PM PDT 24 |
| Finished | Apr 21 04:32:32 PM PDT 24 |
| Peak memory | 201056 kb |
| Host | smart-e9857777-b603-493d-b107-31477a025f46 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511672088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.1511672088 |
| Directory | /workspace/31.uart_stress_all/latest |
| Test location | /workspace/coverage/default/31.uart_stress_all_with_rand_reset.4006562518 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 11553050664 ps |
| CPU time | 134.88 seconds |
| Started | Apr 21 04:32:00 PM PDT 24 |
| Finished | Apr 21 04:34:15 PM PDT 24 |
| Peak memory | 217556 kb |
| Host | smart-946394ac-e61b-4681-a1d9-6f54e4515a09 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006562518 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.4006562518 |
| Directory | /workspace/31.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/31.uart_tx_ovrd.1121477396 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 765090542 ps |
| CPU time | 3.15 seconds |
| Started | Apr 21 04:31:56 PM PDT 24 |
| Finished | Apr 21 04:31:59 PM PDT 24 |
| Peak memory | 200544 kb |
| Host | smart-47f3b674-a495-4aca-b07b-e95f2ccb1b24 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1121477396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1121477396 |
| Directory | /workspace/31.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/31.uart_tx_rx.1988257384 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 53677344998 ps |
| CPU time | 90.75 seconds |
| Started | Apr 21 04:31:50 PM PDT 24 |
| Finished | Apr 21 04:33:21 PM PDT 24 |
| Peak memory | 200936 kb |
| Host | smart-b9d98f5c-123f-4837-9306-936d8615bffc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1988257384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.1988257384 |
| Directory | /workspace/31.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/32.uart_alert_test.3434993179 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 50008103 ps |
| CPU time | 0.58 seconds |
| Started | Apr 21 04:32:16 PM PDT 24 |
| Finished | Apr 21 04:32:17 PM PDT 24 |
| Peak memory | 196204 kb |
| Host | smart-4d779014-510b-4abf-950e-bd9a09575af2 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434993179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.3434993179 |
| Directory | /workspace/32.uart_alert_test/latest |
| Test location | /workspace/coverage/default/32.uart_fifo_full.3832003950 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 103978277352 ps |
| CPU time | 27.16 seconds |
| Started | Apr 21 04:32:06 PM PDT 24 |
| Finished | Apr 21 04:32:33 PM PDT 24 |
| Peak memory | 200848 kb |
| Host | smart-c5415a95-0662-4580-82f2-45d8a73f999d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3832003950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.3832003950 |
| Directory | /workspace/32.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/32.uart_fifo_overflow.2290425445 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 121854990887 ps |
| CPU time | 288.76 seconds |
| Started | Apr 21 04:32:05 PM PDT 24 |
| Finished | Apr 21 04:36:54 PM PDT 24 |
| Peak memory | 200884 kb |
| Host | smart-ce0dd3d9-680a-4ed2-8960-71de6142af29 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2290425445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2290425445 |
| Directory | /workspace/32.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/32.uart_fifo_reset.3606945489 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 50239832655 ps |
| CPU time | 38.83 seconds |
| Started | Apr 21 04:32:07 PM PDT 24 |
| Finished | Apr 21 04:32:46 PM PDT 24 |
| Peak memory | 200828 kb |
| Host | smart-1a1d8413-1a08-42fa-bfb0-97ee9ada8e71 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3606945489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.3606945489 |
| Directory | /workspace/32.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/32.uart_intr.3515513694 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 3594896410 ps |
| CPU time | 7.26 seconds |
| Started | Apr 21 04:32:17 PM PDT 24 |
| Finished | Apr 21 04:32:25 PM PDT 24 |
| Peak memory | 196928 kb |
| Host | smart-add119b5-8117-4e96-9d4e-90803a1b0e9d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515513694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.3515513694 |
| Directory | /workspace/32.uart_intr/latest |
| Test location | /workspace/coverage/default/32.uart_long_xfer_wo_dly.2210293682 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 90655934760 ps |
| CPU time | 427.5 seconds |
| Started | Apr 21 04:32:09 PM PDT 24 |
| Finished | Apr 21 04:39:17 PM PDT 24 |
| Peak memory | 200924 kb |
| Host | smart-8df2743f-0661-42aa-8622-87e52b2e5a03 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2210293682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.2210293682 |
| Directory | /workspace/32.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/32.uart_loopback.3764532206 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 1135819125 ps |
| CPU time | 2.5 seconds |
| Started | Apr 21 04:32:10 PM PDT 24 |
| Finished | Apr 21 04:32:13 PM PDT 24 |
| Peak memory | 196744 kb |
| Host | smart-c9560a75-3e1d-49c5-bb6b-f982794c934f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3764532206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.3764532206 |
| Directory | /workspace/32.uart_loopback/latest |
| Test location | /workspace/coverage/default/32.uart_noise_filter.3748512885 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 151356158886 ps |
| CPU time | 97.21 seconds |
| Started | Apr 21 04:32:09 PM PDT 24 |
| Finished | Apr 21 04:33:46 PM PDT 24 |
| Peak memory | 201080 kb |
| Host | smart-fd3d82fe-2fc1-4bec-9d4e-f154eb2cb34e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3748512885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.3748512885 |
| Directory | /workspace/32.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/32.uart_perf.407804775 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 9628435579 ps |
| CPU time | 267.73 seconds |
| Started | Apr 21 04:32:10 PM PDT 24 |
| Finished | Apr 21 04:36:38 PM PDT 24 |
| Peak memory | 200888 kb |
| Host | smart-baeaae5f-1039-4bb3-83d0-1da8b5b0cf0c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=407804775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.407804775 |
| Directory | /workspace/32.uart_perf/latest |
| Test location | /workspace/coverage/default/32.uart_rx_oversample.116239283 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 7624551891 ps |
| CPU time | 35.92 seconds |
| Started | Apr 21 04:32:06 PM PDT 24 |
| Finished | Apr 21 04:32:43 PM PDT 24 |
| Peak memory | 200072 kb |
| Host | smart-83407e4f-74e7-443b-a63d-f311c89bf4c1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=116239283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.116239283 |
| Directory | /workspace/32.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/32.uart_rx_parity_err.2172469825 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 56920558141 ps |
| CPU time | 85.98 seconds |
| Started | Apr 21 04:32:12 PM PDT 24 |
| Finished | Apr 21 04:33:38 PM PDT 24 |
| Peak memory | 200820 kb |
| Host | smart-98d8c6f3-3cc3-4883-b579-50f75e487eb2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2172469825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.2172469825 |
| Directory | /workspace/32.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/32.uart_rx_start_bit_filter.2880002546 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 34914053971 ps |
| CPU time | 57.69 seconds |
| Started | Apr 21 04:32:12 PM PDT 24 |
| Finished | Apr 21 04:33:10 PM PDT 24 |
| Peak memory | 196644 kb |
| Host | smart-4a70b7fc-8e52-44c3-bc3c-af5b73a4e66c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2880002546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.2880002546 |
| Directory | /workspace/32.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/32.uart_smoke.1664859654 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 902780770 ps |
| CPU time | 2.33 seconds |
| Started | Apr 21 04:32:02 PM PDT 24 |
| Finished | Apr 21 04:32:05 PM PDT 24 |
| Peak memory | 199176 kb |
| Host | smart-f31679bf-d751-4124-8bef-61eed0516fdd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1664859654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.1664859654 |
| Directory | /workspace/32.uart_smoke/latest |
| Test location | /workspace/coverage/default/32.uart_stress_all.502848576 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 173926883465 ps |
| CPU time | 662.29 seconds |
| Started | Apr 21 04:32:15 PM PDT 24 |
| Finished | Apr 21 04:43:18 PM PDT 24 |
| Peak memory | 200868 kb |
| Host | smart-06222ce7-c80c-4a74-a208-c645f253cb55 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502848576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.502848576 |
| Directory | /workspace/32.uart_stress_all/latest |
| Test location | /workspace/coverage/default/32.uart_tx_ovrd.1723169449 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 2254572781 ps |
| CPU time | 2.75 seconds |
| Started | Apr 21 04:32:10 PM PDT 24 |
| Finished | Apr 21 04:32:13 PM PDT 24 |
| Peak memory | 200788 kb |
| Host | smart-fad7035b-42e2-4358-bab4-09d288eafacd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1723169449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.1723169449 |
| Directory | /workspace/32.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/32.uart_tx_rx.946071746 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 187913973521 ps |
| CPU time | 70.75 seconds |
| Started | Apr 21 04:32:04 PM PDT 24 |
| Finished | Apr 21 04:33:15 PM PDT 24 |
| Peak memory | 200876 kb |
| Host | smart-ca074c75-fb83-4fa4-a95f-1b3256af08ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=946071746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.946071746 |
| Directory | /workspace/32.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/33.uart_alert_test.2595696027 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 45486042 ps |
| CPU time | 0.59 seconds |
| Started | Apr 21 04:32:24 PM PDT 24 |
| Finished | Apr 21 04:32:25 PM PDT 24 |
| Peak memory | 196244 kb |
| Host | smart-37c5e053-3354-4996-ac18-d56a8e95e0b5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595696027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.2595696027 |
| Directory | /workspace/33.uart_alert_test/latest |
| Test location | /workspace/coverage/default/33.uart_fifo_full.4165227292 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 129998611681 ps |
| CPU time | 216.51 seconds |
| Started | Apr 21 04:32:17 PM PDT 24 |
| Finished | Apr 21 04:35:54 PM PDT 24 |
| Peak memory | 200908 kb |
| Host | smart-da08e803-a9cf-4714-8832-a66167873a1e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4165227292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.4165227292 |
| Directory | /workspace/33.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/33.uart_fifo_overflow.2195884310 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 24191712416 ps |
| CPU time | 35.16 seconds |
| Started | Apr 21 04:32:19 PM PDT 24 |
| Finished | Apr 21 04:32:55 PM PDT 24 |
| Peak memory | 200892 kb |
| Host | smart-ffc9e635-ccac-4266-9c8e-7543ead97ead |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2195884310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.2195884310 |
| Directory | /workspace/33.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/33.uart_fifo_reset.3728975919 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 114074215983 ps |
| CPU time | 28.41 seconds |
| Started | Apr 21 04:32:17 PM PDT 24 |
| Finished | Apr 21 04:32:46 PM PDT 24 |
| Peak memory | 200820 kb |
| Host | smart-7de72723-c25b-4880-a0a4-46ce7a4e2c05 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3728975919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.3728975919 |
| Directory | /workspace/33.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/33.uart_intr.1008182056 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 4292962964 ps |
| CPU time | 2.42 seconds |
| Started | Apr 21 04:32:19 PM PDT 24 |
| Finished | Apr 21 04:32:22 PM PDT 24 |
| Peak memory | 197340 kb |
| Host | smart-28cf494b-0146-4149-aa47-34c285168afa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008182056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.1008182056 |
| Directory | /workspace/33.uart_intr/latest |
| Test location | /workspace/coverage/default/33.uart_long_xfer_wo_dly.1245118700 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 61361298264 ps |
| CPU time | 241.7 seconds |
| Started | Apr 21 04:32:22 PM PDT 24 |
| Finished | Apr 21 04:36:24 PM PDT 24 |
| Peak memory | 200924 kb |
| Host | smart-36e27e41-dd6a-4e83-8377-7bb2c3b51f84 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1245118700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.1245118700 |
| Directory | /workspace/33.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/33.uart_loopback.132626458 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 1091262070 ps |
| CPU time | 1.33 seconds |
| Started | Apr 21 04:32:20 PM PDT 24 |
| Finished | Apr 21 04:32:22 PM PDT 24 |
| Peak memory | 196312 kb |
| Host | smart-ef7e83e1-1ec0-41ae-b235-c62483e7a04a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=132626458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.132626458 |
| Directory | /workspace/33.uart_loopback/latest |
| Test location | /workspace/coverage/default/33.uart_noise_filter.3672867422 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 236990812153 ps |
| CPU time | 111.18 seconds |
| Started | Apr 21 04:32:20 PM PDT 24 |
| Finished | Apr 21 04:34:11 PM PDT 24 |
| Peak memory | 216644 kb |
| Host | smart-55d2fade-bb8c-41c0-9f77-78baa2c94614 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3672867422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.3672867422 |
| Directory | /workspace/33.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/33.uart_perf.3550081443 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 9434087933 ps |
| CPU time | 149.79 seconds |
| Started | Apr 21 04:32:23 PM PDT 24 |
| Finished | Apr 21 04:34:53 PM PDT 24 |
| Peak memory | 200904 kb |
| Host | smart-f38773bc-2f9e-481b-af79-d45f1df6b3d9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3550081443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.3550081443 |
| Directory | /workspace/33.uart_perf/latest |
| Test location | /workspace/coverage/default/33.uart_rx_oversample.110890670 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 1273560638 ps |
| CPU time | 2.66 seconds |
| Started | Apr 21 04:32:19 PM PDT 24 |
| Finished | Apr 21 04:32:21 PM PDT 24 |
| Peak memory | 198420 kb |
| Host | smart-7a6dccd8-c2f3-45a6-a9f7-be5eb38b0481 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=110890670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.110890670 |
| Directory | /workspace/33.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/33.uart_rx_parity_err.1297323182 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 27465779590 ps |
| CPU time | 36.77 seconds |
| Started | Apr 21 04:32:21 PM PDT 24 |
| Finished | Apr 21 04:32:58 PM PDT 24 |
| Peak memory | 200760 kb |
| Host | smart-a8155c5d-e720-4b54-b2b4-b413d0c204ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1297323182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.1297323182 |
| Directory | /workspace/33.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/33.uart_rx_start_bit_filter.186268153 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 837872007 ps |
| CPU time | 1.97 seconds |
| Started | Apr 21 04:32:21 PM PDT 24 |
| Finished | Apr 21 04:32:23 PM PDT 24 |
| Peak memory | 196532 kb |
| Host | smart-fc0b896f-3cbc-47ee-87f6-b588f1f5b0d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=186268153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.186268153 |
| Directory | /workspace/33.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/33.uart_smoke.2509547010 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 512133613 ps |
| CPU time | 1.21 seconds |
| Started | Apr 21 04:32:14 PM PDT 24 |
| Finished | Apr 21 04:32:16 PM PDT 24 |
| Peak memory | 199468 kb |
| Host | smart-63973040-a1ef-4cb4-a6e4-3572ea57eea8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2509547010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.2509547010 |
| Directory | /workspace/33.uart_smoke/latest |
| Test location | /workspace/coverage/default/33.uart_stress_all.2624370042 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 307887620457 ps |
| CPU time | 221.16 seconds |
| Started | Apr 21 04:32:23 PM PDT 24 |
| Finished | Apr 21 04:36:04 PM PDT 24 |
| Peak memory | 200828 kb |
| Host | smart-5e54f83f-facf-4353-ada4-ec8c7779fc2b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624370042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.2624370042 |
| Directory | /workspace/33.uart_stress_all/latest |
| Test location | /workspace/coverage/default/33.uart_stress_all_with_rand_reset.1564927924 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 117621955457 ps |
| CPU time | 436.42 seconds |
| Started | Apr 21 04:32:24 PM PDT 24 |
| Finished | Apr 21 04:39:40 PM PDT 24 |
| Peak memory | 217536 kb |
| Host | smart-50fc2c4b-da1b-438c-86ac-de685057975c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564927924 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.1564927924 |
| Directory | /workspace/33.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/33.uart_tx_ovrd.2007760240 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 2190435406 ps |
| CPU time | 2.06 seconds |
| Started | Apr 21 04:32:21 PM PDT 24 |
| Finished | Apr 21 04:32:23 PM PDT 24 |
| Peak memory | 199640 kb |
| Host | smart-66b5ff9a-07e9-4606-bec0-75a93ac04d8f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2007760240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.2007760240 |
| Directory | /workspace/33.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/33.uart_tx_rx.4136469932 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 43647258585 ps |
| CPU time | 24.63 seconds |
| Started | Apr 21 04:32:18 PM PDT 24 |
| Finished | Apr 21 04:32:42 PM PDT 24 |
| Peak memory | 200848 kb |
| Host | smart-1b57a3f0-d1f5-4771-9827-bf782fe4a4d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4136469932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.4136469932 |
| Directory | /workspace/33.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/34.uart_alert_test.1915998444 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 22506908 ps |
| CPU time | 0.57 seconds |
| Started | Apr 21 04:32:36 PM PDT 24 |
| Finished | Apr 21 04:32:37 PM PDT 24 |
| Peak memory | 196208 kb |
| Host | smart-9f48e0a7-7860-4711-8401-6468a24b0e4c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915998444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1915998444 |
| Directory | /workspace/34.uart_alert_test/latest |
| Test location | /workspace/coverage/default/34.uart_fifo_full.2027466044 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 17804310691 ps |
| CPU time | 28.24 seconds |
| Started | Apr 21 04:32:29 PM PDT 24 |
| Finished | Apr 21 04:32:58 PM PDT 24 |
| Peak memory | 200836 kb |
| Host | smart-a9127eec-cf0c-4412-a2ed-775efb8fac87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2027466044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.2027466044 |
| Directory | /workspace/34.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/34.uart_fifo_overflow.813038156 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 108827629231 ps |
| CPU time | 167.51 seconds |
| Started | Apr 21 04:32:30 PM PDT 24 |
| Finished | Apr 21 04:35:18 PM PDT 24 |
| Peak memory | 200804 kb |
| Host | smart-39bbf220-3aae-433f-acfe-e59ba6444edd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=813038156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.813038156 |
| Directory | /workspace/34.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/34.uart_fifo_reset.718725519 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 386943178703 ps |
| CPU time | 79.2 seconds |
| Started | Apr 21 04:32:29 PM PDT 24 |
| Finished | Apr 21 04:33:48 PM PDT 24 |
| Peak memory | 200880 kb |
| Host | smart-eb533ace-73f5-46eb-80b0-c826d43e01fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=718725519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.718725519 |
| Directory | /workspace/34.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/34.uart_intr.1251997556 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 16092454416 ps |
| CPU time | 7.33 seconds |
| Started | Apr 21 04:32:28 PM PDT 24 |
| Finished | Apr 21 04:32:36 PM PDT 24 |
| Peak memory | 200852 kb |
| Host | smart-fbfcda13-fbca-4653-82aa-5a2d00cd5ab6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251997556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.1251997556 |
| Directory | /workspace/34.uart_intr/latest |
| Test location | /workspace/coverage/default/34.uart_long_xfer_wo_dly.626526406 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 100457914126 ps |
| CPU time | 254.05 seconds |
| Started | Apr 21 04:32:34 PM PDT 24 |
| Finished | Apr 21 04:36:48 PM PDT 24 |
| Peak memory | 200936 kb |
| Host | smart-bf72419a-172e-4646-896e-5f7b35dfb3b3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=626526406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.626526406 |
| Directory | /workspace/34.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/34.uart_loopback.2470707747 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 7864941345 ps |
| CPU time | 5.54 seconds |
| Started | Apr 21 04:32:33 PM PDT 24 |
| Finished | Apr 21 04:32:39 PM PDT 24 |
| Peak memory | 199876 kb |
| Host | smart-d7ef888d-2b1b-4d30-9180-45ae43e9a689 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2470707747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.2470707747 |
| Directory | /workspace/34.uart_loopback/latest |
| Test location | /workspace/coverage/default/34.uart_noise_filter.2851217608 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 113170436485 ps |
| CPU time | 73.26 seconds |
| Started | Apr 21 04:32:32 PM PDT 24 |
| Finished | Apr 21 04:33:45 PM PDT 24 |
| Peak memory | 199896 kb |
| Host | smart-fe43767c-d0ca-4add-8f36-de4472530e40 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2851217608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.2851217608 |
| Directory | /workspace/34.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/34.uart_perf.2500823144 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 7433170441 ps |
| CPU time | 431.1 seconds |
| Started | Apr 21 04:32:34 PM PDT 24 |
| Finished | Apr 21 04:39:45 PM PDT 24 |
| Peak memory | 200880 kb |
| Host | smart-debe6252-617f-4abd-96fe-b7010dd25b76 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2500823144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.2500823144 |
| Directory | /workspace/34.uart_perf/latest |
| Test location | /workspace/coverage/default/34.uart_rx_oversample.3859047318 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 6232685036 ps |
| CPU time | 55.42 seconds |
| Started | Apr 21 04:32:30 PM PDT 24 |
| Finished | Apr 21 04:33:26 PM PDT 24 |
| Peak memory | 199048 kb |
| Host | smart-11589963-777b-45e0-8a3e-a3965fd8a0fd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3859047318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.3859047318 |
| Directory | /workspace/34.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/34.uart_rx_parity_err.4020993370 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 69625919594 ps |
| CPU time | 106.58 seconds |
| Started | Apr 21 04:32:32 PM PDT 24 |
| Finished | Apr 21 04:34:19 PM PDT 24 |
| Peak memory | 200896 kb |
| Host | smart-a531e4b8-24e0-489d-9f8c-aef6a808ba22 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4020993370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.4020993370 |
| Directory | /workspace/34.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/34.uart_rx_start_bit_filter.1170752305 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 1400586916 ps |
| CPU time | 1.67 seconds |
| Started | Apr 21 04:32:31 PM PDT 24 |
| Finished | Apr 21 04:32:33 PM PDT 24 |
| Peak memory | 196564 kb |
| Host | smart-ecbdb15c-056c-4429-ae74-e4e10bac0fd4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1170752305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.1170752305 |
| Directory | /workspace/34.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/34.uart_smoke.363358807 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 820011561 ps |
| CPU time | 2.43 seconds |
| Started | Apr 21 04:32:26 PM PDT 24 |
| Finished | Apr 21 04:32:29 PM PDT 24 |
| Peak memory | 200432 kb |
| Host | smart-34837330-9020-4946-8525-a3bebc45bded |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=363358807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.363358807 |
| Directory | /workspace/34.uart_smoke/latest |
| Test location | /workspace/coverage/default/34.uart_stress_all.2928521467 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 133534452198 ps |
| CPU time | 237.79 seconds |
| Started | Apr 21 04:32:35 PM PDT 24 |
| Finished | Apr 21 04:36:33 PM PDT 24 |
| Peak memory | 217228 kb |
| Host | smart-541ca360-6488-4a92-9a00-f127d70f47bf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928521467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.2928521467 |
| Directory | /workspace/34.uart_stress_all/latest |
| Test location | /workspace/coverage/default/34.uart_tx_ovrd.3218537213 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 575026932 ps |
| CPU time | 2.4 seconds |
| Started | Apr 21 04:32:30 PM PDT 24 |
| Finished | Apr 21 04:32:33 PM PDT 24 |
| Peak memory | 199616 kb |
| Host | smart-914fe4aa-41df-4447-8351-51b1a1da1da8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3218537213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.3218537213 |
| Directory | /workspace/34.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/34.uart_tx_rx.3888277878 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 23814007239 ps |
| CPU time | 41.99 seconds |
| Started | Apr 21 04:32:29 PM PDT 24 |
| Finished | Apr 21 04:33:12 PM PDT 24 |
| Peak memory | 200936 kb |
| Host | smart-a3f5cbb2-b3b3-4340-97f9-46c3f388fab4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3888277878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.3888277878 |
| Directory | /workspace/34.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/35.uart_alert_test.538922382 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 14632203 ps |
| CPU time | 0.56 seconds |
| Started | Apr 21 04:32:51 PM PDT 24 |
| Finished | Apr 21 04:32:52 PM PDT 24 |
| Peak memory | 196244 kb |
| Host | smart-d309af0f-77f6-4511-aed5-617c778f7a2d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538922382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.538922382 |
| Directory | /workspace/35.uart_alert_test/latest |
| Test location | /workspace/coverage/default/35.uart_fifo_full.1585446146 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 98714140582 ps |
| CPU time | 42.95 seconds |
| Started | Apr 21 04:32:35 PM PDT 24 |
| Finished | Apr 21 04:33:18 PM PDT 24 |
| Peak memory | 200920 kb |
| Host | smart-ff433803-53b2-4201-bbbd-bc6bfcc4753b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1585446146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.1585446146 |
| Directory | /workspace/35.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/35.uart_fifo_overflow.2694832539 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 27702593078 ps |
| CPU time | 23.18 seconds |
| Started | Apr 21 04:32:36 PM PDT 24 |
| Finished | Apr 21 04:33:00 PM PDT 24 |
| Peak memory | 200832 kb |
| Host | smart-1c7d1ded-49f5-4249-be84-56aeedcf0b2d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2694832539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.2694832539 |
| Directory | /workspace/35.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/35.uart_fifo_reset.1296296528 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 200968669340 ps |
| CPU time | 28.09 seconds |
| Started | Apr 21 04:32:40 PM PDT 24 |
| Finished | Apr 21 04:33:08 PM PDT 24 |
| Peak memory | 200932 kb |
| Host | smart-2e876594-f257-4558-86f2-d1b26548135b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1296296528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.1296296528 |
| Directory | /workspace/35.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/35.uart_intr.2642099038 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 16531033435 ps |
| CPU time | 7.08 seconds |
| Started | Apr 21 04:32:42 PM PDT 24 |
| Finished | Apr 21 04:32:49 PM PDT 24 |
| Peak memory | 200328 kb |
| Host | smart-7316aac8-fa41-4f8f-89af-66eac7b514c5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642099038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.2642099038 |
| Directory | /workspace/35.uart_intr/latest |
| Test location | /workspace/coverage/default/35.uart_long_xfer_wo_dly.263895615 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 62172664786 ps |
| CPU time | 183.85 seconds |
| Started | Apr 21 04:32:48 PM PDT 24 |
| Finished | Apr 21 04:35:52 PM PDT 24 |
| Peak memory | 200916 kb |
| Host | smart-b6fc7766-c748-4a40-a61a-3cf91906e128 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=263895615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.263895615 |
| Directory | /workspace/35.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/35.uart_loopback.3909859660 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 8208589410 ps |
| CPU time | 5.54 seconds |
| Started | Apr 21 04:32:49 PM PDT 24 |
| Finished | Apr 21 04:32:55 PM PDT 24 |
| Peak memory | 200196 kb |
| Host | smart-33f37077-f2c5-4afa-b62b-925e49f81aec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3909859660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3909859660 |
| Directory | /workspace/35.uart_loopback/latest |
| Test location | /workspace/coverage/default/35.uart_noise_filter.3764186938 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 164391445402 ps |
| CPU time | 74.54 seconds |
| Started | Apr 21 04:32:43 PM PDT 24 |
| Finished | Apr 21 04:33:57 PM PDT 24 |
| Peak memory | 201092 kb |
| Host | smart-975faa69-dfc8-48a8-8766-f22482d6271e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3764186938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.3764186938 |
| Directory | /workspace/35.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/35.uart_perf.2575339235 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 15352508412 ps |
| CPU time | 239.81 seconds |
| Started | Apr 21 04:32:49 PM PDT 24 |
| Finished | Apr 21 04:36:49 PM PDT 24 |
| Peak memory | 200824 kb |
| Host | smart-929f112a-f63e-44f7-8e94-03ad592397d4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2575339235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.2575339235 |
| Directory | /workspace/35.uart_perf/latest |
| Test location | /workspace/coverage/default/35.uart_rx_oversample.3612759920 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 6187680108 ps |
| CPU time | 45.49 seconds |
| Started | Apr 21 04:32:40 PM PDT 24 |
| Finished | Apr 21 04:33:26 PM PDT 24 |
| Peak memory | 198724 kb |
| Host | smart-d4b77ba9-1de3-48ce-811d-996cd9ca638f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3612759920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.3612759920 |
| Directory | /workspace/35.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/35.uart_rx_start_bit_filter.266878075 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 4645288486 ps |
| CPU time | 1.55 seconds |
| Started | Apr 21 04:32:43 PM PDT 24 |
| Finished | Apr 21 04:32:45 PM PDT 24 |
| Peak memory | 196956 kb |
| Host | smart-ee81b2d0-7fee-4d34-9cb3-c17c80abddbc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=266878075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.266878075 |
| Directory | /workspace/35.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/35.uart_smoke.2226381211 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 456580288 ps |
| CPU time | 1.39 seconds |
| Started | Apr 21 04:32:33 PM PDT 24 |
| Finished | Apr 21 04:32:35 PM PDT 24 |
| Peak memory | 199284 kb |
| Host | smart-e6f2f93f-b4de-4632-8c10-401c6478dde6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2226381211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.2226381211 |
| Directory | /workspace/35.uart_smoke/latest |
| Test location | /workspace/coverage/default/35.uart_stress_all.695485022 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 402390950007 ps |
| CPU time | 406.97 seconds |
| Started | Apr 21 04:32:51 PM PDT 24 |
| Finished | Apr 21 04:39:39 PM PDT 24 |
| Peak memory | 200860 kb |
| Host | smart-05a03d3f-ca62-480b-8386-dfd891429eef |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695485022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.695485022 |
| Directory | /workspace/35.uart_stress_all/latest |
| Test location | /workspace/coverage/default/35.uart_stress_all_with_rand_reset.3091740911 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 246822146625 ps |
| CPU time | 739.46 seconds |
| Started | Apr 21 04:32:49 PM PDT 24 |
| Finished | Apr 21 04:45:09 PM PDT 24 |
| Peak memory | 225896 kb |
| Host | smart-949653d4-9584-4b9d-b496-7ef822ebbe34 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091740911 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.3091740911 |
| Directory | /workspace/35.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/35.uart_tx_ovrd.1856467683 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 7331982759 ps |
| CPU time | 14.07 seconds |
| Started | Apr 21 04:32:45 PM PDT 24 |
| Finished | Apr 21 04:33:00 PM PDT 24 |
| Peak memory | 200764 kb |
| Host | smart-2ebd24f4-046a-4c72-988a-1c09d47f13e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1856467683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.1856467683 |
| Directory | /workspace/35.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/35.uart_tx_rx.2320189867 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 38695939283 ps |
| CPU time | 29.16 seconds |
| Started | Apr 21 04:32:35 PM PDT 24 |
| Finished | Apr 21 04:33:04 PM PDT 24 |
| Peak memory | 200900 kb |
| Host | smart-8030770a-a6ad-4ae3-8a70-afaa141ebcc4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2320189867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.2320189867 |
| Directory | /workspace/35.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/36.uart_alert_test.3164264788 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 15320715 ps |
| CPU time | 0.62 seconds |
| Started | Apr 21 04:33:04 PM PDT 24 |
| Finished | Apr 21 04:33:05 PM PDT 24 |
| Peak memory | 195148 kb |
| Host | smart-a9d7ea82-97e9-40b0-9685-6c788de2b95a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164264788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.3164264788 |
| Directory | /workspace/36.uart_alert_test/latest |
| Test location | /workspace/coverage/default/36.uart_fifo_full.3772592555 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 38403668427 ps |
| CPU time | 69.13 seconds |
| Started | Apr 21 04:32:52 PM PDT 24 |
| Finished | Apr 21 04:34:01 PM PDT 24 |
| Peak memory | 200924 kb |
| Host | smart-db6fefed-d360-4b16-a7c3-5e8d003b590d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3772592555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.3772592555 |
| Directory | /workspace/36.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/36.uart_fifo_overflow.2206424008 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 36714607969 ps |
| CPU time | 61.25 seconds |
| Started | Apr 21 04:32:54 PM PDT 24 |
| Finished | Apr 21 04:33:56 PM PDT 24 |
| Peak memory | 200904 kb |
| Host | smart-78fbf152-5905-45fe-9a4b-28aff3e1b811 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2206424008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.2206424008 |
| Directory | /workspace/36.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/36.uart_fifo_reset.4291412279 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 139153374455 ps |
| CPU time | 87.02 seconds |
| Started | Apr 21 04:32:53 PM PDT 24 |
| Finished | Apr 21 04:34:20 PM PDT 24 |
| Peak memory | 200776 kb |
| Host | smart-82b30e17-961b-450c-a2bd-9a2be2595258 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4291412279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.4291412279 |
| Directory | /workspace/36.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/36.uart_intr.354727896 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 282422488996 ps |
| CPU time | 466.12 seconds |
| Started | Apr 21 04:32:55 PM PDT 24 |
| Finished | Apr 21 04:40:41 PM PDT 24 |
| Peak memory | 200876 kb |
| Host | smart-8c181706-a770-45ee-870b-23c777496aa1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354727896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.354727896 |
| Directory | /workspace/36.uart_intr/latest |
| Test location | /workspace/coverage/default/36.uart_long_xfer_wo_dly.1474036447 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 39996968084 ps |
| CPU time | 115.86 seconds |
| Started | Apr 21 04:33:03 PM PDT 24 |
| Finished | Apr 21 04:34:59 PM PDT 24 |
| Peak memory | 200896 kb |
| Host | smart-10080e0b-8267-49e2-a545-fea7f59f4178 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1474036447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.1474036447 |
| Directory | /workspace/36.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/36.uart_loopback.1702388843 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 4471652223 ps |
| CPU time | 7.36 seconds |
| Started | Apr 21 04:32:59 PM PDT 24 |
| Finished | Apr 21 04:33:07 PM PDT 24 |
| Peak memory | 199652 kb |
| Host | smart-54c8a32b-24cc-436d-90a8-b6329e2c32aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1702388843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.1702388843 |
| Directory | /workspace/36.uart_loopback/latest |
| Test location | /workspace/coverage/default/36.uart_noise_filter.4145184096 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 51341482964 ps |
| CPU time | 82.43 seconds |
| Started | Apr 21 04:32:58 PM PDT 24 |
| Finished | Apr 21 04:34:21 PM PDT 24 |
| Peak memory | 201084 kb |
| Host | smart-26751b42-d89b-44a7-a84e-22e22a432f1b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4145184096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.4145184096 |
| Directory | /workspace/36.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/36.uart_perf.280151769 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 13702384618 ps |
| CPU time | 577.82 seconds |
| Started | Apr 21 04:32:59 PM PDT 24 |
| Finished | Apr 21 04:42:37 PM PDT 24 |
| Peak memory | 200832 kb |
| Host | smart-14fcf820-b850-4959-a234-a844ddb5d75b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=280151769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.280151769 |
| Directory | /workspace/36.uart_perf/latest |
| Test location | /workspace/coverage/default/36.uart_rx_oversample.3026682199 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 3605988343 ps |
| CPU time | 34.02 seconds |
| Started | Apr 21 04:32:55 PM PDT 24 |
| Finished | Apr 21 04:33:29 PM PDT 24 |
| Peak memory | 199032 kb |
| Host | smart-a86010c4-f825-4098-b0ff-06035b650434 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3026682199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3026682199 |
| Directory | /workspace/36.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/36.uart_rx_parity_err.1302574333 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 39203580100 ps |
| CPU time | 79.87 seconds |
| Started | Apr 21 04:32:57 PM PDT 24 |
| Finished | Apr 21 04:34:17 PM PDT 24 |
| Peak memory | 200844 kb |
| Host | smart-f65ad4b3-6921-478a-b0a2-a5d4498a4f89 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1302574333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.1302574333 |
| Directory | /workspace/36.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/36.uart_rx_start_bit_filter.1741939430 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 3867650362 ps |
| CPU time | 2.34 seconds |
| Started | Apr 21 04:32:57 PM PDT 24 |
| Finished | Apr 21 04:32:59 PM PDT 24 |
| Peak memory | 196916 kb |
| Host | smart-364d2186-68fc-4f06-a847-b2d04ac83c07 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1741939430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.1741939430 |
| Directory | /workspace/36.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/36.uart_smoke.2401924398 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 508205987 ps |
| CPU time | 2.33 seconds |
| Started | Apr 21 04:32:52 PM PDT 24 |
| Finished | Apr 21 04:32:54 PM PDT 24 |
| Peak memory | 200820 kb |
| Host | smart-73c3e879-cb34-4fa7-88c9-3bcfbdc4556d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2401924398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.2401924398 |
| Directory | /workspace/36.uart_smoke/latest |
| Test location | /workspace/coverage/default/36.uart_stress_all.2291125934 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 630627742987 ps |
| CPU time | 888.51 seconds |
| Started | Apr 21 04:33:03 PM PDT 24 |
| Finished | Apr 21 04:47:52 PM PDT 24 |
| Peak memory | 200884 kb |
| Host | smart-5fa1525d-d391-4bea-b1a2-d556b5781457 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291125934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.2291125934 |
| Directory | /workspace/36.uart_stress_all/latest |
| Test location | /workspace/coverage/default/36.uart_stress_all_with_rand_reset.3466778492 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 21965355324 ps |
| CPU time | 94.09 seconds |
| Started | Apr 21 04:33:02 PM PDT 24 |
| Finished | Apr 21 04:34:36 PM PDT 24 |
| Peak memory | 209456 kb |
| Host | smart-365d9c9f-1aab-45a5-9bc5-d9a489e1dfa0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466778492 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.3466778492 |
| Directory | /workspace/36.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/36.uart_tx_ovrd.3568733424 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 1783121872 ps |
| CPU time | 1.6 seconds |
| Started | Apr 21 04:32:58 PM PDT 24 |
| Finished | Apr 21 04:32:59 PM PDT 24 |
| Peak memory | 199308 kb |
| Host | smart-b04dd8f7-7bac-46f4-92d4-3d0eb3a6ea1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3568733424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3568733424 |
| Directory | /workspace/36.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/36.uart_tx_rx.665671997 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 36653507693 ps |
| CPU time | 18.16 seconds |
| Started | Apr 21 04:32:53 PM PDT 24 |
| Finished | Apr 21 04:33:12 PM PDT 24 |
| Peak memory | 200824 kb |
| Host | smart-3f9bc593-419d-4804-b88b-6c5bac19e289 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=665671997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.665671997 |
| Directory | /workspace/36.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/37.uart_alert_test.3826322527 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 74772455 ps |
| CPU time | 0.56 seconds |
| Started | Apr 21 04:33:15 PM PDT 24 |
| Finished | Apr 21 04:33:15 PM PDT 24 |
| Peak memory | 196208 kb |
| Host | smart-a08f4f1a-3832-47f3-9b9b-d8a0ef50ec0c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826322527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.3826322527 |
| Directory | /workspace/37.uart_alert_test/latest |
| Test location | /workspace/coverage/default/37.uart_fifo_full.2220179763 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 17262428825 ps |
| CPU time | 26.94 seconds |
| Started | Apr 21 04:33:06 PM PDT 24 |
| Finished | Apr 21 04:33:33 PM PDT 24 |
| Peak memory | 200844 kb |
| Host | smart-8fdcabb9-1264-40bc-a38d-0a9ffb9ecc9f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2220179763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.2220179763 |
| Directory | /workspace/37.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/37.uart_fifo_overflow.3903644651 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 31846164843 ps |
| CPU time | 60.91 seconds |
| Started | Apr 21 04:33:04 PM PDT 24 |
| Finished | Apr 21 04:34:05 PM PDT 24 |
| Peak memory | 200908 kb |
| Host | smart-885a9146-b74e-475d-a98d-dc24dc06aeef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3903644651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.3903644651 |
| Directory | /workspace/37.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/37.uart_fifo_reset.3420634948 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 110547572720 ps |
| CPU time | 173.21 seconds |
| Started | Apr 21 04:33:06 PM PDT 24 |
| Finished | Apr 21 04:35:59 PM PDT 24 |
| Peak memory | 200844 kb |
| Host | smart-270bd4ec-318f-4036-a704-4d159f20f746 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3420634948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.3420634948 |
| Directory | /workspace/37.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/37.uart_intr.3871969027 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 26851344508 ps |
| CPU time | 7.29 seconds |
| Started | Apr 21 04:33:06 PM PDT 24 |
| Finished | Apr 21 04:33:14 PM PDT 24 |
| Peak memory | 200904 kb |
| Host | smart-12b02013-3bfe-4550-bebb-6d0d3f0f7270 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871969027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.3871969027 |
| Directory | /workspace/37.uart_intr/latest |
| Test location | /workspace/coverage/default/37.uart_long_xfer_wo_dly.3748255549 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 109121217097 ps |
| CPU time | 923.98 seconds |
| Started | Apr 21 04:33:12 PM PDT 24 |
| Finished | Apr 21 04:48:36 PM PDT 24 |
| Peak memory | 200916 kb |
| Host | smart-475e0c7f-330c-490b-b897-8421a05978fe |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3748255549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.3748255549 |
| Directory | /workspace/37.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/37.uart_loopback.1881246997 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 7217104754 ps |
| CPU time | 11.74 seconds |
| Started | Apr 21 04:33:10 PM PDT 24 |
| Finished | Apr 21 04:33:22 PM PDT 24 |
| Peak memory | 199284 kb |
| Host | smart-000d5d96-436d-4f7a-810b-8955342e036d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1881246997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.1881246997 |
| Directory | /workspace/37.uart_loopback/latest |
| Test location | /workspace/coverage/default/37.uart_noise_filter.2749802210 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 16170032292 ps |
| CPU time | 27.3 seconds |
| Started | Apr 21 04:33:06 PM PDT 24 |
| Finished | Apr 21 04:33:34 PM PDT 24 |
| Peak memory | 199084 kb |
| Host | smart-64a3fe50-e25b-4705-be52-d2cad16bbe61 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2749802210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.2749802210 |
| Directory | /workspace/37.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/37.uart_perf.1557297612 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 3125895393 ps |
| CPU time | 48.84 seconds |
| Started | Apr 21 04:33:10 PM PDT 24 |
| Finished | Apr 21 04:34:00 PM PDT 24 |
| Peak memory | 200796 kb |
| Host | smart-dc01fa6c-2645-4fce-83ce-934f11e38c4d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1557297612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.1557297612 |
| Directory | /workspace/37.uart_perf/latest |
| Test location | /workspace/coverage/default/37.uart_rx_oversample.1828211818 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 4801232481 ps |
| CPU time | 10.06 seconds |
| Started | Apr 21 04:33:06 PM PDT 24 |
| Finished | Apr 21 04:33:17 PM PDT 24 |
| Peak memory | 200096 kb |
| Host | smart-6110fa75-f093-4ead-9560-f02809189529 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1828211818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.1828211818 |
| Directory | /workspace/37.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/37.uart_rx_parity_err.4138687204 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 141092027526 ps |
| CPU time | 28.86 seconds |
| Started | Apr 21 04:33:06 PM PDT 24 |
| Finished | Apr 21 04:33:35 PM PDT 24 |
| Peak memory | 200844 kb |
| Host | smart-ee5a3f0b-d11b-4af4-82c2-8917eee29910 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4138687204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.4138687204 |
| Directory | /workspace/37.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/37.uart_rx_start_bit_filter.2941602210 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 33240852834 ps |
| CPU time | 10.04 seconds |
| Started | Apr 21 04:33:06 PM PDT 24 |
| Finished | Apr 21 04:33:17 PM PDT 24 |
| Peak memory | 196968 kb |
| Host | smart-a4eb93eb-7ccb-4fe5-8d48-333910d4977f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2941602210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.2941602210 |
| Directory | /workspace/37.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/37.uart_smoke.1131902018 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 467787164 ps |
| CPU time | 1.88 seconds |
| Started | Apr 21 04:33:04 PM PDT 24 |
| Finished | Apr 21 04:33:06 PM PDT 24 |
| Peak memory | 199716 kb |
| Host | smart-50f0f0e0-bb32-4eb5-8f7d-7de9ff4b3ffc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1131902018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.1131902018 |
| Directory | /workspace/37.uart_smoke/latest |
| Test location | /workspace/coverage/default/37.uart_stress_all.4280689651 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 251052060005 ps |
| CPU time | 445.72 seconds |
| Started | Apr 21 04:33:15 PM PDT 24 |
| Finished | Apr 21 04:40:41 PM PDT 24 |
| Peak memory | 200820 kb |
| Host | smart-4ab1e96b-906f-40dd-a55d-9f225d18c809 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280689651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.4280689651 |
| Directory | /workspace/37.uart_stress_all/latest |
| Test location | /workspace/coverage/default/37.uart_stress_all_with_rand_reset.3710948220 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 68154382455 ps |
| CPU time | 1819.19 seconds |
| Started | Apr 21 04:33:11 PM PDT 24 |
| Finished | Apr 21 05:03:31 PM PDT 24 |
| Peak memory | 225436 kb |
| Host | smart-8d907fae-5713-4dd7-829a-e608b3da7c9e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710948220 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.3710948220 |
| Directory | /workspace/37.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/37.uart_tx_ovrd.2588914668 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 1785090941 ps |
| CPU time | 1.75 seconds |
| Started | Apr 21 04:33:09 PM PDT 24 |
| Finished | Apr 21 04:33:11 PM PDT 24 |
| Peak memory | 199224 kb |
| Host | smart-2123852e-9b0b-4d1a-9cf1-84530292516b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2588914668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.2588914668 |
| Directory | /workspace/37.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/37.uart_tx_rx.573549207 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 98528386362 ps |
| CPU time | 92.15 seconds |
| Started | Apr 21 04:33:05 PM PDT 24 |
| Finished | Apr 21 04:34:37 PM PDT 24 |
| Peak memory | 200828 kb |
| Host | smart-838901c6-b35b-4e88-adf3-4aab62dd43f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=573549207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.573549207 |
| Directory | /workspace/37.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/38.uart_alert_test.1732314652 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 38395776 ps |
| CPU time | 0.56 seconds |
| Started | Apr 21 04:33:32 PM PDT 24 |
| Finished | Apr 21 04:33:32 PM PDT 24 |
| Peak memory | 196244 kb |
| Host | smart-86297e52-dcf3-41e8-9827-2772702793cd |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732314652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.1732314652 |
| Directory | /workspace/38.uart_alert_test/latest |
| Test location | /workspace/coverage/default/38.uart_fifo_full.258211405 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 20088984628 ps |
| CPU time | 30.55 seconds |
| Started | Apr 21 04:33:18 PM PDT 24 |
| Finished | Apr 21 04:33:48 PM PDT 24 |
| Peak memory | 200884 kb |
| Host | smart-db65a717-5b2f-4665-bdfb-870e48ec1d38 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=258211405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.258211405 |
| Directory | /workspace/38.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/38.uart_fifo_overflow.3755188020 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 90457226978 ps |
| CPU time | 50.71 seconds |
| Started | Apr 21 04:33:18 PM PDT 24 |
| Finished | Apr 21 04:34:09 PM PDT 24 |
| Peak memory | 200936 kb |
| Host | smart-3501ffc1-bdb6-4024-a8b1-943df3dfe115 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3755188020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.3755188020 |
| Directory | /workspace/38.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/38.uart_fifo_reset.4328793 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 13086222726 ps |
| CPU time | 23.14 seconds |
| Started | Apr 21 04:33:20 PM PDT 24 |
| Finished | Apr 21 04:33:44 PM PDT 24 |
| Peak memory | 200896 kb |
| Host | smart-d8f94beb-3482-4b3a-b5e0-b116c199e087 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4328793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.4328793 |
| Directory | /workspace/38.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/38.uart_intr.2963843263 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 47072934026 ps |
| CPU time | 18.81 seconds |
| Started | Apr 21 04:33:19 PM PDT 24 |
| Finished | Apr 21 04:33:38 PM PDT 24 |
| Peak memory | 200816 kb |
| Host | smart-a3fdedcb-9d9a-4757-a3db-6de8ce97e577 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963843263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.2963843263 |
| Directory | /workspace/38.uart_intr/latest |
| Test location | /workspace/coverage/default/38.uart_long_xfer_wo_dly.3158752421 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 46937845610 ps |
| CPU time | 160.55 seconds |
| Started | Apr 21 04:33:26 PM PDT 24 |
| Finished | Apr 21 04:36:07 PM PDT 24 |
| Peak memory | 200852 kb |
| Host | smart-6efd83e2-0a17-46f3-98c4-6707285487ac |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3158752421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.3158752421 |
| Directory | /workspace/38.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/38.uart_loopback.3886961149 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 5813608720 ps |
| CPU time | 7.43 seconds |
| Started | Apr 21 04:33:23 PM PDT 24 |
| Finished | Apr 21 04:33:31 PM PDT 24 |
| Peak memory | 199608 kb |
| Host | smart-de0ec8b4-0986-4cf5-a4ea-f3e5d1abe461 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3886961149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.3886961149 |
| Directory | /workspace/38.uart_loopback/latest |
| Test location | /workspace/coverage/default/38.uart_noise_filter.3990833015 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 27888679222 ps |
| CPU time | 19.12 seconds |
| Started | Apr 21 04:33:22 PM PDT 24 |
| Finished | Apr 21 04:33:41 PM PDT 24 |
| Peak memory | 199152 kb |
| Host | smart-b70c8bb4-731d-44a2-87dd-528c22fdba23 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3990833015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.3990833015 |
| Directory | /workspace/38.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/38.uart_perf.2166609836 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 6191798788 ps |
| CPU time | 292.02 seconds |
| Started | Apr 21 04:33:23 PM PDT 24 |
| Finished | Apr 21 04:38:15 PM PDT 24 |
| Peak memory | 200824 kb |
| Host | smart-2727f158-5076-4742-b68c-0f750ce5c386 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2166609836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.2166609836 |
| Directory | /workspace/38.uart_perf/latest |
| Test location | /workspace/coverage/default/38.uart_rx_oversample.153830006 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 5228978038 ps |
| CPU time | 3.34 seconds |
| Started | Apr 21 04:33:22 PM PDT 24 |
| Finished | Apr 21 04:33:25 PM PDT 24 |
| Peak memory | 199476 kb |
| Host | smart-a0005ad0-d0a9-4155-b230-1f21bb21d3e9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=153830006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.153830006 |
| Directory | /workspace/38.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/38.uart_rx_parity_err.2556540015 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 113200374406 ps |
| CPU time | 39.27 seconds |
| Started | Apr 21 04:33:22 PM PDT 24 |
| Finished | Apr 21 04:34:02 PM PDT 24 |
| Peak memory | 200816 kb |
| Host | smart-0e1edc3b-03d8-4fbd-af44-6d318068f4a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2556540015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.2556540015 |
| Directory | /workspace/38.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/38.uart_rx_start_bit_filter.4215941421 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 34952819646 ps |
| CPU time | 14.68 seconds |
| Started | Apr 21 04:33:22 PM PDT 24 |
| Finished | Apr 21 04:33:37 PM PDT 24 |
| Peak memory | 197224 kb |
| Host | smart-bf00849b-a89e-4683-b6ab-7f16148e6682 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4215941421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.4215941421 |
| Directory | /workspace/38.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/38.uart_smoke.3152508127 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 532383869 ps |
| CPU time | 2.18 seconds |
| Started | Apr 21 04:33:15 PM PDT 24 |
| Finished | Apr 21 04:33:18 PM PDT 24 |
| Peak memory | 199204 kb |
| Host | smart-d80438ec-50db-424b-a5e0-d953e9d08248 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3152508127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.3152508127 |
| Directory | /workspace/38.uart_smoke/latest |
| Test location | /workspace/coverage/default/38.uart_stress_all.1249622148 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 197389097327 ps |
| CPU time | 994.96 seconds |
| Started | Apr 21 04:33:28 PM PDT 24 |
| Finished | Apr 21 04:50:03 PM PDT 24 |
| Peak memory | 200904 kb |
| Host | smart-54e9d58f-c060-4a41-b3c1-6b44602e7338 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249622148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.1249622148 |
| Directory | /workspace/38.uart_stress_all/latest |
| Test location | /workspace/coverage/default/38.uart_stress_all_with_rand_reset.4217160130 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 163857477288 ps |
| CPU time | 996.6 seconds |
| Started | Apr 21 04:33:26 PM PDT 24 |
| Finished | Apr 21 04:50:03 PM PDT 24 |
| Peak memory | 217360 kb |
| Host | smart-17107a5f-72cb-4bfc-8f86-59eca60e049b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217160130 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.4217160130 |
| Directory | /workspace/38.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/38.uart_tx_ovrd.671707002 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 1699377278 ps |
| CPU time | 3.57 seconds |
| Started | Apr 21 04:33:23 PM PDT 24 |
| Finished | Apr 21 04:33:27 PM PDT 24 |
| Peak memory | 199804 kb |
| Host | smart-784bcc44-f148-49f0-a7a9-82b57b33732e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=671707002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.671707002 |
| Directory | /workspace/38.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/38.uart_tx_rx.3198256258 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 86227298422 ps |
| CPU time | 153.79 seconds |
| Started | Apr 21 04:33:14 PM PDT 24 |
| Finished | Apr 21 04:35:48 PM PDT 24 |
| Peak memory | 200912 kb |
| Host | smart-7ead50cb-36cd-4d01-9ff2-991d5b60e139 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3198256258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.3198256258 |
| Directory | /workspace/38.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/39.uart_alert_test.2917530582 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 11668745 ps |
| CPU time | 0.58 seconds |
| Started | Apr 21 04:33:37 PM PDT 24 |
| Finished | Apr 21 04:33:38 PM PDT 24 |
| Peak memory | 196244 kb |
| Host | smart-349a1845-b5bd-4d70-a08a-ec05679a8df2 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917530582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.2917530582 |
| Directory | /workspace/39.uart_alert_test/latest |
| Test location | /workspace/coverage/default/39.uart_fifo_full.750265893 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 132044616942 ps |
| CPU time | 58.49 seconds |
| Started | Apr 21 04:33:29 PM PDT 24 |
| Finished | Apr 21 04:34:28 PM PDT 24 |
| Peak memory | 200864 kb |
| Host | smart-267d3757-b1c8-4cc9-8008-ccf6d2c99f8f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=750265893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.750265893 |
| Directory | /workspace/39.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/39.uart_fifo_overflow.574244109 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 163407507465 ps |
| CPU time | 28.91 seconds |
| Started | Apr 21 04:33:35 PM PDT 24 |
| Finished | Apr 21 04:34:04 PM PDT 24 |
| Peak memory | 200900 kb |
| Host | smart-3bdbe5a3-26cb-4b93-a4cb-3740dbae313d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=574244109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.574244109 |
| Directory | /workspace/39.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/39.uart_fifo_reset.3762576356 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 46217134374 ps |
| CPU time | 69.23 seconds |
| Started | Apr 21 04:33:32 PM PDT 24 |
| Finished | Apr 21 04:34:42 PM PDT 24 |
| Peak memory | 200884 kb |
| Host | smart-2dc66dc9-3efa-424e-841b-ae407586b98e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3762576356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.3762576356 |
| Directory | /workspace/39.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/39.uart_intr.2777486414 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 1907057520 ps |
| CPU time | 2.93 seconds |
| Started | Apr 21 04:33:31 PM PDT 24 |
| Finished | Apr 21 04:33:34 PM PDT 24 |
| Peak memory | 201000 kb |
| Host | smart-87447973-b1fc-4bec-b370-1f9ab302096c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777486414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.2777486414 |
| Directory | /workspace/39.uart_intr/latest |
| Test location | /workspace/coverage/default/39.uart_long_xfer_wo_dly.2750845275 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 113782972334 ps |
| CPU time | 726.56 seconds |
| Started | Apr 21 04:33:34 PM PDT 24 |
| Finished | Apr 21 04:45:41 PM PDT 24 |
| Peak memory | 200860 kb |
| Host | smart-81822528-c3c9-4cf8-a989-c072d0e3b194 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2750845275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.2750845275 |
| Directory | /workspace/39.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/39.uart_loopback.4047605275 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 2614504840 ps |
| CPU time | 2.96 seconds |
| Started | Apr 21 04:33:32 PM PDT 24 |
| Finished | Apr 21 04:33:35 PM PDT 24 |
| Peak memory | 200032 kb |
| Host | smart-7a86b191-9322-48b9-80a0-519def492f10 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4047605275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.4047605275 |
| Directory | /workspace/39.uart_loopback/latest |
| Test location | /workspace/coverage/default/39.uart_noise_filter.903046082 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 116642514119 ps |
| CPU time | 44.33 seconds |
| Started | Apr 21 04:33:32 PM PDT 24 |
| Finished | Apr 21 04:34:16 PM PDT 24 |
| Peak memory | 200600 kb |
| Host | smart-3a7c22d7-dc24-4428-bfd3-8d668fc7721e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=903046082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.903046082 |
| Directory | /workspace/39.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/39.uart_perf.510354937 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 3979090403 ps |
| CPU time | 45.97 seconds |
| Started | Apr 21 04:33:32 PM PDT 24 |
| Finished | Apr 21 04:34:19 PM PDT 24 |
| Peak memory | 200944 kb |
| Host | smart-6ec5a443-114f-49fa-98c7-fcb9b335f74f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=510354937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.510354937 |
| Directory | /workspace/39.uart_perf/latest |
| Test location | /workspace/coverage/default/39.uart_rx_oversample.1612033306 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 7213652958 ps |
| CPU time | 32.58 seconds |
| Started | Apr 21 04:33:32 PM PDT 24 |
| Finished | Apr 21 04:34:05 PM PDT 24 |
| Peak memory | 199568 kb |
| Host | smart-b7872c80-d1b1-4cdc-973c-8490c8fbce2a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1612033306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.1612033306 |
| Directory | /workspace/39.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/39.uart_rx_parity_err.3407540910 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 17150576148 ps |
| CPU time | 29.46 seconds |
| Started | Apr 21 04:33:34 PM PDT 24 |
| Finished | Apr 21 04:34:03 PM PDT 24 |
| Peak memory | 200840 kb |
| Host | smart-58a1857b-4ddd-4423-8471-49716fcec20f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3407540910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.3407540910 |
| Directory | /workspace/39.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/39.uart_rx_start_bit_filter.184121935 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 4302993678 ps |
| CPU time | 7.39 seconds |
| Started | Apr 21 04:33:34 PM PDT 24 |
| Finished | Apr 21 04:33:42 PM PDT 24 |
| Peak memory | 196928 kb |
| Host | smart-09653741-1dc6-4c37-b8fd-b6c27fe9bbe5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=184121935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.184121935 |
| Directory | /workspace/39.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/39.uart_smoke.3098966301 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 492578720 ps |
| CPU time | 1.97 seconds |
| Started | Apr 21 04:33:29 PM PDT 24 |
| Finished | Apr 21 04:33:31 PM PDT 24 |
| Peak memory | 199580 kb |
| Host | smart-ea084f8b-163f-442a-9950-01e1a1cdfa4a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3098966301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.3098966301 |
| Directory | /workspace/39.uart_smoke/latest |
| Test location | /workspace/coverage/default/39.uart_stress_all_with_rand_reset.3894270683 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 234135511494 ps |
| CPU time | 432.77 seconds |
| Started | Apr 21 04:33:38 PM PDT 24 |
| Finished | Apr 21 04:40:51 PM PDT 24 |
| Peak memory | 217568 kb |
| Host | smart-01a77088-9645-42af-a2ea-2a78ce2696a8 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894270683 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.3894270683 |
| Directory | /workspace/39.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/39.uart_tx_ovrd.1116560854 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 841854205 ps |
| CPU time | 1.41 seconds |
| Started | Apr 21 04:33:34 PM PDT 24 |
| Finished | Apr 21 04:33:36 PM PDT 24 |
| Peak memory | 199612 kb |
| Host | smart-f059ebb5-f140-4ada-8d96-501b030a4e50 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1116560854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1116560854 |
| Directory | /workspace/39.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/39.uart_tx_rx.2101346801 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 53732015630 ps |
| CPU time | 18.67 seconds |
| Started | Apr 21 04:33:27 PM PDT 24 |
| Finished | Apr 21 04:33:46 PM PDT 24 |
| Peak memory | 200848 kb |
| Host | smart-88fbf736-91bb-4cdb-a4c4-ba61ce4fe324 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2101346801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.2101346801 |
| Directory | /workspace/39.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/4.uart_alert_test.339876099 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 123877487 ps |
| CPU time | 0.56 seconds |
| Started | Apr 21 04:26:24 PM PDT 24 |
| Finished | Apr 21 04:26:25 PM PDT 24 |
| Peak memory | 195164 kb |
| Host | smart-7bbe8f88-09cf-4de9-be3c-caeaaa350824 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339876099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.339876099 |
| Directory | /workspace/4.uart_alert_test/latest |
| Test location | /workspace/coverage/default/4.uart_fifo_full.251294146 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 34315462997 ps |
| CPU time | 15.56 seconds |
| Started | Apr 21 04:26:14 PM PDT 24 |
| Finished | Apr 21 04:26:29 PM PDT 24 |
| Peak memory | 200956 kb |
| Host | smart-52bd1e1f-d3c6-4733-ba44-3b53f56ec088 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=251294146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.251294146 |
| Directory | /workspace/4.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/4.uart_fifo_overflow.619690769 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 34215061993 ps |
| CPU time | 19.08 seconds |
| Started | Apr 21 04:26:14 PM PDT 24 |
| Finished | Apr 21 04:26:33 PM PDT 24 |
| Peak memory | 200852 kb |
| Host | smart-a78de7bb-9e25-4f1e-963c-59c6132d6715 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=619690769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.619690769 |
| Directory | /workspace/4.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/4.uart_fifo_reset.1642788137 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 90107060623 ps |
| CPU time | 41.55 seconds |
| Started | Apr 21 04:26:12 PM PDT 24 |
| Finished | Apr 21 04:26:54 PM PDT 24 |
| Peak memory | 200832 kb |
| Host | smart-178b5831-ddef-42df-8543-8f38c5d81204 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1642788137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.1642788137 |
| Directory | /workspace/4.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/4.uart_intr.1140074799 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 56104038772 ps |
| CPU time | 45.42 seconds |
| Started | Apr 21 04:26:24 PM PDT 24 |
| Finished | Apr 21 04:27:10 PM PDT 24 |
| Peak memory | 200892 kb |
| Host | smart-9f65ab6c-4a52-4d63-ad2c-c93e276dd9ad |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140074799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.1140074799 |
| Directory | /workspace/4.uart_intr/latest |
| Test location | /workspace/coverage/default/4.uart_long_xfer_wo_dly.2973343605 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 112896556860 ps |
| CPU time | 454.15 seconds |
| Started | Apr 21 04:26:25 PM PDT 24 |
| Finished | Apr 21 04:33:59 PM PDT 24 |
| Peak memory | 200808 kb |
| Host | smart-54a30d37-0c21-4ee0-afc5-0c4ef978f684 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2973343605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.2973343605 |
| Directory | /workspace/4.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/4.uart_loopback.2212876100 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 6440116888 ps |
| CPU time | 12.47 seconds |
| Started | Apr 21 04:26:20 PM PDT 24 |
| Finished | Apr 21 04:26:33 PM PDT 24 |
| Peak memory | 200920 kb |
| Host | smart-a0920b0a-bcf3-4cf6-8f93-3090ed83304e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2212876100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.2212876100 |
| Directory | /workspace/4.uart_loopback/latest |
| Test location | /workspace/coverage/default/4.uart_noise_filter.3746630543 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 22490774964 ps |
| CPU time | 18.68 seconds |
| Started | Apr 21 04:26:19 PM PDT 24 |
| Finished | Apr 21 04:26:38 PM PDT 24 |
| Peak memory | 201012 kb |
| Host | smart-b1ad72ea-d430-41bc-afc3-6f6b81085357 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3746630543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.3746630543 |
| Directory | /workspace/4.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/4.uart_perf.3038212915 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 8201308683 ps |
| CPU time | 393.36 seconds |
| Started | Apr 21 04:26:24 PM PDT 24 |
| Finished | Apr 21 04:32:58 PM PDT 24 |
| Peak memory | 200892 kb |
| Host | smart-9c3c12a9-2013-4950-86f1-0048fb0c5c78 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3038212915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.3038212915 |
| Directory | /workspace/4.uart_perf/latest |
| Test location | /workspace/coverage/default/4.uart_rx_oversample.1845594914 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 2503138792 ps |
| CPU time | 8.3 seconds |
| Started | Apr 21 04:26:16 PM PDT 24 |
| Finished | Apr 21 04:26:24 PM PDT 24 |
| Peak memory | 199300 kb |
| Host | smart-281b03c6-0ead-4d1a-9d1d-4a67bb25bd49 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1845594914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.1845594914 |
| Directory | /workspace/4.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/4.uart_rx_parity_err.3053815853 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 22322406894 ps |
| CPU time | 38.38 seconds |
| Started | Apr 21 04:26:24 PM PDT 24 |
| Finished | Apr 21 04:27:03 PM PDT 24 |
| Peak memory | 200552 kb |
| Host | smart-df13e14f-a55c-4edd-aae6-b0ec261b4c2f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3053815853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.3053815853 |
| Directory | /workspace/4.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/4.uart_rx_start_bit_filter.2695795138 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 38604708603 ps |
| CPU time | 17.2 seconds |
| Started | Apr 21 04:26:17 PM PDT 24 |
| Finished | Apr 21 04:26:34 PM PDT 24 |
| Peak memory | 196652 kb |
| Host | smart-c2a0128f-b06a-45b7-8f88-4201f3b38601 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2695795138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.2695795138 |
| Directory | /workspace/4.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/4.uart_sec_cm.1149462151 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 53165388 ps |
| CPU time | 0.84 seconds |
| Started | Apr 21 04:26:25 PM PDT 24 |
| Finished | Apr 21 04:26:26 PM PDT 24 |
| Peak memory | 218696 kb |
| Host | smart-caa24109-ad72-4534-bf23-47ec7afcfc02 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149462151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.1149462151 |
| Directory | /workspace/4.uart_sec_cm/latest |
| Test location | /workspace/coverage/default/4.uart_smoke.350031733 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 688242232 ps |
| CPU time | 3.17 seconds |
| Started | Apr 21 04:26:14 PM PDT 24 |
| Finished | Apr 21 04:26:18 PM PDT 24 |
| Peak memory | 200236 kb |
| Host | smart-00651db3-d12e-4059-9ec5-9ffbc44c8426 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=350031733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.350031733 |
| Directory | /workspace/4.uart_smoke/latest |
| Test location | /workspace/coverage/default/4.uart_tx_ovrd.3642740479 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 504406724 ps |
| CPU time | 1.46 seconds |
| Started | Apr 21 04:26:20 PM PDT 24 |
| Finished | Apr 21 04:26:22 PM PDT 24 |
| Peak memory | 197852 kb |
| Host | smart-e7b3d81a-3cf8-4d8e-950e-0660cc5c42cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3642740479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.3642740479 |
| Directory | /workspace/4.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/4.uart_tx_rx.3312870693 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 77213385945 ps |
| CPU time | 32.2 seconds |
| Started | Apr 21 04:26:13 PM PDT 24 |
| Finished | Apr 21 04:26:46 PM PDT 24 |
| Peak memory | 200784 kb |
| Host | smart-0b372444-c150-4ed6-96c1-2f68046b998c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3312870693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3312870693 |
| Directory | /workspace/4.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/40.uart_alert_test.2856351374 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 14129950 ps |
| CPU time | 0.58 seconds |
| Started | Apr 21 04:33:49 PM PDT 24 |
| Finished | Apr 21 04:33:50 PM PDT 24 |
| Peak memory | 196248 kb |
| Host | smart-97942eb6-d19e-4fa9-8d55-61c8e8568e78 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856351374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.2856351374 |
| Directory | /workspace/40.uart_alert_test/latest |
| Test location | /workspace/coverage/default/40.uart_fifo_full.1423579732 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 163364563252 ps |
| CPU time | 70.31 seconds |
| Started | Apr 21 04:33:40 PM PDT 24 |
| Finished | Apr 21 04:34:50 PM PDT 24 |
| Peak memory | 200928 kb |
| Host | smart-65f54ad0-cd37-4b8b-8a2a-388053a8978d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1423579732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.1423579732 |
| Directory | /workspace/40.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/40.uart_fifo_overflow.1535952197 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 131490237500 ps |
| CPU time | 72.95 seconds |
| Started | Apr 21 04:33:43 PM PDT 24 |
| Finished | Apr 21 04:34:56 PM PDT 24 |
| Peak memory | 200912 kb |
| Host | smart-86f54581-e7ed-4754-b24a-8205867e6c2a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1535952197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.1535952197 |
| Directory | /workspace/40.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/40.uart_fifo_reset.815483440 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 71196644588 ps |
| CPU time | 364.68 seconds |
| Started | Apr 21 04:33:41 PM PDT 24 |
| Finished | Apr 21 04:39:46 PM PDT 24 |
| Peak memory | 200848 kb |
| Host | smart-0368f5af-d14a-4056-bf20-5a2a9d9e06d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=815483440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.815483440 |
| Directory | /workspace/40.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/40.uart_intr.3583467522 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 205646426353 ps |
| CPU time | 28.03 seconds |
| Started | Apr 21 04:33:43 PM PDT 24 |
| Finished | Apr 21 04:34:12 PM PDT 24 |
| Peak memory | 199268 kb |
| Host | smart-af62b4d7-ee24-44bd-b611-78931a030a10 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583467522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.3583467522 |
| Directory | /workspace/40.uart_intr/latest |
| Test location | /workspace/coverage/default/40.uart_long_xfer_wo_dly.459893904 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 236049121244 ps |
| CPU time | 357.87 seconds |
| Started | Apr 21 04:33:47 PM PDT 24 |
| Finished | Apr 21 04:39:45 PM PDT 24 |
| Peak memory | 200892 kb |
| Host | smart-26258eae-3a82-4755-9b1f-d21a14036a0c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=459893904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.459893904 |
| Directory | /workspace/40.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/40.uart_loopback.3163192281 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 7759953858 ps |
| CPU time | 16.94 seconds |
| Started | Apr 21 04:33:49 PM PDT 24 |
| Finished | Apr 21 04:34:06 PM PDT 24 |
| Peak memory | 200844 kb |
| Host | smart-9ab3e28e-67c6-4ff3-b641-1622a3bde23b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3163192281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.3163192281 |
| Directory | /workspace/40.uart_loopback/latest |
| Test location | /workspace/coverage/default/40.uart_noise_filter.2748978241 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 44023535223 ps |
| CPU time | 42.15 seconds |
| Started | Apr 21 04:33:41 PM PDT 24 |
| Finished | Apr 21 04:34:24 PM PDT 24 |
| Peak memory | 199444 kb |
| Host | smart-b715f742-d2d4-4fd4-ae59-9db0c51f3b80 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2748978241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.2748978241 |
| Directory | /workspace/40.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/40.uart_perf.1439060681 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 7566533948 ps |
| CPU time | 243.97 seconds |
| Started | Apr 21 04:33:47 PM PDT 24 |
| Finished | Apr 21 04:37:51 PM PDT 24 |
| Peak memory | 200880 kb |
| Host | smart-dcf72f69-780c-443a-85b1-1f9c3bc450c0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1439060681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.1439060681 |
| Directory | /workspace/40.uart_perf/latest |
| Test location | /workspace/coverage/default/40.uart_rx_oversample.2523001306 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 4884027128 ps |
| CPU time | 45.62 seconds |
| Started | Apr 21 04:33:41 PM PDT 24 |
| Finished | Apr 21 04:34:27 PM PDT 24 |
| Peak memory | 200280 kb |
| Host | smart-a5caa621-ced9-49b1-a35d-f0d16903e367 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2523001306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.2523001306 |
| Directory | /workspace/40.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/40.uart_rx_parity_err.2922462497 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 78199579940 ps |
| CPU time | 89.25 seconds |
| Started | Apr 21 04:33:45 PM PDT 24 |
| Finished | Apr 21 04:35:14 PM PDT 24 |
| Peak memory | 200684 kb |
| Host | smart-d68de433-571e-426b-87d5-6211ca89ec15 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2922462497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.2922462497 |
| Directory | /workspace/40.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/40.uart_rx_start_bit_filter.888741222 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 4553833306 ps |
| CPU time | 1.31 seconds |
| Started | Apr 21 04:33:42 PM PDT 24 |
| Finished | Apr 21 04:33:44 PM PDT 24 |
| Peak memory | 197200 kb |
| Host | smart-64a03df3-71f4-44b6-b384-1ec91487b239 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=888741222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.888741222 |
| Directory | /workspace/40.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/40.uart_smoke.3263480335 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 5896972838 ps |
| CPU time | 19.84 seconds |
| Started | Apr 21 04:33:41 PM PDT 24 |
| Finished | Apr 21 04:34:01 PM PDT 24 |
| Peak memory | 200824 kb |
| Host | smart-7070757e-e114-41f9-91bf-1b7be0917a85 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3263480335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3263480335 |
| Directory | /workspace/40.uart_smoke/latest |
| Test location | /workspace/coverage/default/40.uart_stress_all.3919599457 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 369762397862 ps |
| CPU time | 244.94 seconds |
| Started | Apr 21 04:33:49 PM PDT 24 |
| Finished | Apr 21 04:37:54 PM PDT 24 |
| Peak memory | 200884 kb |
| Host | smart-f1846b5d-1f55-463d-9b51-9dca2e94007e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919599457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3919599457 |
| Directory | /workspace/40.uart_stress_all/latest |
| Test location | /workspace/coverage/default/40.uart_stress_all_with_rand_reset.2579492074 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 20148605863 ps |
| CPU time | 619.76 seconds |
| Started | Apr 21 04:33:48 PM PDT 24 |
| Finished | Apr 21 04:44:08 PM PDT 24 |
| Peak memory | 212416 kb |
| Host | smart-8f1a9640-5c9d-44e1-bfd8-00e410127e6e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579492074 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.2579492074 |
| Directory | /workspace/40.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/40.uart_tx_ovrd.478563502 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 6737577206 ps |
| CPU time | 10.56 seconds |
| Started | Apr 21 04:33:44 PM PDT 24 |
| Finished | Apr 21 04:33:55 PM PDT 24 |
| Peak memory | 200744 kb |
| Host | smart-9c463ddb-c05d-4c7f-8046-03b555d7deb4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=478563502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.478563502 |
| Directory | /workspace/40.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/40.uart_tx_rx.1944204687 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 53855181230 ps |
| CPU time | 126.82 seconds |
| Started | Apr 21 04:33:40 PM PDT 24 |
| Finished | Apr 21 04:35:47 PM PDT 24 |
| Peak memory | 200916 kb |
| Host | smart-6a3dc9ca-ca85-4545-9ffd-9371ff32c714 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1944204687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.1944204687 |
| Directory | /workspace/40.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/41.uart_alert_test.3120766330 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 12926873 ps |
| CPU time | 0.57 seconds |
| Started | Apr 21 04:34:03 PM PDT 24 |
| Finished | Apr 21 04:34:04 PM PDT 24 |
| Peak memory | 196236 kb |
| Host | smart-914345aa-dee5-4ded-abb4-bb2b2a889aac |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120766330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.3120766330 |
| Directory | /workspace/41.uart_alert_test/latest |
| Test location | /workspace/coverage/default/41.uart_fifo_full.1683463560 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 94030029904 ps |
| CPU time | 52.4 seconds |
| Started | Apr 21 04:33:50 PM PDT 24 |
| Finished | Apr 21 04:34:43 PM PDT 24 |
| Peak memory | 200876 kb |
| Host | smart-e345fe8f-7224-4853-b19a-9fcebaa39279 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1683463560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.1683463560 |
| Directory | /workspace/41.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/41.uart_fifo_overflow.3587308469 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 57084194868 ps |
| CPU time | 95.88 seconds |
| Started | Apr 21 04:33:55 PM PDT 24 |
| Finished | Apr 21 04:35:31 PM PDT 24 |
| Peak memory | 200872 kb |
| Host | smart-5e52f4d8-6260-4494-854b-343401060106 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3587308469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.3587308469 |
| Directory | /workspace/41.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/41.uart_fifo_reset.755651913 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 143950761467 ps |
| CPU time | 165.89 seconds |
| Started | Apr 21 04:33:53 PM PDT 24 |
| Finished | Apr 21 04:36:39 PM PDT 24 |
| Peak memory | 200876 kb |
| Host | smart-d1d5b0aa-4984-40ba-a87a-216c35e7441c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=755651913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.755651913 |
| Directory | /workspace/41.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/41.uart_intr.1763152068 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 46817873060 ps |
| CPU time | 10.77 seconds |
| Started | Apr 21 04:33:54 PM PDT 24 |
| Finished | Apr 21 04:34:05 PM PDT 24 |
| Peak memory | 200868 kb |
| Host | smart-fdbc7b7c-b0a6-4c2f-a2d5-844eb68860e3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763152068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.1763152068 |
| Directory | /workspace/41.uart_intr/latest |
| Test location | /workspace/coverage/default/41.uart_long_xfer_wo_dly.1617759741 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 138103491199 ps |
| CPU time | 204.69 seconds |
| Started | Apr 21 04:33:57 PM PDT 24 |
| Finished | Apr 21 04:37:22 PM PDT 24 |
| Peak memory | 200876 kb |
| Host | smart-8480a695-d6a5-4013-9a79-32df259d7de3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1617759741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.1617759741 |
| Directory | /workspace/41.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/41.uart_loopback.4171915410 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 9648781766 ps |
| CPU time | 7.68 seconds |
| Started | Apr 21 04:33:59 PM PDT 24 |
| Finished | Apr 21 04:34:06 PM PDT 24 |
| Peak memory | 201048 kb |
| Host | smart-75c34e63-50d4-4d28-9e7e-c5f99133fcc2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4171915410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.4171915410 |
| Directory | /workspace/41.uart_loopback/latest |
| Test location | /workspace/coverage/default/41.uart_noise_filter.3057624667 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 91276509030 ps |
| CPU time | 41.47 seconds |
| Started | Apr 21 04:33:51 PM PDT 24 |
| Finished | Apr 21 04:34:32 PM PDT 24 |
| Peak memory | 201172 kb |
| Host | smart-d944fc5e-5cd5-4781-a70d-21c44ad6b16d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3057624667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.3057624667 |
| Directory | /workspace/41.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/41.uart_perf.2747734243 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 14500546342 ps |
| CPU time | 532.88 seconds |
| Started | Apr 21 04:33:58 PM PDT 24 |
| Finished | Apr 21 04:42:52 PM PDT 24 |
| Peak memory | 200864 kb |
| Host | smart-abfe059a-fd35-448b-9f1f-bbd903b43397 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2747734243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.2747734243 |
| Directory | /workspace/41.uart_perf/latest |
| Test location | /workspace/coverage/default/41.uart_rx_oversample.3881121013 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 3502965277 ps |
| CPU time | 29.45 seconds |
| Started | Apr 21 04:33:56 PM PDT 24 |
| Finished | Apr 21 04:34:26 PM PDT 24 |
| Peak memory | 199048 kb |
| Host | smart-7a35ec88-fa07-4cf0-8410-01d30a093fbd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3881121013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.3881121013 |
| Directory | /workspace/41.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/41.uart_rx_parity_err.1675845511 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 155501112584 ps |
| CPU time | 260.85 seconds |
| Started | Apr 21 04:33:55 PM PDT 24 |
| Finished | Apr 21 04:38:16 PM PDT 24 |
| Peak memory | 200848 kb |
| Host | smart-4dfd9499-22b6-47f2-a945-613312b92efe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1675845511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.1675845511 |
| Directory | /workspace/41.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/41.uart_rx_start_bit_filter.1925175984 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 25983243137 ps |
| CPU time | 21.1 seconds |
| Started | Apr 21 04:33:55 PM PDT 24 |
| Finished | Apr 21 04:34:16 PM PDT 24 |
| Peak memory | 197680 kb |
| Host | smart-1a0c1318-14a7-4d7d-93d6-33d6d75c7008 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1925175984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.1925175984 |
| Directory | /workspace/41.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/41.uart_smoke.2296444078 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 128066634 ps |
| CPU time | 1.1 seconds |
| Started | Apr 21 04:33:50 PM PDT 24 |
| Finished | Apr 21 04:33:52 PM PDT 24 |
| Peak memory | 199152 kb |
| Host | smart-bfc01938-9a8c-4460-b28e-b3bb2aabd152 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2296444078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2296444078 |
| Directory | /workspace/41.uart_smoke/latest |
| Test location | /workspace/coverage/default/41.uart_stress_all.4229152824 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 221501710368 ps |
| CPU time | 184.54 seconds |
| Started | Apr 21 04:34:03 PM PDT 24 |
| Finished | Apr 21 04:37:08 PM PDT 24 |
| Peak memory | 200784 kb |
| Host | smart-35ef4fd9-904d-4685-b475-7332dc255b95 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229152824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.4229152824 |
| Directory | /workspace/41.uart_stress_all/latest |
| Test location | /workspace/coverage/default/41.uart_tx_ovrd.1736366177 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 12113194602 ps |
| CPU time | 7.4 seconds |
| Started | Apr 21 04:34:00 PM PDT 24 |
| Finished | Apr 21 04:34:08 PM PDT 24 |
| Peak memory | 200868 kb |
| Host | smart-c123b15e-5b5f-4776-be3f-c6701ed8b36f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1736366177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.1736366177 |
| Directory | /workspace/41.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/41.uart_tx_rx.1194245414 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 33435978701 ps |
| CPU time | 15.18 seconds |
| Started | Apr 21 04:33:51 PM PDT 24 |
| Finished | Apr 21 04:34:07 PM PDT 24 |
| Peak memory | 200708 kb |
| Host | smart-69c37d21-455a-4767-914c-5d4de75b86b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1194245414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.1194245414 |
| Directory | /workspace/41.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/42.uart_alert_test.3316896615 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 18841156 ps |
| CPU time | 0.58 seconds |
| Started | Apr 21 04:34:12 PM PDT 24 |
| Finished | Apr 21 04:34:13 PM PDT 24 |
| Peak memory | 196240 kb |
| Host | smart-b8b991c5-d206-4fad-bb49-5f2319ce16ce |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316896615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.3316896615 |
| Directory | /workspace/42.uart_alert_test/latest |
| Test location | /workspace/coverage/default/42.uart_fifo_full.2419706239 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 157227415902 ps |
| CPU time | 179.53 seconds |
| Started | Apr 21 04:34:05 PM PDT 24 |
| Finished | Apr 21 04:37:05 PM PDT 24 |
| Peak memory | 200904 kb |
| Host | smart-22ff618f-422d-4d4e-bffc-339bda9043bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2419706239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.2419706239 |
| Directory | /workspace/42.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/42.uart_fifo_overflow.2731401034 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 60801800331 ps |
| CPU time | 27.07 seconds |
| Started | Apr 21 04:34:08 PM PDT 24 |
| Finished | Apr 21 04:34:35 PM PDT 24 |
| Peak memory | 200920 kb |
| Host | smart-6e4bf2b5-dc6e-427b-95da-335f12b37033 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2731401034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.2731401034 |
| Directory | /workspace/42.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/42.uart_fifo_reset.693260726 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 34647050297 ps |
| CPU time | 29.65 seconds |
| Started | Apr 21 04:34:08 PM PDT 24 |
| Finished | Apr 21 04:34:38 PM PDT 24 |
| Peak memory | 200916 kb |
| Host | smart-c3b1c327-b0eb-4693-b5e4-b26e120922ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=693260726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.693260726 |
| Directory | /workspace/42.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/42.uart_intr.3850423009 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 13168021537 ps |
| CPU time | 41.92 seconds |
| Started | Apr 21 04:34:07 PM PDT 24 |
| Finished | Apr 21 04:34:49 PM PDT 24 |
| Peak memory | 200788 kb |
| Host | smart-5ffe623d-359d-40d7-be6e-30b9f087d998 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850423009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.3850423009 |
| Directory | /workspace/42.uart_intr/latest |
| Test location | /workspace/coverage/default/42.uart_long_xfer_wo_dly.3854206883 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 126723656854 ps |
| CPU time | 346.34 seconds |
| Started | Apr 21 04:34:12 PM PDT 24 |
| Finished | Apr 21 04:39:58 PM PDT 24 |
| Peak memory | 200948 kb |
| Host | smart-c2d68643-e831-41c5-b863-a3cae019b075 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3854206883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.3854206883 |
| Directory | /workspace/42.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/42.uart_loopback.106313394 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 64589541 ps |
| CPU time | 0.9 seconds |
| Started | Apr 21 04:34:12 PM PDT 24 |
| Finished | Apr 21 04:34:13 PM PDT 24 |
| Peak memory | 199048 kb |
| Host | smart-a02e595d-d63a-4aca-9563-7e5e28b4b9a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=106313394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.106313394 |
| Directory | /workspace/42.uart_loopback/latest |
| Test location | /workspace/coverage/default/42.uart_noise_filter.1792439588 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 229752196041 ps |
| CPU time | 76.64 seconds |
| Started | Apr 21 04:34:07 PM PDT 24 |
| Finished | Apr 21 04:35:24 PM PDT 24 |
| Peak memory | 201048 kb |
| Host | smart-46b47d58-43f9-41ce-b0d3-3ec80ffa3ba8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1792439588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.1792439588 |
| Directory | /workspace/42.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/42.uart_perf.3192854452 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 7812168034 ps |
| CPU time | 244.7 seconds |
| Started | Apr 21 04:34:11 PM PDT 24 |
| Finished | Apr 21 04:38:16 PM PDT 24 |
| Peak memory | 201088 kb |
| Host | smart-4c95cbd9-fa47-4edb-9f0d-72c169ed4f7d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3192854452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.3192854452 |
| Directory | /workspace/42.uart_perf/latest |
| Test location | /workspace/coverage/default/42.uart_rx_oversample.3099637910 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 5164012472 ps |
| CPU time | 25.24 seconds |
| Started | Apr 21 04:34:06 PM PDT 24 |
| Finished | Apr 21 04:34:32 PM PDT 24 |
| Peak memory | 200256 kb |
| Host | smart-e8a836f5-02a0-47fb-b298-83fae0152dc7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3099637910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3099637910 |
| Directory | /workspace/42.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/42.uart_rx_parity_err.1949334439 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 198723421759 ps |
| CPU time | 135.06 seconds |
| Started | Apr 21 04:34:10 PM PDT 24 |
| Finished | Apr 21 04:36:25 PM PDT 24 |
| Peak memory | 200824 kb |
| Host | smart-ad1bc4a5-aec0-463f-94df-38eaacad4acf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1949334439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.1949334439 |
| Directory | /workspace/42.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/42.uart_rx_start_bit_filter.2625810717 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 44365718574 ps |
| CPU time | 19.83 seconds |
| Started | Apr 21 04:34:08 PM PDT 24 |
| Finished | Apr 21 04:34:29 PM PDT 24 |
| Peak memory | 196616 kb |
| Host | smart-6b7398d0-ae1f-4630-84c1-9166ff951f41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2625810717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.2625810717 |
| Directory | /workspace/42.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/42.uart_smoke.584303494 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 505662710 ps |
| CPU time | 2 seconds |
| Started | Apr 21 04:34:03 PM PDT 24 |
| Finished | Apr 21 04:34:06 PM PDT 24 |
| Peak memory | 200764 kb |
| Host | smart-185e543f-8903-41c9-a040-fae1b285df86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=584303494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.584303494 |
| Directory | /workspace/42.uart_smoke/latest |
| Test location | /workspace/coverage/default/42.uart_stress_all.3158748862 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 778980084726 ps |
| CPU time | 96.22 seconds |
| Started | Apr 21 04:34:13 PM PDT 24 |
| Finished | Apr 21 04:35:49 PM PDT 24 |
| Peak memory | 200860 kb |
| Host | smart-9dd4d895-aadd-463f-a27d-e21b2c9eb683 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158748862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.3158748862 |
| Directory | /workspace/42.uart_stress_all/latest |
| Test location | /workspace/coverage/default/42.uart_stress_all_with_rand_reset.3114056157 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 61507560608 ps |
| CPU time | 970.18 seconds |
| Started | Apr 21 04:34:12 PM PDT 24 |
| Finished | Apr 21 04:50:23 PM PDT 24 |
| Peak memory | 225696 kb |
| Host | smart-25fa839a-0f29-44f8-ba0b-2d53af043991 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114056157 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.3114056157 |
| Directory | /workspace/42.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/42.uart_tx_ovrd.2759100141 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 14150837608 ps |
| CPU time | 7.61 seconds |
| Started | Apr 21 04:34:10 PM PDT 24 |
| Finished | Apr 21 04:34:18 PM PDT 24 |
| Peak memory | 200380 kb |
| Host | smart-be884bb1-e615-43c6-bcc4-a1036f5a5ad7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2759100141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.2759100141 |
| Directory | /workspace/42.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/42.uart_tx_rx.2490366758 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 16301300156 ps |
| CPU time | 6.18 seconds |
| Started | Apr 21 04:34:03 PM PDT 24 |
| Finished | Apr 21 04:34:09 PM PDT 24 |
| Peak memory | 198616 kb |
| Host | smart-b0e7f21b-ee29-42b5-aa87-29794b5f1d78 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2490366758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.2490366758 |
| Directory | /workspace/42.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/43.uart_alert_test.425139176 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 109996258 ps |
| CPU time | 0.54 seconds |
| Started | Apr 21 04:34:25 PM PDT 24 |
| Finished | Apr 21 04:34:26 PM PDT 24 |
| Peak memory | 196248 kb |
| Host | smart-f915e125-5fd9-4519-ad6f-fea99cdfc4be |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425139176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.425139176 |
| Directory | /workspace/43.uart_alert_test/latest |
| Test location | /workspace/coverage/default/43.uart_fifo_full.3745293474 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 155892569381 ps |
| CPU time | 39.52 seconds |
| Started | Apr 21 04:34:14 PM PDT 24 |
| Finished | Apr 21 04:34:53 PM PDT 24 |
| Peak memory | 200944 kb |
| Host | smart-a741184d-d6b8-4e79-a650-1fdf68980a11 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3745293474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.3745293474 |
| Directory | /workspace/43.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/43.uart_fifo_overflow.1147776984 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 43878101913 ps |
| CPU time | 76.16 seconds |
| Started | Apr 21 04:34:14 PM PDT 24 |
| Finished | Apr 21 04:35:31 PM PDT 24 |
| Peak memory | 200832 kb |
| Host | smart-d72f0e17-179f-4286-860c-df635f98b98a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1147776984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1147776984 |
| Directory | /workspace/43.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/43.uart_fifo_reset.1606399001 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 51096433593 ps |
| CPU time | 29.99 seconds |
| Started | Apr 21 04:34:17 PM PDT 24 |
| Finished | Apr 21 04:34:47 PM PDT 24 |
| Peak memory | 200904 kb |
| Host | smart-5bc1c212-e034-49ce-9bec-442488d94e56 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1606399001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.1606399001 |
| Directory | /workspace/43.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/43.uart_intr.885163717 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 52101495257 ps |
| CPU time | 30.22 seconds |
| Started | Apr 21 04:34:17 PM PDT 24 |
| Finished | Apr 21 04:34:48 PM PDT 24 |
| Peak memory | 200292 kb |
| Host | smart-7ced2877-f155-43a1-91e2-395113722f4f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885163717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.885163717 |
| Directory | /workspace/43.uart_intr/latest |
| Test location | /workspace/coverage/default/43.uart_loopback.4028832816 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 12674944813 ps |
| CPU time | 12.69 seconds |
| Started | Apr 21 04:34:22 PM PDT 24 |
| Finished | Apr 21 04:34:35 PM PDT 24 |
| Peak memory | 200504 kb |
| Host | smart-a361b11c-3d1e-433b-9ad1-8da1a02d4264 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4028832816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.4028832816 |
| Directory | /workspace/43.uart_loopback/latest |
| Test location | /workspace/coverage/default/43.uart_noise_filter.2204012038 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 195294819024 ps |
| CPU time | 107.8 seconds |
| Started | Apr 21 04:34:17 PM PDT 24 |
| Finished | Apr 21 04:36:05 PM PDT 24 |
| Peak memory | 201096 kb |
| Host | smart-30064dda-04f2-42a4-aae6-8fd13f5dc6ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2204012038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.2204012038 |
| Directory | /workspace/43.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/43.uart_perf.3506298758 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 11189640680 ps |
| CPU time | 170.91 seconds |
| Started | Apr 21 04:34:22 PM PDT 24 |
| Finished | Apr 21 04:37:13 PM PDT 24 |
| Peak memory | 200880 kb |
| Host | smart-66254924-e499-434b-a0bc-046731e15758 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3506298758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.3506298758 |
| Directory | /workspace/43.uart_perf/latest |
| Test location | /workspace/coverage/default/43.uart_rx_oversample.4283355466 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 4408252769 ps |
| CPU time | 13.84 seconds |
| Started | Apr 21 04:34:17 PM PDT 24 |
| Finished | Apr 21 04:34:31 PM PDT 24 |
| Peak memory | 199452 kb |
| Host | smart-43f71d6d-9927-4c7e-b0ee-b373670611e4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4283355466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.4283355466 |
| Directory | /workspace/43.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/43.uart_rx_parity_err.3548666491 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 96990094648 ps |
| CPU time | 74.32 seconds |
| Started | Apr 21 04:34:20 PM PDT 24 |
| Finished | Apr 21 04:35:34 PM PDT 24 |
| Peak memory | 200852 kb |
| Host | smart-2143dd7e-3d97-4023-8849-59226e7f6b90 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3548666491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.3548666491 |
| Directory | /workspace/43.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/43.uart_rx_start_bit_filter.341643020 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 33294992924 ps |
| CPU time | 28.44 seconds |
| Started | Apr 21 04:34:19 PM PDT 24 |
| Finished | Apr 21 04:34:47 PM PDT 24 |
| Peak memory | 196712 kb |
| Host | smart-d56c6097-3511-4a1f-a6c0-665b51d4187b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=341643020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.341643020 |
| Directory | /workspace/43.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/43.uart_smoke.314676978 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 722710803 ps |
| CPU time | 2.44 seconds |
| Started | Apr 21 04:34:16 PM PDT 24 |
| Finished | Apr 21 04:34:19 PM PDT 24 |
| Peak memory | 199696 kb |
| Host | smart-b52c5022-d190-4c90-92f2-e5427942ff29 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=314676978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.314676978 |
| Directory | /workspace/43.uart_smoke/latest |
| Test location | /workspace/coverage/default/43.uart_stress_all.1976995912 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 127880119219 ps |
| CPU time | 1112.42 seconds |
| Started | Apr 21 04:34:23 PM PDT 24 |
| Finished | Apr 21 04:52:56 PM PDT 24 |
| Peak memory | 200836 kb |
| Host | smart-7b1434e0-c882-44b4-ae51-4c63ef6f2f92 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976995912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.1976995912 |
| Directory | /workspace/43.uart_stress_all/latest |
| Test location | /workspace/coverage/default/43.uart_stress_all_with_rand_reset.1209367259 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 310992572471 ps |
| CPU time | 693.55 seconds |
| Started | Apr 21 04:34:24 PM PDT 24 |
| Finished | Apr 21 04:45:58 PM PDT 24 |
| Peak memory | 217536 kb |
| Host | smart-e3111484-d4d6-40a0-a47d-15ff537e6648 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209367259 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.1209367259 |
| Directory | /workspace/43.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/43.uart_tx_ovrd.2294938969 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 2494747018 ps |
| CPU time | 2.61 seconds |
| Started | Apr 21 04:34:20 PM PDT 24 |
| Finished | Apr 21 04:34:23 PM PDT 24 |
| Peak memory | 199896 kb |
| Host | smart-065176d1-6962-438e-8938-695bfed3015f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2294938969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.2294938969 |
| Directory | /workspace/43.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/43.uart_tx_rx.4033221989 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 37932373641 ps |
| CPU time | 64.59 seconds |
| Started | Apr 21 04:34:16 PM PDT 24 |
| Finished | Apr 21 04:35:21 PM PDT 24 |
| Peak memory | 200880 kb |
| Host | smart-b9be94ae-0f2a-4218-a364-9d8eb830f1c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4033221989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.4033221989 |
| Directory | /workspace/43.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/44.uart_alert_test.4129253204 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 13636282 ps |
| CPU time | 0.58 seconds |
| Started | Apr 21 04:34:35 PM PDT 24 |
| Finished | Apr 21 04:34:36 PM PDT 24 |
| Peak memory | 196200 kb |
| Host | smart-ea374ac9-a7e8-4984-b2e4-4826912927e9 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129253204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.4129253204 |
| Directory | /workspace/44.uart_alert_test/latest |
| Test location | /workspace/coverage/default/44.uart_fifo_full.858695516 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 10632411226 ps |
| CPU time | 5.24 seconds |
| Started | Apr 21 04:34:28 PM PDT 24 |
| Finished | Apr 21 04:34:33 PM PDT 24 |
| Peak memory | 200448 kb |
| Host | smart-0a159ce7-ef9a-4fa1-b652-5cd80f6517fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=858695516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.858695516 |
| Directory | /workspace/44.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/44.uart_fifo_overflow.1891411516 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 81063420120 ps |
| CPU time | 18.11 seconds |
| Started | Apr 21 04:34:27 PM PDT 24 |
| Finished | Apr 21 04:34:46 PM PDT 24 |
| Peak memory | 198676 kb |
| Host | smart-fb02d176-237b-41f9-9969-db22a78acac0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1891411516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1891411516 |
| Directory | /workspace/44.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/44.uart_fifo_reset.4010593585 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 113771634595 ps |
| CPU time | 56.58 seconds |
| Started | Apr 21 04:34:26 PM PDT 24 |
| Finished | Apr 21 04:35:23 PM PDT 24 |
| Peak memory | 200856 kb |
| Host | smart-7bf21863-abbe-41d7-8170-31e54dde3d33 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4010593585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.4010593585 |
| Directory | /workspace/44.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/44.uart_intr.1666659859 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 277183811658 ps |
| CPU time | 238.58 seconds |
| Started | Apr 21 04:34:31 PM PDT 24 |
| Finished | Apr 21 04:38:29 PM PDT 24 |
| Peak memory | 200792 kb |
| Host | smart-b94dd73f-0417-4388-b000-3f1fefc67943 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666659859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.1666659859 |
| Directory | /workspace/44.uart_intr/latest |
| Test location | /workspace/coverage/default/44.uart_long_xfer_wo_dly.1836666569 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 107225661374 ps |
| CPU time | 772.13 seconds |
| Started | Apr 21 04:34:38 PM PDT 24 |
| Finished | Apr 21 04:47:30 PM PDT 24 |
| Peak memory | 200864 kb |
| Host | smart-2bc158fb-a590-4905-809a-dd79ccff0803 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1836666569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.1836666569 |
| Directory | /workspace/44.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/44.uart_loopback.504293796 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 9889834343 ps |
| CPU time | 8.65 seconds |
| Started | Apr 21 04:34:34 PM PDT 24 |
| Finished | Apr 21 04:34:42 PM PDT 24 |
| Peak memory | 200620 kb |
| Host | smart-b892ea3a-023e-4759-a799-dbebf1e90f21 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=504293796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.504293796 |
| Directory | /workspace/44.uart_loopback/latest |
| Test location | /workspace/coverage/default/44.uart_noise_filter.1677518571 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 24840530939 ps |
| CPU time | 47.01 seconds |
| Started | Apr 21 04:34:33 PM PDT 24 |
| Finished | Apr 21 04:35:20 PM PDT 24 |
| Peak memory | 199440 kb |
| Host | smart-8726fd5d-b98b-4616-b6c7-ba5fbb4b6110 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1677518571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.1677518571 |
| Directory | /workspace/44.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/44.uart_perf.4081588037 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 14310739343 ps |
| CPU time | 103.89 seconds |
| Started | Apr 21 04:34:35 PM PDT 24 |
| Finished | Apr 21 04:36:20 PM PDT 24 |
| Peak memory | 200944 kb |
| Host | smart-ebaa680c-37aa-4ad9-9590-ca32a7a456bf |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4081588037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.4081588037 |
| Directory | /workspace/44.uart_perf/latest |
| Test location | /workspace/coverage/default/44.uart_rx_oversample.3108469908 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 3405161168 ps |
| CPU time | 6.4 seconds |
| Started | Apr 21 04:34:33 PM PDT 24 |
| Finished | Apr 21 04:34:40 PM PDT 24 |
| Peak memory | 198960 kb |
| Host | smart-b36ef0fc-8909-4332-aa59-69b37c6220af |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3108469908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.3108469908 |
| Directory | /workspace/44.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/44.uart_rx_parity_err.935038300 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 121269820288 ps |
| CPU time | 259.92 seconds |
| Started | Apr 21 04:34:31 PM PDT 24 |
| Finished | Apr 21 04:38:51 PM PDT 24 |
| Peak memory | 200800 kb |
| Host | smart-445cd941-6763-45b0-a17b-0938f5704cbc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=935038300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.935038300 |
| Directory | /workspace/44.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/44.uart_rx_start_bit_filter.1999952378 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 44661787376 ps |
| CPU time | 72.7 seconds |
| Started | Apr 21 04:34:31 PM PDT 24 |
| Finished | Apr 21 04:35:44 PM PDT 24 |
| Peak memory | 196924 kb |
| Host | smart-6baaba13-13a1-45dd-84a8-c25a7d29829d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1999952378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.1999952378 |
| Directory | /workspace/44.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/44.uart_smoke.3926900129 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 474139263 ps |
| CPU time | 2.29 seconds |
| Started | Apr 21 04:34:25 PM PDT 24 |
| Finished | Apr 21 04:34:28 PM PDT 24 |
| Peak memory | 200708 kb |
| Host | smart-27e5e9db-26a8-4070-9fa0-f9f014731c8c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3926900129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.3926900129 |
| Directory | /workspace/44.uart_smoke/latest |
| Test location | /workspace/coverage/default/44.uart_stress_all.2952328177 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 177708811089 ps |
| CPU time | 410.16 seconds |
| Started | Apr 21 04:34:38 PM PDT 24 |
| Finished | Apr 21 04:41:28 PM PDT 24 |
| Peak memory | 200856 kb |
| Host | smart-38b0852f-3319-4830-b1cd-7f2c24a5f62b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952328177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2952328177 |
| Directory | /workspace/44.uart_stress_all/latest |
| Test location | /workspace/coverage/default/44.uart_stress_all_with_rand_reset.1281400668 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 31772693993 ps |
| CPU time | 198.43 seconds |
| Started | Apr 21 04:34:35 PM PDT 24 |
| Finished | Apr 21 04:37:54 PM PDT 24 |
| Peak memory | 213240 kb |
| Host | smart-ab340ab9-a75b-4ef7-877a-69c256dd63cf |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281400668 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.1281400668 |
| Directory | /workspace/44.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/44.uart_tx_ovrd.2381043121 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 2343558072 ps |
| CPU time | 2.85 seconds |
| Started | Apr 21 04:34:31 PM PDT 24 |
| Finished | Apr 21 04:34:34 PM PDT 24 |
| Peak memory | 200012 kb |
| Host | smart-82f97bae-a285-41f2-a346-31803a0945d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2381043121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.2381043121 |
| Directory | /workspace/44.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/44.uart_tx_rx.495500589 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 39639950994 ps |
| CPU time | 51.27 seconds |
| Started | Apr 21 04:34:24 PM PDT 24 |
| Finished | Apr 21 04:35:15 PM PDT 24 |
| Peak memory | 200840 kb |
| Host | smart-a62f8b59-ecab-4c34-8654-4da9d8c7b145 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=495500589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.495500589 |
| Directory | /workspace/44.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/45.uart_alert_test.1397096623 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 44206322 ps |
| CPU time | 0.59 seconds |
| Started | Apr 21 04:34:48 PM PDT 24 |
| Finished | Apr 21 04:34:49 PM PDT 24 |
| Peak memory | 196244 kb |
| Host | smart-910a5e26-fcf2-4bda-9f39-b3d9fbc48c53 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397096623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.1397096623 |
| Directory | /workspace/45.uart_alert_test/latest |
| Test location | /workspace/coverage/default/45.uart_fifo_full.1384267103 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 185697755451 ps |
| CPU time | 76.76 seconds |
| Started | Apr 21 04:34:37 PM PDT 24 |
| Finished | Apr 21 04:35:54 PM PDT 24 |
| Peak memory | 200816 kb |
| Host | smart-9b1d2605-1bcc-4947-b44f-6677ae64f2f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1384267103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.1384267103 |
| Directory | /workspace/45.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/45.uart_fifo_overflow.1721466757 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 10672417405 ps |
| CPU time | 5.07 seconds |
| Started | Apr 21 04:34:38 PM PDT 24 |
| Finished | Apr 21 04:34:43 PM PDT 24 |
| Peak memory | 200764 kb |
| Host | smart-1664ab14-3f75-4682-9c39-212ba6182bca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1721466757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.1721466757 |
| Directory | /workspace/45.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/45.uart_fifo_reset.408922586 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 115811145991 ps |
| CPU time | 47.6 seconds |
| Started | Apr 21 04:34:38 PM PDT 24 |
| Finished | Apr 21 04:35:26 PM PDT 24 |
| Peak memory | 200880 kb |
| Host | smart-92bc1f2b-adaf-44e6-82fd-9aeb8da48000 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=408922586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.408922586 |
| Directory | /workspace/45.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/45.uart_intr.2699335377 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 134642654869 ps |
| CPU time | 335.95 seconds |
| Started | Apr 21 04:34:38 PM PDT 24 |
| Finished | Apr 21 04:40:15 PM PDT 24 |
| Peak memory | 200516 kb |
| Host | smart-3ab563e1-eb5d-4059-a5f7-46f23532af26 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699335377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.2699335377 |
| Directory | /workspace/45.uart_intr/latest |
| Test location | /workspace/coverage/default/45.uart_long_xfer_wo_dly.1040720643 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 110899890913 ps |
| CPU time | 669.46 seconds |
| Started | Apr 21 04:34:43 PM PDT 24 |
| Finished | Apr 21 04:45:53 PM PDT 24 |
| Peak memory | 200808 kb |
| Host | smart-0873bea3-e7c0-4379-9db8-7848f4e3318e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1040720643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.1040720643 |
| Directory | /workspace/45.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/45.uart_loopback.2535534427 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 564000358 ps |
| CPU time | 0.87 seconds |
| Started | Apr 21 04:34:39 PM PDT 24 |
| Finished | Apr 21 04:34:40 PM PDT 24 |
| Peak memory | 197004 kb |
| Host | smart-1e776870-aa22-4e07-a3e6-f6d7f9d4ae03 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2535534427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.2535534427 |
| Directory | /workspace/45.uart_loopback/latest |
| Test location | /workspace/coverage/default/45.uart_noise_filter.950377596 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 67017861658 ps |
| CPU time | 27.35 seconds |
| Started | Apr 21 04:34:36 PM PDT 24 |
| Finished | Apr 21 04:35:04 PM PDT 24 |
| Peak memory | 200436 kb |
| Host | smart-d5316d28-d411-44eb-8bd2-cac0719b7626 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=950377596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.950377596 |
| Directory | /workspace/45.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/45.uart_perf.2424551813 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 22253452367 ps |
| CPU time | 302.22 seconds |
| Started | Apr 21 04:34:38 PM PDT 24 |
| Finished | Apr 21 04:39:41 PM PDT 24 |
| Peak memory | 200944 kb |
| Host | smart-70b3e8ea-5363-43f7-bb86-f91f03228a7f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2424551813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.2424551813 |
| Directory | /workspace/45.uart_perf/latest |
| Test location | /workspace/coverage/default/45.uart_rx_oversample.4161333569 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 5082411079 ps |
| CPU time | 12.4 seconds |
| Started | Apr 21 04:34:37 PM PDT 24 |
| Finished | Apr 21 04:34:50 PM PDT 24 |
| Peak memory | 199100 kb |
| Host | smart-8d2237e1-6646-46c3-8a6a-966153b8e57a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4161333569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.4161333569 |
| Directory | /workspace/45.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/45.uart_rx_parity_err.507266135 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 72935347089 ps |
| CPU time | 29.85 seconds |
| Started | Apr 21 04:34:41 PM PDT 24 |
| Finished | Apr 21 04:35:11 PM PDT 24 |
| Peak memory | 200536 kb |
| Host | smart-092badb6-672b-4bc1-8001-d8add220c826 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=507266135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.507266135 |
| Directory | /workspace/45.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/45.uart_rx_start_bit_filter.1405920477 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 35753518025 ps |
| CPU time | 57.52 seconds |
| Started | Apr 21 04:34:39 PM PDT 24 |
| Finished | Apr 21 04:35:37 PM PDT 24 |
| Peak memory | 196888 kb |
| Host | smart-b087e5e4-82c3-4788-a087-8d6cf205060a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1405920477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.1405920477 |
| Directory | /workspace/45.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/45.uart_smoke.1274187749 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 490779577 ps |
| CPU time | 1.25 seconds |
| Started | Apr 21 04:34:35 PM PDT 24 |
| Finished | Apr 21 04:34:36 PM PDT 24 |
| Peak memory | 200784 kb |
| Host | smart-6354f5c7-35ae-48bb-91dc-71041ed2be6a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1274187749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.1274187749 |
| Directory | /workspace/45.uart_smoke/latest |
| Test location | /workspace/coverage/default/45.uart_stress_all_with_rand_reset.869521250 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 71478144650 ps |
| CPU time | 751.63 seconds |
| Started | Apr 21 04:34:41 PM PDT 24 |
| Finished | Apr 21 04:47:13 PM PDT 24 |
| Peak memory | 225692 kb |
| Host | smart-9e0ee498-f5ba-4140-9d4e-3c12f06c52c3 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869521250 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.869521250 |
| Directory | /workspace/45.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/45.uart_tx_ovrd.2042927135 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 500060320 ps |
| CPU time | 1.64 seconds |
| Started | Apr 21 04:34:40 PM PDT 24 |
| Finished | Apr 21 04:34:42 PM PDT 24 |
| Peak memory | 198644 kb |
| Host | smart-4a2b310d-24ee-4a72-b3fc-4e7b1d607c1a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2042927135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.2042927135 |
| Directory | /workspace/45.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/45.uart_tx_rx.3003247363 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 91261915539 ps |
| CPU time | 52.53 seconds |
| Started | Apr 21 04:34:39 PM PDT 24 |
| Finished | Apr 21 04:35:32 PM PDT 24 |
| Peak memory | 200864 kb |
| Host | smart-87440e31-970e-4e8b-9ad7-5f683646a197 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3003247363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.3003247363 |
| Directory | /workspace/45.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/46.uart_alert_test.1493446787 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 14723712 ps |
| CPU time | 0.57 seconds |
| Started | Apr 21 04:34:50 PM PDT 24 |
| Finished | Apr 21 04:34:51 PM PDT 24 |
| Peak memory | 196192 kb |
| Host | smart-9cfcc00c-ab5e-48fb-8f73-15003b32aed7 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493446787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.1493446787 |
| Directory | /workspace/46.uart_alert_test/latest |
| Test location | /workspace/coverage/default/46.uart_fifo_full.1144663785 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 113448799103 ps |
| CPU time | 192.79 seconds |
| Started | Apr 21 04:34:52 PM PDT 24 |
| Finished | Apr 21 04:38:05 PM PDT 24 |
| Peak memory | 200848 kb |
| Host | smart-42e86e3f-367e-4908-9473-0a5eb68a705a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1144663785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1144663785 |
| Directory | /workspace/46.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/46.uart_fifo_overflow.2374854192 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 39879578460 ps |
| CPU time | 20.74 seconds |
| Started | Apr 21 04:34:47 PM PDT 24 |
| Finished | Apr 21 04:35:08 PM PDT 24 |
| Peak memory | 200828 kb |
| Host | smart-6e5ba05f-2754-45fb-b963-1a37ff388b22 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2374854192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.2374854192 |
| Directory | /workspace/46.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/46.uart_fifo_reset.1653070131 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 61497395443 ps |
| CPU time | 47.94 seconds |
| Started | Apr 21 04:34:52 PM PDT 24 |
| Finished | Apr 21 04:35:40 PM PDT 24 |
| Peak memory | 200912 kb |
| Host | smart-50c633fa-412f-45ad-9bd8-834949a733de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1653070131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.1653070131 |
| Directory | /workspace/46.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/46.uart_intr.3590938228 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 15995143313 ps |
| CPU time | 35.88 seconds |
| Started | Apr 21 04:34:52 PM PDT 24 |
| Finished | Apr 21 04:35:28 PM PDT 24 |
| Peak memory | 200888 kb |
| Host | smart-ceb70b8b-583d-46cf-8666-86b89121fc28 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590938228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.3590938228 |
| Directory | /workspace/46.uart_intr/latest |
| Test location | /workspace/coverage/default/46.uart_long_xfer_wo_dly.967668921 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 87961712619 ps |
| CPU time | 680.89 seconds |
| Started | Apr 21 04:34:53 PM PDT 24 |
| Finished | Apr 21 04:46:14 PM PDT 24 |
| Peak memory | 200820 kb |
| Host | smart-60a9ab34-7ca4-4db1-9c2a-6d0ddab52576 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=967668921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.967668921 |
| Directory | /workspace/46.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/46.uart_loopback.345519965 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 6273894571 ps |
| CPU time | 6.13 seconds |
| Started | Apr 21 04:34:47 PM PDT 24 |
| Finished | Apr 21 04:34:54 PM PDT 24 |
| Peak memory | 198872 kb |
| Host | smart-7c6c84f4-f80f-4d13-ad9d-4129c0712849 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=345519965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.345519965 |
| Directory | /workspace/46.uart_loopback/latest |
| Test location | /workspace/coverage/default/46.uart_noise_filter.3442591355 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 88871999099 ps |
| CPU time | 11.45 seconds |
| Started | Apr 21 04:34:47 PM PDT 24 |
| Finished | Apr 21 04:34:59 PM PDT 24 |
| Peak memory | 199628 kb |
| Host | smart-1805bf35-ebca-414d-8c06-ca23eb9feb22 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3442591355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.3442591355 |
| Directory | /workspace/46.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/46.uart_perf.2285106417 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 12118119834 ps |
| CPU time | 224.48 seconds |
| Started | Apr 21 04:34:48 PM PDT 24 |
| Finished | Apr 21 04:38:33 PM PDT 24 |
| Peak memory | 200892 kb |
| Host | smart-615396d7-9622-4b57-9682-37f8d5788305 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2285106417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.2285106417 |
| Directory | /workspace/46.uart_perf/latest |
| Test location | /workspace/coverage/default/46.uart_rx_oversample.108279662 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 6873434268 ps |
| CPU time | 63.08 seconds |
| Started | Apr 21 04:34:52 PM PDT 24 |
| Finished | Apr 21 04:35:55 PM PDT 24 |
| Peak memory | 200096 kb |
| Host | smart-a22197fe-a97a-443e-a18c-206f30a73a86 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=108279662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.108279662 |
| Directory | /workspace/46.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/46.uart_rx_parity_err.4152743282 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 202446897377 ps |
| CPU time | 383.8 seconds |
| Started | Apr 21 04:34:53 PM PDT 24 |
| Finished | Apr 21 04:41:17 PM PDT 24 |
| Peak memory | 200880 kb |
| Host | smart-fe87856d-c4f6-4b4e-b500-ec7ecdfa8bde |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4152743282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.4152743282 |
| Directory | /workspace/46.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/46.uart_rx_start_bit_filter.2286023209 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 5059818654 ps |
| CPU time | 1.45 seconds |
| Started | Apr 21 04:34:48 PM PDT 24 |
| Finished | Apr 21 04:34:50 PM PDT 24 |
| Peak memory | 196944 kb |
| Host | smart-ac2464af-650b-4449-a3b0-f49e5490f76d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2286023209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.2286023209 |
| Directory | /workspace/46.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/46.uart_smoke.3347197736 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 123616508 ps |
| CPU time | 0.92 seconds |
| Started | Apr 21 04:34:45 PM PDT 24 |
| Finished | Apr 21 04:34:46 PM PDT 24 |
| Peak memory | 197992 kb |
| Host | smart-047e2fa1-ddf0-408f-980a-e4c5129650a6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3347197736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.3347197736 |
| Directory | /workspace/46.uart_smoke/latest |
| Test location | /workspace/coverage/default/46.uart_stress_all.1915388275 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 346505734545 ps |
| CPU time | 434.98 seconds |
| Started | Apr 21 04:34:52 PM PDT 24 |
| Finished | Apr 21 04:42:07 PM PDT 24 |
| Peak memory | 200852 kb |
| Host | smart-a8094453-2fc8-4ed1-a54a-9087a04a12bd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915388275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.1915388275 |
| Directory | /workspace/46.uart_stress_all/latest |
| Test location | /workspace/coverage/default/46.uart_stress_all_with_rand_reset.1547867332 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 156311126739 ps |
| CPU time | 620.37 seconds |
| Started | Apr 21 04:34:50 PM PDT 24 |
| Finished | Apr 21 04:45:10 PM PDT 24 |
| Peak memory | 229648 kb |
| Host | smart-3f3b5ef5-b9fb-41ff-a9fb-05fff1d85633 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547867332 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.1547867332 |
| Directory | /workspace/46.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/46.uart_tx_ovrd.31765328 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 2930016447 ps |
| CPU time | 2.81 seconds |
| Started | Apr 21 04:34:48 PM PDT 24 |
| Finished | Apr 21 04:34:51 PM PDT 24 |
| Peak memory | 199356 kb |
| Host | smart-46b82a39-f55c-4503-b0f5-f770d32e9b7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=31765328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.31765328 |
| Directory | /workspace/46.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/46.uart_tx_rx.3976377815 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 29322274086 ps |
| CPU time | 54.32 seconds |
| Started | Apr 21 04:34:44 PM PDT 24 |
| Finished | Apr 21 04:35:38 PM PDT 24 |
| Peak memory | 200784 kb |
| Host | smart-fd7de374-e84a-437d-a819-7f913231e72b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3976377815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.3976377815 |
| Directory | /workspace/46.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/47.uart_alert_test.303823909 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 15077729 ps |
| CPU time | 0.63 seconds |
| Started | Apr 21 04:35:03 PM PDT 24 |
| Finished | Apr 21 04:35:04 PM PDT 24 |
| Peak memory | 196248 kb |
| Host | smart-28a760fe-8f3b-412b-a5eb-88323c1be8e1 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303823909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.303823909 |
| Directory | /workspace/47.uart_alert_test/latest |
| Test location | /workspace/coverage/default/47.uart_fifo_full.1193646105 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 195502048366 ps |
| CPU time | 289.58 seconds |
| Started | Apr 21 04:34:56 PM PDT 24 |
| Finished | Apr 21 04:39:46 PM PDT 24 |
| Peak memory | 200896 kb |
| Host | smart-69f6ad1b-a010-4751-900e-001f03fd78dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1193646105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.1193646105 |
| Directory | /workspace/47.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/47.uart_fifo_overflow.1291208119 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 35156390217 ps |
| CPU time | 33.06 seconds |
| Started | Apr 21 04:34:55 PM PDT 24 |
| Finished | Apr 21 04:35:28 PM PDT 24 |
| Peak memory | 200792 kb |
| Host | smart-37e83870-49b2-47c8-8412-92b3e088c3d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1291208119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.1291208119 |
| Directory | /workspace/47.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/47.uart_fifo_reset.3710504948 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 130480748035 ps |
| CPU time | 222.93 seconds |
| Started | Apr 21 04:34:55 PM PDT 24 |
| Finished | Apr 21 04:38:38 PM PDT 24 |
| Peak memory | 200936 kb |
| Host | smart-d66b33c6-00ab-43bc-881f-fb78beabd5a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3710504948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.3710504948 |
| Directory | /workspace/47.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/47.uart_intr.1154068289 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 8452004312 ps |
| CPU time | 4.5 seconds |
| Started | Apr 21 04:34:53 PM PDT 24 |
| Finished | Apr 21 04:34:58 PM PDT 24 |
| Peak memory | 197860 kb |
| Host | smart-ce33e162-fa77-4beb-a532-edba3a206bf4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154068289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.1154068289 |
| Directory | /workspace/47.uart_intr/latest |
| Test location | /workspace/coverage/default/47.uart_long_xfer_wo_dly.3204922799 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 144369494442 ps |
| CPU time | 361.07 seconds |
| Started | Apr 21 04:35:00 PM PDT 24 |
| Finished | Apr 21 04:41:02 PM PDT 24 |
| Peak memory | 200848 kb |
| Host | smart-2bff7bce-3653-4e3e-8143-c1b6f6cface0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3204922799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.3204922799 |
| Directory | /workspace/47.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/47.uart_loopback.3320460793 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 5098151729 ps |
| CPU time | 4.32 seconds |
| Started | Apr 21 04:34:56 PM PDT 24 |
| Finished | Apr 21 04:35:01 PM PDT 24 |
| Peak memory | 200776 kb |
| Host | smart-53d49f40-13eb-4ca0-9255-891aa430eb98 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3320460793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.3320460793 |
| Directory | /workspace/47.uart_loopback/latest |
| Test location | /workspace/coverage/default/47.uart_noise_filter.3819083340 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 136713647654 ps |
| CPU time | 72.35 seconds |
| Started | Apr 21 04:34:55 PM PDT 24 |
| Finished | Apr 21 04:36:07 PM PDT 24 |
| Peak memory | 200540 kb |
| Host | smart-e8aac375-8726-4eaf-8cd3-60d2eadfd012 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3819083340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.3819083340 |
| Directory | /workspace/47.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/47.uart_perf.2225531398 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 7517226313 ps |
| CPU time | 424.22 seconds |
| Started | Apr 21 04:35:00 PM PDT 24 |
| Finished | Apr 21 04:42:04 PM PDT 24 |
| Peak memory | 200828 kb |
| Host | smart-ee49b48b-8117-4254-894f-f6da66b8e617 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2225531398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.2225531398 |
| Directory | /workspace/47.uart_perf/latest |
| Test location | /workspace/coverage/default/47.uart_rx_oversample.3208297763 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 1174674732 ps |
| CPU time | 1.59 seconds |
| Started | Apr 21 04:34:55 PM PDT 24 |
| Finished | Apr 21 04:34:56 PM PDT 24 |
| Peak memory | 197392 kb |
| Host | smart-0ee72fa8-fb40-4464-87bb-625e23fb89cc |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3208297763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.3208297763 |
| Directory | /workspace/47.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/47.uart_rx_parity_err.2452258676 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 27055650772 ps |
| CPU time | 45.94 seconds |
| Started | Apr 21 04:34:58 PM PDT 24 |
| Finished | Apr 21 04:35:44 PM PDT 24 |
| Peak memory | 200876 kb |
| Host | smart-d8062c33-92fc-4a1f-b9b0-e4d88b56c4e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2452258676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.2452258676 |
| Directory | /workspace/47.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/47.uart_rx_start_bit_filter.42035098 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 3791116672 ps |
| CPU time | 5.97 seconds |
| Started | Apr 21 04:34:57 PM PDT 24 |
| Finished | Apr 21 04:35:03 PM PDT 24 |
| Peak memory | 197176 kb |
| Host | smart-86361bc8-fcb7-4195-859c-a1efeadaad13 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=42035098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.42035098 |
| Directory | /workspace/47.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/47.uart_smoke.3921764188 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 854275805 ps |
| CPU time | 2.85 seconds |
| Started | Apr 21 04:34:51 PM PDT 24 |
| Finished | Apr 21 04:34:54 PM PDT 24 |
| Peak memory | 199192 kb |
| Host | smart-60833b22-29d4-483e-b236-7af3eb7ed382 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3921764188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.3921764188 |
| Directory | /workspace/47.uart_smoke/latest |
| Test location | /workspace/coverage/default/47.uart_stress_all_with_rand_reset.977840730 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 86299083844 ps |
| CPU time | 395.9 seconds |
| Started | Apr 21 04:35:05 PM PDT 24 |
| Finished | Apr 21 04:41:41 PM PDT 24 |
| Peak memory | 217368 kb |
| Host | smart-dd9373cb-8363-48a8-b7b0-4debe0f0a29f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977840730 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.977840730 |
| Directory | /workspace/47.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/47.uart_tx_ovrd.4215317699 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 823341927 ps |
| CPU time | 3.21 seconds |
| Started | Apr 21 04:34:56 PM PDT 24 |
| Finished | Apr 21 04:35:00 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-8e5b9692-cbc5-47f3-8e97-4da7010bee2b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4215317699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.4215317699 |
| Directory | /workspace/47.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/47.uart_tx_rx.4003088860 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 48413464227 ps |
| CPU time | 108.32 seconds |
| Started | Apr 21 04:34:53 PM PDT 24 |
| Finished | Apr 21 04:36:42 PM PDT 24 |
| Peak memory | 200864 kb |
| Host | smart-bb569012-de1b-4ed2-a5ad-14d71c28f2c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4003088860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.4003088860 |
| Directory | /workspace/47.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/48.uart_alert_test.1599781251 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 14219043 ps |
| CPU time | 0.58 seconds |
| Started | Apr 21 04:35:16 PM PDT 24 |
| Finished | Apr 21 04:35:17 PM PDT 24 |
| Peak memory | 196240 kb |
| Host | smart-6c2d6060-3429-4494-ba22-b07406db1fd7 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599781251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.1599781251 |
| Directory | /workspace/48.uart_alert_test/latest |
| Test location | /workspace/coverage/default/48.uart_fifo_full.2759731041 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 85706549735 ps |
| CPU time | 65.29 seconds |
| Started | Apr 21 04:35:03 PM PDT 24 |
| Finished | Apr 21 04:36:08 PM PDT 24 |
| Peak memory | 200876 kb |
| Host | smart-55f88c77-650c-47b9-92f3-e1dedc140dc5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2759731041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2759731041 |
| Directory | /workspace/48.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/48.uart_fifo_overflow.2902324599 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 97708928281 ps |
| CPU time | 16.29 seconds |
| Started | Apr 21 04:35:07 PM PDT 24 |
| Finished | Apr 21 04:35:23 PM PDT 24 |
| Peak memory | 200904 kb |
| Host | smart-09ee87a7-95d3-4370-94dc-ea9550dcbdef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2902324599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.2902324599 |
| Directory | /workspace/48.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/48.uart_fifo_reset.249044847 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 31797803855 ps |
| CPU time | 112.32 seconds |
| Started | Apr 21 04:35:06 PM PDT 24 |
| Finished | Apr 21 04:36:59 PM PDT 24 |
| Peak memory | 200916 kb |
| Host | smart-495a8e41-f979-4983-af0a-3a6f4b703cc9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=249044847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.249044847 |
| Directory | /workspace/48.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/48.uart_intr.3369209549 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 53964465497 ps |
| CPU time | 29.74 seconds |
| Started | Apr 21 04:35:06 PM PDT 24 |
| Finished | Apr 21 04:35:36 PM PDT 24 |
| Peak memory | 200928 kb |
| Host | smart-83c52f25-b7d1-45f5-9911-35c594d08f52 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369209549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.3369209549 |
| Directory | /workspace/48.uart_intr/latest |
| Test location | /workspace/coverage/default/48.uart_long_xfer_wo_dly.3921128360 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 89267402715 ps |
| CPU time | 759.1 seconds |
| Started | Apr 21 04:35:15 PM PDT 24 |
| Finished | Apr 21 04:47:55 PM PDT 24 |
| Peak memory | 200848 kb |
| Host | smart-c355e1cc-4ddf-4ceb-9c45-e59097d140f0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3921128360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.3921128360 |
| Directory | /workspace/48.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/48.uart_loopback.363243990 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 8852236487 ps |
| CPU time | 33.14 seconds |
| Started | Apr 21 04:35:12 PM PDT 24 |
| Finished | Apr 21 04:35:46 PM PDT 24 |
| Peak memory | 200620 kb |
| Host | smart-a33a9200-2cfe-40c6-b44f-92a8be61fa30 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=363243990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.363243990 |
| Directory | /workspace/48.uart_loopback/latest |
| Test location | /workspace/coverage/default/48.uart_noise_filter.2135998869 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 135710152097 ps |
| CPU time | 247.41 seconds |
| Started | Apr 21 04:35:08 PM PDT 24 |
| Finished | Apr 21 04:39:15 PM PDT 24 |
| Peak memory | 208788 kb |
| Host | smart-d7ff00ff-5f3f-4630-8be4-16291d886f91 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2135998869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.2135998869 |
| Directory | /workspace/48.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/48.uart_perf.1186622882 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 5600940680 ps |
| CPU time | 55.77 seconds |
| Started | Apr 21 04:35:13 PM PDT 24 |
| Finished | Apr 21 04:36:09 PM PDT 24 |
| Peak memory | 200896 kb |
| Host | smart-cb204cdd-8fc4-488c-af61-1efea897586d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1186622882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.1186622882 |
| Directory | /workspace/48.uart_perf/latest |
| Test location | /workspace/coverage/default/48.uart_rx_oversample.432423003 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 5238255578 ps |
| CPU time | 26.16 seconds |
| Started | Apr 21 04:35:06 PM PDT 24 |
| Finished | Apr 21 04:35:32 PM PDT 24 |
| Peak memory | 200076 kb |
| Host | smart-9c8de52a-83f6-454f-ad97-a812a6ade370 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=432423003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.432423003 |
| Directory | /workspace/48.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/48.uart_rx_parity_err.3063018030 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 44345035354 ps |
| CPU time | 45.38 seconds |
| Started | Apr 21 04:35:06 PM PDT 24 |
| Finished | Apr 21 04:35:51 PM PDT 24 |
| Peak memory | 200916 kb |
| Host | smart-c2aa818e-e63a-433c-9178-dbfbbe036a4e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3063018030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.3063018030 |
| Directory | /workspace/48.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/48.uart_rx_start_bit_filter.1233302966 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 60635322182 ps |
| CPU time | 65.5 seconds |
| Started | Apr 21 04:35:07 PM PDT 24 |
| Finished | Apr 21 04:36:13 PM PDT 24 |
| Peak memory | 196944 kb |
| Host | smart-50083605-0673-4397-9e47-f889635c8868 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1233302966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1233302966 |
| Directory | /workspace/48.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/48.uart_smoke.3969877308 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 522986264 ps |
| CPU time | 1.42 seconds |
| Started | Apr 21 04:35:04 PM PDT 24 |
| Finished | Apr 21 04:35:06 PM PDT 24 |
| Peak memory | 199504 kb |
| Host | smart-559345ee-ca21-4bb6-be2d-2f4e7bd70e8f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3969877308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3969877308 |
| Directory | /workspace/48.uart_smoke/latest |
| Test location | /workspace/coverage/default/48.uart_stress_all_with_rand_reset.3804760204 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 46069426406 ps |
| CPU time | 517.14 seconds |
| Started | Apr 21 04:35:15 PM PDT 24 |
| Finished | Apr 21 04:43:52 PM PDT 24 |
| Peak memory | 217336 kb |
| Host | smart-7291b4f8-f00b-4a9d-8dfd-5a34df032c79 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804760204 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.3804760204 |
| Directory | /workspace/48.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/48.uart_tx_ovrd.1719325703 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 3921411314 ps |
| CPU time | 2.3 seconds |
| Started | Apr 21 04:35:14 PM PDT 24 |
| Finished | Apr 21 04:35:16 PM PDT 24 |
| Peak memory | 200796 kb |
| Host | smart-61be1492-a320-445b-a80d-34e9e0b7b6cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1719325703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.1719325703 |
| Directory | /workspace/48.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/48.uart_tx_rx.790978364 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 117502999153 ps |
| CPU time | 45.14 seconds |
| Started | Apr 21 04:35:03 PM PDT 24 |
| Finished | Apr 21 04:35:49 PM PDT 24 |
| Peak memory | 200936 kb |
| Host | smart-e7593639-2d77-4ff8-99aa-7cf794ca5717 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=790978364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.790978364 |
| Directory | /workspace/48.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/49.uart_alert_test.699648333 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 175316066 ps |
| CPU time | 0.56 seconds |
| Started | Apr 21 04:35:21 PM PDT 24 |
| Finished | Apr 21 04:35:22 PM PDT 24 |
| Peak memory | 196276 kb |
| Host | smart-3435042a-cb79-4ee3-88e4-0320b6ac41d1 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699648333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.699648333 |
| Directory | /workspace/49.uart_alert_test/latest |
| Test location | /workspace/coverage/default/49.uart_fifo_full.1121727263 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 325035872958 ps |
| CPU time | 328.75 seconds |
| Started | Apr 21 04:35:15 PM PDT 24 |
| Finished | Apr 21 04:40:44 PM PDT 24 |
| Peak memory | 200936 kb |
| Host | smart-2030b0b8-14d7-49b8-97ab-9a19de279f4b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1121727263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.1121727263 |
| Directory | /workspace/49.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/49.uart_fifo_overflow.1943328561 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 56800400450 ps |
| CPU time | 22.52 seconds |
| Started | Apr 21 04:35:22 PM PDT 24 |
| Finished | Apr 21 04:35:45 PM PDT 24 |
| Peak memory | 200908 kb |
| Host | smart-d29937b3-6c3a-40ee-9ed2-a8dce87d3130 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1943328561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.1943328561 |
| Directory | /workspace/49.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/49.uart_fifo_reset.686155460 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 8175727687 ps |
| CPU time | 16.94 seconds |
| Started | Apr 21 04:35:18 PM PDT 24 |
| Finished | Apr 21 04:35:35 PM PDT 24 |
| Peak memory | 200888 kb |
| Host | smart-1fb4c53c-0f59-4c8a-a582-a781d264559b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=686155460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.686155460 |
| Directory | /workspace/49.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/49.uart_intr.2233225561 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 2982886917 ps |
| CPU time | 2.61 seconds |
| Started | Apr 21 04:35:17 PM PDT 24 |
| Finished | Apr 21 04:35:20 PM PDT 24 |
| Peak memory | 197552 kb |
| Host | smart-ef832279-acef-4b0f-b925-e4e7cbd005d5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233225561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.2233225561 |
| Directory | /workspace/49.uart_intr/latest |
| Test location | /workspace/coverage/default/49.uart_long_xfer_wo_dly.550421448 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 58346130703 ps |
| CPU time | 291.8 seconds |
| Started | Apr 21 04:35:20 PM PDT 24 |
| Finished | Apr 21 04:40:12 PM PDT 24 |
| Peak memory | 200888 kb |
| Host | smart-d171d4b6-17ad-4055-a465-1de148ab84dd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=550421448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.550421448 |
| Directory | /workspace/49.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/49.uart_loopback.966598329 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 11007001636 ps |
| CPU time | 10.33 seconds |
| Started | Apr 21 04:35:21 PM PDT 24 |
| Finished | Apr 21 04:35:31 PM PDT 24 |
| Peak memory | 200760 kb |
| Host | smart-4fc0d12e-e84e-4f0b-8829-3478f752cc56 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=966598329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.966598329 |
| Directory | /workspace/49.uart_loopback/latest |
| Test location | /workspace/coverage/default/49.uart_noise_filter.3280615308 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 38888552587 ps |
| CPU time | 67.63 seconds |
| Started | Apr 21 04:35:18 PM PDT 24 |
| Finished | Apr 21 04:36:26 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-65378c2b-b6e3-4f91-b5c2-23ef48e95e88 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3280615308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.3280615308 |
| Directory | /workspace/49.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/49.uart_perf.1448681824 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 25259148026 ps |
| CPU time | 268.45 seconds |
| Started | Apr 21 04:35:22 PM PDT 24 |
| Finished | Apr 21 04:39:50 PM PDT 24 |
| Peak memory | 200916 kb |
| Host | smart-ffe31758-bbca-4cf2-967c-35731e5cb58c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1448681824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.1448681824 |
| Directory | /workspace/49.uart_perf/latest |
| Test location | /workspace/coverage/default/49.uart_rx_oversample.1434091816 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 7118815583 ps |
| CPU time | 16.71 seconds |
| Started | Apr 21 04:35:17 PM PDT 24 |
| Finished | Apr 21 04:35:34 PM PDT 24 |
| Peak memory | 199012 kb |
| Host | smart-c5cd2079-0908-46da-bb06-753413d9d799 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1434091816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.1434091816 |
| Directory | /workspace/49.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/49.uart_rx_parity_err.398939144 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 70159223514 ps |
| CPU time | 91.76 seconds |
| Started | Apr 21 04:35:19 PM PDT 24 |
| Finished | Apr 21 04:36:50 PM PDT 24 |
| Peak memory | 200108 kb |
| Host | smart-09a17c5d-a7c9-4f1b-a38f-7a816f29c541 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=398939144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.398939144 |
| Directory | /workspace/49.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/49.uart_rx_start_bit_filter.1942700491 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 654303771 ps |
| CPU time | 1.22 seconds |
| Started | Apr 21 04:35:21 PM PDT 24 |
| Finished | Apr 21 04:35:22 PM PDT 24 |
| Peak memory | 196556 kb |
| Host | smart-c321c5f2-7d30-4ed3-a885-d3d600432727 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1942700491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.1942700491 |
| Directory | /workspace/49.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/49.uart_smoke.1945814380 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 582345203 ps |
| CPU time | 1.49 seconds |
| Started | Apr 21 04:35:16 PM PDT 24 |
| Finished | Apr 21 04:35:17 PM PDT 24 |
| Peak memory | 200408 kb |
| Host | smart-86d05e24-bf7e-4a9b-8433-17a652b8a862 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1945814380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.1945814380 |
| Directory | /workspace/49.uart_smoke/latest |
| Test location | /workspace/coverage/default/49.uart_stress_all.3319128848 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 870747233445 ps |
| CPU time | 167.65 seconds |
| Started | Apr 21 04:35:22 PM PDT 24 |
| Finished | Apr 21 04:38:10 PM PDT 24 |
| Peak memory | 200924 kb |
| Host | smart-7fe5c408-ec03-403b-958d-93800d9fa1f2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319128848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.3319128848 |
| Directory | /workspace/49.uart_stress_all/latest |
| Test location | /workspace/coverage/default/49.uart_stress_all_with_rand_reset.479438485 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 63495114670 ps |
| CPU time | 163.22 seconds |
| Started | Apr 21 04:35:21 PM PDT 24 |
| Finished | Apr 21 04:38:04 PM PDT 24 |
| Peak memory | 215540 kb |
| Host | smart-b5a0252a-9093-410a-a91c-1db12eb8c985 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479438485 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.479438485 |
| Directory | /workspace/49.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/49.uart_tx_ovrd.323422994 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 8011344550 ps |
| CPU time | 11.1 seconds |
| Started | Apr 21 04:35:21 PM PDT 24 |
| Finished | Apr 21 04:35:32 PM PDT 24 |
| Peak memory | 200536 kb |
| Host | smart-218ae306-5803-4f83-ad7a-9bfa3cef38d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=323422994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.323422994 |
| Directory | /workspace/49.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/49.uart_tx_rx.747358439 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 8989924021 ps |
| CPU time | 17.49 seconds |
| Started | Apr 21 04:35:15 PM PDT 24 |
| Finished | Apr 21 04:35:33 PM PDT 24 |
| Peak memory | 200896 kb |
| Host | smart-45b42551-a3b0-4369-9e03-c72b79a0fc87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=747358439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.747358439 |
| Directory | /workspace/49.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/5.uart_alert_test.2396817315 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 18294289 ps |
| CPU time | 0.59 seconds |
| Started | Apr 21 04:26:40 PM PDT 24 |
| Finished | Apr 21 04:26:41 PM PDT 24 |
| Peak memory | 196244 kb |
| Host | smart-431aec9e-d1c5-4972-a2bc-dfe46bd18ac0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396817315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.2396817315 |
| Directory | /workspace/5.uart_alert_test/latest |
| Test location | /workspace/coverage/default/5.uart_fifo_full.1611691168 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 18722460245 ps |
| CPU time | 29.43 seconds |
| Started | Apr 21 04:26:25 PM PDT 24 |
| Finished | Apr 21 04:26:55 PM PDT 24 |
| Peak memory | 200844 kb |
| Host | smart-79e67174-cda4-4f02-93a3-3198c858e6fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1611691168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1611691168 |
| Directory | /workspace/5.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/5.uart_fifo_overflow.470618098 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 85774579725 ps |
| CPU time | 43.18 seconds |
| Started | Apr 21 04:26:26 PM PDT 24 |
| Finished | Apr 21 04:27:09 PM PDT 24 |
| Peak memory | 200848 kb |
| Host | smart-3a709aad-784e-46fc-bd41-923bfa665501 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=470618098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.470618098 |
| Directory | /workspace/5.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/5.uart_fifo_reset.3515441371 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 6038486072 ps |
| CPU time | 10.32 seconds |
| Started | Apr 21 04:26:28 PM PDT 24 |
| Finished | Apr 21 04:26:39 PM PDT 24 |
| Peak memory | 200676 kb |
| Host | smart-9ca65065-75d9-4817-9099-c6ef7f5d1c44 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3515441371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.3515441371 |
| Directory | /workspace/5.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/5.uart_intr.3807601976 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 23500028437 ps |
| CPU time | 17.01 seconds |
| Started | Apr 21 04:26:28 PM PDT 24 |
| Finished | Apr 21 04:26:45 PM PDT 24 |
| Peak memory | 200668 kb |
| Host | smart-637bcc1f-2e32-428c-8be7-f134b93dfc5e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807601976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.3807601976 |
| Directory | /workspace/5.uart_intr/latest |
| Test location | /workspace/coverage/default/5.uart_long_xfer_wo_dly.4089978443 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 185454687547 ps |
| CPU time | 187.75 seconds |
| Started | Apr 21 04:26:36 PM PDT 24 |
| Finished | Apr 21 04:29:44 PM PDT 24 |
| Peak memory | 200880 kb |
| Host | smart-29646d78-3e43-4a70-8bb8-695ad7ef6d75 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4089978443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.4089978443 |
| Directory | /workspace/5.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/5.uart_loopback.192326276 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 4317837886 ps |
| CPU time | 4.61 seconds |
| Started | Apr 21 04:26:33 PM PDT 24 |
| Finished | Apr 21 04:26:38 PM PDT 24 |
| Peak memory | 198940 kb |
| Host | smart-90a01c30-db1c-4731-b3ae-2f48eacf737c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=192326276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.192326276 |
| Directory | /workspace/5.uart_loopback/latest |
| Test location | /workspace/coverage/default/5.uart_noise_filter.4128046054 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 127261931643 ps |
| CPU time | 58.99 seconds |
| Started | Apr 21 04:26:29 PM PDT 24 |
| Finished | Apr 21 04:27:28 PM PDT 24 |
| Peak memory | 200128 kb |
| Host | smart-04de09aa-450f-4c00-90a9-ffa38bd1ef82 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4128046054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.4128046054 |
| Directory | /workspace/5.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/5.uart_perf.2529707501 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 10993889854 ps |
| CPU time | 438.88 seconds |
| Started | Apr 21 04:26:33 PM PDT 24 |
| Finished | Apr 21 04:33:52 PM PDT 24 |
| Peak memory | 200840 kb |
| Host | smart-69e43975-154a-4203-836d-8c4af46307c1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2529707501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2529707501 |
| Directory | /workspace/5.uart_perf/latest |
| Test location | /workspace/coverage/default/5.uart_rx_oversample.2241654160 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 3396564869 ps |
| CPU time | 7.65 seconds |
| Started | Apr 21 04:26:29 PM PDT 24 |
| Finished | Apr 21 04:26:37 PM PDT 24 |
| Peak memory | 199296 kb |
| Host | smart-ce833c2b-7f55-487f-bd3d-82a9912c0cc4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2241654160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.2241654160 |
| Directory | /workspace/5.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/5.uart_rx_parity_err.2617107524 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 152365540409 ps |
| CPU time | 129.84 seconds |
| Started | Apr 21 04:26:31 PM PDT 24 |
| Finished | Apr 21 04:28:41 PM PDT 24 |
| Peak memory | 200724 kb |
| Host | smart-a06eed49-b53f-4fab-9c14-bb03f73d75de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2617107524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.2617107524 |
| Directory | /workspace/5.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/5.uart_rx_start_bit_filter.1797232858 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 4701572698 ps |
| CPU time | 2.47 seconds |
| Started | Apr 21 04:26:30 PM PDT 24 |
| Finished | Apr 21 04:26:33 PM PDT 24 |
| Peak memory | 196932 kb |
| Host | smart-49310143-d462-43b4-a806-ba9791e4a27d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1797232858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1797232858 |
| Directory | /workspace/5.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/5.uart_smoke.3121839346 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 5969383841 ps |
| CPU time | 28.12 seconds |
| Started | Apr 21 04:26:23 PM PDT 24 |
| Finished | Apr 21 04:26:51 PM PDT 24 |
| Peak memory | 200824 kb |
| Host | smart-eb25082f-7e2b-4024-9560-3a11f453e318 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3121839346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.3121839346 |
| Directory | /workspace/5.uart_smoke/latest |
| Test location | /workspace/coverage/default/5.uart_stress_all.2383502706 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 469867939797 ps |
| CPU time | 591.97 seconds |
| Started | Apr 21 04:26:37 PM PDT 24 |
| Finished | Apr 21 04:36:30 PM PDT 24 |
| Peak memory | 209240 kb |
| Host | smart-99f047d2-6b30-4a66-b553-e737198fcfbe |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383502706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.2383502706 |
| Directory | /workspace/5.uart_stress_all/latest |
| Test location | /workspace/coverage/default/5.uart_stress_all_with_rand_reset.1038989480 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 85440040910 ps |
| CPU time | 771.07 seconds |
| Started | Apr 21 04:26:36 PM PDT 24 |
| Finished | Apr 21 04:39:27 PM PDT 24 |
| Peak memory | 217272 kb |
| Host | smart-c9263a78-efd1-48e2-a5e9-6c4e38c651fe |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038989480 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.1038989480 |
| Directory | /workspace/5.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/5.uart_tx_ovrd.1592863598 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 1962249319 ps |
| CPU time | 2.1 seconds |
| Started | Apr 21 04:26:31 PM PDT 24 |
| Finished | Apr 21 04:26:33 PM PDT 24 |
| Peak memory | 199552 kb |
| Host | smart-01b7c6e9-b2f7-43ad-a612-b713ddbd69d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1592863598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1592863598 |
| Directory | /workspace/5.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/5.uart_tx_rx.4284831899 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 61526934275 ps |
| CPU time | 110.44 seconds |
| Started | Apr 21 04:26:25 PM PDT 24 |
| Finished | Apr 21 04:28:15 PM PDT 24 |
| Peak memory | 200904 kb |
| Host | smart-27f091ec-4b7e-4ec6-9fa7-588d6beae82c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4284831899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.4284831899 |
| Directory | /workspace/5.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/50.uart_fifo_reset.852921159 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 59041456395 ps |
| CPU time | 203.69 seconds |
| Started | Apr 21 04:35:23 PM PDT 24 |
| Finished | Apr 21 04:38:47 PM PDT 24 |
| Peak memory | 200860 kb |
| Host | smart-f7b9969b-05dd-48d2-b927-0841bfce5c19 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=852921159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.852921159 |
| Directory | /workspace/50.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/50.uart_stress_all_with_rand_reset.504333483 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 77484149189 ps |
| CPU time | 909.48 seconds |
| Started | Apr 21 04:35:23 PM PDT 24 |
| Finished | Apr 21 04:50:33 PM PDT 24 |
| Peak memory | 232604 kb |
| Host | smart-f35bfb46-b958-4a45-ab92-78178875d227 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504333483 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.504333483 |
| Directory | /workspace/50.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/51.uart_fifo_reset.3756186238 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 96328593422 ps |
| CPU time | 18.52 seconds |
| Started | Apr 21 04:35:24 PM PDT 24 |
| Finished | Apr 21 04:35:42 PM PDT 24 |
| Peak memory | 200712 kb |
| Host | smart-7ae6cf8f-dfa0-4c4c-98bb-c4669f30916c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3756186238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.3756186238 |
| Directory | /workspace/51.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/51.uart_stress_all_with_rand_reset.3215615585 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 76651047708 ps |
| CPU time | 496.25 seconds |
| Started | Apr 21 04:35:24 PM PDT 24 |
| Finished | Apr 21 04:43:40 PM PDT 24 |
| Peak memory | 226696 kb |
| Host | smart-5030a6e8-068a-4ee0-b15c-1a7fb28bc9a1 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215615585 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.3215615585 |
| Directory | /workspace/51.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/52.uart_fifo_reset.576920140 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 19604640947 ps |
| CPU time | 36.17 seconds |
| Started | Apr 21 04:35:23 PM PDT 24 |
| Finished | Apr 21 04:35:59 PM PDT 24 |
| Peak memory | 200652 kb |
| Host | smart-11cfddcf-95e9-48ae-a84f-123d2ba3b59d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=576920140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.576920140 |
| Directory | /workspace/52.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/52.uart_stress_all_with_rand_reset.95608952 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 153569517450 ps |
| CPU time | 682.62 seconds |
| Started | Apr 21 04:35:22 PM PDT 24 |
| Finished | Apr 21 04:46:45 PM PDT 24 |
| Peak memory | 212560 kb |
| Host | smart-77fb8114-1a25-4d9c-9ba4-ffedbf5d301f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95608952 -assert nopostpro c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.95608952 |
| Directory | /workspace/52.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/53.uart_fifo_reset.424304668 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 104494802408 ps |
| CPU time | 91.18 seconds |
| Started | Apr 21 04:35:27 PM PDT 24 |
| Finished | Apr 21 04:36:58 PM PDT 24 |
| Peak memory | 200780 kb |
| Host | smart-ef51d60b-438b-4c5f-a3ea-837f611a8388 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=424304668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.424304668 |
| Directory | /workspace/53.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/53.uart_stress_all_with_rand_reset.226302338 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 29434174688 ps |
| CPU time | 385.44 seconds |
| Started | Apr 21 04:35:27 PM PDT 24 |
| Finished | Apr 21 04:41:52 PM PDT 24 |
| Peak memory | 217520 kb |
| Host | smart-b5d6e480-afa9-4cf2-a9eb-65bb58f7efa0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226302338 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.226302338 |
| Directory | /workspace/53.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/54.uart_fifo_reset.2088576565 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 176392771536 ps |
| CPU time | 46.71 seconds |
| Started | Apr 21 04:35:25 PM PDT 24 |
| Finished | Apr 21 04:36:12 PM PDT 24 |
| Peak memory | 200860 kb |
| Host | smart-8ac5115c-442c-4ea1-811a-acfb960d345b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2088576565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.2088576565 |
| Directory | /workspace/54.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/54.uart_stress_all_with_rand_reset.1790003035 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 327365056579 ps |
| CPU time | 790.31 seconds |
| Started | Apr 21 04:35:28 PM PDT 24 |
| Finished | Apr 21 04:48:39 PM PDT 24 |
| Peak memory | 225812 kb |
| Host | smart-16a4ccef-5b47-4067-95e1-e863b06dea1d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790003035 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.1790003035 |
| Directory | /workspace/54.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/55.uart_fifo_reset.3285149236 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 34636815478 ps |
| CPU time | 26.34 seconds |
| Started | Apr 21 04:35:30 PM PDT 24 |
| Finished | Apr 21 04:35:56 PM PDT 24 |
| Peak memory | 200852 kb |
| Host | smart-af374fc4-62ca-4754-b0bd-4bf00b32f4f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3285149236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.3285149236 |
| Directory | /workspace/55.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/55.uart_stress_all_with_rand_reset.3625540442 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 294112221975 ps |
| CPU time | 738.37 seconds |
| Started | Apr 21 04:35:31 PM PDT 24 |
| Finished | Apr 21 04:47:49 PM PDT 24 |
| Peak memory | 217364 kb |
| Host | smart-a54a76d0-3af4-4cb9-b659-b0557052f42c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625540442 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.3625540442 |
| Directory | /workspace/55.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/56.uart_fifo_reset.1108105961 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 45587292926 ps |
| CPU time | 82.94 seconds |
| Started | Apr 21 04:35:32 PM PDT 24 |
| Finished | Apr 21 04:36:55 PM PDT 24 |
| Peak memory | 200928 kb |
| Host | smart-ea559e5c-1fbd-4104-be7f-85f4669f3ce3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1108105961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1108105961 |
| Directory | /workspace/56.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/56.uart_stress_all_with_rand_reset.4098860656 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 237656501409 ps |
| CPU time | 867.47 seconds |
| Started | Apr 21 04:35:31 PM PDT 24 |
| Finished | Apr 21 04:49:59 PM PDT 24 |
| Peak memory | 217360 kb |
| Host | smart-b5b841b5-43e5-4851-b1d7-1939654dc857 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098860656 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.4098860656 |
| Directory | /workspace/56.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/57.uart_fifo_reset.2603661306 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 130031276076 ps |
| CPU time | 68.86 seconds |
| Started | Apr 21 04:35:34 PM PDT 24 |
| Finished | Apr 21 04:36:43 PM PDT 24 |
| Peak memory | 200832 kb |
| Host | smart-cf09b83f-40ed-4834-950c-6076dd0c5654 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2603661306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.2603661306 |
| Directory | /workspace/57.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/57.uart_stress_all_with_rand_reset.1932619968 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 14745590500 ps |
| CPU time | 638.1 seconds |
| Started | Apr 21 04:35:35 PM PDT 24 |
| Finished | Apr 21 04:46:14 PM PDT 24 |
| Peak memory | 209172 kb |
| Host | smart-0b788a8f-773a-4641-83fb-9b04c5254c09 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932619968 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.1932619968 |
| Directory | /workspace/57.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/58.uart_fifo_reset.81034620 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 143852267132 ps |
| CPU time | 257.54 seconds |
| Started | Apr 21 04:35:35 PM PDT 24 |
| Finished | Apr 21 04:39:53 PM PDT 24 |
| Peak memory | 200920 kb |
| Host | smart-1d1d7f20-54bd-4b69-9578-d5eec42e250c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=81034620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.81034620 |
| Directory | /workspace/58.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/58.uart_stress_all_with_rand_reset.3185149316 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 60865007875 ps |
| CPU time | 489.83 seconds |
| Started | Apr 21 04:35:35 PM PDT 24 |
| Finished | Apr 21 04:43:45 PM PDT 24 |
| Peak memory | 217004 kb |
| Host | smart-0b91f8c1-2166-4069-b77c-099e592ce6ac |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185149316 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.3185149316 |
| Directory | /workspace/58.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/59.uart_fifo_reset.3705610849 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 114972999467 ps |
| CPU time | 43.93 seconds |
| Started | Apr 21 04:35:35 PM PDT 24 |
| Finished | Apr 21 04:36:19 PM PDT 24 |
| Peak memory | 200868 kb |
| Host | smart-8dd80c0c-488a-4e91-9c71-16b16f95b97e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3705610849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.3705610849 |
| Directory | /workspace/59.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/59.uart_stress_all_with_rand_reset.486163436 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 107815506746 ps |
| CPU time | 420.07 seconds |
| Started | Apr 21 04:35:38 PM PDT 24 |
| Finished | Apr 21 04:42:38 PM PDT 24 |
| Peak memory | 217320 kb |
| Host | smart-96ac374f-422e-4431-a66c-5cbf979ed047 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486163436 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.486163436 |
| Directory | /workspace/59.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/6.uart_alert_test.2473048339 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 43523362 ps |
| CPU time | 0.56 seconds |
| Started | Apr 21 04:26:54 PM PDT 24 |
| Finished | Apr 21 04:26:55 PM PDT 24 |
| Peak memory | 196240 kb |
| Host | smart-762d4e0a-482a-41b5-ac3a-b890fa6b49ea |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473048339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.2473048339 |
| Directory | /workspace/6.uart_alert_test/latest |
| Test location | /workspace/coverage/default/6.uart_fifo_full.473935183 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 136276775567 ps |
| CPU time | 113.65 seconds |
| Started | Apr 21 04:26:42 PM PDT 24 |
| Finished | Apr 21 04:28:36 PM PDT 24 |
| Peak memory | 200796 kb |
| Host | smart-62e8fed3-3e6a-4391-83e7-37b37f421c12 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=473935183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.473935183 |
| Directory | /workspace/6.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/6.uart_fifo_overflow.420449573 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 119937845325 ps |
| CPU time | 119.17 seconds |
| Started | Apr 21 04:26:43 PM PDT 24 |
| Finished | Apr 21 04:28:43 PM PDT 24 |
| Peak memory | 200884 kb |
| Host | smart-760a03a8-1b57-4bc6-bafa-36d12e7129ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=420449573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.420449573 |
| Directory | /workspace/6.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/6.uart_intr.3719592293 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 200445238889 ps |
| CPU time | 20.26 seconds |
| Started | Apr 21 04:26:45 PM PDT 24 |
| Finished | Apr 21 04:27:05 PM PDT 24 |
| Peak memory | 200540 kb |
| Host | smart-d7d64342-e81b-4821-90b0-84a7dd8065b7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719592293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.3719592293 |
| Directory | /workspace/6.uart_intr/latest |
| Test location | /workspace/coverage/default/6.uart_long_xfer_wo_dly.1763315722 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 30582891287 ps |
| CPU time | 162.52 seconds |
| Started | Apr 21 04:26:54 PM PDT 24 |
| Finished | Apr 21 04:29:37 PM PDT 24 |
| Peak memory | 200924 kb |
| Host | smart-ae85bf71-4b66-4829-8529-1fae30b1f2e9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1763315722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.1763315722 |
| Directory | /workspace/6.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/6.uart_loopback.3111146319 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 61939223 ps |
| CPU time | 0.63 seconds |
| Started | Apr 21 04:26:51 PM PDT 24 |
| Finished | Apr 21 04:26:52 PM PDT 24 |
| Peak memory | 196684 kb |
| Host | smart-22736a5b-b9dc-411e-973c-6c26959a35df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3111146319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.3111146319 |
| Directory | /workspace/6.uart_loopback/latest |
| Test location | /workspace/coverage/default/6.uart_noise_filter.3976087636 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 44432508020 ps |
| CPU time | 75.18 seconds |
| Started | Apr 21 04:26:45 PM PDT 24 |
| Finished | Apr 21 04:28:00 PM PDT 24 |
| Peak memory | 199428 kb |
| Host | smart-c09905f4-930e-4f00-8d54-f7e7324b987a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3976087636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.3976087636 |
| Directory | /workspace/6.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/6.uart_perf.1703419428 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 19861651010 ps |
| CPU time | 986.82 seconds |
| Started | Apr 21 04:26:53 PM PDT 24 |
| Finished | Apr 21 04:43:20 PM PDT 24 |
| Peak memory | 200920 kb |
| Host | smart-d472e43d-2716-4fa4-a9f7-e0b632ea6d4f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1703419428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.1703419428 |
| Directory | /workspace/6.uart_perf/latest |
| Test location | /workspace/coverage/default/6.uart_rx_oversample.1759319278 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 1181953114 ps |
| CPU time | 1.19 seconds |
| Started | Apr 21 04:26:46 PM PDT 24 |
| Finished | Apr 21 04:26:48 PM PDT 24 |
| Peak memory | 196440 kb |
| Host | smart-0b351bf2-28dc-4bdb-bf31-de7ad1e67d7a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1759319278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.1759319278 |
| Directory | /workspace/6.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/6.uart_rx_parity_err.3648530153 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 268333611992 ps |
| CPU time | 77.92 seconds |
| Started | Apr 21 04:26:51 PM PDT 24 |
| Finished | Apr 21 04:28:09 PM PDT 24 |
| Peak memory | 200848 kb |
| Host | smart-dac62f37-dc61-4dda-9c83-906fdbd829d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3648530153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.3648530153 |
| Directory | /workspace/6.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/6.uart_rx_start_bit_filter.621954294 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 2831352936 ps |
| CPU time | 2.05 seconds |
| Started | Apr 21 04:26:45 PM PDT 24 |
| Finished | Apr 21 04:26:47 PM PDT 24 |
| Peak memory | 196644 kb |
| Host | smart-ca761a90-bd22-457c-803c-839f0c62dc1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=621954294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.621954294 |
| Directory | /workspace/6.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/6.uart_smoke.3181202250 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 5842202769 ps |
| CPU time | 13.33 seconds |
| Started | Apr 21 04:26:40 PM PDT 24 |
| Finished | Apr 21 04:26:54 PM PDT 24 |
| Peak memory | 200564 kb |
| Host | smart-8f7219f3-7332-4041-a850-70fe399ddd06 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3181202250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.3181202250 |
| Directory | /workspace/6.uart_smoke/latest |
| Test location | /workspace/coverage/default/6.uart_stress_all.1007859965 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 330518297819 ps |
| CPU time | 516.38 seconds |
| Started | Apr 21 04:26:54 PM PDT 24 |
| Finished | Apr 21 04:35:30 PM PDT 24 |
| Peak memory | 209244 kb |
| Host | smart-017ecb5a-7785-4875-b111-205a1da16149 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007859965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.1007859965 |
| Directory | /workspace/6.uart_stress_all/latest |
| Test location | /workspace/coverage/default/6.uart_stress_all_with_rand_reset.3140149370 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 318354314220 ps |
| CPU time | 850.58 seconds |
| Started | Apr 21 04:26:51 PM PDT 24 |
| Finished | Apr 21 04:41:02 PM PDT 24 |
| Peak memory | 226488 kb |
| Host | smart-a7555878-0908-42e5-ae39-daf931b426c3 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140149370 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.3140149370 |
| Directory | /workspace/6.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/6.uart_tx_ovrd.1045096860 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 7742851754 ps |
| CPU time | 14.21 seconds |
| Started | Apr 21 04:26:47 PM PDT 24 |
| Finished | Apr 21 04:27:01 PM PDT 24 |
| Peak memory | 200772 kb |
| Host | smart-3c3f601b-5b54-4913-95ae-0c638ea141ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1045096860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.1045096860 |
| Directory | /workspace/6.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/6.uart_tx_rx.1348205844 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 250173717865 ps |
| CPU time | 77.58 seconds |
| Started | Apr 21 04:26:40 PM PDT 24 |
| Finished | Apr 21 04:27:58 PM PDT 24 |
| Peak memory | 200920 kb |
| Host | smart-c31e434f-6765-4aec-8ca4-39852c90705c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1348205844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.1348205844 |
| Directory | /workspace/6.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/60.uart_fifo_reset.1236452434 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 49174518884 ps |
| CPU time | 13.7 seconds |
| Started | Apr 21 04:35:37 PM PDT 24 |
| Finished | Apr 21 04:35:50 PM PDT 24 |
| Peak memory | 200832 kb |
| Host | smart-4b295b2c-cd82-4e0e-bc03-d5684ca2d048 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1236452434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1236452434 |
| Directory | /workspace/60.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/61.uart_fifo_reset.611180596 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 19414878373 ps |
| CPU time | 32.48 seconds |
| Started | Apr 21 04:35:39 PM PDT 24 |
| Finished | Apr 21 04:36:11 PM PDT 24 |
| Peak memory | 201040 kb |
| Host | smart-43f56bea-3a54-4852-a997-96ad435ebc81 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=611180596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.611180596 |
| Directory | /workspace/61.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/61.uart_stress_all_with_rand_reset.4179113078 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 27584419991 ps |
| CPU time | 344.09 seconds |
| Started | Apr 21 04:35:41 PM PDT 24 |
| Finished | Apr 21 04:41:25 PM PDT 24 |
| Peak memory | 216472 kb |
| Host | smart-61ccacba-acab-43ef-a664-b41696afc478 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179113078 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.4179113078 |
| Directory | /workspace/61.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/62.uart_fifo_reset.958493082 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 172399607488 ps |
| CPU time | 399.66 seconds |
| Started | Apr 21 04:35:41 PM PDT 24 |
| Finished | Apr 21 04:42:21 PM PDT 24 |
| Peak memory | 200836 kb |
| Host | smart-bb37c401-e689-45b7-b86e-76636aede73f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=958493082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.958493082 |
| Directory | /workspace/62.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/62.uart_stress_all_with_rand_reset.644103247 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 59125067981 ps |
| CPU time | 144.71 seconds |
| Started | Apr 21 04:35:47 PM PDT 24 |
| Finished | Apr 21 04:38:12 PM PDT 24 |
| Peak memory | 216388 kb |
| Host | smart-afcee355-8e5e-4799-9d15-b1f23e472bc5 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644103247 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.644103247 |
| Directory | /workspace/62.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/63.uart_fifo_reset.3263483461 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 51233853120 ps |
| CPU time | 23.91 seconds |
| Started | Apr 21 04:35:45 PM PDT 24 |
| Finished | Apr 21 04:36:09 PM PDT 24 |
| Peak memory | 200864 kb |
| Host | smart-593bf661-136e-4b2e-a908-0d0c48965259 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3263483461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.3263483461 |
| Directory | /workspace/63.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/63.uart_stress_all_with_rand_reset.3531211123 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 60229917760 ps |
| CPU time | 141.53 seconds |
| Started | Apr 21 04:35:45 PM PDT 24 |
| Finished | Apr 21 04:38:07 PM PDT 24 |
| Peak memory | 211848 kb |
| Host | smart-b5f0b32d-0d54-40e0-9e1e-c2874b6bb46c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531211123 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.3531211123 |
| Directory | /workspace/63.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/64.uart_fifo_reset.1836711960 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 143172369404 ps |
| CPU time | 62.5 seconds |
| Started | Apr 21 04:35:48 PM PDT 24 |
| Finished | Apr 21 04:36:51 PM PDT 24 |
| Peak memory | 200920 kb |
| Host | smart-e0cd3939-0824-4a91-a90b-e8ef5de8cf8a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1836711960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.1836711960 |
| Directory | /workspace/64.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/64.uart_stress_all_with_rand_reset.4148961570 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 264110739893 ps |
| CPU time | 1323.48 seconds |
| Started | Apr 21 04:35:49 PM PDT 24 |
| Finished | Apr 21 04:57:52 PM PDT 24 |
| Peak memory | 225800 kb |
| Host | smart-e3c9ede4-4d60-4622-b205-53c91186cf89 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148961570 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.4148961570 |
| Directory | /workspace/64.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/65.uart_fifo_reset.926392418 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 11971996072 ps |
| CPU time | 17.59 seconds |
| Started | Apr 21 04:35:51 PM PDT 24 |
| Finished | Apr 21 04:36:09 PM PDT 24 |
| Peak memory | 200820 kb |
| Host | smart-2a65be85-a95e-4eff-8244-f82fc94b075a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=926392418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.926392418 |
| Directory | /workspace/65.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/66.uart_fifo_reset.1768017580 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 267535226689 ps |
| CPU time | 198.75 seconds |
| Started | Apr 21 04:35:53 PM PDT 24 |
| Finished | Apr 21 04:39:12 PM PDT 24 |
| Peak memory | 200792 kb |
| Host | smart-8d338739-2cb0-4468-9aa4-d9f002de25b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1768017580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.1768017580 |
| Directory | /workspace/66.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/66.uart_stress_all_with_rand_reset.4034112497 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 21059158098 ps |
| CPU time | 132.64 seconds |
| Started | Apr 21 04:35:51 PM PDT 24 |
| Finished | Apr 21 04:38:04 PM PDT 24 |
| Peak memory | 209140 kb |
| Host | smart-2b02cf80-a244-4492-8261-aef5260334ef |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034112497 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.4034112497 |
| Directory | /workspace/66.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/67.uart_fifo_reset.2512582497 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 74068225958 ps |
| CPU time | 31.18 seconds |
| Started | Apr 21 04:35:55 PM PDT 24 |
| Finished | Apr 21 04:36:26 PM PDT 24 |
| Peak memory | 200888 kb |
| Host | smart-c9d0d63c-6661-40e3-bc75-02ea2a69df5a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2512582497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.2512582497 |
| Directory | /workspace/67.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/67.uart_stress_all_with_rand_reset.3423989216 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 98725442427 ps |
| CPU time | 339.86 seconds |
| Started | Apr 21 04:35:54 PM PDT 24 |
| Finished | Apr 21 04:41:34 PM PDT 24 |
| Peak memory | 217476 kb |
| Host | smart-7b0bb01c-cbe8-48cd-b1de-0b5c6bf0e085 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423989216 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.3423989216 |
| Directory | /workspace/67.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/68.uart_stress_all_with_rand_reset.2539149928 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 286880486592 ps |
| CPU time | 994.77 seconds |
| Started | Apr 21 04:35:55 PM PDT 24 |
| Finished | Apr 21 04:52:31 PM PDT 24 |
| Peak memory | 226736 kb |
| Host | smart-0dffdede-dbe4-4e4b-b8f4-9a23da78ce40 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539149928 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.2539149928 |
| Directory | /workspace/68.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/69.uart_fifo_reset.2664415462 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 31993092296 ps |
| CPU time | 50.35 seconds |
| Started | Apr 21 04:35:54 PM PDT 24 |
| Finished | Apr 21 04:36:45 PM PDT 24 |
| Peak memory | 200912 kb |
| Host | smart-9dacc8dc-2794-4b5a-ae58-dc7693263d36 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2664415462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.2664415462 |
| Directory | /workspace/69.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/69.uart_stress_all_with_rand_reset.1766775729 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 68421355481 ps |
| CPU time | 559.45 seconds |
| Started | Apr 21 04:35:54 PM PDT 24 |
| Finished | Apr 21 04:45:14 PM PDT 24 |
| Peak memory | 225768 kb |
| Host | smart-9202deba-d859-407c-b858-71e43fde83b0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766775729 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.1766775729 |
| Directory | /workspace/69.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/7.uart_alert_test.1040193711 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 36542621 ps |
| CPU time | 0.58 seconds |
| Started | Apr 21 04:27:07 PM PDT 24 |
| Finished | Apr 21 04:27:08 PM PDT 24 |
| Peak memory | 195728 kb |
| Host | smart-2c787904-24ab-43d8-bf07-bbd1edd40247 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040193711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.1040193711 |
| Directory | /workspace/7.uart_alert_test/latest |
| Test location | /workspace/coverage/default/7.uart_fifo_full.3393545615 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 271533706908 ps |
| CPU time | 528.01 seconds |
| Started | Apr 21 04:26:56 PM PDT 24 |
| Finished | Apr 21 04:35:44 PM PDT 24 |
| Peak memory | 200908 kb |
| Host | smart-4d350873-df61-433d-9a0a-0aa91c1f46d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3393545615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.3393545615 |
| Directory | /workspace/7.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/7.uart_fifo_overflow.3574794814 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 139212067950 ps |
| CPU time | 238.29 seconds |
| Started | Apr 21 04:26:58 PM PDT 24 |
| Finished | Apr 21 04:30:57 PM PDT 24 |
| Peak memory | 200848 kb |
| Host | smart-a6c83087-8304-4d93-9dfc-484ec815daa9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3574794814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.3574794814 |
| Directory | /workspace/7.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/7.uart_fifo_reset.2481362323 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 90288745732 ps |
| CPU time | 66.35 seconds |
| Started | Apr 21 04:26:58 PM PDT 24 |
| Finished | Apr 21 04:28:05 PM PDT 24 |
| Peak memory | 200904 kb |
| Host | smart-7cd44165-551c-47a4-8186-6e8e81c8071f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2481362323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2481362323 |
| Directory | /workspace/7.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/7.uart_intr.3480189914 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 22435221811 ps |
| CPU time | 35.92 seconds |
| Started | Apr 21 04:27:01 PM PDT 24 |
| Finished | Apr 21 04:27:37 PM PDT 24 |
| Peak memory | 200836 kb |
| Host | smart-ba5c902b-0c39-46e1-abe7-81f93d285a2e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480189914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.3480189914 |
| Directory | /workspace/7.uart_intr/latest |
| Test location | /workspace/coverage/default/7.uart_long_xfer_wo_dly.1132114518 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 158923286787 ps |
| CPU time | 355.93 seconds |
| Started | Apr 21 04:27:04 PM PDT 24 |
| Finished | Apr 21 04:33:00 PM PDT 24 |
| Peak memory | 200924 kb |
| Host | smart-51dc5d44-e7e4-41a4-af64-d5b3b8707ca9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1132114518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.1132114518 |
| Directory | /workspace/7.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/7.uart_loopback.2249055319 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 5723707078 ps |
| CPU time | 12.07 seconds |
| Started | Apr 21 04:27:04 PM PDT 24 |
| Finished | Apr 21 04:27:17 PM PDT 24 |
| Peak memory | 200744 kb |
| Host | smart-f2037c90-5bbc-45ba-910a-0a950a3aa7bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2249055319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.2249055319 |
| Directory | /workspace/7.uart_loopback/latest |
| Test location | /workspace/coverage/default/7.uart_noise_filter.2907811890 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 60065896589 ps |
| CPU time | 29.09 seconds |
| Started | Apr 21 04:27:01 PM PDT 24 |
| Finished | Apr 21 04:27:30 PM PDT 24 |
| Peak memory | 201072 kb |
| Host | smart-7a9334a8-b9a2-4bcb-b76a-ca5ce782cf70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2907811890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.2907811890 |
| Directory | /workspace/7.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/7.uart_perf.1974398314 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 3592218762 ps |
| CPU time | 56.64 seconds |
| Started | Apr 21 04:27:04 PM PDT 24 |
| Finished | Apr 21 04:28:01 PM PDT 24 |
| Peak memory | 200856 kb |
| Host | smart-8d1d5c8d-2c64-47c3-957a-0bf84dccf405 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1974398314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.1974398314 |
| Directory | /workspace/7.uart_perf/latest |
| Test location | /workspace/coverage/default/7.uart_rx_oversample.127953014 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 3648033309 ps |
| CPU time | 32.64 seconds |
| Started | Apr 21 04:27:01 PM PDT 24 |
| Finished | Apr 21 04:27:34 PM PDT 24 |
| Peak memory | 200320 kb |
| Host | smart-8f5d30cc-d169-406a-a5e0-39a4833e60ac |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=127953014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.127953014 |
| Directory | /workspace/7.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/7.uart_rx_parity_err.1800046809 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 61798787789 ps |
| CPU time | 30.73 seconds |
| Started | Apr 21 04:27:03 PM PDT 24 |
| Finished | Apr 21 04:27:35 PM PDT 24 |
| Peak memory | 200820 kb |
| Host | smart-488552e3-e3eb-4f10-b53b-705d9b3e6dbd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1800046809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1800046809 |
| Directory | /workspace/7.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/7.uart_rx_start_bit_filter.1486194253 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 41131007578 ps |
| CPU time | 12.98 seconds |
| Started | Apr 21 04:27:01 PM PDT 24 |
| Finished | Apr 21 04:27:14 PM PDT 24 |
| Peak memory | 196936 kb |
| Host | smart-1d64b82b-ccc7-496f-8970-ca5676b23239 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1486194253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1486194253 |
| Directory | /workspace/7.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/7.uart_smoke.1421039872 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 5837933404 ps |
| CPU time | 15.87 seconds |
| Started | Apr 21 04:26:56 PM PDT 24 |
| Finished | Apr 21 04:27:12 PM PDT 24 |
| Peak memory | 200588 kb |
| Host | smart-4d2fa31c-c4e3-48a2-a277-ec51be6c3fbb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1421039872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.1421039872 |
| Directory | /workspace/7.uart_smoke/latest |
| Test location | /workspace/coverage/default/7.uart_stress_all_with_rand_reset.134112778 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 34849752459 ps |
| CPU time | 346.55 seconds |
| Started | Apr 21 04:27:05 PM PDT 24 |
| Finished | Apr 21 04:32:51 PM PDT 24 |
| Peak memory | 217524 kb |
| Host | smart-c4faa08a-24dd-4bf3-b12b-94984ef65eae |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134112778 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.134112778 |
| Directory | /workspace/7.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/7.uart_tx_ovrd.3494121135 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 6282231839 ps |
| CPU time | 16.12 seconds |
| Started | Apr 21 04:27:06 PM PDT 24 |
| Finished | Apr 21 04:27:22 PM PDT 24 |
| Peak memory | 200820 kb |
| Host | smart-85802b9f-4723-4554-8586-dea9c21e57c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3494121135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.3494121135 |
| Directory | /workspace/7.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/7.uart_tx_rx.2598781067 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 26299923927 ps |
| CPU time | 49.57 seconds |
| Started | Apr 21 04:26:55 PM PDT 24 |
| Finished | Apr 21 04:27:45 PM PDT 24 |
| Peak memory | 200900 kb |
| Host | smart-f6af8ad3-e470-4663-9838-5dd38c44131f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2598781067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2598781067 |
| Directory | /workspace/7.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/70.uart_fifo_reset.4226216138 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 87159846582 ps |
| CPU time | 69.84 seconds |
| Started | Apr 21 04:35:56 PM PDT 24 |
| Finished | Apr 21 04:37:06 PM PDT 24 |
| Peak memory | 200872 kb |
| Host | smart-72e1b859-7642-401b-82d7-8dd4f323b77f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4226216138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.4226216138 |
| Directory | /workspace/70.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/70.uart_stress_all_with_rand_reset.4099188492 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 67306151421 ps |
| CPU time | 522.42 seconds |
| Started | Apr 21 04:35:57 PM PDT 24 |
| Finished | Apr 21 04:44:40 PM PDT 24 |
| Peak memory | 226716 kb |
| Host | smart-73973a4a-5716-4391-bd20-6e4b90e87c01 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099188492 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.4099188492 |
| Directory | /workspace/70.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/71.uart_fifo_reset.493863024 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 68570591037 ps |
| CPU time | 292.48 seconds |
| Started | Apr 21 04:36:02 PM PDT 24 |
| Finished | Apr 21 04:40:54 PM PDT 24 |
| Peak memory | 200856 kb |
| Host | smart-4c4eeca2-d0a6-4c08-afa5-e168a8936052 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=493863024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.493863024 |
| Directory | /workspace/71.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/71.uart_stress_all_with_rand_reset.3527194368 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 17861249035 ps |
| CPU time | 270.88 seconds |
| Started | Apr 21 04:35:58 PM PDT 24 |
| Finished | Apr 21 04:40:29 PM PDT 24 |
| Peak memory | 216440 kb |
| Host | smart-40c7d144-a612-42d7-a7a0-ec62c0d1a9ac |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527194368 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.3527194368 |
| Directory | /workspace/71.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/72.uart_fifo_reset.2720093409 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 107933403110 ps |
| CPU time | 25.78 seconds |
| Started | Apr 21 04:36:00 PM PDT 24 |
| Finished | Apr 21 04:36:26 PM PDT 24 |
| Peak memory | 201076 kb |
| Host | smart-94419180-fcc3-4180-b843-28bb53755e60 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2720093409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.2720093409 |
| Directory | /workspace/72.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/72.uart_stress_all_with_rand_reset.3202621128 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 110149172594 ps |
| CPU time | 1392.56 seconds |
| Started | Apr 21 04:36:00 PM PDT 24 |
| Finished | Apr 21 04:59:13 PM PDT 24 |
| Peak memory | 230828 kb |
| Host | smart-05292db9-6954-4fa0-8ebf-3ee8a3b78453 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202621128 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.3202621128 |
| Directory | /workspace/72.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/73.uart_stress_all_with_rand_reset.2010385797 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 97036408747 ps |
| CPU time | 295.95 seconds |
| Started | Apr 21 04:36:01 PM PDT 24 |
| Finished | Apr 21 04:40:57 PM PDT 24 |
| Peak memory | 217572 kb |
| Host | smart-975aa502-896b-49b9-a72b-0b34bae367f3 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010385797 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.2010385797 |
| Directory | /workspace/73.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/74.uart_stress_all_with_rand_reset.1039258239 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 57372588649 ps |
| CPU time | 683.99 seconds |
| Started | Apr 21 04:36:02 PM PDT 24 |
| Finished | Apr 21 04:47:27 PM PDT 24 |
| Peak memory | 217456 kb |
| Host | smart-d86377c5-cdef-4190-bc0c-047176a1a1c0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039258239 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.1039258239 |
| Directory | /workspace/74.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/76.uart_fifo_reset.3276525372 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 10728011820 ps |
| CPU time | 18.86 seconds |
| Started | Apr 21 04:36:02 PM PDT 24 |
| Finished | Apr 21 04:36:21 PM PDT 24 |
| Peak memory | 200836 kb |
| Host | smart-33af4487-b674-46f9-a7e5-2d02afd8559f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3276525372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.3276525372 |
| Directory | /workspace/76.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/76.uart_stress_all_with_rand_reset.1657459711 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 380277491429 ps |
| CPU time | 1548.62 seconds |
| Started | Apr 21 04:36:04 PM PDT 24 |
| Finished | Apr 21 05:01:53 PM PDT 24 |
| Peak memory | 228644 kb |
| Host | smart-0a3f592b-25b9-4dd7-837e-edb3993ad821 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657459711 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.1657459711 |
| Directory | /workspace/76.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/77.uart_fifo_reset.2797592278 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 106735283737 ps |
| CPU time | 404.72 seconds |
| Started | Apr 21 04:36:04 PM PDT 24 |
| Finished | Apr 21 04:42:49 PM PDT 24 |
| Peak memory | 200860 kb |
| Host | smart-c5bb5f1e-04e5-4876-8d91-d16dc5208058 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2797592278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.2797592278 |
| Directory | /workspace/77.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/77.uart_stress_all_with_rand_reset.2124033744 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 58616260635 ps |
| CPU time | 653.23 seconds |
| Started | Apr 21 04:36:06 PM PDT 24 |
| Finished | Apr 21 04:46:59 PM PDT 24 |
| Peak memory | 228208 kb |
| Host | smart-9c4ed746-d493-4b41-9520-8b4a486bdcda |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124033744 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.2124033744 |
| Directory | /workspace/77.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/78.uart_fifo_reset.818975689 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 121346188681 ps |
| CPU time | 213.99 seconds |
| Started | Apr 21 04:36:05 PM PDT 24 |
| Finished | Apr 21 04:39:39 PM PDT 24 |
| Peak memory | 200824 kb |
| Host | smart-48a9d459-3114-419c-a179-b03db859f1be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=818975689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.818975689 |
| Directory | /workspace/78.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/78.uart_stress_all_with_rand_reset.692748528 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 139463151427 ps |
| CPU time | 910.39 seconds |
| Started | Apr 21 04:36:06 PM PDT 24 |
| Finished | Apr 21 04:51:16 PM PDT 24 |
| Peak memory | 233652 kb |
| Host | smart-fc5c1d09-ffc7-4fb2-ae9a-2c135a27f3fd |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692748528 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.692748528 |
| Directory | /workspace/78.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/79.uart_fifo_reset.486820849 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 170600080173 ps |
| CPU time | 22.32 seconds |
| Started | Apr 21 04:36:07 PM PDT 24 |
| Finished | Apr 21 04:36:30 PM PDT 24 |
| Peak memory | 200908 kb |
| Host | smart-918047ff-a33c-4123-b9bf-1ba77ac57f45 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=486820849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.486820849 |
| Directory | /workspace/79.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/79.uart_stress_all_with_rand_reset.1875403846 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 296873758884 ps |
| CPU time | 798.32 seconds |
| Started | Apr 21 04:36:08 PM PDT 24 |
| Finished | Apr 21 04:49:26 PM PDT 24 |
| Peak memory | 232564 kb |
| Host | smart-09ea6755-bcb6-4302-b999-f677a821cd1c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875403846 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.1875403846 |
| Directory | /workspace/79.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/8.uart_alert_test.3412781984 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 167716807 ps |
| CPU time | 0.56 seconds |
| Started | Apr 21 04:27:23 PM PDT 24 |
| Finished | Apr 21 04:27:23 PM PDT 24 |
| Peak memory | 196268 kb |
| Host | smart-696deb6f-e14b-4808-8cea-d8c664a7fa4c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412781984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.3412781984 |
| Directory | /workspace/8.uart_alert_test/latest |
| Test location | /workspace/coverage/default/8.uart_fifo_full.1912128036 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 366485973268 ps |
| CPU time | 49.34 seconds |
| Started | Apr 21 04:27:09 PM PDT 24 |
| Finished | Apr 21 04:27:59 PM PDT 24 |
| Peak memory | 200884 kb |
| Host | smart-bac28973-6c1c-46dd-b02f-413371124493 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1912128036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.1912128036 |
| Directory | /workspace/8.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/8.uart_fifo_overflow.3430989897 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 161161632862 ps |
| CPU time | 93.33 seconds |
| Started | Apr 21 04:27:09 PM PDT 24 |
| Finished | Apr 21 04:28:43 PM PDT 24 |
| Peak memory | 200900 kb |
| Host | smart-d7c894be-6145-458e-8dde-5700de658751 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3430989897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.3430989897 |
| Directory | /workspace/8.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/8.uart_fifo_reset.3803747101 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 39736631426 ps |
| CPU time | 60.35 seconds |
| Started | Apr 21 04:27:12 PM PDT 24 |
| Finished | Apr 21 04:28:13 PM PDT 24 |
| Peak memory | 200696 kb |
| Host | smart-3ae27ae4-a763-4d0f-8c1a-dc6cce5a0b2c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3803747101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.3803747101 |
| Directory | /workspace/8.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/8.uart_intr.2200560354 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 166791725322 ps |
| CPU time | 128.33 seconds |
| Started | Apr 21 04:27:14 PM PDT 24 |
| Finished | Apr 21 04:29:23 PM PDT 24 |
| Peak memory | 197472 kb |
| Host | smart-cdcc4676-f0e0-41ea-8f21-71c459393d8b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200560354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.2200560354 |
| Directory | /workspace/8.uart_intr/latest |
| Test location | /workspace/coverage/default/8.uart_long_xfer_wo_dly.1954587567 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 245468358957 ps |
| CPU time | 386.06 seconds |
| Started | Apr 21 04:27:19 PM PDT 24 |
| Finished | Apr 21 04:33:45 PM PDT 24 |
| Peak memory | 200884 kb |
| Host | smart-79bb9d03-3f0b-4302-983d-94c3b75eb81f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1954587567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.1954587567 |
| Directory | /workspace/8.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/8.uart_loopback.2480419514 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 12346725055 ps |
| CPU time | 14.05 seconds |
| Started | Apr 21 04:27:17 PM PDT 24 |
| Finished | Apr 21 04:27:31 PM PDT 24 |
| Peak memory | 200012 kb |
| Host | smart-aef631e5-fa58-4b5b-ac81-77fa68bcb85a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2480419514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.2480419514 |
| Directory | /workspace/8.uart_loopback/latest |
| Test location | /workspace/coverage/default/8.uart_noise_filter.1223190218 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 50035210303 ps |
| CPU time | 81.95 seconds |
| Started | Apr 21 04:27:16 PM PDT 24 |
| Finished | Apr 21 04:28:38 PM PDT 24 |
| Peak memory | 209260 kb |
| Host | smart-d3c88a82-bcca-4f67-a03c-e4e94c125c57 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1223190218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.1223190218 |
| Directory | /workspace/8.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/8.uart_perf.3543186790 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 12580400471 ps |
| CPU time | 698.64 seconds |
| Started | Apr 21 04:27:19 PM PDT 24 |
| Finished | Apr 21 04:38:58 PM PDT 24 |
| Peak memory | 200900 kb |
| Host | smart-3dcc6427-a978-4a63-afcc-d31c579b1c1d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3543186790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3543186790 |
| Directory | /workspace/8.uart_perf/latest |
| Test location | /workspace/coverage/default/8.uart_rx_oversample.1029735019 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 2559838253 ps |
| CPU time | 2.86 seconds |
| Started | Apr 21 04:27:15 PM PDT 24 |
| Finished | Apr 21 04:27:18 PM PDT 24 |
| Peak memory | 199680 kb |
| Host | smart-2d4f3090-c237-46dc-9c38-3f4301e1d4fc |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1029735019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.1029735019 |
| Directory | /workspace/8.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/8.uart_rx_parity_err.429631972 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 120709999834 ps |
| CPU time | 131.43 seconds |
| Started | Apr 21 04:27:18 PM PDT 24 |
| Finished | Apr 21 04:29:30 PM PDT 24 |
| Peak memory | 200884 kb |
| Host | smart-0705b231-7506-4b48-adff-86de511be8b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=429631972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.429631972 |
| Directory | /workspace/8.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/8.uart_rx_start_bit_filter.1942536969 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 4577040951 ps |
| CPU time | 7.93 seconds |
| Started | Apr 21 04:27:19 PM PDT 24 |
| Finished | Apr 21 04:27:27 PM PDT 24 |
| Peak memory | 196920 kb |
| Host | smart-da80a6c1-96b3-46b8-9917-86971fabab6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1942536969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1942536969 |
| Directory | /workspace/8.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/8.uart_smoke.308626026 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 430126433 ps |
| CPU time | 2.53 seconds |
| Started | Apr 21 04:27:10 PM PDT 24 |
| Finished | Apr 21 04:27:12 PM PDT 24 |
| Peak memory | 200388 kb |
| Host | smart-7fbc4f4d-be6c-419a-bad1-7d0de35eaf3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=308626026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.308626026 |
| Directory | /workspace/8.uart_smoke/latest |
| Test location | /workspace/coverage/default/8.uart_stress_all.3301668235 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 313529963739 ps |
| CPU time | 202.5 seconds |
| Started | Apr 21 04:27:23 PM PDT 24 |
| Finished | Apr 21 04:30:46 PM PDT 24 |
| Peak memory | 200952 kb |
| Host | smart-242a579f-2038-48ec-ae09-a3a383df5663 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301668235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.3301668235 |
| Directory | /workspace/8.uart_stress_all/latest |
| Test location | /workspace/coverage/default/8.uart_stress_all_with_rand_reset.313173271 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 361131808254 ps |
| CPU time | 856.61 seconds |
| Started | Apr 21 04:27:19 PM PDT 24 |
| Finished | Apr 21 04:41:36 PM PDT 24 |
| Peak memory | 225688 kb |
| Host | smart-b40391b7-8852-4705-91b0-be2919d7924a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313173271 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.313173271 |
| Directory | /workspace/8.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/8.uart_tx_ovrd.3762910695 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 6540738992 ps |
| CPU time | 23.25 seconds |
| Started | Apr 21 04:27:18 PM PDT 24 |
| Finished | Apr 21 04:27:42 PM PDT 24 |
| Peak memory | 200812 kb |
| Host | smart-87653f56-897f-48e5-b215-2968b5c56407 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3762910695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3762910695 |
| Directory | /workspace/8.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/8.uart_tx_rx.2173301893 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 144953513587 ps |
| CPU time | 204.53 seconds |
| Started | Apr 21 04:27:09 PM PDT 24 |
| Finished | Apr 21 04:30:33 PM PDT 24 |
| Peak memory | 200904 kb |
| Host | smart-ddf9aeae-191d-493b-aad3-b84fc173dbe1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2173301893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.2173301893 |
| Directory | /workspace/8.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/80.uart_stress_all_with_rand_reset.2400191577 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 25165080181 ps |
| CPU time | 159.21 seconds |
| Started | Apr 21 04:36:10 PM PDT 24 |
| Finished | Apr 21 04:38:49 PM PDT 24 |
| Peak memory | 216348 kb |
| Host | smart-68c44a3d-7c49-49ce-99c4-c26caa082733 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400191577 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.2400191577 |
| Directory | /workspace/80.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/81.uart_fifo_reset.2420366431 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 134729095872 ps |
| CPU time | 53.9 seconds |
| Started | Apr 21 04:36:10 PM PDT 24 |
| Finished | Apr 21 04:37:04 PM PDT 24 |
| Peak memory | 200868 kb |
| Host | smart-efbee2d9-3c85-443a-bcfe-a7e0ee1549d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2420366431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.2420366431 |
| Directory | /workspace/81.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/81.uart_stress_all_with_rand_reset.2038769175 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 77680228150 ps |
| CPU time | 432.36 seconds |
| Started | Apr 21 04:36:13 PM PDT 24 |
| Finished | Apr 21 04:43:26 PM PDT 24 |
| Peak memory | 216632 kb |
| Host | smart-ead7e49a-c2c5-4f8b-8f75-db287ed834c2 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038769175 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.2038769175 |
| Directory | /workspace/81.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/82.uart_fifo_reset.1314871441 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 157564534551 ps |
| CPU time | 234.52 seconds |
| Started | Apr 21 04:36:12 PM PDT 24 |
| Finished | Apr 21 04:40:07 PM PDT 24 |
| Peak memory | 200872 kb |
| Host | smart-daa47699-788a-4356-a3e5-a5221ae4acea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1314871441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.1314871441 |
| Directory | /workspace/82.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/82.uart_stress_all_with_rand_reset.1085819575 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 26973974295 ps |
| CPU time | 309.52 seconds |
| Started | Apr 21 04:36:13 PM PDT 24 |
| Finished | Apr 21 04:41:23 PM PDT 24 |
| Peak memory | 217220 kb |
| Host | smart-cfa91d1b-d3cd-4a34-8d5a-ddaecd3b4d02 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085819575 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.1085819575 |
| Directory | /workspace/82.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/83.uart_fifo_reset.1537560516 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 56825201305 ps |
| CPU time | 76.89 seconds |
| Started | Apr 21 04:36:12 PM PDT 24 |
| Finished | Apr 21 04:37:29 PM PDT 24 |
| Peak memory | 200896 kb |
| Host | smart-57ffb69b-8c08-4a6d-aebe-504d3be6a560 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1537560516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.1537560516 |
| Directory | /workspace/83.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/83.uart_stress_all_with_rand_reset.327522893 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 250800097690 ps |
| CPU time | 1155.99 seconds |
| Started | Apr 21 04:36:16 PM PDT 24 |
| Finished | Apr 21 04:55:32 PM PDT 24 |
| Peak memory | 217384 kb |
| Host | smart-13f62ee0-6bff-4149-ab57-46f40cf15fa6 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327522893 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.327522893 |
| Directory | /workspace/83.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/84.uart_fifo_reset.1720906584 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 106449169992 ps |
| CPU time | 65.61 seconds |
| Started | Apr 21 04:36:15 PM PDT 24 |
| Finished | Apr 21 04:37:21 PM PDT 24 |
| Peak memory | 200924 kb |
| Host | smart-c53e0dd5-2237-4972-ad03-a5e6fbb9ee22 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1720906584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.1720906584 |
| Directory | /workspace/84.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/84.uart_stress_all_with_rand_reset.4064174932 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 21627574780 ps |
| CPU time | 276.52 seconds |
| Started | Apr 21 04:36:14 PM PDT 24 |
| Finished | Apr 21 04:40:51 PM PDT 24 |
| Peak memory | 217476 kb |
| Host | smart-24328827-c944-4760-8fce-65519bbc4600 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064174932 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.4064174932 |
| Directory | /workspace/84.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/85.uart_stress_all_with_rand_reset.3034786544 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 98482950306 ps |
| CPU time | 335.16 seconds |
| Started | Apr 21 04:36:15 PM PDT 24 |
| Finished | Apr 21 04:41:50 PM PDT 24 |
| Peak memory | 210616 kb |
| Host | smart-41c24fa2-4421-43b6-a742-6acf82f983d1 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034786544 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.3034786544 |
| Directory | /workspace/85.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/86.uart_fifo_reset.950093190 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 18074595392 ps |
| CPU time | 17.5 seconds |
| Started | Apr 21 04:36:18 PM PDT 24 |
| Finished | Apr 21 04:36:36 PM PDT 24 |
| Peak memory | 200832 kb |
| Host | smart-83649978-3b0a-4f56-9c33-f06b1fa5e6d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=950093190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.950093190 |
| Directory | /workspace/86.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/86.uart_stress_all_with_rand_reset.1535125568 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 132000747504 ps |
| CPU time | 407.95 seconds |
| Started | Apr 21 04:36:17 PM PDT 24 |
| Finished | Apr 21 04:43:05 PM PDT 24 |
| Peak memory | 217304 kb |
| Host | smart-06abb068-c490-43c5-be9e-310f31ff690e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535125568 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.1535125568 |
| Directory | /workspace/86.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/87.uart_fifo_reset.3153723428 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 20100360774 ps |
| CPU time | 34.86 seconds |
| Started | Apr 21 04:36:18 PM PDT 24 |
| Finished | Apr 21 04:36:53 PM PDT 24 |
| Peak memory | 200868 kb |
| Host | smart-9d1a55d2-3ef0-430c-8488-b3f5ab911253 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3153723428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.3153723428 |
| Directory | /workspace/87.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/87.uart_stress_all_with_rand_reset.1876721290 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 107801815841 ps |
| CPU time | 619.51 seconds |
| Started | Apr 21 04:36:20 PM PDT 24 |
| Finished | Apr 21 04:46:39 PM PDT 24 |
| Peak memory | 217324 kb |
| Host | smart-87ef598b-e686-4c66-886b-9f7af2b734f3 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876721290 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.1876721290 |
| Directory | /workspace/87.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/88.uart_fifo_reset.2077326826 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 20556195469 ps |
| CPU time | 35.75 seconds |
| Started | Apr 21 04:36:21 PM PDT 24 |
| Finished | Apr 21 04:36:57 PM PDT 24 |
| Peak memory | 200908 kb |
| Host | smart-b07185cf-07ed-457c-a6d0-9d604c51ef19 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2077326826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.2077326826 |
| Directory | /workspace/88.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/88.uart_stress_all_with_rand_reset.2532587760 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 85083826208 ps |
| CPU time | 1168.35 seconds |
| Started | Apr 21 04:36:20 PM PDT 24 |
| Finished | Apr 21 04:55:48 PM PDT 24 |
| Peak memory | 217316 kb |
| Host | smart-b52667b4-a91c-4c86-82d4-0787eebbaf97 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532587760 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.2532587760 |
| Directory | /workspace/88.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/89.uart_fifo_reset.289434522 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 115261293359 ps |
| CPU time | 115.35 seconds |
| Started | Apr 21 04:36:20 PM PDT 24 |
| Finished | Apr 21 04:38:16 PM PDT 24 |
| Peak memory | 200824 kb |
| Host | smart-78f2c056-b267-4a5a-bda0-080be6feb0c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=289434522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.289434522 |
| Directory | /workspace/89.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/89.uart_stress_all_with_rand_reset.2290006665 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 69212538890 ps |
| CPU time | 1239.9 seconds |
| Started | Apr 21 04:36:23 PM PDT 24 |
| Finished | Apr 21 04:57:03 PM PDT 24 |
| Peak memory | 214392 kb |
| Host | smart-cfe18ac0-f59e-42b7-9f88-c89ae3ef9304 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290006665 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.2290006665 |
| Directory | /workspace/89.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/9.uart_alert_test.377253457 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 23382509 ps |
| CPU time | 0.56 seconds |
| Started | Apr 21 04:27:33 PM PDT 24 |
| Finished | Apr 21 04:27:34 PM PDT 24 |
| Peak memory | 196224 kb |
| Host | smart-a9eda403-06f6-4218-840b-931332118a69 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377253457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.377253457 |
| Directory | /workspace/9.uart_alert_test/latest |
| Test location | /workspace/coverage/default/9.uart_fifo_full.3869028057 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 164780032981 ps |
| CPU time | 82.47 seconds |
| Started | Apr 21 04:27:25 PM PDT 24 |
| Finished | Apr 21 04:28:48 PM PDT 24 |
| Peak memory | 200864 kb |
| Host | smart-30710760-eca2-45b3-ad14-f92ec8005f65 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3869028057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.3869028057 |
| Directory | /workspace/9.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/9.uart_fifo_overflow.1569295867 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 112785360950 ps |
| CPU time | 186.85 seconds |
| Started | Apr 21 04:27:25 PM PDT 24 |
| Finished | Apr 21 04:30:32 PM PDT 24 |
| Peak memory | 200888 kb |
| Host | smart-5d31c78b-7b03-46e2-bd51-99fde9aabbee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1569295867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1569295867 |
| Directory | /workspace/9.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/9.uart_fifo_reset.1399094094 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 57887986921 ps |
| CPU time | 58.11 seconds |
| Started | Apr 21 04:27:25 PM PDT 24 |
| Finished | Apr 21 04:28:23 PM PDT 24 |
| Peak memory | 201016 kb |
| Host | smart-152bbdfd-e72f-4842-a052-d002ee8c37ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1399094094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1399094094 |
| Directory | /workspace/9.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/9.uart_intr.3549885158 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 18003416268 ps |
| CPU time | 19.54 seconds |
| Started | Apr 21 04:27:26 PM PDT 24 |
| Finished | Apr 21 04:27:46 PM PDT 24 |
| Peak memory | 200872 kb |
| Host | smart-33b86c9f-1d3a-4c84-8cc2-8fda5307c12e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549885158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.3549885158 |
| Directory | /workspace/9.uart_intr/latest |
| Test location | /workspace/coverage/default/9.uart_long_xfer_wo_dly.4241168882 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 114101334408 ps |
| CPU time | 812.18 seconds |
| Started | Apr 21 04:27:30 PM PDT 24 |
| Finished | Apr 21 04:41:02 PM PDT 24 |
| Peak memory | 200896 kb |
| Host | smart-f6106d4d-10cd-4118-bb40-db96977449a0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4241168882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.4241168882 |
| Directory | /workspace/9.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/9.uart_loopback.3775484832 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 8791089947 ps |
| CPU time | 15.57 seconds |
| Started | Apr 21 04:27:32 PM PDT 24 |
| Finished | Apr 21 04:27:48 PM PDT 24 |
| Peak memory | 198584 kb |
| Host | smart-2116e945-1a42-4f88-98ca-d0d2f4ed835e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3775484832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.3775484832 |
| Directory | /workspace/9.uart_loopback/latest |
| Test location | /workspace/coverage/default/9.uart_noise_filter.3383883684 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 69794741580 ps |
| CPU time | 64.33 seconds |
| Started | Apr 21 04:27:28 PM PDT 24 |
| Finished | Apr 21 04:28:33 PM PDT 24 |
| Peak memory | 201088 kb |
| Host | smart-c90aabd4-6a99-4e05-8e04-3d18ec550357 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3383883684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.3383883684 |
| Directory | /workspace/9.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/9.uart_perf.4283865252 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 15318640513 ps |
| CPU time | 797.06 seconds |
| Started | Apr 21 04:27:30 PM PDT 24 |
| Finished | Apr 21 04:40:47 PM PDT 24 |
| Peak memory | 200900 kb |
| Host | smart-59abb795-6a02-429c-a330-9cb134f6d940 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4283865252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.4283865252 |
| Directory | /workspace/9.uart_perf/latest |
| Test location | /workspace/coverage/default/9.uart_rx_oversample.393914805 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 7444193364 ps |
| CPU time | 15.74 seconds |
| Started | Apr 21 04:27:26 PM PDT 24 |
| Finished | Apr 21 04:27:42 PM PDT 24 |
| Peak memory | 200088 kb |
| Host | smart-a35e3ce4-97ab-49c3-aad3-c4c353583eb7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=393914805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.393914805 |
| Directory | /workspace/9.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/9.uart_rx_parity_err.2184013141 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 103711688673 ps |
| CPU time | 43.83 seconds |
| Started | Apr 21 04:27:32 PM PDT 24 |
| Finished | Apr 21 04:28:16 PM PDT 24 |
| Peak memory | 200872 kb |
| Host | smart-9bd25b8f-e09a-419d-8762-9de5bbbba451 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2184013141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.2184013141 |
| Directory | /workspace/9.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/9.uart_rx_start_bit_filter.2219209800 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 38194667233 ps |
| CPU time | 62.75 seconds |
| Started | Apr 21 04:27:28 PM PDT 24 |
| Finished | Apr 21 04:28:31 PM PDT 24 |
| Peak memory | 196664 kb |
| Host | smart-2ad69207-546d-4549-a47b-22a5ec781fc8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2219209800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.2219209800 |
| Directory | /workspace/9.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/9.uart_smoke.348908252 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 5446487639 ps |
| CPU time | 14.56 seconds |
| Started | Apr 21 04:27:22 PM PDT 24 |
| Finished | Apr 21 04:27:37 PM PDT 24 |
| Peak memory | 200588 kb |
| Host | smart-523616e1-70f2-4f23-ad61-a24856abb72d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=348908252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.348908252 |
| Directory | /workspace/9.uart_smoke/latest |
| Test location | /workspace/coverage/default/9.uart_stress_all.1667031727 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 86376902498 ps |
| CPU time | 152.94 seconds |
| Started | Apr 21 04:27:34 PM PDT 24 |
| Finished | Apr 21 04:30:07 PM PDT 24 |
| Peak memory | 201052 kb |
| Host | smart-f3e60667-c03c-4bb8-8ed6-6fb0b9bacf8d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667031727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.1667031727 |
| Directory | /workspace/9.uart_stress_all/latest |
| Test location | /workspace/coverage/default/9.uart_stress_all_with_rand_reset.1402237456 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 9948895935 ps |
| CPU time | 79.81 seconds |
| Started | Apr 21 04:27:33 PM PDT 24 |
| Finished | Apr 21 04:28:53 PM PDT 24 |
| Peak memory | 209372 kb |
| Host | smart-ce1b138b-1ce5-464d-ab30-fece9f6cde0f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402237456 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.1402237456 |
| Directory | /workspace/9.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/9.uart_tx_ovrd.3906924530 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 1213061034 ps |
| CPU time | 1.48 seconds |
| Started | Apr 21 04:27:31 PM PDT 24 |
| Finished | Apr 21 04:27:33 PM PDT 24 |
| Peak memory | 199304 kb |
| Host | smart-bbc2ad0a-7b0c-44b1-be34-ee6a14645065 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3906924530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.3906924530 |
| Directory | /workspace/9.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/9.uart_tx_rx.2202271097 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 66173977176 ps |
| CPU time | 166.12 seconds |
| Started | Apr 21 04:27:26 PM PDT 24 |
| Finished | Apr 21 04:30:12 PM PDT 24 |
| Peak memory | 200908 kb |
| Host | smart-8fff1512-0b14-4d39-b352-a7b66152638c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2202271097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.2202271097 |
| Directory | /workspace/9.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/90.uart_fifo_reset.3664548932 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 216964369582 ps |
| CPU time | 29.85 seconds |
| Started | Apr 21 04:36:21 PM PDT 24 |
| Finished | Apr 21 04:36:51 PM PDT 24 |
| Peak memory | 200892 kb |
| Host | smart-ddbe77f3-b127-4018-8feb-804be4ea84f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3664548932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.3664548932 |
| Directory | /workspace/90.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/90.uart_stress_all_with_rand_reset.4049126284 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 51331799088 ps |
| CPU time | 1023.78 seconds |
| Started | Apr 21 04:36:22 PM PDT 24 |
| Finished | Apr 21 04:53:26 PM PDT 24 |
| Peak memory | 217348 kb |
| Host | smart-185b341c-98e8-48c6-a76c-ae25a8bf193d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049126284 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.4049126284 |
| Directory | /workspace/90.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/91.uart_stress_all_with_rand_reset.1539108154 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 245195456904 ps |
| CPU time | 666.89 seconds |
| Started | Apr 21 04:36:25 PM PDT 24 |
| Finished | Apr 21 04:47:32 PM PDT 24 |
| Peak memory | 217484 kb |
| Host | smart-11b822b2-8a3d-45cb-a7e4-e58ff4e9fe88 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539108154 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.1539108154 |
| Directory | /workspace/91.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/92.uart_fifo_reset.3749820451 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 14637396335 ps |
| CPU time | 25.51 seconds |
| Started | Apr 21 04:36:25 PM PDT 24 |
| Finished | Apr 21 04:36:51 PM PDT 24 |
| Peak memory | 200860 kb |
| Host | smart-4f124ec8-a29b-40c4-bfe8-7d3d6be315b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3749820451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.3749820451 |
| Directory | /workspace/92.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/92.uart_stress_all_with_rand_reset.2411278028 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 113957692460 ps |
| CPU time | 371.76 seconds |
| Started | Apr 21 04:36:24 PM PDT 24 |
| Finished | Apr 21 04:42:36 PM PDT 24 |
| Peak memory | 211084 kb |
| Host | smart-33a10fae-3c3e-4a2a-b9fb-ce7d8930f8ab |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411278028 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.2411278028 |
| Directory | /workspace/92.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/93.uart_fifo_reset.2032436360 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 119623039986 ps |
| CPU time | 275.71 seconds |
| Started | Apr 21 04:36:28 PM PDT 24 |
| Finished | Apr 21 04:41:04 PM PDT 24 |
| Peak memory | 200856 kb |
| Host | smart-247c7abc-bda1-4664-b4ad-ea39df41adda |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2032436360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.2032436360 |
| Directory | /workspace/93.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/94.uart_fifo_reset.1888890593 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 15984611439 ps |
| CPU time | 22.92 seconds |
| Started | Apr 21 04:36:30 PM PDT 24 |
| Finished | Apr 21 04:36:54 PM PDT 24 |
| Peak memory | 200892 kb |
| Host | smart-c09a7632-38d0-4089-af50-09d7433d7e4e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1888890593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.1888890593 |
| Directory | /workspace/94.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/94.uart_stress_all_with_rand_reset.1145046300 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 26922994382 ps |
| CPU time | 380.25 seconds |
| Started | Apr 21 04:36:31 PM PDT 24 |
| Finished | Apr 21 04:42:52 PM PDT 24 |
| Peak memory | 216036 kb |
| Host | smart-4f44c78a-748e-4eb6-8072-d889f73b20d4 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145046300 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.1145046300 |
| Directory | /workspace/94.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/95.uart_fifo_reset.1423469880 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 61422172437 ps |
| CPU time | 344.52 seconds |
| Started | Apr 21 04:36:32 PM PDT 24 |
| Finished | Apr 21 04:42:17 PM PDT 24 |
| Peak memory | 200924 kb |
| Host | smart-f3e790ca-46e3-413e-b101-3af663b71f37 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1423469880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.1423469880 |
| Directory | /workspace/95.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/95.uart_stress_all_with_rand_reset.3510958425 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 11776920043 ps |
| CPU time | 643.56 seconds |
| Started | Apr 21 04:36:33 PM PDT 24 |
| Finished | Apr 21 04:47:17 PM PDT 24 |
| Peak memory | 200908 kb |
| Host | smart-1218f7fa-d0ef-4169-88bb-2b10689066a9 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510958425 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.3510958425 |
| Directory | /workspace/95.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/96.uart_fifo_reset.3899096512 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 90298236900 ps |
| CPU time | 235.23 seconds |
| Started | Apr 21 04:36:34 PM PDT 24 |
| Finished | Apr 21 04:40:30 PM PDT 24 |
| Peak memory | 200844 kb |
| Host | smart-60f4239c-255a-4ddb-80c7-7ae5f0203768 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3899096512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3899096512 |
| Directory | /workspace/96.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/96.uart_stress_all_with_rand_reset.3669188240 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 173772661032 ps |
| CPU time | 797.09 seconds |
| Started | Apr 21 04:36:36 PM PDT 24 |
| Finished | Apr 21 04:49:53 PM PDT 24 |
| Peak memory | 225744 kb |
| Host | smart-1e508572-64d4-4a15-9609-a095fbfea70a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669188240 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.3669188240 |
| Directory | /workspace/96.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/97.uart_fifo_reset.3158728922 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 114267089602 ps |
| CPU time | 192.46 seconds |
| Started | Apr 21 04:36:37 PM PDT 24 |
| Finished | Apr 21 04:39:50 PM PDT 24 |
| Peak memory | 200896 kb |
| Host | smart-b53084d0-e9b0-42bb-bb54-c3c877545ea1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3158728922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.3158728922 |
| Directory | /workspace/97.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/97.uart_stress_all_with_rand_reset.3960876452 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 38289250133 ps |
| CPU time | 536.34 seconds |
| Started | Apr 21 04:36:34 PM PDT 24 |
| Finished | Apr 21 04:45:30 PM PDT 24 |
| Peak memory | 217372 kb |
| Host | smart-278ee001-be95-4151-9a6c-bd30dec2471f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960876452 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.3960876452 |
| Directory | /workspace/97.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/98.uart_fifo_reset.1528919167 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 200717347996 ps |
| CPU time | 110.69 seconds |
| Started | Apr 21 04:36:37 PM PDT 24 |
| Finished | Apr 21 04:38:28 PM PDT 24 |
| Peak memory | 200900 kb |
| Host | smart-41be7d57-75b5-4c58-85cd-21d4fc187384 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1528919167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.1528919167 |
| Directory | /workspace/98.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/98.uart_stress_all_with_rand_reset.1546756525 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 70753967736 ps |
| CPU time | 843.83 seconds |
| Started | Apr 21 04:36:45 PM PDT 24 |
| Finished | Apr 21 04:50:49 PM PDT 24 |
| Peak memory | 213844 kb |
| Host | smart-992c5c80-4d0f-4d01-bbe4-d1e539ec51e3 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546756525 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.1546756525 |
| Directory | /workspace/98.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/99.uart_fifo_reset.1303187993 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 60783971363 ps |
| CPU time | 61.01 seconds |
| Started | Apr 21 04:36:39 PM PDT 24 |
| Finished | Apr 21 04:37:40 PM PDT 24 |
| Peak memory | 200844 kb |
| Host | smart-41e2600c-e184-440f-bd88-e9afc3ae5cdf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1303187993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.1303187993 |
| Directory | /workspace/99.uart_fifo_reset/latest |
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