Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	116580	1			T1	55		T2	51		T3	1903
all_values[1]	116580	1			T1	55		T2	51		T3	1903
all_values[2]	116580	1			T1	55		T2	51		T3	1903
all_values[3]	116580	1			T1	55		T2	51		T3	1903
all_values[4]	116580	1			T1	55		T2	51		T3	1903
all_values[5]	116580	1			T1	55		T2	51		T3	1903
all_values[6]	116580	1			T1	55		T2	51		T3	1903
all_values[7]	116580	1			T1	55		T2	51		T3	1903

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

478901

1

T1

191

T2

236

T3

9627

auto[1]

453739

1

T1

249

T2

172

T3

5597

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

876572

1

T1

429

T2

394

T3

14810

auto[1]

56068

1

T1

11

T2

14

T3

414

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	37190	1			T1	49		T2	19		T3	481
all_values[0]	auto[0]	auto[1]	23618	1			T1	1		T3	381		T4	53
all_values[0]	auto[1]	auto[0]	34565	1			T1	5		T2	23		T3	1018
all_values[0]	auto[1]	auto[1]	21207	1			T2	9		T3	23		T4	107
all_values[1]	auto[0]	auto[0]	55575	1			T1	27		T2	5		T3	1595
all_values[1]	auto[0]	auto[1]	1642	1			T4	5		T8	5		T11	13
all_values[1]	auto[1]	auto[0]	57753	1			T1	28		T2	45		T3	308
all_values[1]	auto[1]	auto[1]	1610	1			T2	1		T4	12		T7	5
all_values[2]	auto[0]	auto[0]	59196	1			T1	8		T2	42		T3	1003
all_values[2]	auto[0]	auto[1]	2701	1			T1	1		T2	4		T3	5
all_values[2]	auto[1]	auto[0]	52183	1			T1	37		T2	5		T3	890
all_values[2]	auto[1]	auto[1]	2500	1			T1	9		T3	5		T4	8
all_values[3]	auto[0]	auto[0]	58174	1			T1	11		T2	14		T3	1568
all_values[3]	auto[0]	auto[1]	283	1			T4	2		T13	1		T48	1
all_values[3]	auto[1]	auto[0]	57831	1			T1	44		T2	37		T3	335
all_values[3]	auto[1]	auto[1]	292	1			T11	1		T13	3		T17	1
all_values[4]	auto[0]	auto[0]	59877	1			T1	16		T2	46		T3	1181
all_values[4]	auto[0]	auto[1]	447	1			T11	1		T17	6		T20	7
all_values[4]	auto[1]	auto[0]	55838	1			T1	39		T2	5		T3	722
all_values[4]	auto[1]	auto[1]	418	1			T4	11		T14	2		T15	16
all_values[5]	auto[0]	auto[0]	57629	1			T1	19		T2	46		T3	378
all_values[5]	auto[0]	auto[1]	182	1			T14	2		T20	3		T32	1
all_values[5]	auto[1]	auto[0]	58610	1			T1	36		T2	5		T3	1525
all_values[5]	auto[1]	auto[1]	159	1			T19	2		T32	3		T33	1
all_values[6]	auto[0]	auto[0]	62097	1			T1	46		T2	46		T3	1389
all_values[6]	auto[0]	auto[1]	183	1			T14	3		T19	1		T32	1
all_values[6]	auto[1]	auto[0]	54147	1			T1	9		T2	5		T3	514
all_values[6]	auto[1]	auto[1]	153	1			T20	3		T19	2		T32	3
all_values[7]	auto[0]	auto[0]	59801	1			T1	13		T2	14		T3	1646
all_values[7]	auto[0]	auto[1]	306	1			T4	2		T14	1		T20	3
all_values[7]	auto[1]	auto[0]	56106	1			T1	42		T2	37		T3	257
all_values[7]	auto[1]	auto[1]	367	1			T14	3		T13	2		T19	1