Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2261	1			T2	1		T4	8		T5	9
auto[BaudRate115200]	2073	1			T2	1		T3	2		T4	11
auto[BaudRate230400]	1912	1			T3	3		T4	5		T8	1
auto[BaudRate128Kbps]	2044	1			T2	2		T4	5		T5	3
auto[BaudRate256Kbps]	2223	1			T1	2		T2	1		T3	4
auto[BaudRate1Mbps]	1765	1			T1	2		T4	11		T6	1
auto[BaudRate1p5Mbps]	1320	1			T1	4		T3	1		T6	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1478	1			T12	8		T326	4		T148	8
freqs[25]	1017	1			T8	12		T11	2		T41	7
freqs[48]	521	1			T42	3		T132	5		T291	2
freqs[50]	516	1			T9	8		T21	10		T106	4
freqs[100]	1419	1			T10	47		T16	2		T51	5

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	216	1			T12	3		T137	1		T135	2
auto[BaudRate9600]	freqs[25]	232	1			T8	1		T110	2		T53	1
auto[BaudRate9600]	freqs[48]	83	1			T291	1		T216	3		T164	2
auto[BaudRate9600]	freqs[50]	93	1			T9	2		T21	2		T106	4
auto[BaudRate9600]	freqs[100]	243	1			T10	9		T277	3		T264	4
auto[BaudRate115200]	freqs[24]	223	1			T12	1		T148	1		T137	1
auto[BaudRate115200]	freqs[25]	154	1			T8	1		T110	1		T17	1
auto[BaudRate115200]	freqs[48]	87	1			T291	1		T164	3		T169	1
auto[BaudRate115200]	freqs[50]	69	1			T9	3		T273	4		T31	2
auto[BaudRate115200]	freqs[100]	188	1			T277	1		T264	1		T278	1
auto[BaudRate230400]	freqs[24]	193	1			T12	2		T326	2		T148	1
auto[BaudRate230400]	freqs[25]	130	1			T8	1		T110	3		T53	1
auto[BaudRate230400]	freqs[48]	63	1			T132	1		T176	3		T164	1
auto[BaudRate230400]	freqs[50]	79	1			T9	1		T21	3		T273	2
auto[BaudRate230400]	freqs[100]	168	1			T10	3		T16	1		T51	1
auto[BaudRate128Kbps]	freqs[24]	227	1			T12	1		T326	1		T148	2
auto[BaudRate128Kbps]	freqs[25]	131	1			T8	3		T11	2		T41	3
auto[BaudRate128Kbps]	freqs[48]	72	1			T42	3		T176	1		T167	3
auto[BaudRate128Kbps]	freqs[50]	71	1			T21	3		T273	3		T31	1
auto[BaudRate128Kbps]	freqs[100]	192	1			T10	3		T51	1		T277	3
auto[BaudRate256Kbps]	freqs[24]	239	1			T12	1		T148	2		T137	2
auto[BaudRate256Kbps]	freqs[25]	141	1			T8	1		T41	1		T19	4
auto[BaudRate256Kbps]	freqs[48]	82	1			T132	2		T216	2		T176	1
auto[BaudRate256Kbps]	freqs[50]	72	1			T21	1		T273	1		T31	4
auto[BaudRate256Kbps]	freqs[100]	222	1			T10	17		T277	2		T286	1
auto[BaudRate1Mbps]	freqs[24]	272	1			T326	1		T148	2		T137	2
auto[BaudRate1Mbps]	freqs[25]	134	1			T8	3		T41	3		T110	2
auto[BaudRate1Mbps]	freqs[48]	72	1			T132	1		T216	2		T176	1
auto[BaudRate1Mbps]	freqs[50]	76	1			T9	1		T273	2		T121	2
auto[BaudRate1Mbps]	freqs[100]	203	1			T10	6		T16	1		T51	3
auto[BaudRate1p5Mbps]	freqs[25]	95	1			T8	2		T110	1		T47	1
auto[BaudRate1p5Mbps]	freqs[48]	62	1			T132	1		T216	2		T176	2
auto[BaudRate1p5Mbps]	freqs[50]	56	1			T9	1		T21	1		T31	2
auto[BaudRate1p5Mbps]	freqs[100]	203	1			T10	9		T277	5		T264	2

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded