Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.43	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	9	121	93.08

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	9	121	93.08	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	32853899	1			T1	115441		T2	61		T3	840567
all_levels[1]	200630	1			T1	3902		T2	18		T3	223
all_levels[2]	2599	1			T2	1		T4	18		T7	1
all_levels[3]	1143	1			T2	2		T4	10		T6	1
all_levels[4]	702	1			T2	1		T4	2		T6	1
all_levels[5]	554	1			T2	1		T4	4		T8	2
all_levels[6]	461	1			T4	3		T8	1		T9	1
all_levels[7]	354	1			T4	3		T8	1		T9	1
all_levels[8]	285	1			T8	1		T37	1		T13	1
all_levels[9]	304	1			T4	2		T6	1		T9	2
all_levels[10]	244	1			T2	1		T9	1		T129	2
all_levels[11]	194	1			T2	1		T4	1		T6	1
all_levels[12]	162	1			T4	1		T92	1		T129	1
all_levels[13]	159	1			T2	1		T12	1		T45	1
all_levels[14]	129	1			T12	1		T15	1		T130	2
all_levels[15]	154	1			T2	1		T9	1		T13	1
all_levels[16]	101	1			T129	1		T12	1		T13	2
all_levels[17]	124	1			T50	3		T53	2		T19	1
all_levels[18]	95	1			T2	1		T7	1		T129	1
all_levels[19]	104	1			T12	1		T13	2		T46	2
all_levels[20]	75	1			T15	1		T19	1		T130	1
all_levels[21]	87	1			T9	1		T46	1		T110	1
all_levels[22]	65	1			T45	1		T52	1		T53	1
all_levels[23]	68	1			T19	2		T130	1		T131	1
all_levels[24]	61	1			T46	1		T132	1		T130	2
all_levels[25]	74	1			T13	2		T50	1		T52	2
all_levels[26]	46	1			T130	1		T133	1		T126	1
all_levels[27]	40	1			T4	1		T134	1		T126	1
all_levels[28]	45	1			T129	1		T15	1		T135	1
all_levels[29]	34	1			T136	1		T50	2		T137	1
all_levels[30]	41	1			T13	1		T110	2		T48	1
all_levels[31]	33	1			T29	1		T30	1		T135	1
all_levels[32]	29	1			T7	1		T15	1		T138	1
all_levels[33]	39	1			T6	1		T48	1		T50	1
all_levels[34]	38	1			T15	1		T139	1		T140	1
all_levels[35]	32	1			T2	1		T7	3		T13	1
all_levels[36]	20	1			T6	1		T12	1		T48	1
all_levels[37]	23	1			T15	1		T141	1		T142	1
all_levels[38]	25	1			T143	2		T128	1		T144	1
all_levels[39]	23	1			T136	1		T145	1		T146	1
all_levels[40]	19	1			T48	1		T20	1		T147	1
all_levels[41]	27	1			T148	2		T149	1		T150	1
all_levels[42]	24	1			T148	1		T30	1		T151	1
all_levels[43]	18	1			T15	2		T119	1		T152	2
all_levels[44]	11	1			T147	1		T153	1		T154	2
all_levels[45]	25	1			T19	1		T119	1		T155	1
all_levels[46]	16	1			T140	2		T127	1		T156	1
all_levels[47]	18	1			T157	1		T145	1		T158	3
all_levels[48]	16	1			T159	1		T160	1		T161	2
all_levels[49]	5	1			T157	1		T162	1		T163	1
all_levels[50]	8	1			T164	1		T165	1		T166	1
all_levels[51]	9	1			T149	1		T158	1		T167	1
all_levels[52]	12	1			T127	1		T168	1		T169	1
all_levels[53]	7	1			T170	1		T171	2		T172	1
all_levels[54]	7	1			T170	1		T160	1		T173	1
all_levels[55]	15	1			T131	1		T174	1		T175	3
all_levels[56]	12	1			T176	1		T54	2		T177	1
all_levels[57]	7	1			T178	1		T163	1		T179	1
all_levels[58]	12	1			T19	1		T126	1		T180	1
all_levels[59]	10	1			T12	1		T181	1		T182	3
all_levels[60]	4	1			T168	1		T183	1		T59	1
all_levels[61]	4	1			T157	1		T184	1		T185	1
all_levels[62]	17	1			T164	1		T186	1		T187	3
all_levels[63]	1	1			T188	1		-	-		-	-
all_levels[64]	105	1			T12	3		T13	2		T148	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33059063

1

T1

119343

T2

86

T3

840790

auto[1]

4641

1

T2

4

T4

18

T5

2

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	9	121	93.08	9

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[37]]	[auto[1]]	0	1	1
[all_levels[49] , all_levels[50] , all_levels[51]]	[auto[1]]	--	--	3
[all_levels[54]]	[auto[1]]	0	1	1
[all_levels[56]]	[auto[1]]	0	1	1
[all_levels[60] , all_levels[61]]	[auto[1]]	--	--	2
[all_levels[63]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	32849756	1			T1	115441		T2	57		T3	840567
all_levels[0]	auto[1]	4143	1			T2	4		T4	18		T5	2
all_levels[1]	auto[0]	200537	1			T1	3902		T2	18		T3	223
all_levels[1]	auto[1]	93	1			T9	2		T36	1		T111	3
all_levels[2]	auto[0]	2572	1			T2	1		T4	18		T7	1
all_levels[2]	auto[1]	27	1			T189	1		T190	2		T191	1
all_levels[3]	auto[0]	1120	1			T2	2		T4	10		T6	1
all_levels[3]	auto[1]	23	1			T140	1		T190	1		T192	1
all_levels[4]	auto[0]	687	1			T2	1		T4	2		T6	1
all_levels[4]	auto[1]	15	1			T189	1		T193	1		T150	2
all_levels[5]	auto[0]	535	1			T2	1		T4	4		T8	2
all_levels[5]	auto[1]	19	1			T20	1		T140	2		T187	2
all_levels[6]	auto[0]	442	1			T4	3		T8	1		T9	1
all_levels[6]	auto[1]	19	1			T152	1		T194	1		T186	2
all_levels[7]	auto[0]	341	1			T4	3		T8	1		T9	1
all_levels[7]	auto[1]	13	1			T195	1		T128	2		T196	1
all_levels[8]	auto[0]	273	1			T8	1		T37	1		T13	1
all_levels[8]	auto[1]	12	1			T197	1		T143	1		T198	2
all_levels[9]	auto[0]	280	1			T4	2		T6	1		T9	2
all_levels[9]	auto[1]	24	1			T197	1		T190	1		T195	1
all_levels[10]	auto[0]	226	1			T2	1		T9	1		T129	2
all_levels[10]	auto[1]	18	1			T199	1		T200	3		T201	3
all_levels[11]	auto[0]	182	1			T2	1		T4	1		T6	1
all_levels[11]	auto[1]	12	1			T161	1		T202	3		T203	2
all_levels[12]	auto[0]	155	1			T4	1		T92	1		T129	1
all_levels[12]	auto[1]	7	1			T204	1		T205	1		T206	1
all_levels[13]	auto[0]	150	1			T2	1		T12	1		T45	1
all_levels[13]	auto[1]	9	1			T53	1		T207	1		T208	1
all_levels[14]	auto[0]	125	1			T12	1		T15	1		T130	2
all_levels[14]	auto[1]	4	1			T209	1		T210	1		T211	1
all_levels[15]	auto[0]	142	1			T2	1		T9	1		T13	1
all_levels[15]	auto[1]	12	1			T150	2		T212	1		T213	2
all_levels[16]	auto[0]	99	1			T129	1		T12	1		T13	2
all_levels[16]	auto[1]	2	1			T214	1		T215	1		-	-
all_levels[17]	auto[0]	114	1			T50	2		T53	1		T19	1
all_levels[17]	auto[1]	10	1			T50	1		T53	1		T216	1
all_levels[18]	auto[0]	88	1			T2	1		T7	1		T129	1
all_levels[18]	auto[1]	7	1			T217	3		T164	2		T218	1
all_levels[19]	auto[0]	96	1			T12	1		T13	2		T46	2
all_levels[19]	auto[1]	8	1			T121	1		T157	1		T219	1
all_levels[20]	auto[0]	64	1			T15	1		T19	1		T130	1
all_levels[20]	auto[1]	11	1			T190	1		T175	4		T220	1
all_levels[21]	auto[0]	77	1			T9	1		T46	1		T110	1
all_levels[21]	auto[1]	10	1			T164	1		T221	4		T222	1
all_levels[22]	auto[0]	62	1			T45	1		T52	1		T53	1
all_levels[22]	auto[1]	3	1			T223	1		T224	1		T225	1
all_levels[23]	auto[0]	59	1			T19	2		T130	1		T131	1
all_levels[23]	auto[1]	9	1			T226	1		T165	5		T227	2
all_levels[24]	auto[0]	56	1			T46	1		T132	1		T130	2
all_levels[24]	auto[1]	5	1			T228	4		T229	1		-	-
all_levels[25]	auto[0]	59	1			T13	2		T50	1		T52	1
all_levels[25]	auto[1]	15	1			T52	1		T230	1		T231	4
all_levels[26]	auto[0]	44	1			T130	1		T133	1		T126	1
all_levels[26]	auto[1]	2	1			T147	1		T232	1		-	-
all_levels[27]	auto[0]	37	1			T4	1		T134	1		T126	1
all_levels[27]	auto[1]	3	1			T166	2		T233	1		-	-
all_levels[28]	auto[0]	41	1			T129	1		T15	1		T135	1
all_levels[28]	auto[1]	4	1			T234	2		T235	2		-	-
all_levels[29]	auto[0]	32	1			T136	1		T50	1		T137	1
all_levels[29]	auto[1]	2	1			T50	1		T236	1		-	-
all_levels[30]	auto[0]	34	1			T13	1		T110	2		T48	1
all_levels[30]	auto[1]	7	1			T20	1		T237	1		T238	2
all_levels[31]	auto[0]	30	1			T29	1		T30	1		T135	1
all_levels[31]	auto[1]	3	1			T239	2		T240	1		-	-
all_levels[32]	auto[0]	26	1			T7	1		T15	1		T138	1
all_levels[32]	auto[1]	3	1			T241	2		T242	1		-	-
all_levels[33]	auto[0]	37	1			T6	1		T48	1		T50	1
all_levels[33]	auto[1]	2	1			T225	1		T243	1		-	-
all_levels[34]	auto[0]	31	1			T15	1		T139	1		T140	1
all_levels[34]	auto[1]	7	1			T244	1		T245	3		T78	3
all_levels[35]	auto[0]	28	1			T2	1		T7	2		T13	1
all_levels[35]	auto[1]	4	1			T7	1		T246	2		T247	1
all_levels[36]	auto[0]	19	1			T6	1		T12	1		T48	1
all_levels[36]	auto[1]	1	1			T248	1		-	-		-	-
all_levels[37]	auto[0]	23	1			T15	1		T141	1		T142	1
all_levels[38]	auto[0]	22	1			T143	1		T128	1		T144	1
all_levels[38]	auto[1]	3	1			T143	1		T249	1		T250	1
all_levels[39]	auto[0]	19	1			T136	1		T145	1		T146	1
all_levels[39]	auto[1]	4	1			T251	1		T230	3		-	-
all_levels[40]	auto[0]	18	1			T48	1		T20	1		T147	1
all_levels[40]	auto[1]	1	1			T252	1		-	-		-	-
all_levels[41]	auto[0]	23	1			T148	1		T149	1		T150	1
all_levels[41]	auto[1]	4	1			T148	1		T203	1		T253	1
all_levels[42]	auto[0]	22	1			T148	1		T30	1		T151	1
all_levels[42]	auto[1]	2	1			T194	1		T147	1		-	-
all_levels[43]	auto[0]	17	1			T15	2		T119	1		T152	1
all_levels[43]	auto[1]	1	1			T152	1		-	-		-	-
all_levels[44]	auto[0]	10	1			T147	1		T153	1		T154	1
all_levels[44]	auto[1]	1	1			T154	1		-	-		-	-
all_levels[45]	auto[0]	18	1			T19	1		T119	1		T155	1
all_levels[45]	auto[1]	7	1			T254	7		-	-		-	-
all_levels[46]	auto[0]	15	1			T140	1		T127	1		T156	1
all_levels[46]	auto[1]	1	1			T140	1		-	-		-	-
all_levels[47]	auto[0]	16	1			T157	1		T145	1		T158	1
all_levels[47]	auto[1]	2	1			T158	2		-	-		-	-
all_levels[48]	auto[0]	15	1			T159	1		T160	1		T161	1
all_levels[48]	auto[1]	1	1			T161	1		-	-		-	-
all_levels[49]	auto[0]	5	1			T157	1		T162	1		T163	1
all_levels[50]	auto[0]	8	1			T164	1		T165	1		T166	1
all_levels[51]	auto[0]	9	1			T149	1		T158	1		T167	1
all_levels[52]	auto[0]	9	1			T127	1		T168	1		T169	1
all_levels[52]	auto[1]	3	1			T156	2		T255	1		-	-
all_levels[53]	auto[0]	6	1			T170	1		T171	1		T172	1
all_levels[53]	auto[1]	1	1			T171	1		-	-		-	-
all_levels[54]	auto[0]	7	1			T170	1		T160	1		T173	1
all_levels[55]	auto[0]	8	1			T131	1		T174	1		T175	1
all_levels[55]	auto[1]	7	1			T175	2		T256	1		T257	4
all_levels[56]	auto[0]	12	1			T176	1		T54	2		T177	1
all_levels[57]	auto[0]	6	1			T178	1		T163	1		T179	1
all_levels[57]	auto[1]	1	1			T258	1		-	-		-	-
all_levels[58]	auto[0]	11	1			T19	1		T126	1		T180	1
all_levels[58]	auto[1]	1	1			T259	1		-	-		-	-
all_levels[59]	auto[0]	8	1			T12	1		T181	1		T182	1
all_levels[59]	auto[1]	2	1			T182	2		-	-		-	-
all_levels[60]	auto[0]	4	1			T168	1		T183	1		T59	1
all_levels[61]	auto[0]	4	1			T157	1		T184	1		T185	1
all_levels[62]	auto[0]	11	1			T164	1		T186	1		T187	1
all_levels[62]	auto[1]	6	1			T187	2		T193	1		T260	3
all_levels[63]	auto[0]	1	1			T188	1		-	-		-	-
all_levels[64]	auto[0]	80	1			T12	3		T13	2		T148	1
all_levels[64]	auto[1]	25	1			T261	1		T157	2		T164	1