Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	116580	1			T1	55		T2	51		T3	1903
all_pins[1]	116580	1			T1	55		T2	51		T3	1903
all_pins[2]	116580	1			T1	55		T2	51		T3	1903
all_pins[3]	116580	1			T1	55		T2	51		T3	1903
all_pins[4]	116580	1			T1	55		T2	51		T3	1903
all_pins[5]	116580	1			T1	55		T2	51		T3	1903
all_pins[6]	116580	1			T1	55		T2	51		T3	1903
all_pins[7]	116580	1			T1	55		T2	51		T3	1903

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	905032	1			T1	431		T2	398		T3	15196
values[0x1]	27608	1			T1	9		T2	10		T3	28
transitions[0x0=>0x1]	26600	1			T1	9		T2	10		T3	28
transitions[0x1=>0x0]	26171	1			T1	9		T2	9		T3	27

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	95293	1			T1	55		T2	42		T3	1880
all_pins[0]	values[0x1]	21287	1			T2	9		T3	23		T4	108
all_pins[0]	transitions[0x0=>0x1]	20777	1			T2	9		T3	23		T4	97
all_pins[0]	transitions[0x1=>0x0]	1103	1			T2	1		T4	1		T7	5
all_pins[1]	values[0x0]	114967	1			T1	55		T2	50		T3	1903
all_pins[1]	values[0x1]	1613	1			T2	1		T4	12		T7	5
all_pins[1]	transitions[0x0=>0x1]	1513	1			T2	1		T4	12		T7	5
all_pins[1]	transitions[0x1=>0x0]	2463	1			T1	9		T3	5		T4	9
all_pins[2]	values[0x0]	114017	1			T1	46		T2	51		T3	1898
all_pins[2]	values[0x1]	2563	1			T1	9		T3	5		T4	9
all_pins[2]	transitions[0x0=>0x1]	2497	1			T1	9		T3	5		T4	9
all_pins[2]	transitions[0x1=>0x0]	226	1			T11	1		T13	2		T17	1
all_pins[3]	values[0x0]	116288	1			T1	55		T2	51		T3	1903
all_pins[3]	values[0x1]	292	1			T11	1		T13	3		T17	1
all_pins[3]	transitions[0x0=>0x1]	257	1			T11	1		T13	3		T17	1
all_pins[3]	transitions[0x1=>0x0]	383	1			T4	11		T14	2		T15	16
all_pins[4]	values[0x0]	116162	1			T1	55		T2	51		T3	1903
all_pins[4]	values[0x1]	418	1			T4	11		T14	2		T15	16
all_pins[4]	transitions[0x0=>0x1]	357	1			T4	11		T14	2		T15	16
all_pins[4]	transitions[0x1=>0x0]	141	1			T20	1		T32	1		T33	1
all_pins[5]	values[0x0]	116378	1			T1	55		T2	51		T3	1903
all_pins[5]	values[0x1]	202	1			T20	2		T19	2		T32	3
all_pins[5]	transitions[0x0=>0x1]	166	1			T20	2		T32	2		T33	1
all_pins[5]	transitions[0x1=>0x0]	831	1			T4	5		T7	2		T8	1
all_pins[6]	values[0x0]	115713	1			T1	55		T2	51		T3	1903
all_pins[6]	values[0x1]	867	1			T4	5		T7	2		T8	1
all_pins[6]	transitions[0x0=>0x1]	818	1			T4	5		T7	2		T8	1
all_pins[6]	transitions[0x1=>0x0]	317	1			T14	3		T13	2		T30	3
all_pins[7]	values[0x0]	116214	1			T1	55		T2	51		T3	1903
all_pins[7]	values[0x1]	366	1			T14	3		T13	2		T19	1
all_pins[7]	transitions[0x0=>0x1]	215	1			T14	2		T19	1		T30	6
all_pins[7]	transitions[0x1=>0x0]	20707	1			T2	8		T3	22		T4	107