Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7616242	1			T1	6387		T2	4		T3	129001
all_levels[1]	2111627	1			T1	108		T2	65		T3	14388
all_levels[2]	458014	1			T1	125		T2	1		T3	8089
all_levels[3]	270510	1			T1	128		T3	8060		T4	29
all_levels[4]	292212	1			T1	97		T3	8086		T4	9858
all_levels[5]	220481	1			T1	112		T2	1		T3	8089
all_levels[6]	220848	1			T1	138		T3	8083		T4	6
all_levels[7]	231158	1			T1	125		T2	1		T3	8074
all_levels[8]	412250	1			T1	111		T3	8052		T4	4
all_levels[9]	675343	1			T1	133		T3	8083		T4	58
all_levels[10]	296908	1			T1	122		T3	8089		T4	3
all_levels[11]	400458	1			T1	124		T2	3		T3	8085
all_levels[12]	222762	1			T1	130		T2	2		T3	8067
all_levels[13]	445899	1			T1	112		T3	8157		T4	49
all_levels[14]	316321	1			T1	103		T3	9236		T4	61
all_levels[15]	216598	1			T1	107		T3	9229		T8	1
all_levels[16]	317878	1			T1	111		T3	9206		T4	3
all_levels[17]	238298	1			T1	122		T2	1		T3	9239
all_levels[18]	382474	1			T1	121		T3	9233		T8	1
all_levels[19]	193464	1			T1	121		T3	9219		T4	38
all_levels[20]	191434	1			T1	117		T3	9235		T4	3
all_levels[21]	234300	1			T1	116		T3	9216		T4	5
all_levels[22]	262640	1			T1	118		T3	9212		T4	11
all_levels[23]	357104	1			T1	122		T3	9216		T4	5
all_levels[24]	245453	1			T1	126		T3	9211		T4	6
all_levels[25]	221123	1			T1	95		T3	9161		T4	5
all_levels[26]	348665	1			T1	128		T3	8058		T4	2
all_levels[27]	191352	1			T1	109		T2	3		T3	8082
all_levels[28]	195981	1			T1	125		T3	8059		T37	12
all_levels[29]	237795	1			T1	117		T2	9		T3	8086
all_levels[30]	208796	1			T1	110		T3	8082		T7	4
all_levels[31]	908562	1			T1	3823		T3	48960		T7	1
all_levels[32]	13920387	1			T1	105601		T3	400448		T4	40

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33059063

1

T1

119343

T2

86

T3

840790

auto[1]

4274

1

T1

1

T2

4

T3

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	7613997	1			T1	6387		T2	3		T3	129001
all_levels[0]	auto[1]	2245	1			T2	1		T4	1		T6	3
all_levels[1]	auto[0]	2111260	1			T1	108		T2	64		T3	14388
all_levels[1]	auto[1]	367	1			T2	1		T6	2		T9	1
all_levels[2]	auto[0]	457980	1			T1	125		T2	1		T3	8089
all_levels[2]	auto[1]	34	1			T4	1		T15	1		T48	1
all_levels[3]	auto[0]	270390	1			T1	128		T3	8060		T4	14
all_levels[3]	auto[1]	120	1			T4	15		T190	1		T264	1
all_levels[4]	auto[0]	292178	1			T1	97		T3	8086		T4	9858
all_levels[4]	auto[1]	34	1			T50	2		T299	1		T228	2
all_levels[5]	auto[0]	220446	1			T1	112		T2	1		T3	8089
all_levels[5]	auto[1]	35	1			T9	2		T136	4		T298	1
all_levels[6]	auto[0]	220816	1			T1	138		T3	8083		T4	6
all_levels[6]	auto[1]	32	1			T294	1		T168	1		T332	1
all_levels[7]	auto[0]	230970	1			T1	125		T2	1		T3	8074
all_levels[7]	auto[1]	188	1			T11	5		T136	1		T17	14
all_levels[8]	auto[0]	412220	1			T1	111		T3	8052		T4	4
all_levels[8]	auto[1]	30	1			T190	2		T134	1		T186	2
all_levels[9]	auto[0]	675323	1			T1	133		T3	8083		T4	58
all_levels[9]	auto[1]	20	1			T261	1		T164	1		T195	1
all_levels[10]	auto[0]	296883	1			T1	122		T3	8089		T4	3
all_levels[10]	auto[1]	25	1			T147	1		T198	1		T333	1
all_levels[11]	auto[0]	400427	1			T1	124		T2	2		T3	8085
all_levels[11]	auto[1]	31	1			T2	1		T21	1		T307	1
all_levels[12]	auto[0]	222738	1			T1	130		T2	2		T3	8067
all_levels[12]	auto[1]	24	1			T37	2		T50	1		T204	1
all_levels[13]	auto[0]	445880	1			T1	112		T3	8157		T4	49
all_levels[13]	auto[1]	19	1			T9	1		T147	2		T166	2
all_levels[14]	auto[0]	316294	1			T1	103		T3	9236		T4	61
all_levels[14]	auto[1]	27	1			T204	1		T293	1		T157	1
all_levels[15]	auto[0]	216401	1			T1	107		T3	9229		T8	1
all_levels[15]	auto[1]	197	1			T334	3		T55	7		T219	1
all_levels[16]	auto[0]	317851	1			T1	111		T3	9206		T4	3
all_levels[16]	auto[1]	27	1			T248	1		T284	2		T157	2
all_levels[17]	auto[0]	238278	1			T1	122		T2	1		T3	9239
all_levels[17]	auto[1]	20	1			T20	1		T320	1		T200	1
all_levels[18]	auto[0]	382444	1			T1	121		T3	9233		T8	1
all_levels[18]	auto[1]	30	1			T148	2		T290	1		T33	1
all_levels[19]	auto[0]	193439	1			T1	121		T3	9219		T4	38
all_levels[19]	auto[1]	25	1			T189	1		T121	2		T230	2
all_levels[20]	auto[0]	191401	1			T1	117		T3	9235		T4	3
all_levels[20]	auto[1]	33	1			T294	1		T335	1		T336	2
all_levels[21]	auto[0]	234282	1			T1	116		T3	9216		T4	5
all_levels[21]	auto[1]	18	1			T278	1		T195	2		T113	2
all_levels[22]	auto[0]	262613	1			T1	118		T3	9212		T4	11
all_levels[22]	auto[1]	27	1			T13	1		T134	2		T154	3
all_levels[23]	auto[0]	357090	1			T1	122		T3	9216		T4	5
all_levels[23]	auto[1]	14	1			T7	1		T299	1		T332	2
all_levels[24]	auto[0]	245442	1			T1	126		T3	9211		T4	6
all_levels[24]	auto[1]	11	1			T147	1		T128	1		T160	1
all_levels[25]	auto[0]	221106	1			T1	95		T3	9161		T4	5
all_levels[25]	auto[1]	17	1			T52	1		T337	1		T207	1
all_levels[26]	auto[0]	348649	1			T1	128		T3	8058		T4	2
all_levels[26]	auto[1]	16	1			T50	1		T148	1		T338	1
all_levels[27]	auto[0]	191332	1			T1	109		T2	3		T3	8082
all_levels[27]	auto[1]	20	1			T109	1		T138	1		T321	1
all_levels[28]	auto[0]	195958	1			T1	125		T3	8059		T37	12
all_levels[28]	auto[1]	23	1			T264	2		T186	2		T193	1
all_levels[29]	auto[0]	237780	1			T1	117		T2	8		T3	8086
all_levels[29]	auto[1]	15	1			T2	1		T111	2		T52	2
all_levels[30]	auto[0]	208782	1			T1	110		T3	8082		T7	4
all_levels[30]	auto[1]	14	1			T217	1		T154	2		T196	1
all_levels[31]	auto[0]	908534	1			T1	3823		T3	48960		T7	1
all_levels[31]	auto[1]	28	1			T109	1		T248	1		T152	4
all_levels[32]	auto[0]	13919879	1			T1	105600		T3	400447		T4	39
all_levels[32]	auto[1]	508	1			T1	1		T3	1		T4	1