Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	721	1			T14	4		T20	4		T19	4
all_values[1]	721	1			T14	4		T20	4		T19	4
all_values[2]	721	1			T14	4		T20	4		T19	4
all_values[3]	721	1			T14	4		T20	4		T19	4
all_values[4]	721	1			T14	4		T20	4		T19	4
all_values[5]	721	1			T14	4		T20	4		T19	4
all_values[6]	721	1			T14	4		T20	4		T19	4
all_values[7]	721	1			T14	4		T20	4		T19	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3109

1

T14

17

T20

24

T19

20

auto[1]

2659

1

T14

15

T20

8

T19

12

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2133

1

T14

10

T20

7

T19

12

auto[1]

3635

1

T14

22

T20

25

T19

20

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3410

1

T14

18

T20

14

T19

19

auto[1]

2358

1

T14

14

T20

18

T19

13

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	4	44	91.67	4
Automatically Generated Cross Bins	48	4	44	91.67	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	238	1			T14	1		T20	1		T19	1
all_values[0]	auto[0]	auto[1]	auto[1]	203	1			T14	2		T33	3		T125	4
all_values[0]	auto[1]	auto[0]	auto[1]	157	1			T20	2		T19	2		T32	2
all_values[0]	auto[1]	auto[1]	auto[1]	123	1			T14	1		T20	1		T19	1
all_values[1]	auto[0]	auto[0]	auto[0]	225	1			T14	1		T20	2		T19	3
all_values[1]	auto[0]	auto[1]	auto[0]	198	1			T14	2		T19	1		T32	2
all_values[1]	auto[1]	auto[0]	auto[1]	154	1			T20	2		T32	2		T126	1
all_values[1]	auto[1]	auto[1]	auto[1]	144	1			T14	1		T32	1		T33	3
all_values[2]	auto[0]	auto[0]	auto[0]	149	1			T20	1		T127	3		T128	3
all_values[2]	auto[0]	auto[0]	auto[1]	83	1			T14	1		T20	1		T19	1
all_values[2]	auto[0]	auto[1]	auto[0]	112	1			T33	1		T126	2		T127	3
all_values[2]	auto[0]	auto[1]	auto[1]	74	1			T14	1		T32	1		T55	3
all_values[2]	auto[1]	auto[0]	auto[1]	164	1			T14	2		T20	2		T19	3
all_values[2]	auto[1]	auto[1]	auto[1]	139	1			T33	1		T126	3		T127	2
all_values[3]	auto[0]	auto[0]	auto[0]	162	1			T14	1		T32	2		T33	1
all_values[3]	auto[0]	auto[0]	auto[1]	71	1			T33	1		T126	2		T127	1
all_values[3]	auto[0]	auto[1]	auto[0]	123	1			T14	2		T19	1		T32	1
all_values[3]	auto[0]	auto[1]	auto[1]	67	1			T20	1		T19	1		T127	2
all_values[3]	auto[1]	auto[0]	auto[1]	158	1			T20	1		T19	1		T32	2
all_values[3]	auto[1]	auto[1]	auto[1]	140	1			T14	1		T20	2		T19	1
all_values[4]	auto[0]	auto[0]	auto[0]	176	1			T14	1		T32	2		T33	1
all_values[4]	auto[0]	auto[0]	auto[1]	57	1			T20	1		T19	1		T126	1
all_values[4]	auto[0]	auto[1]	auto[0]	126	1			T20	1		T32	1		T33	2
all_values[4]	auto[0]	auto[1]	auto[1]	76	1			T19	1		T32	2		T33	1
all_values[4]	auto[1]	auto[0]	auto[1]	157	1			T20	2		T19	2		T32	1
all_values[4]	auto[1]	auto[1]	auto[1]	129	1			T14	3		T32	1		T33	2
all_values[5]	auto[0]	auto[0]	auto[0]	171	1			T14	2		T20	1		T19	1
all_values[5]	auto[0]	auto[0]	auto[1]	70	1			T14	1		T20	1		T32	1
all_values[5]	auto[0]	auto[1]	auto[0]	124	1			T19	1		T32	1		T33	1
all_values[5]	auto[0]	auto[1]	auto[1]	68	1			T19	1		T32	2		T33	1
all_values[5]	auto[1]	auto[0]	auto[1]	164	1			T14	1		T20	2		T32	1
all_values[5]	auto[1]	auto[1]	auto[1]	124	1			T19	1		T32	1		T33	1
all_values[6]	auto[0]	auto[0]	auto[0]	144	1			T14	1		T20	1		T19	1
all_values[6]	auto[0]	auto[0]	auto[1]	70	1			T14	1		T33	1		T127	1
all_values[6]	auto[0]	auto[1]	auto[0]	137	1			T33	4		T127	6		T128	6
all_values[6]	auto[0]	auto[1]	auto[1]	65	1			T20	1		T19	1		T32	1
all_values[6]	auto[1]	auto[0]	auto[1]	167	1			T14	2		T19	1		T32	3
all_values[6]	auto[1]	auto[1]	auto[1]	138	1			T20	2		T19	1		T32	2
all_values[7]	auto[0]	auto[0]	auto[0]	141	1			T20	1		T19	3		T33	1
all_values[7]	auto[0]	auto[0]	auto[1]	71	1			T20	1		T32	1		T126	4
all_values[7]	auto[0]	auto[1]	auto[0]	145	1			T19	1		T32	3		T33	3
all_values[7]	auto[0]	auto[1]	auto[1]	64	1			T14	1		T125	1		T128	2
all_values[7]	auto[1]	auto[0]	auto[1]	160	1			T14	2		T20	2		T32	1
all_values[7]	auto[1]	auto[1]	auto[1]	140	1			T14	1		T32	2		T33	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal