Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	125245	1			T1	10		T2	314		T3	27
all_values[1]	125245	1			T1	10		T2	314		T3	27
all_values[2]	125245	1			T1	10		T2	314		T3	27
all_values[3]	125245	1			T1	10		T2	314		T3	27
all_values[4]	125245	1			T1	10		T2	314		T3	27
all_values[5]	125245	1			T1	10		T2	314		T3	27
all_values[6]	125245	1			T1	10		T2	314		T3	27
all_values[7]	125245	1			T1	10		T2	314		T3	27

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

511121

1

T1

62

T2

922

T3

100

auto[1]

490839

1

T1

18

T2

1590

T3

116

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

943878

1

T1

69

T2

2345

T3

206

auto[1]

58082

1

T1

11

T2

167

T3

10

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	38845	1			T2	116		T7	2		T8	868
all_values[0]	auto[0]	auto[1]	22405	1			T1	10		T2	133		T3	4
all_values[0]	auto[1]	auto[0]	40532	1			T2	36		T3	21		T4	8
all_values[0]	auto[1]	auto[1]	23463	1			T2	29		T3	2		T4	5
all_values[1]	auto[0]	auto[0]	65408	1			T1	10		T2	48		T3	15
all_values[1]	auto[0]	auto[1]	1902	1			T4	4		T7	10		T9	1
all_values[1]	auto[1]	auto[0]	56240	1			T2	266		T3	12		T4	3
all_values[1]	auto[1]	auto[1]	1695	1			T4	1		T9	37		T30	4
all_values[2]	auto[0]	auto[0]	65812	1			T1	2		T2	48		T3	15
all_values[2]	auto[0]	auto[1]	2916	1			T2	2		T3	2		T8	6
all_values[2]	auto[1]	auto[0]	53888	1			T1	7		T2	261		T3	8
all_values[2]	auto[1]	auto[1]	2629	1			T1	1		T2	3		T3	2
all_values[3]	auto[0]	auto[0]	67744	1			T1	10		T2	283		T3	21
all_values[3]	auto[0]	auto[1]	329	1			T7	3		T12	6		T13	3
all_values[3]	auto[1]	auto[0]	56829	1			T2	31		T3	6		T4	11
all_values[3]	auto[1]	auto[1]	343	1			T9	2		T12	1		T13	1
all_values[4]	auto[0]	auto[0]	59127	1			T1	10		T2	48		T3	16
all_values[4]	auto[0]	auto[1]	509	1			T9	2		T13	1		T14	4
all_values[4]	auto[1]	auto[0]	65136	1			T2	266		T3	11		T4	16
all_values[4]	auto[1]	auto[1]	473	1			T7	1		T9	4		T13	5
all_values[5]	auto[0]	auto[0]	59293	1			T1	2		T2	102		T3	11
all_values[5]	auto[0]	auto[1]	189	1			T13	3		T14	1		T24	2
all_values[5]	auto[1]	auto[0]	65585	1			T1	8		T2	212		T3	16
all_values[5]	auto[1]	auto[1]	178	1			T105	1		T93	3		T106	1
all_values[6]	auto[0]	auto[0]	64059	1			T1	10		T2	99		T3	14
all_values[6]	auto[0]	auto[1]	193	1			T28	1		T105	1		T93	3
all_values[6]	auto[1]	auto[0]	60789	1			T2	215		T3	13		T4	19
all_values[6]	auto[1]	auto[1]	204	1			T13	1		T14	2		T24	3
all_values[7]	auto[0]	auto[0]	62097	1			T1	8		T2	43		T3	2
all_values[7]	auto[0]	auto[1]	293	1			T7	1		T9	8		T13	2
all_values[7]	auto[1]	auto[0]	62494	1			T1	2		T2	271		T3	25
all_values[7]	auto[1]	auto[1]	361	1			T13	1		T72	1		T97	12