Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2608

1

T1

1

T2

11

T3

1

auto[UartRx]

2608

1

T1

1

T2

11

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4593	1			T1	2		T2	13		T3	2
values[1]	52	1			T2	1		T16	1		T26	3
values[2]	57	1			T2	1		T26	1		T27	2
values[3]	48	1			T9	1		T16	1		T24	1
values[4]	71	1			T2	1		T9	1		T13	1
values[5]	59	1			T9	1		T13	1		T16	2
values[6]	56	1			T2	3		T9	2		T13	1
values[7]	66	1			T9	1		T24	1		T25	1
values[8]	60	1			T13	2		T14	1		T25	1
values[9]	58	1			T2	2		T24	1		T25	3
values[10]	63	1			T9	2		T13	1		T24	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2403	1			T1	1		T2	8		T3	1
auto[UartTx]	values[1]	19	1			T26	1		T94	1		T109	1
auto[UartTx]	values[2]	20	1			T27	1		T28	1		T132	1
auto[UartTx]	values[3]	15	1			T16	1		T108	1		T109	1
auto[UartTx]	values[4]	24	1			T14	2		T26	2		T28	1
auto[UartTx]	values[5]	21	1			T13	1		T16	1		T24	1
auto[UartTx]	values[6]	17	1			T2	1		T9	1		T93	1
auto[UartTx]	values[7]	15	1			T93	1		T108	2		T293	1
auto[UartTx]	values[8]	14	1			T27	1		T261	1		T142	1
auto[UartTx]	values[9]	20	1			T2	1		T25	3		T26	1
auto[UartTx]	values[10]	25	1			T13	1		T28	2		T105	1
auto[UartRx]	values[0]	2190	1			T1	1		T2	5		T3	1
auto[UartRx]	values[1]	33	1			T2	1		T16	1		T26	2
auto[UartRx]	values[2]	37	1			T2	1		T26	1		T27	1
auto[UartRx]	values[3]	33	1			T9	1		T24	1		T25	2
auto[UartRx]	values[4]	47	1			T2	1		T9	1		T13	1
auto[UartRx]	values[5]	38	1			T9	1		T16	1		T24	1
auto[UartRx]	values[6]	39	1			T2	2		T9	1		T13	1
auto[UartRx]	values[7]	51	1			T9	1		T24	1		T25	1
auto[UartRx]	values[8]	46	1			T13	2		T14	1		T25	1
auto[UartRx]	values[9]	38	1			T2	1		T24	1		T26	1
auto[UartRx]	values[10]	38	1			T9	2		T24	1		T26	1