Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2600	1			T1	1		T2	11		T3	1
auto[BaudRate115200]	2314	1			T1	2		T2	14		T4	3
auto[BaudRate230400]	2174	1			T1	1		T2	11		T3	1
auto[BaudRate128Kbps]	2280	1			T1	1		T2	3		T4	2
auto[BaudRate256Kbps]	2538	1			T2	12		T3	1		T4	4
auto[BaudRate1Mbps]	1986	1			T2	8		T3	1		T4	1
auto[BaudRate1p5Mbps]	1483	1			T2	11		T3	2		T4	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1395	1			T7	3		T95	60		T259	2
freqs[25]	1505	1			T4	15		T9	97		T311	27
freqs[48]	606	1			T30	6		T129	7		T34	9
freqs[50]	770	1			T32	9		T35	15		T71	1
freqs[100]	1452	1			T2	70		T6	21		T29	9

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	220	1			T95	12		T115	2		T260	2
auto[BaudRate9600]	freqs[25]	193	1			T4	3		T9	9		T311	6
auto[BaudRate9600]	freqs[48]	94	1			T30	1		T129	2		T34	2
auto[BaudRate9600]	freqs[50]	117	1			T32	1		T35	15		T71	1
auto[BaudRate9600]	freqs[100]	253	1			T2	11		T6	6		T286	1
auto[BaudRate115200]	freqs[24]	196	1			T7	1		T95	12		T115	3
auto[BaudRate115200]	freqs[25]	221	1			T4	3		T9	13		T311	3
auto[BaudRate115200]	freqs[48]	84	1			T30	1		T129	1		T24	9
auto[BaudRate115200]	freqs[50]	110	1			T32	1		T136	2		T295	1
auto[BaudRate115200]	freqs[100]	179	1			T2	14		T6	3		T29	3
auto[BaudRate230400]	freqs[24]	175	1			T95	3		T115	3		T265	3
auto[BaudRate230400]	freqs[25]	225	1			T4	1		T9	22		T311	6
auto[BaudRate230400]	freqs[48]	90	1			T129	2		T34	2		T24	9
auto[BaudRate230400]	freqs[50]	82	1			T32	3		T136	2		T312	2
auto[BaudRate230400]	freqs[100]	184	1			T2	11		T29	1		T299	1
auto[BaudRate128Kbps]	freqs[24]	185	1			T7	2		T95	9		T115	3
auto[BaudRate128Kbps]	freqs[25]	225	1			T4	2		T9	16		T311	6
auto[BaudRate128Kbps]	freqs[48]	83	1			T34	1		T24	13		T246	2
auto[BaudRate128Kbps]	freqs[50]	94	1			T32	1		T136	1		T295	1
auto[BaudRate128Kbps]	freqs[100]	228	1			T2	3		T29	1		T286	2
auto[BaudRate256Kbps]	freqs[24]	239	1			T95	12		T259	2		T38	3
auto[BaudRate256Kbps]	freqs[25]	286	1			T4	4		T9	14		T96	2
auto[BaudRate256Kbps]	freqs[48]	93	1			T30	1		T34	3		T24	14
auto[BaudRate256Kbps]	freqs[50]	96	1			T32	2		T39	3		T313	3
auto[BaudRate256Kbps]	freqs[100]	189	1			T2	12		T29	3		T279	1
auto[BaudRate1Mbps]	freqs[24]	265	1			T95	9		T38	1		T115	10
auto[BaudRate1Mbps]	freqs[25]	232	1			T4	1		T9	18		T311	3
auto[BaudRate1Mbps]	freqs[48]	76	1			T30	1		T34	1		T24	13
auto[BaudRate1Mbps]	freqs[50]	134	1			T32	1		T39	3		T281	3
auto[BaudRate1Mbps]	freqs[100]	204	1			T2	8		T6	9		T279	1
auto[BaudRate1p5Mbps]	freqs[25]	123	1			T4	1		T9	5		T311	3
auto[BaudRate1p5Mbps]	freqs[48]	86	1			T30	2		T129	2		T24	5
auto[BaudRate1p5Mbps]	freqs[50]	137	1			T39	4		T136	3		T281	4
auto[BaudRate1p5Mbps]	freqs[100]	215	1			T2	11		T6	3		T29	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded