Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.94	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	8	122	93.85

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	8	122	93.85	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	35552473	1			T1	22		T2	132434		T3	18
all_levels[1]	211101	1			T1	3		T2	35		T4	43
all_levels[2]	2533	1			T1	1		T4	2		T9	8
all_levels[3]	1174	1			T1	2		T2	2		T3	1
all_levels[4]	852	1			T1	1		T9	5		T10	3
all_levels[5]	593	1			T1	1		T3	1		T4	1
all_levels[6]	473	1			T3	2		T4	2		T9	3
all_levels[7]	395	1			T1	1		T3	1		T9	2
all_levels[8]	318	1			T3	1		T9	1		T69	3
all_levels[9]	236	1			T13	1		T72	1		T110	1
all_levels[10]	217	1			T9	1		T111	1		T31	1
all_levels[11]	183	1			T9	1		T30	1		T13	1
all_levels[12]	177	1			T1	1		T9	1		T13	1
all_levels[13]	173	1			T9	1		T12	1		T31	3
all_levels[14]	135	1			T3	1		T16	1		T97	1
all_levels[15]	115	1			T13	1		T97	1		T24	2
all_levels[16]	115	1			T30	2		T112	1		T97	2
all_levels[17]	90	1			T2	1		T30	1		T72	1
all_levels[18]	80	1			T9	1		T32	1		T97	1
all_levels[19]	74	1			T110	1		T111	1		T16	1
all_levels[20]	79	1			T9	1		T97	1		T98	1
all_levels[21]	67	1			T24	1		T41	1		T113	2
all_levels[22]	64	1			T30	1		T97	1		T114	1
all_levels[23]	43	1			T3	1		T9	2		T30	1
all_levels[24]	62	1			T32	2		T16	1		T97	1
all_levels[25]	50	1			T110	1		T16	1		T14	2
all_levels[26]	41	1			T9	1		T30	1		T32	1
all_levels[27]	50	1			T9	1		T30	1		T31	1
all_levels[28]	42	1			T33	1		T16	1		T115	1
all_levels[29]	39	1			T116	1		T117	1		T118	1
all_levels[30]	46	1			T115	1		T119	1		T120	1
all_levels[31]	38	1			T2	1		T3	1		T121	1
all_levels[32]	30	1			T122	2		T99	1		T123	1
all_levels[33]	35	1			T98	1		T124	2		T125	1
all_levels[34]	23	1			T30	1		T24	1		T98	1
all_levels[35]	23	1			T97	1		T126	1		T127	3
all_levels[36]	22	1			T3	1		T125	1		T128	1
all_levels[37]	25	1			T129	1		T130	1		T131	2
all_levels[38]	21	1			T27	1		T132	1		T133	1
all_levels[39]	11	1			T114	1		T134	1		T135	1
all_levels[40]	17	1			T136	1		T91	1		T137	2
all_levels[41]	27	1			T3	1		T115	1		T138	1
all_levels[42]	19	1			T30	1		T127	1		T136	2
all_levels[43]	31	1			T30	1		T114	1		T133	2
all_levels[44]	14	1			T32	1		T109	1		T139	1
all_levels[45]	14	1			T114	1		T140	1		T141	1
all_levels[46]	14	1			T34	1		T133	1		T142	1
all_levels[47]	12	1			T143	1		T144	1		T145	2
all_levels[48]	11	1			T146	1		T141	1		T147	1
all_levels[49]	16	1			T148	1		T149	1		T144	1
all_levels[50]	13	1			T9	1		T150	2		T151	1
all_levels[51]	15	1			T41	3		T152	1		T153	1
all_levels[52]	11	1			T142	1		T154	1		T144	1
all_levels[53]	8	1			T142	1		T155	1		T156	2
all_levels[54]	9	1			T125	1		T132	1		T157	1
all_levels[55]	5	1			T28	1		T158	3		T159	1
all_levels[56]	9	1			T16	1		T160	1		T152	1
all_levels[57]	11	1			T12	2		T16	1		T125	1
all_levels[58]	11	1			T160	1		T161	1		T162	2
all_levels[59]	12	1			T130	1		T125	1		T149	1
all_levels[60]	6	1			T163	1		T164	1		T165	1
all_levels[61]	4	1			T166	1		T167	1		T51	1
all_levels[62]	10	1			T132	1		T142	1		T168	1
all_levels[63]	8	1			T152	1		T169	1		T170	1
all_levels[64]	130	1			T32	2		T114	1		T43	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35767882

1

T1

32

T2

132465

T3

29

auto[1]

4873

1

T2

8

T5

1

T6

2

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	8	122	93.85	8

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[34]]	[auto[1]]	0	1	1
[all_levels[36]]	[auto[1]]	0	1	1
[all_levels[39]]	[auto[1]]	0	1	1
[all_levels[52]]	[auto[1]]	0	1	1
[all_levels[54]]	[auto[1]]	0	1	1
[all_levels[60] , all_levels[61]]	[auto[1]]	--	--	2
[all_levels[63]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	35548039	1			T1	22		T2	132426		T3	18
all_levels[0]	auto[1]	4434	1			T2	8		T5	1		T6	2
all_levels[1]	auto[0]	211029	1			T1	3		T2	35		T4	43
all_levels[1]	auto[1]	72	1			T16	3		T171	1		T34	1
all_levels[2]	auto[0]	2515	1			T1	1		T4	2		T9	8
all_levels[2]	auto[1]	18	1			T113	2		T172	1		T91	1
all_levels[3]	auto[0]	1161	1			T1	2		T2	2		T3	1
all_levels[3]	auto[1]	13	1			T32	1		T173	1		T158	2
all_levels[4]	auto[0]	822	1			T1	1		T9	5		T10	3
all_levels[4]	auto[1]	30	1			T98	1		T94	2		T174	1
all_levels[5]	auto[0]	578	1			T1	1		T3	1		T4	1
all_levels[5]	auto[1]	15	1			T175	1		T176	1		T177	1
all_levels[6]	auto[0]	457	1			T3	2		T4	2		T9	3
all_levels[6]	auto[1]	16	1			T41	1		T178	2		T179	2
all_levels[7]	auto[0]	374	1			T1	1		T3	1		T9	2
all_levels[7]	auto[1]	21	1			T180	1		T181	1		T182	2
all_levels[8]	auto[0]	299	1			T3	1		T9	1		T69	3
all_levels[8]	auto[1]	19	1			T183	4		T184	1		T185	1
all_levels[9]	auto[0]	226	1			T13	1		T72	1		T110	1
all_levels[9]	auto[1]	10	1			T175	1		T186	1		T187	3
all_levels[10]	auto[0]	205	1			T9	1		T111	1		T31	1
all_levels[10]	auto[1]	12	1			T99	1		T178	1		T118	1
all_levels[11]	auto[0]	180	1			T9	1		T30	1		T13	1
all_levels[11]	auto[1]	3	1			T188	2		T189	1		-	-
all_levels[12]	auto[0]	168	1			T1	1		T9	1		T13	1
all_levels[12]	auto[1]	9	1			T124	1		T132	1		T190	1
all_levels[13]	auto[0]	157	1			T9	1		T12	1		T31	3
all_levels[13]	auto[1]	16	1			T136	3		T191	1		T192	3
all_levels[14]	auto[0]	121	1			T3	1		T16	1		T97	1
all_levels[14]	auto[1]	14	1			T139	1		T193	1		T194	1
all_levels[15]	auto[0]	104	1			T13	1		T97	1		T24	2
all_levels[15]	auto[1]	11	1			T121	2		T195	2		T196	1
all_levels[16]	auto[0]	103	1			T30	1		T112	1		T97	2
all_levels[16]	auto[1]	12	1			T30	1		T139	1		T197	1
all_levels[17]	auto[0]	85	1			T2	1		T30	1		T72	1
all_levels[17]	auto[1]	5	1			T136	3		T157	1		T198	1
all_levels[18]	auto[0]	71	1			T9	1		T32	1		T97	1
all_levels[18]	auto[1]	9	1			T199	4		T200	3		T201	2
all_levels[19]	auto[0]	66	1			T110	1		T111	1		T16	1
all_levels[19]	auto[1]	8	1			T202	1		T203	2		T204	1
all_levels[20]	auto[0]	74	1			T9	1		T97	1		T98	1
all_levels[20]	auto[1]	5	1			T28	1		T192	1		T205	1
all_levels[21]	auto[0]	65	1			T24	1		T41	1		T113	1
all_levels[21]	auto[1]	2	1			T113	1		T206	1		-	-
all_levels[22]	auto[0]	60	1			T30	1		T97	1		T114	1
all_levels[22]	auto[1]	4	1			T125	1		T207	1		T208	1
all_levels[23]	auto[0]	42	1			T3	1		T9	2		T30	1
all_levels[23]	auto[1]	1	1			T209	1		-	-		-	-
all_levels[24]	auto[0]	55	1			T32	1		T16	1		T97	1
all_levels[24]	auto[1]	7	1			T32	1		T114	1		T164	1
all_levels[25]	auto[0]	43	1			T110	1		T16	1		T14	2
all_levels[25]	auto[1]	7	1			T84	4		T186	1		T210	1
all_levels[26]	auto[0]	38	1			T9	1		T30	1		T32	1
all_levels[26]	auto[1]	3	1			T156	3		-	-		-	-
all_levels[27]	auto[0]	48	1			T9	1		T30	1		T31	1
all_levels[27]	auto[1]	2	1			T153	1		T211	1		-	-
all_levels[28]	auto[0]	40	1			T33	1		T16	1		T115	1
all_levels[28]	auto[1]	2	1			T202	1		T212	1		-	-
all_levels[29]	auto[0]	35	1			T116	1		T117	1		T118	1
all_levels[29]	auto[1]	4	1			T213	1		T214	1		T215	2
all_levels[30]	auto[0]	37	1			T115	1		T119	1		T120	1
all_levels[30]	auto[1]	9	1			T216	2		T217	1		T218	1
all_levels[31]	auto[0]	32	1			T2	1		T3	1		T121	1
all_levels[31]	auto[1]	6	1			T219	3		T220	1		T221	2
all_levels[32]	auto[0]	27	1			T122	1		T99	1		T123	1
all_levels[32]	auto[1]	3	1			T122	1		T222	2		-	-
all_levels[33]	auto[0]	31	1			T98	1		T124	1		T125	1
all_levels[33]	auto[1]	4	1			T124	1		T223	1		T211	1
all_levels[34]	auto[0]	23	1			T30	1		T24	1		T98	1
all_levels[35]	auto[0]	19	1			T97	1		T126	1		T127	2
all_levels[35]	auto[1]	4	1			T127	1		T224	1		T225	1
all_levels[36]	auto[0]	22	1			T3	1		T125	1		T128	1
all_levels[37]	auto[0]	21	1			T129	1		T130	1		T131	1
all_levels[37]	auto[1]	4	1			T131	1		T141	1		T226	1
all_levels[38]	auto[0]	19	1			T27	1		T132	1		T133	1
all_levels[38]	auto[1]	2	1			T91	1		T227	1		-	-
all_levels[39]	auto[0]	11	1			T114	1		T134	1		T135	1
all_levels[40]	auto[0]	15	1			T136	1		T91	1		T137	1
all_levels[40]	auto[1]	2	1			T137	1		T204	1		-	-
all_levels[41]	auto[0]	24	1			T3	1		T115	1		T138	1
all_levels[41]	auto[1]	3	1			T228	1		T229	2		-	-
all_levels[42]	auto[0]	17	1			T30	1		T127	1		T136	2
all_levels[42]	auto[1]	2	1			T125	1		T230	1		-	-
all_levels[43]	auto[0]	26	1			T30	1		T114	1		T133	2
all_levels[43]	auto[1]	5	1			T47	2		T229	1		T231	1
all_levels[44]	auto[0]	13	1			T32	1		T109	1		T139	1
all_levels[44]	auto[1]	1	1			T232	1		-	-		-	-
all_levels[45]	auto[0]	12	1			T114	1		T140	1		T141	1
all_levels[45]	auto[1]	2	1			T233	2		-	-		-	-
all_levels[46]	auto[0]	13	1			T34	1		T133	1		T142	1
all_levels[46]	auto[1]	1	1			T234	1		-	-		-	-
all_levels[47]	auto[0]	10	1			T143	1		T144	1		T145	2
all_levels[47]	auto[1]	2	1			T235	2		-	-		-	-
all_levels[48]	auto[0]	10	1			T146	1		T141	1		T147	1
all_levels[48]	auto[1]	1	1			T236	1		-	-		-	-
all_levels[49]	auto[0]	15	1			T148	1		T149	1		T144	1
all_levels[49]	auto[1]	1	1			T228	1		-	-		-	-
all_levels[50]	auto[0]	12	1			T9	1		T150	1		T151	1
all_levels[50]	auto[1]	1	1			T150	1		-	-		-	-
all_levels[51]	auto[0]	10	1			T41	1		T152	1		T153	1
all_levels[51]	auto[1]	5	1			T41	2		T188	3		-	-
all_levels[52]	auto[0]	11	1			T142	1		T154	1		T144	1
all_levels[53]	auto[0]	7	1			T142	1		T155	1		T156	1
all_levels[53]	auto[1]	1	1			T156	1		-	-		-	-
all_levels[54]	auto[0]	9	1			T125	1		T132	1		T157	1
all_levels[55]	auto[0]	3	1			T28	1		T158	1		T159	1
all_levels[55]	auto[1]	2	1			T158	2		-	-		-	-
all_levels[56]	auto[0]	8	1			T16	1		T160	1		T152	1
all_levels[56]	auto[1]	1	1			T237	1		-	-		-	-
all_levels[57]	auto[0]	9	1			T12	1		T16	1		T125	1
all_levels[57]	auto[1]	2	1			T12	1		T199	1		-	-
all_levels[58]	auto[0]	10	1			T160	1		T161	1		T162	2
all_levels[58]	auto[1]	1	1			T238	1		-	-		-	-
all_levels[59]	auto[0]	8	1			T130	1		T125	1		T149	1
all_levels[59]	auto[1]	4	1			T239	1		T240	1		T241	2
all_levels[60]	auto[0]	6	1			T163	1		T164	1		T165	1
all_levels[61]	auto[0]	4	1			T166	1		T167	1		T51	1
all_levels[62]	auto[0]	9	1			T132	1		T142	1		T168	1
all_levels[62]	auto[1]	1	1			T242	1		-	-		-	-
all_levels[63]	auto[0]	8	1			T152	1		T169	1		T170	1
all_levels[64]	auto[0]	111	1			T32	2		T114	1		T43	1
all_levels[64]	auto[1]	19	1			T160	1		T132	1		T206	1