Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	125245	1			T1	10		T2	314		T3	27
all_pins[1]	125245	1			T1	10		T2	314		T3	27
all_pins[2]	125245	1			T1	10		T2	314		T3	27
all_pins[3]	125245	1			T1	10		T2	314		T3	27
all_pins[4]	125245	1			T1	10		T2	314		T3	27
all_pins[5]	125245	1			T1	10		T2	314		T3	27
all_pins[6]	125245	1			T1	10		T2	314		T3	27
all_pins[7]	125245	1			T1	10		T2	314		T3	27

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	971663	1			T1	79		T2	2480		T3	212
values[0x1]	30297	1			T1	1		T2	32		T3	4
transitions[0x0=>0x1]	28899	1			T1	1		T2	32		T3	4
transitions[0x1=>0x0]	28495	1			T1	1		T2	32		T3	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	101701	1			T1	10		T2	285		T3	25
all_pins[0]	values[0x1]	23544	1			T2	29		T3	2		T4	5
all_pins[0]	transitions[0x0=>0x1]	22778	1			T2	29		T3	2		T4	4
all_pins[0]	transitions[0x1=>0x0]	930	1			T9	33		T30	4		T13	6
all_pins[1]	values[0x0]	123549	1			T1	10		T2	314		T3	27
all_pins[1]	values[0x1]	1696	1			T4	1		T9	37		T30	4
all_pins[1]	transitions[0x0=>0x1]	1589	1			T9	37		T30	4		T13	51
all_pins[1]	transitions[0x1=>0x0]	2592	1			T1	1		T2	3		T3	2
all_pins[2]	values[0x0]	122546	1			T1	9		T2	311		T3	25
all_pins[2]	values[0x1]	2699	1			T1	1		T2	3		T3	2
all_pins[2]	transitions[0x0=>0x1]	2615	1			T1	1		T2	3		T3	2
all_pins[2]	transitions[0x1=>0x0]	259	1			T9	2		T13	1		T71	1
all_pins[3]	values[0x0]	124902	1			T1	10		T2	314		T3	27
all_pins[3]	values[0x1]	343	1			T9	2		T12	1		T13	1
all_pins[3]	transitions[0x0=>0x1]	292	1			T9	2		T12	1		T13	1
all_pins[3]	transitions[0x1=>0x0]	422	1			T7	1		T9	4		T13	5
all_pins[4]	values[0x0]	124772	1			T1	10		T2	314		T3	27
all_pins[4]	values[0x1]	473	1			T7	1		T9	4		T13	5
all_pins[4]	transitions[0x0=>0x1]	393	1			T7	1		T9	4		T13	4
all_pins[4]	transitions[0x1=>0x0]	147	1			T93	1		T107	2		T117	1
all_pins[5]	values[0x0]	125018	1			T1	10		T2	314		T3	27
all_pins[5]	values[0x1]	227	1			T13	1		T71	2		T243	1
all_pins[5]	transitions[0x0=>0x1]	172	1			T13	1		T71	2		T243	1
all_pins[5]	transitions[0x1=>0x0]	899	1			T4	2		T9	1		T10	1
all_pins[6]	values[0x0]	124291	1			T1	10		T2	314		T3	27
all_pins[6]	values[0x1]	954	1			T4	2		T9	1		T10	1
all_pins[6]	transitions[0x0=>0x1]	895	1			T4	2		T9	1		T10	1
all_pins[6]	transitions[0x1=>0x0]	302	1			T13	1		T72	1		T97	12
all_pins[7]	values[0x0]	124884	1			T1	10		T2	314		T3	27
all_pins[7]	values[0x1]	361	1			T13	1		T72	1		T97	12
all_pins[7]	transitions[0x0=>0x1]	165	1			T13	1		T97	12		T25	1
all_pins[7]	transitions[0x1=>0x0]	22944	1			T2	29		T3	1		T4	4