Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7005792	1			T1	1		T2	36159		T3	4
all_levels[1]	1236541	1			T2	1243		T4	9		T8	1141
all_levels[2]	400271	1			T2	1960		T3	2		T4	3
all_levels[3]	311625	1			T1	7		T2	1855		T4	12
all_levels[4]	609592	1			T2	1242		T4	1		T8	31215
all_levels[5]	307101	1			T1	2		T2	1955		T4	8
all_levels[6]	623957	1			T1	2		T2	1754		T4	2
all_levels[7]	221297	1			T2	1791		T4	4		T8	2294
all_levels[8]	673537	1			T2	1914		T3	2		T8	2288
all_levels[9]	230417	1			T2	1283		T4	1		T8	2255
all_levels[10]	580525	1			T2	1935		T4	6		T8	124651
all_levels[11]	278977	1			T2	1484		T4	10		T8	2263
all_levels[12]	580699	1			T2	1478		T8	2294		T9	56
all_levels[13]	379836	1			T2	1273		T8	2286		T9	51
all_levels[14]	222923	1			T2	1949		T8	2285		T9	46
all_levels[15]	638814	1			T2	1317		T8	2295		T9	30
all_levels[16]	350486	1			T2	1879		T4	8		T8	2259
all_levels[17]	215795	1			T1	2		T2	1777		T4	22
all_levels[18]	401375	1			T1	1		T2	1951		T4	86
all_levels[19]	208166	1			T1	2		T2	1401		T4	3
all_levels[20]	235800	1			T2	1907		T4	10		T8	2267
all_levels[21]	264677	1			T1	1		T2	1951		T4	1
all_levels[22]	384722	1			T2	1400		T4	5		T8	178572
all_levels[23]	281410	1			T2	1481		T4	4		T8	2249
all_levels[24]	231547	1			T2	1610		T4	2		T8	2294
all_levels[25]	204149	1			T2	1358		T3	2		T8	2294
all_levels[26]	489699	1			T2	1922		T8	2279		T9	36
all_levels[27]	634042	1			T2	997		T8	2284		T9	32
all_levels[28]	316258	1			T2	1896		T8	2291		T9	7255
all_levels[29]	353443	1			T2	1560		T8	2260		T9	32
all_levels[30]	225096	1			T2	1535		T8	2295		T9	34
all_levels[31]	532787	1			T2	1304		T8	2749		T9	134
all_levels[32]	16140875	1			T1	14		T2	45948		T3	20

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35767882

1

T1

32

T2

132465

T3

29

auto[1]

4349

1

T2

4

T3

1

T4

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	7003435	1			T1	1		T2	36155		T3	4
all_levels[0]	auto[1]	2357	1			T2	4		T7	24		T9	24
all_levels[1]	auto[0]	1236174	1			T2	1243		T4	9		T8	1141
all_levels[1]	auto[1]	367	1			T11	2		T111	1		T112	1
all_levels[2]	auto[0]	400235	1			T2	1960		T3	2		T4	3
all_levels[2]	auto[1]	36	1			T12	1		T270	1		T132	2
all_levels[3]	auto[0]	311499	1			T1	7		T2	1855		T4	12
all_levels[3]	auto[1]	126	1			T17	13		T113	2		T93	9
all_levels[4]	auto[0]	609562	1			T2	1242		T4	1		T8	31215
all_levels[4]	auto[1]	30	1			T109	6		T275	2		T314	1
all_levels[5]	auto[0]	307073	1			T1	2		T2	1955		T4	8
all_levels[5]	auto[1]	28	1			T25	1		T246	1		T315	1
all_levels[6]	auto[0]	623918	1			T1	2		T2	1754		T4	2
all_levels[6]	auto[1]	39	1			T123	4		T174	1		T316	1
all_levels[7]	auto[0]	221190	1			T2	1791		T4	4		T8	2294
all_levels[7]	auto[1]	107	1			T112	1		T17	2		T93	5
all_levels[8]	auto[0]	673510	1			T2	1914		T3	2		T8	2288
all_levels[8]	auto[1]	27	1			T10	1		T34	1		T121	1
all_levels[9]	auto[0]	230377	1			T2	1283		T4	1		T8	2255
all_levels[9]	auto[1]	40	1			T160	2		T317	2		T183	1
all_levels[10]	auto[0]	580503	1			T2	1935		T4	6		T8	124651
all_levels[10]	auto[1]	22	1			T69	1		T108	1		T109	1
all_levels[11]	auto[0]	278948	1			T2	1484		T4	10		T8	2263
all_levels[11]	auto[1]	29	1			T27	2		T127	2		T261	1
all_levels[12]	auto[0]	580680	1			T2	1478		T8	2294		T9	56
all_levels[12]	auto[1]	19	1			T127	2		T172	1		T318	1
all_levels[13]	auto[0]	379809	1			T2	1273		T8	2286		T9	51
all_levels[13]	auto[1]	27	1			T319	1		T124	1		T172	2
all_levels[14]	auto[0]	222896	1			T2	1949		T8	2285		T9	46
all_levels[14]	auto[1]	27	1			T11	1		T28	2		T320	1
all_levels[15]	auto[0]	638643	1			T2	1317		T8	2295		T9	30
all_levels[15]	auto[1]	171	1			T17	5		T28	6		T195	2
all_levels[16]	auto[0]	350460	1			T2	1879		T4	8		T8	2259
all_levels[16]	auto[1]	26	1			T115	1		T178	1		T280	1
all_levels[17]	auto[0]	215778	1			T1	2		T2	1777		T4	22
all_levels[17]	auto[1]	17	1			T34	1		T301	1		T321	1
all_levels[18]	auto[0]	401353	1			T1	1		T2	1951		T4	85
all_levels[18]	auto[1]	22	1			T4	1		T301	1		T293	1
all_levels[19]	auto[0]	208146	1			T1	2		T2	1401		T4	3
all_levels[19]	auto[1]	20	1			T115	1		T127	2		T119	2
all_levels[20]	auto[0]	235774	1			T2	1907		T4	10		T8	2267
all_levels[20]	auto[1]	26	1			T256	1		T93	1		T106	1
all_levels[21]	auto[0]	264664	1			T1	1		T2	1951		T4	1
all_levels[21]	auto[1]	13	1			T111	1		T109	1		T261	1
all_levels[22]	auto[0]	384702	1			T2	1400		T4	5		T8	178572
all_levels[22]	auto[1]	20	1			T114	1		T160	1		T193	1
all_levels[23]	auto[0]	281391	1			T2	1481		T4	4		T8	2249
all_levels[23]	auto[1]	19	1			T322	1		T323	1		T324	1
all_levels[24]	auto[0]	231531	1			T2	1610		T4	2		T8	2294
all_levels[24]	auto[1]	16	1			T264	1		T270	2		T325	1
all_levels[25]	auto[0]	204131	1			T2	1358		T3	2		T8	2294
all_levels[25]	auto[1]	18	1			T43	1		T261	1		T321	3
all_levels[26]	auto[0]	489676	1			T2	1922		T8	2279		T9	36
all_levels[26]	auto[1]	23	1			T12	4		T89	1		T91	1
all_levels[27]	auto[0]	634032	1			T2	997		T8	2284		T9	32
all_levels[27]	auto[1]	10	1			T326	1		T157	1		T327	1
all_levels[28]	auto[0]	316231	1			T2	1896		T8	2291		T9	7255
all_levels[28]	auto[1]	27	1			T33	1		T125	1		T328	1
all_levels[29]	auto[0]	353419	1			T2	1560		T8	2260		T9	32
all_levels[29]	auto[1]	24	1			T130	2		T122	1		T213	2
all_levels[30]	auto[0]	225074	1			T2	1535		T8	2295		T9	34
all_levels[30]	auto[1]	22	1			T139	1		T172	2		T206	1
all_levels[31]	auto[0]	532756	1			T2	1304		T8	2749		T9	134
all_levels[31]	auto[1]	31	1			T249	1		T98	1		T127	1
all_levels[32]	auto[0]	16140312	1			T1	14		T2	45948		T3	19
all_levels[32]	auto[1]	563	1			T3	1		T8	1		T9	1