Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	829	1			T13	4		T14	7		T24	4
all_values[1]	829	1			T13	4		T14	7		T24	4
all_values[2]	829	1			T13	4		T14	7		T24	4
all_values[3]	829	1			T13	4		T14	7		T24	4
all_values[4]	829	1			T13	4		T14	7		T24	4
all_values[5]	829	1			T13	4		T14	7		T24	4
all_values[6]	829	1			T13	4		T14	7		T24	4
all_values[7]	829	1			T13	4		T14	7		T24	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3562

1

T13

18

T14

34

T24

15

auto[1]

3070

1

T13

14

T14

22

T24

17

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2473

1

T13

9

T14

17

T24

13

auto[1]

4159

1

T13

23

T14

39

T24

19

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3936

1

T13

17

T14

33

T24

19

auto[1]

2696

1

T13

15

T14

23

T24

13

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	4	44	91.67	4
Automatically Generated Cross Bins	48	4	44	91.67	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	258	1			T13	2		T14	3		T105	2
all_values[0]	auto[0]	auto[1]	auto[1]	233	1			T13	2		T14	2		T24	2
all_values[0]	auto[1]	auto[0]	auto[1]	173	1			T14	1		T27	1		T105	2
all_values[0]	auto[1]	auto[1]	auto[1]	165	1			T14	1		T24	2		T27	1
all_values[1]	auto[0]	auto[0]	auto[0]	271	1			T13	3		T14	2		T24	1
all_values[1]	auto[0]	auto[1]	auto[0]	231	1			T14	3		T24	1		T27	3
all_values[1]	auto[1]	auto[0]	auto[1]	180	1			T13	1		T14	1		T28	2
all_values[1]	auto[1]	auto[1]	auto[1]	147	1			T14	1		T24	2		T27	1
all_values[2]	auto[0]	auto[0]	auto[0]	175	1			T14	1		T105	1		T93	1
all_values[2]	auto[0]	auto[0]	auto[1]	87	1			T24	1		T27	1		T93	1
all_values[2]	auto[0]	auto[1]	auto[0]	149	1			T13	1		T24	1		T27	1
all_values[2]	auto[0]	auto[1]	auto[1]	84	1			T14	2		T27	1		T105	1
all_values[2]	auto[1]	auto[0]	auto[1]	171	1			T14	1		T24	1		T27	1
all_values[2]	auto[1]	auto[1]	auto[1]	163	1			T13	3		T14	3		T24	1
all_values[3]	auto[0]	auto[0]	auto[0]	166	1			T14	1		T24	1		T28	4
all_values[3]	auto[0]	auto[0]	auto[1]	77	1			T13	1		T105	1		T93	1
all_values[3]	auto[0]	auto[1]	auto[0]	141	1			T24	3		T27	3		T93	1
all_values[3]	auto[0]	auto[1]	auto[1]	96	1			T14	3		T105	3		T106	2
all_values[3]	auto[1]	auto[0]	auto[1]	201	1			T13	2		T14	1		T105	2
all_values[3]	auto[1]	auto[1]	auto[1]	148	1			T13	1		T14	2		T27	1
all_values[4]	auto[0]	auto[0]	auto[0]	173	1			T14	1		T24	2		T106	2
all_values[4]	auto[0]	auto[0]	auto[1]	86	1			T14	2		T27	1		T105	1
all_values[4]	auto[0]	auto[1]	auto[0]	135	1			T13	2		T24	1		T107	2
all_values[4]	auto[0]	auto[1]	auto[1]	87	1			T27	1		T28	1		T105	2
all_values[4]	auto[1]	auto[0]	auto[1]	204	1			T13	1		T14	3		T24	1
all_values[4]	auto[1]	auto[1]	auto[1]	144	1			T13	1		T14	1		T28	3
all_values[5]	auto[0]	auto[0]	auto[0]	193	1			T14	4		T24	2		T27	3
all_values[5]	auto[0]	auto[0]	auto[1]	74	1			T13	1		T24	1		T28	1
all_values[5]	auto[0]	auto[1]	auto[0]	158	1			T27	1		T105	1		T93	2
all_values[5]	auto[0]	auto[1]	auto[1]	66	1			T93	2		T107	1		T108	2
all_values[5]	auto[1]	auto[0]	auto[1]	192	1			T13	3		T14	3		T24	1
all_values[5]	auto[1]	auto[1]	auto[1]	146	1			T93	3		T106	1		T107	1
all_values[6]	auto[0]	auto[0]	auto[0]	180	1			T14	3		T105	1		T108	4
all_values[6]	auto[0]	auto[0]	auto[1]	77	1			T105	1		T108	1		T109	1
all_values[6]	auto[0]	auto[1]	auto[0]	148	1			T13	2		T14	1		T27	1
all_values[6]	auto[0]	auto[1]	auto[1]	80	1			T14	1		T24	1		T27	2
all_values[6]	auto[1]	auto[0]	auto[1]	182	1			T13	1		T14	1		T105	1
all_values[6]	auto[1]	auto[1]	auto[1]	162	1			T13	1		T14	1		T24	3
all_values[7]	auto[0]	auto[0]	auto[0]	209	1			T13	1		T14	1		T24	1
all_values[7]	auto[0]	auto[0]	auto[1]	61	1			T13	2		T14	3		T24	1
all_values[7]	auto[0]	auto[1]	auto[0]	144	1			T28	1		T105	6		T93	2
all_values[7]	auto[0]	auto[1]	auto[1]	97	1			T27	1		T28	1		T93	1
all_values[7]	auto[1]	auto[0]	auto[1]	172	1			T14	2		T24	2		T93	1
all_values[7]	auto[1]	auto[1]	auto[1]	146	1			T13	1		T14	1		T27	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal