Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.28 99.27 97.95 100.00 98.80 100.00 99.64


Total test records in report: 1320
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T1257 /workspace/coverage/cover_reg_top/11.uart_csr_rw.4068060536 Apr 25 12:36:04 PM PDT 24 Apr 25 12:36:07 PM PDT 24 136135431 ps
T1258 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.1132199793 Apr 25 12:35:57 PM PDT 24 Apr 25 12:36:01 PM PDT 24 39378485 ps
T1259 /workspace/coverage/cover_reg_top/19.uart_csr_rw.1597622482 Apr 25 12:36:19 PM PDT 24 Apr 25 12:36:21 PM PDT 24 46068172 ps
T1260 /workspace/coverage/cover_reg_top/10.uart_csr_rw.1454550187 Apr 25 12:36:05 PM PDT 24 Apr 25 12:36:09 PM PDT 24 16663096 ps
T1261 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1491976589 Apr 25 12:36:20 PM PDT 24 Apr 25 12:36:22 PM PDT 24 22830119 ps
T1262 /workspace/coverage/cover_reg_top/8.uart_csr_rw.1526914793 Apr 25 12:36:19 PM PDT 24 Apr 25 12:36:20 PM PDT 24 18755471 ps
T1263 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.856331045 Apr 25 12:36:05 PM PDT 24 Apr 25 12:36:10 PM PDT 24 373189123 ps
T1264 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.523952713 Apr 25 12:36:24 PM PDT 24 Apr 25 12:36:25 PM PDT 24 92271586 ps
T1265 /workspace/coverage/cover_reg_top/13.uart_tl_errors.3128905006 Apr 25 12:37:42 PM PDT 24 Apr 25 12:37:47 PM PDT 24 43137117 ps
T1266 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.4148474676 Apr 25 12:35:57 PM PDT 24 Apr 25 12:36:00 PM PDT 24 47288297 ps
T1267 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.368828656 Apr 25 12:36:24 PM PDT 24 Apr 25 12:36:26 PM PDT 24 156648207 ps
T1268 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1906332324 Apr 25 12:36:20 PM PDT 24 Apr 25 12:36:22 PM PDT 24 52835628 ps
T1269 /workspace/coverage/cover_reg_top/10.uart_tl_errors.2057248459 Apr 25 12:36:24 PM PDT 24 Apr 25 12:36:27 PM PDT 24 101138742 ps
T55 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2991366504 Apr 25 12:35:54 PM PDT 24 Apr 25 12:35:58 PM PDT 24 60176330 ps
T1270 /workspace/coverage/cover_reg_top/13.uart_intr_test.314568934 Apr 25 12:36:15 PM PDT 24 Apr 25 12:36:17 PM PDT 24 91199983 ps
T1271 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1389546000 Apr 25 12:36:20 PM PDT 24 Apr 25 12:36:23 PM PDT 24 335659721 ps
T1272 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.4260321479 Apr 25 12:36:05 PM PDT 24 Apr 25 12:36:09 PM PDT 24 22573098 ps
T1273 /workspace/coverage/cover_reg_top/24.uart_intr_test.3627901823 Apr 25 12:37:23 PM PDT 24 Apr 25 12:37:26 PM PDT 24 59135845 ps
T1274 /workspace/coverage/cover_reg_top/38.uart_intr_test.3695805636 Apr 25 12:36:14 PM PDT 24 Apr 25 12:36:17 PM PDT 24 22714924 ps
T1275 /workspace/coverage/cover_reg_top/9.uart_tl_errors.1233597674 Apr 25 12:36:09 PM PDT 24 Apr 25 12:36:13 PM PDT 24 31361162 ps
T1276 /workspace/coverage/cover_reg_top/1.uart_tl_errors.20965774 Apr 25 12:36:09 PM PDT 24 Apr 25 12:36:13 PM PDT 24 84477749 ps
T1277 /workspace/coverage/cover_reg_top/12.uart_csr_rw.2445481773 Apr 25 12:36:12 PM PDT 24 Apr 25 12:36:15 PM PDT 24 162968816 ps
T1278 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1756270617 Apr 25 12:35:52 PM PDT 24 Apr 25 12:35:55 PM PDT 24 56983082 ps
T1279 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.3138952993 Apr 25 12:36:11 PM PDT 24 Apr 25 12:36:15 PM PDT 24 18039561 ps
T1280 /workspace/coverage/cover_reg_top/9.uart_csr_rw.2367760241 Apr 25 12:36:05 PM PDT 24 Apr 25 12:36:08 PM PDT 24 12257423 ps
T1281 /workspace/coverage/cover_reg_top/17.uart_tl_errors.4153965396 Apr 25 12:36:01 PM PDT 24 Apr 25 12:36:06 PM PDT 24 196824477 ps
T1282 /workspace/coverage/cover_reg_top/18.uart_tl_errors.3516436124 Apr 25 12:36:14 PM PDT 24 Apr 25 12:36:17 PM PDT 24 272321530 ps
T1283 /workspace/coverage/cover_reg_top/45.uart_intr_test.1496985177 Apr 25 12:36:26 PM PDT 24 Apr 25 12:36:28 PM PDT 24 13212655 ps
T56 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.350480058 Apr 25 12:35:58 PM PDT 24 Apr 25 12:36:09 PM PDT 24 518004720 ps
T1284 /workspace/coverage/cover_reg_top/7.uart_csr_rw.685908998 Apr 25 12:36:11 PM PDT 24 Apr 25 12:36:14 PM PDT 24 12337747 ps
T57 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2134226878 Apr 25 12:36:01 PM PDT 24 Apr 25 12:36:04 PM PDT 24 112979504 ps
T1285 /workspace/coverage/cover_reg_top/19.uart_intr_test.3487333651 Apr 25 12:37:24 PM PDT 24 Apr 25 12:37:26 PM PDT 24 16150657 ps
T1286 /workspace/coverage/cover_reg_top/6.uart_csr_rw.910469024 Apr 25 12:36:04 PM PDT 24 Apr 25 12:36:07 PM PDT 24 20001496 ps
T1287 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3699433697 Apr 25 12:36:13 PM PDT 24 Apr 25 12:36:16 PM PDT 24 60794603 ps
T1288 /workspace/coverage/cover_reg_top/37.uart_intr_test.57091928 Apr 25 12:37:24 PM PDT 24 Apr 25 12:37:26 PM PDT 24 14033962 ps
T1289 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.4038474330 Apr 25 12:36:07 PM PDT 24 Apr 25 12:36:10 PM PDT 24 76768446 ps
T1290 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.1764189201 Apr 25 12:35:58 PM PDT 24 Apr 25 12:36:02 PM PDT 24 33337434 ps
T1291 /workspace/coverage/cover_reg_top/14.uart_tl_errors.858448394 Apr 25 12:36:08 PM PDT 24 Apr 25 12:36:12 PM PDT 24 298567240 ps
T1292 /workspace/coverage/cover_reg_top/2.uart_intr_test.3251774976 Apr 25 12:35:50 PM PDT 24 Apr 25 12:35:52 PM PDT 24 45730047 ps
T1293 /workspace/coverage/cover_reg_top/17.uart_intr_test.959898537 Apr 25 12:36:05 PM PDT 24 Apr 25 12:36:09 PM PDT 24 30946917 ps
T1294 /workspace/coverage/cover_reg_top/6.uart_tl_errors.2512685471 Apr 25 12:36:05 PM PDT 24 Apr 25 12:36:09 PM PDT 24 30221399 ps
T1295 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.353617297 Apr 25 12:36:19 PM PDT 24 Apr 25 12:36:20 PM PDT 24 151298817 ps
T1296 /workspace/coverage/cover_reg_top/47.uart_intr_test.3762767909 Apr 25 12:36:24 PM PDT 24 Apr 25 12:36:26 PM PDT 24 13185647 ps
T1297 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1905550328 Apr 25 12:37:37 PM PDT 24 Apr 25 12:37:39 PM PDT 24 100820090 ps
T1298 /workspace/coverage/cover_reg_top/30.uart_intr_test.2950986145 Apr 25 12:36:16 PM PDT 24 Apr 25 12:36:18 PM PDT 24 53141612 ps
T1299 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.317962694 Apr 25 12:36:01 PM PDT 24 Apr 25 12:36:05 PM PDT 24 35426917 ps
T1300 /workspace/coverage/cover_reg_top/3.uart_intr_test.2591755788 Apr 25 12:35:57 PM PDT 24 Apr 25 12:36:00 PM PDT 24 13463902 ps
T1301 /workspace/coverage/cover_reg_top/18.uart_csr_rw.3888885276 Apr 25 12:36:02 PM PDT 24 Apr 25 12:36:06 PM PDT 24 51331365 ps
T1302 /workspace/coverage/cover_reg_top/20.uart_intr_test.2266251089 Apr 25 12:36:27 PM PDT 24 Apr 25 12:36:28 PM PDT 24 12165657 ps
T58 /workspace/coverage/cover_reg_top/17.uart_csr_rw.315831733 Apr 25 12:37:43 PM PDT 24 Apr 25 12:37:46 PM PDT 24 82099655 ps
T1303 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.211948489 Apr 25 12:36:13 PM PDT 24 Apr 25 12:36:16 PM PDT 24 61891586 ps
T1304 /workspace/coverage/cover_reg_top/14.uart_csr_rw.3921239085 Apr 25 12:36:05 PM PDT 24 Apr 25 12:36:09 PM PDT 24 16897261 ps
T1305 /workspace/coverage/cover_reg_top/32.uart_intr_test.1027451109 Apr 25 12:37:23 PM PDT 24 Apr 25 12:37:26 PM PDT 24 12838158 ps
T1306 /workspace/coverage/cover_reg_top/19.uart_tl_errors.1241349800 Apr 25 12:36:12 PM PDT 24 Apr 25 12:36:17 PM PDT 24 112356405 ps
T1307 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1567377820 Apr 25 12:35:54 PM PDT 24 Apr 25 12:35:57 PM PDT 24 70365474 ps
T1308 /workspace/coverage/cover_reg_top/16.uart_tl_errors.947391952 Apr 25 12:36:23 PM PDT 24 Apr 25 12:36:25 PM PDT 24 216537843 ps
T1309 /workspace/coverage/cover_reg_top/15.uart_intr_test.2817974175 Apr 25 12:36:13 PM PDT 24 Apr 25 12:36:16 PM PDT 24 12102927 ps
T1310 /workspace/coverage/cover_reg_top/49.uart_intr_test.1297788757 Apr 25 12:36:21 PM PDT 24 Apr 25 12:36:23 PM PDT 24 57221412 ps
T1311 /workspace/coverage/cover_reg_top/27.uart_intr_test.2773172166 Apr 25 12:36:23 PM PDT 24 Apr 25 12:36:25 PM PDT 24 12834663 ps
T1312 /workspace/coverage/cover_reg_top/44.uart_intr_test.779867580 Apr 25 12:36:25 PM PDT 24 Apr 25 12:36:26 PM PDT 24 21320183 ps
T1313 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.329232184 Apr 25 12:36:11 PM PDT 24 Apr 25 12:36:14 PM PDT 24 37821746 ps
T1314 /workspace/coverage/cover_reg_top/18.uart_intr_test.4247698795 Apr 25 12:37:24 PM PDT 24 Apr 25 12:37:26 PM PDT 24 15218100 ps
T1315 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.751822505 Apr 25 12:36:04 PM PDT 24 Apr 25 12:36:08 PM PDT 24 518216640 ps
T1316 /workspace/coverage/cover_reg_top/9.uart_intr_test.3059307011 Apr 25 12:36:07 PM PDT 24 Apr 25 12:36:10 PM PDT 24 12827513 ps
T81 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.547941861 Apr 25 12:36:11 PM PDT 24 Apr 25 12:36:14 PM PDT 24 100085186 ps
T1317 /workspace/coverage/cover_reg_top/11.uart_tl_errors.3452678785 Apr 25 12:35:59 PM PDT 24 Apr 25 12:36:04 PM PDT 24 62887082 ps
T1318 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2380683066 Apr 25 12:36:09 PM PDT 24 Apr 25 12:36:12 PM PDT 24 30013690 ps
T1319 /workspace/coverage/cover_reg_top/8.uart_intr_test.1733351784 Apr 25 12:36:03 PM PDT 24 Apr 25 12:36:06 PM PDT 24 71769548 ps
T104 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.111335933 Apr 25 12:36:14 PM PDT 24 Apr 25 12:36:17 PM PDT 24 89550468 ps
T1320 /workspace/coverage/cover_reg_top/8.uart_tl_errors.984201861 Apr 25 12:36:10 PM PDT 24 Apr 25 12:36:15 PM PDT 24 101514826 ps

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.4000803202
Short name T9
Test name
Test status
Simulation time 326389003801 ps
CPU time 984.19 seconds
Started Apr 25 01:32:40 PM PDT 24
Finished Apr 25 01:49:04 PM PDT 24
Peak memory 232968 kb
Host smart-c9dec1f7-b137-42c3-8495-df535110590e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000803202 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.4000803202
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.1773896379
Short name T16
Test name
Test status
Simulation time 168828659823 ps
CPU time 651.69 seconds
Started Apr 25 01:37:30 PM PDT 24
Finished Apr 25 01:48:23 PM PDT 24
Peak memory 225264 kb
Host smart-b5a0f400-8574-4eed-9dda-352f1f0418c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773896379 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.1773896379
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.3232219524
Short name T13
Test name
Test status
Simulation time 156826061855 ps
CPU time 839.02 seconds
Started Apr 25 01:40:17 PM PDT 24
Finished Apr 25 01:54:16 PM PDT 24
Peak memory 216808 kb
Host smart-d74c2eff-72dd-43f4-adbb-726e7701b363
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232219524 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.3232219524
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_stress_all.2909920727
Short name T115
Test name
Test status
Simulation time 385049143949 ps
CPU time 583.58 seconds
Started Apr 25 01:36:35 PM PDT 24
Finished Apr 25 01:46:19 PM PDT 24
Peak memory 200428 kb
Host smart-32cbd5a6-36dd-4e1a-9870-3682b69a2bef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909920727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.2909920727
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.1190232936
Short name T109
Test name
Test status
Simulation time 631151810836 ps
CPU time 1727.96 seconds
Started Apr 25 01:40:23 PM PDT 24
Finished Apr 25 02:09:11 PM PDT 24
Peak memory 233364 kb
Host smart-3c475400-954f-455c-bdae-4127096bd258
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190232936 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.1190232936
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_stress_all.2334809200
Short name T98
Test name
Test status
Simulation time 418286847160 ps
CPU time 221.31 seconds
Started Apr 25 01:37:28 PM PDT 24
Finished Apr 25 01:41:10 PM PDT 24
Peak memory 208864 kb
Host smart-3e06b9d4-eb80-4729-b234-d59798430cc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334809200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.2334809200
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.1153733172
Short name T25
Test name
Test status
Simulation time 119653914704 ps
CPU time 737.58 seconds
Started Apr 25 01:38:03 PM PDT 24
Finished Apr 25 01:50:22 PM PDT 24
Peak memory 225176 kb
Host smart-e3ab02a1-466b-4be8-ac4f-659466670bd4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153733172 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.1153733172
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_stress_all.2927924027
Short name T127
Test name
Test status
Simulation time 653210286661 ps
CPU time 189.25 seconds
Started Apr 25 01:32:38 PM PDT 24
Finished Apr 25 01:35:48 PM PDT 24
Peak memory 200420 kb
Host smart-57baaf98-c83b-42f4-b227-03f78528caac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927924027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.2927924027
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_sec_cm.687930833
Short name T21
Test name
Test status
Simulation time 37965483 ps
CPU time 0.78 seconds
Started Apr 25 01:32:37 PM PDT 24
Finished Apr 25 01:32:38 PM PDT 24
Peak memory 218456 kb
Host smart-a30a98b7-1c5b-4cc9-b2eb-7acc0aa145cd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687930833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.687930833
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.2142287247
Short name T2
Test name
Test status
Simulation time 41586741385 ps
CPU time 538.54 seconds
Started Apr 25 01:39:55 PM PDT 24
Finished Apr 25 01:48:54 PM PDT 24
Peak memory 217056 kb
Host smart-e292c76f-f805-412a-a50e-65583333ed0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142287247 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.2142287247
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.3954981254
Short name T375
Test name
Test status
Simulation time 12267206 ps
CPU time 0.57 seconds
Started Apr 25 01:35:13 PM PDT 24
Finished Apr 25 01:35:15 PM PDT 24
Peak memory 195804 kb
Host smart-65fd3604-f563-45ef-b17b-62ab6802def6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954981254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.3954981254
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.1867118228
Short name T132
Test name
Test status
Simulation time 345005991685 ps
CPU time 1144.02 seconds
Started Apr 25 01:39:36 PM PDT 24
Finished Apr 25 01:58:41 PM PDT 24
Peak memory 229424 kb
Host smart-2e89e813-c658-4d5a-8aac-d07ac8f719d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867118228 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.1867118228
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.1585698878
Short name T142
Test name
Test status
Simulation time 814046517952 ps
CPU time 949.38 seconds
Started Apr 25 01:35:52 PM PDT 24
Finished Apr 25 01:51:42 PM PDT 24
Peak memory 225368 kb
Host smart-7c7d9f34-ce22-422e-b654-f2d3f9126318
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585698878 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.1585698878
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.2786991324
Short name T77
Test name
Test status
Simulation time 201947678 ps
CPU time 0.98 seconds
Started Apr 25 12:36:10 PM PDT 24
Finished Apr 25 12:36:14 PM PDT 24
Peak memory 199060 kb
Host smart-48125857-d16a-4e08-be77-7a3159641b8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786991324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.2786991324
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/default/45.uart_stress_all.2696633000
Short name T152
Test name
Test status
Simulation time 388883341513 ps
CPU time 94.99 seconds
Started Apr 25 01:39:20 PM PDT 24
Finished Apr 25 01:40:55 PM PDT 24
Peak memory 200420 kb
Host smart-29ba6fcf-1a46-4197-84a9-27c820d51c4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696633000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2696633000
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.1780567932
Short name T39
Test name
Test status
Simulation time 106420406558 ps
CPU time 493.3 seconds
Started Apr 25 01:32:34 PM PDT 24
Finished Apr 25 01:40:48 PM PDT 24
Peak memory 200428 kb
Host smart-5ca20d70-28bf-4758-a234-bc64d6eedcb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1780567932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.1780567932
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.3391194045
Short name T53
Test name
Test status
Simulation time 17814731 ps
CPU time 0.59 seconds
Started Apr 25 12:36:03 PM PDT 24
Finished Apr 25 12:36:06 PM PDT 24
Peak memory 195532 kb
Host smart-ed3fa185-af9c-4334-acc6-92251142ce26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391194045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3391194045
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.2098640948
Short name T24
Test name
Test status
Simulation time 93068643379 ps
CPU time 485.23 seconds
Started Apr 25 01:39:48 PM PDT 24
Finished Apr 25 01:47:54 PM PDT 24
Peak memory 225216 kb
Host smart-70117321-5be7-4303-ad65-906030f66c93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098640948 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.2098640948
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.5280892
Short name T261
Test name
Test status
Simulation time 492500997399 ps
CPU time 714.9 seconds
Started Apr 25 01:34:03 PM PDT 24
Finished Apr 25 01:45:59 PM PDT 24
Peak memory 225276 kb
Host smart-bffa1733-97a7-4b6c-909a-04a0bce9e585
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5280892 -assert nopostproc
+UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.5280892
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.891247072
Short name T93
Test name
Test status
Simulation time 97290621231 ps
CPU time 812.47 seconds
Started Apr 25 01:36:31 PM PDT 24
Finished Apr 25 01:50:04 PM PDT 24
Peak memory 225228 kb
Host smart-0d2f0ea4-a07f-4951-bba3-ca40b149160a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891247072 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.891247072
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.1976302507
Short name T28
Test name
Test status
Simulation time 244823855851 ps
CPU time 314.91 seconds
Started Apr 25 01:40:36 PM PDT 24
Finished Apr 25 01:45:51 PM PDT 24
Peak memory 211744 kb
Host smart-f31c45e6-26ae-4ed8-a698-db18e55dd0c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976302507 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.1976302507
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.111335933
Short name T104
Test name
Test status
Simulation time 89550468 ps
CPU time 1.28 seconds
Started Apr 25 12:36:14 PM PDT 24
Finished Apr 25 12:36:17 PM PDT 24
Peak memory 199340 kb
Host smart-47ed3e75-d410-4962-82a9-cc708b90f6e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111335933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.111335933
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.3314475947
Short name T125
Test name
Test status
Simulation time 143840618119 ps
CPU time 140.4 seconds
Started Apr 25 01:41:11 PM PDT 24
Finished Apr 25 01:43:31 PM PDT 24
Peak memory 200360 kb
Host smart-13461b0c-4f41-41c6-8b83-291656ea1680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314475947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.3314475947
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.713493570
Short name T161
Test name
Test status
Simulation time 219018790207 ps
CPU time 107.21 seconds
Started Apr 25 01:38:59 PM PDT 24
Finished Apr 25 01:40:47 PM PDT 24
Peak memory 200364 kb
Host smart-73854df8-d270-4760-ac3e-cdcee2a479ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713493570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.713493570
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.178509562
Short name T136
Test name
Test status
Simulation time 28037639256 ps
CPU time 29.66 seconds
Started Apr 25 01:41:29 PM PDT 24
Finished Apr 25 01:41:59 PM PDT 24
Peak memory 200348 kb
Host smart-f7acc024-0866-4e42-b3d6-da5a96722be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178509562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.178509562
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_stress_all.992790102
Short name T476
Test name
Test status
Simulation time 864267179324 ps
CPU time 150.07 seconds
Started Apr 25 01:37:03 PM PDT 24
Finished Apr 25 01:39:34 PM PDT 24
Peak memory 200384 kb
Host smart-71c71592-5359-4e92-bc8c-ae0e0affc845
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992790102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.992790102
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.1334099096
Short name T693
Test name
Test status
Simulation time 18249425440 ps
CPU time 15.41 seconds
Started Apr 25 01:36:40 PM PDT 24
Finished Apr 25 01:36:56 PM PDT 24
Peak memory 200400 kb
Host smart-4db47c88-c99a-440a-8eb5-0db456f2ef58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334099096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.1334099096
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.1664961252
Short name T214
Test name
Test status
Simulation time 64928283692 ps
CPU time 55.96 seconds
Started Apr 25 01:42:24 PM PDT 24
Finished Apr 25 01:43:20 PM PDT 24
Peak memory 200248 kb
Host smart-989c41bf-19e5-4dbd-83e5-7ae70ba8c3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664961252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.1664961252
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.3835679362
Short name T288
Test name
Test status
Simulation time 262236930285 ps
CPU time 51.59 seconds
Started Apr 25 01:41:35 PM PDT 24
Finished Apr 25 01:42:27 PM PDT 24
Peak memory 200312 kb
Host smart-92578bb0-fd61-41db-999c-344b0cde5b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835679362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3835679362
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_stress_all.427181800
Short name T135
Test name
Test status
Simulation time 410998147264 ps
CPU time 765.5 seconds
Started Apr 25 01:35:54 PM PDT 24
Finished Apr 25 01:48:40 PM PDT 24
Peak memory 200388 kb
Host smart-65cf7aff-dba6-454e-81d8-f9c7d488c311
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427181800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.427181800
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.1901891597
Short name T210
Test name
Test status
Simulation time 110079176109 ps
CPU time 224.71 seconds
Started Apr 25 01:36:55 PM PDT 24
Finished Apr 25 01:40:40 PM PDT 24
Peak memory 200356 kb
Host smart-2f16555e-9c8d-4048-895b-9f8f924696b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901891597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.1901891597
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.1356860327
Short name T915
Test name
Test status
Simulation time 19209953360 ps
CPU time 9.88 seconds
Started Apr 25 01:35:40 PM PDT 24
Finished Apr 25 01:35:51 PM PDT 24
Peak memory 200120 kb
Host smart-ce2af520-a0d1-484f-ba6f-47e7f47013c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356860327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.1356860327
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.2482595942
Short name T302
Test name
Test status
Simulation time 126986373504 ps
CPU time 231.03 seconds
Started Apr 25 01:38:24 PM PDT 24
Finished Apr 25 01:42:16 PM PDT 24
Peak memory 200424 kb
Host smart-57e648d1-691f-4eb8-901c-86bb804df99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482595942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.2482595942
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.4060109888
Short name T227
Test name
Test status
Simulation time 23131159633 ps
CPU time 33.24 seconds
Started Apr 25 01:41:38 PM PDT 24
Finished Apr 25 01:42:12 PM PDT 24
Peak memory 200428 kb
Host smart-6b11b75b-4f3e-4b62-9539-9ab120264e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060109888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.4060109888
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.1574760527
Short name T1141
Test name
Test status
Simulation time 108200066698 ps
CPU time 24.8 seconds
Started Apr 25 01:41:29 PM PDT 24
Finished Apr 25 01:41:54 PM PDT 24
Peak memory 200360 kb
Host smart-eb083f36-e046-4eb9-b269-4aed4b8c4246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574760527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.1574760527
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.1165004432
Short name T41
Test name
Test status
Simulation time 85345917896 ps
CPU time 39.53 seconds
Started Apr 25 01:41:35 PM PDT 24
Finished Apr 25 01:42:15 PM PDT 24
Peak memory 200396 kb
Host smart-4bef5416-04ad-4d01-8e8e-95f502e81816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165004432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.1165004432
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.1514115308
Short name T239
Test name
Test status
Simulation time 84003789186 ps
CPU time 66.16 seconds
Started Apr 25 01:41:46 PM PDT 24
Finished Apr 25 01:42:53 PM PDT 24
Peak memory 200428 kb
Host smart-79ea691a-06eb-4e6d-b32c-d1cb27d3bad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514115308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.1514115308
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.1594519970
Short name T199
Test name
Test status
Simulation time 19794238480 ps
CPU time 34.24 seconds
Started Apr 25 01:32:44 PM PDT 24
Finished Apr 25 01:33:18 PM PDT 24
Peak memory 200400 kb
Host smart-0b934d94-31f6-4922-8362-556eb716adc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594519970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.1594519970
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_stress_all.3082890965
Short name T316
Test name
Test status
Simulation time 227324441998 ps
CPU time 508.19 seconds
Started Apr 25 01:34:42 PM PDT 24
Finished Apr 25 01:43:11 PM PDT 24
Peak memory 200420 kb
Host smart-6f4d7337-006d-47e8-aeb7-326c0ce68c62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082890965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.3082890965
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.3186102775
Short name T211
Test name
Test status
Simulation time 192352518991 ps
CPU time 715.81 seconds
Started Apr 25 01:35:14 PM PDT 24
Finished Apr 25 01:47:11 PM PDT 24
Peak memory 216992 kb
Host smart-7eac3b20-2b34-4a19-a118-2e30ddb798cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186102775 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.3186102775
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.381301761
Short name T218
Test name
Test status
Simulation time 53200585686 ps
CPU time 39.79 seconds
Started Apr 25 01:41:17 PM PDT 24
Finished Apr 25 01:41:57 PM PDT 24
Peak memory 200256 kb
Host smart-f63eddf5-8a4c-4b31-b536-2fbd43c26e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381301761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.381301761
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.75147390
Short name T226
Test name
Test status
Simulation time 35483583183 ps
CPU time 16.51 seconds
Started Apr 25 01:41:26 PM PDT 24
Finished Apr 25 01:41:43 PM PDT 24
Peak memory 200352 kb
Host smart-5e65187e-b93d-4a42-96fb-bc7970cd7b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75147390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.75147390
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.2938157259
Short name T767
Test name
Test status
Simulation time 9408898064 ps
CPU time 15.65 seconds
Started Apr 25 01:41:34 PM PDT 24
Finished Apr 25 01:41:51 PM PDT 24
Peak memory 200404 kb
Host smart-a8b27f5f-9b81-4da1-81eb-6a5fbfdc3be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938157259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.2938157259
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.3797886924
Short name T202
Test name
Test status
Simulation time 12700656363 ps
CPU time 10.18 seconds
Started Apr 25 01:41:57 PM PDT 24
Finished Apr 25 01:42:08 PM PDT 24
Peak memory 200416 kb
Host smart-a65f6fc9-3e35-4e0c-b3f1-94e065353b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797886924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.3797886924
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.1362511638
Short name T238
Test name
Test status
Simulation time 59333772488 ps
CPU time 26.23 seconds
Started Apr 25 01:41:57 PM PDT 24
Finished Apr 25 01:42:24 PM PDT 24
Peak memory 200340 kb
Host smart-b13e7159-e516-4994-b3b3-fa72697f4ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362511638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.1362511638
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.2378165581
Short name T626
Test name
Test status
Simulation time 39284985151 ps
CPU time 70.74 seconds
Started Apr 25 01:42:08 PM PDT 24
Finished Apr 25 01:43:19 PM PDT 24
Peak memory 200368 kb
Host smart-38c99ee7-de28-48ac-8d9c-3f604c638783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378165581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.2378165581
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.2632089646
Short name T188
Test name
Test status
Simulation time 204525878250 ps
CPU time 56.9 seconds
Started Apr 25 01:42:28 PM PDT 24
Finished Apr 25 01:43:25 PM PDT 24
Peak memory 200432 kb
Host smart-4c8a0804-36f2-4a02-bd71-588080da7e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632089646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.2632089646
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.882445192
Short name T228
Test name
Test status
Simulation time 19182811967 ps
CPU time 35.24 seconds
Started Apr 25 01:42:20 PM PDT 24
Finished Apr 25 01:42:55 PM PDT 24
Peak memory 200400 kb
Host smart-716e8ecf-a7eb-4ea9-ac10-42c2521f7179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882445192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.882445192
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_noise_filter.894176790
Short name T376
Test name
Test status
Simulation time 103124977112 ps
CPU time 47.21 seconds
Started Apr 25 01:37:05 PM PDT 24
Finished Apr 25 01:37:52 PM PDT 24
Peak memory 198768 kb
Host smart-95e74276-00d3-4e2d-855e-146d9a80adb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894176790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.894176790
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.3282356488
Short name T137
Test name
Test status
Simulation time 23909412973 ps
CPU time 51.01 seconds
Started Apr 25 01:37:31 PM PDT 24
Finished Apr 25 01:38:23 PM PDT 24
Peak memory 200436 kb
Host smart-8cd007dc-19ce-49c0-8f07-84613c1dccd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282356488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.3282356488
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.257939058
Short name T156
Test name
Test status
Simulation time 138412069628 ps
CPU time 511.05 seconds
Started Apr 25 01:39:26 PM PDT 24
Finished Apr 25 01:47:58 PM PDT 24
Peak memory 217016 kb
Host smart-3c627ce1-9881-40e3-a90d-ebd29489ec8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257939058 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.257939058
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.1210034244
Short name T47
Test name
Test status
Simulation time 555387365521 ps
CPU time 711.05 seconds
Started Apr 25 01:32:51 PM PDT 24
Finished Apr 25 01:44:44 PM PDT 24
Peak memory 226216 kb
Host smart-7b4c604a-7ea7-4d7d-9789-083dbf855481
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210034244 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.1210034244
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.2241330120
Short name T123
Test name
Test status
Simulation time 51704667083 ps
CPU time 25.51 seconds
Started Apr 25 01:40:45 PM PDT 24
Finished Apr 25 01:41:10 PM PDT 24
Peak memory 200376 kb
Host smart-7237e7d4-ae8b-4281-80bc-61b14a11afbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241330120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.2241330120
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.3613984343
Short name T963
Test name
Test status
Simulation time 15335246261 ps
CPU time 88.31 seconds
Started Apr 25 01:40:47 PM PDT 24
Finished Apr 25 01:42:16 PM PDT 24
Peak memory 200420 kb
Host smart-acd6e10a-82f5-4605-8bc9-5ff1472c3131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613984343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.3613984343
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.1606169474
Short name T139
Test name
Test status
Simulation time 113730770447 ps
CPU time 34.15 seconds
Started Apr 25 01:40:45 PM PDT 24
Finished Apr 25 01:41:20 PM PDT 24
Peak memory 200364 kb
Host smart-0c0b1ba5-4e6b-4e57-9dbc-fc9279d240f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606169474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.1606169474
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.1734515567
Short name T209
Test name
Test status
Simulation time 28810312575 ps
CPU time 52.47 seconds
Started Apr 25 01:40:51 PM PDT 24
Finished Apr 25 01:41:44 PM PDT 24
Peak memory 200440 kb
Host smart-2f1c9f25-391d-43b2-b8dc-bceecd40ad0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734515567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.1734515567
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.3396858376
Short name T206
Test name
Test status
Simulation time 161640497701 ps
CPU time 20.32 seconds
Started Apr 25 01:40:52 PM PDT 24
Finished Apr 25 01:41:13 PM PDT 24
Peak memory 200312 kb
Host smart-95bc63bd-79c8-41a6-8ea7-f285b3769bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396858376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.3396858376
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.1847939124
Short name T219
Test name
Test status
Simulation time 55744879011 ps
CPU time 40.48 seconds
Started Apr 25 01:41:03 PM PDT 24
Finished Apr 25 01:41:44 PM PDT 24
Peak memory 200428 kb
Host smart-0753e5bd-4e27-4455-8780-e20cd12fc145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847939124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1847939124
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.657365520
Short name T232
Test name
Test status
Simulation time 67818331358 ps
CPU time 171.87 seconds
Started Apr 25 01:41:03 PM PDT 24
Finished Apr 25 01:43:56 PM PDT 24
Peak memory 200384 kb
Host smart-c0aeb8d5-1784-4374-8876-337edf89c82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657365520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.657365520
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.3606590808
Short name T242
Test name
Test status
Simulation time 169385779228 ps
CPU time 70.44 seconds
Started Apr 25 01:41:09 PM PDT 24
Finished Apr 25 01:42:20 PM PDT 24
Peak memory 200520 kb
Host smart-8f07385d-1e45-4dbf-8c1d-e6e1815f3e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606590808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3606590808
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.2919265291
Short name T71
Test name
Test status
Simulation time 268067973162 ps
CPU time 261.94 seconds
Started Apr 25 01:35:24 PM PDT 24
Finished Apr 25 01:39:46 PM PDT 24
Peak memory 200428 kb
Host smart-5434e0fa-320c-4c39-9b64-0b4d493e8505
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919265291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.2919265291
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/19.uart_fifo_full.3174417568
Short name T411
Test name
Test status
Simulation time 150627661717 ps
CPU time 479.96 seconds
Started Apr 25 01:35:40 PM PDT 24
Finished Apr 25 01:43:41 PM PDT 24
Peak memory 200376 kb
Host smart-44a352d9-0b81-4360-8f7d-0979e830ef0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174417568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.3174417568
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.3866804239
Short name T233
Test name
Test status
Simulation time 173390273378 ps
CPU time 72.17 seconds
Started Apr 25 01:41:33 PM PDT 24
Finished Apr 25 01:42:46 PM PDT 24
Peak memory 200432 kb
Host smart-51dd09d1-ff6a-4986-a27d-10c469fb443c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866804239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.3866804239
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.215039130
Short name T158
Test name
Test status
Simulation time 172954717003 ps
CPU time 30.58 seconds
Started Apr 25 01:41:40 PM PDT 24
Finished Apr 25 01:42:11 PM PDT 24
Peak memory 200416 kb
Host smart-7bfceb3d-8b9f-47b7-a967-85566528e967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215039130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.215039130
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.2119846961
Short name T237
Test name
Test status
Simulation time 21813525919 ps
CPU time 36.2 seconds
Started Apr 25 01:41:47 PM PDT 24
Finished Apr 25 01:42:23 PM PDT 24
Peak memory 200388 kb
Host smart-3bd03bb5-8c60-48c5-b9a5-49790857ad19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119846961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.2119846961
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.2337564069
Short name T222
Test name
Test status
Simulation time 227266394707 ps
CPU time 78.01 seconds
Started Apr 25 01:41:57 PM PDT 24
Finished Apr 25 01:43:15 PM PDT 24
Peak memory 200364 kb
Host smart-14659a28-f58c-4166-9258-5db87154432d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337564069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.2337564069
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.2503134473
Short name T234
Test name
Test status
Simulation time 173603052134 ps
CPU time 47.5 seconds
Started Apr 25 01:42:18 PM PDT 24
Finished Apr 25 01:43:06 PM PDT 24
Peak memory 200448 kb
Host smart-1291a0d7-a069-445b-a2e0-d93266b745d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503134473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.2503134473
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.1160802372
Short name T150
Test name
Test status
Simulation time 13409092127 ps
CPU time 13.22 seconds
Started Apr 25 01:39:55 PM PDT 24
Finished Apr 25 01:40:09 PM PDT 24
Peak memory 200364 kb
Host smart-446f4c39-39cb-4373-a001-e12f309b5c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160802372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1160802372
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.1826937658
Short name T236
Test name
Test status
Simulation time 91711026053 ps
CPU time 851.55 seconds
Started Apr 25 01:34:21 PM PDT 24
Finished Apr 25 01:48:33 PM PDT 24
Peak memory 216816 kb
Host smart-10e76371-c662-4c9f-b322-8906b1bf2081
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826937658 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.1826937658
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.1133451502
Short name T235
Test name
Test status
Simulation time 55646723216 ps
CPU time 491.93 seconds
Started Apr 25 01:40:34 PM PDT 24
Finished Apr 25 01:48:46 PM PDT 24
Peak memory 210180 kb
Host smart-edb714fe-6199-4c7e-a39c-2ceb9f7a1d5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133451502 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.1133451502
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.266163661
Short name T1219
Test name
Test status
Simulation time 132156047 ps
CPU time 0.75 seconds
Started Apr 25 12:35:56 PM PDT 24
Finished Apr 25 12:35:59 PM PDT 24
Peak memory 196480 kb
Host smart-0a7e05b2-d7d2-43d4-bb9b-59797bd82631
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266163661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.266163661
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.350480058
Short name T56
Test name
Test status
Simulation time 518004720 ps
CPU time 2.5 seconds
Started Apr 25 12:35:58 PM PDT 24
Finished Apr 25 12:36:09 PM PDT 24
Peak memory 198168 kb
Host smart-30387052-b7b3-474b-bc2c-0e256039045a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350480058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.350480058
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3976472282
Short name T1247
Test name
Test status
Simulation time 14241792 ps
CPU time 0.59 seconds
Started Apr 25 12:35:48 PM PDT 24
Finished Apr 25 12:35:50 PM PDT 24
Peak memory 195504 kb
Host smart-5739df36-a20f-41dd-aeb7-8c8dfc17f968
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976472282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.3976472282
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3299010264
Short name T1255
Test name
Test status
Simulation time 31860036 ps
CPU time 0.86 seconds
Started Apr 25 12:36:09 PM PDT 24
Finished Apr 25 12:36:12 PM PDT 24
Peak memory 200076 kb
Host smart-6184da0b-3958-4673-a564-d768f129f3de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299010264 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.3299010264
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.1839124894
Short name T54
Test name
Test status
Simulation time 11414435 ps
CPU time 0.59 seconds
Started Apr 25 12:36:01 PM PDT 24
Finished Apr 25 12:36:04 PM PDT 24
Peak memory 194744 kb
Host smart-c00df64f-d47f-425a-b861-97c5dbccf56b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839124894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.1839124894
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.1270002617
Short name T1203
Test name
Test status
Simulation time 15210347 ps
CPU time 0.62 seconds
Started Apr 25 12:35:55 PM PDT 24
Finished Apr 25 12:35:59 PM PDT 24
Peak memory 194556 kb
Host smart-674873a0-16c4-4e1b-9b61-e10726ee45af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270002617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.1270002617
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.4148474676
Short name T1266
Test name
Test status
Simulation time 47288297 ps
CPU time 0.72 seconds
Started Apr 25 12:35:57 PM PDT 24
Finished Apr 25 12:36:00 PM PDT 24
Peak memory 197136 kb
Host smart-a3b28f96-cc6d-49ec-861c-2a7fe9e8fb02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148474676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.4148474676
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.903315929
Short name T1215
Test name
Test status
Simulation time 461023930 ps
CPU time 1.39 seconds
Started Apr 25 12:36:01 PM PDT 24
Finished Apr 25 12:36:05 PM PDT 24
Peak memory 200220 kb
Host smart-4d0c434f-218f-4887-95cc-5a12ac88ce04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903315929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.903315929
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.4264466044
Short name T103
Test name
Test status
Simulation time 43351789 ps
CPU time 0.97 seconds
Started Apr 25 12:35:55 PM PDT 24
Finished Apr 25 12:35:59 PM PDT 24
Peak memory 198892 kb
Host smart-0b9989f2-c473-4d3d-84f2-bd569bc1a5c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264466044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.4264466044
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1362145704
Short name T1237
Test name
Test status
Simulation time 22075673 ps
CPU time 0.67 seconds
Started Apr 25 12:35:59 PM PDT 24
Finished Apr 25 12:36:02 PM PDT 24
Peak memory 195496 kb
Host smart-aa604f84-bbf4-46ba-bb25-6bfaea03075f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362145704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.1362145704
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1901087632
Short name T1231
Test name
Test status
Simulation time 361743914 ps
CPU time 2.5 seconds
Started Apr 25 12:35:56 PM PDT 24
Finished Apr 25 12:36:02 PM PDT 24
Peak memory 198060 kb
Host smart-3d6c0be2-55fc-46ae-8077-a733d074f6b1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901087632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.1901087632
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.662382282
Short name T1234
Test name
Test status
Simulation time 28287543 ps
CPU time 0.59 seconds
Started Apr 25 12:35:55 PM PDT 24
Finished Apr 25 12:35:59 PM PDT 24
Peak memory 195540 kb
Host smart-3fcdc0dc-7c4a-41cc-9db0-1d7a57fc178c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662382282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.662382282
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.329232184
Short name T1313
Test name
Test status
Simulation time 37821746 ps
CPU time 0.73 seconds
Started Apr 25 12:36:11 PM PDT 24
Finished Apr 25 12:36:14 PM PDT 24
Peak memory 198508 kb
Host smart-8058a9ac-f533-40a4-98f0-6dc1ef1392e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329232184 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.329232184
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.1929141602
Short name T1227
Test name
Test status
Simulation time 12928278 ps
CPU time 0.56 seconds
Started Apr 25 12:35:51 PM PDT 24
Finished Apr 25 12:35:53 PM PDT 24
Peak memory 194556 kb
Host smart-56f1af85-81be-4211-abb7-47f28859407a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929141602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.1929141602
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3763310497
Short name T61
Test name
Test status
Simulation time 102080454 ps
CPU time 0.77 seconds
Started Apr 25 12:36:02 PM PDT 24
Finished Apr 25 12:36:05 PM PDT 24
Peak memory 197120 kb
Host smart-0b239401-7835-43a1-adae-a07dca3fb416
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763310497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.3763310497
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.20965774
Short name T1276
Test name
Test status
Simulation time 84477749 ps
CPU time 1.55 seconds
Started Apr 25 12:36:09 PM PDT 24
Finished Apr 25 12:36:13 PM PDT 24
Peak memory 200220 kb
Host smart-3e471584-0685-4018-9342-5c314f1bfe3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20965774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.20965774
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3147685920
Short name T80
Test name
Test status
Simulation time 339243088 ps
CPU time 1.29 seconds
Started Apr 25 12:36:02 PM PDT 24
Finished Apr 25 12:36:06 PM PDT 24
Peak memory 199488 kb
Host smart-300ff4b5-6510-4fa7-94c9-d789effab22a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147685920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.3147685920
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.453202778
Short name T1253
Test name
Test status
Simulation time 24674116 ps
CPU time 1.29 seconds
Started Apr 25 12:36:10 PM PDT 24
Finished Apr 25 12:36:14 PM PDT 24
Peak memory 200160 kb
Host smart-bc339068-9328-4359-b454-128c8be87f5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453202778 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.453202778
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.1454550187
Short name T1260
Test name
Test status
Simulation time 16663096 ps
CPU time 0.63 seconds
Started Apr 25 12:36:05 PM PDT 24
Finished Apr 25 12:36:09 PM PDT 24
Peak memory 195724 kb
Host smart-6b77e23f-03fd-427f-82c7-484da19ea060
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454550187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.1454550187
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.2787753337
Short name T1244
Test name
Test status
Simulation time 23701934 ps
CPU time 0.6 seconds
Started Apr 25 12:35:53 PM PDT 24
Finished Apr 25 12:35:56 PM PDT 24
Peak memory 194488 kb
Host smart-e099e5c2-7f2a-40ef-b45e-be4b15c8722d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787753337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.2787753337
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1906332324
Short name T1268
Test name
Test status
Simulation time 52835628 ps
CPU time 0.77 seconds
Started Apr 25 12:36:20 PM PDT 24
Finished Apr 25 12:36:22 PM PDT 24
Peak memory 197116 kb
Host smart-e37ea6f8-1483-416e-8d80-979e0e4c7826
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906332324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.1906332324
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.2057248459
Short name T1269
Test name
Test status
Simulation time 101138742 ps
CPU time 2.02 seconds
Started Apr 25 12:36:24 PM PDT 24
Finished Apr 25 12:36:27 PM PDT 24
Peak memory 200192 kb
Host smart-4a420b79-7eb5-426a-9331-2e968f0eee3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057248459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.2057248459
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.751822505
Short name T1315
Test name
Test status
Simulation time 518216640 ps
CPU time 1.29 seconds
Started Apr 25 12:36:04 PM PDT 24
Finished Apr 25 12:36:08 PM PDT 24
Peak memory 199328 kb
Host smart-63d6468c-35aa-432e-a423-a4d9e0cbf4ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751822505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.751822505
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1367317176
Short name T1202
Test name
Test status
Simulation time 68748857 ps
CPU time 0.92 seconds
Started Apr 25 12:36:22 PM PDT 24
Finished Apr 25 12:36:24 PM PDT 24
Peak memory 200012 kb
Host smart-fdeb9961-a676-4d14-b227-6e2058219487
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367317176 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.1367317176
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.4068060536
Short name T1257
Test name
Test status
Simulation time 136135431 ps
CPU time 0.6 seconds
Started Apr 25 12:36:04 PM PDT 24
Finished Apr 25 12:36:07 PM PDT 24
Peak memory 195624 kb
Host smart-6bcda181-2864-48b2-b0d1-089b9fa3ab52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068060536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.4068060536
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.2415683442
Short name T1192
Test name
Test status
Simulation time 12209508 ps
CPU time 0.57 seconds
Started Apr 25 12:36:12 PM PDT 24
Finished Apr 25 12:36:15 PM PDT 24
Peak memory 194528 kb
Host smart-5a37fe69-0b1d-40af-aeed-707eb12a218b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415683442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.2415683442
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.2399400115
Short name T67
Test name
Test status
Simulation time 22025749 ps
CPU time 0.67 seconds
Started Apr 25 12:36:25 PM PDT 24
Finished Apr 25 12:36:26 PM PDT 24
Peak memory 195728 kb
Host smart-d088f92d-2c15-41f0-ac62-5a927d1ee232
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399400115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.2399400115
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.3452678785
Short name T1317
Test name
Test status
Simulation time 62887082 ps
CPU time 1.49 seconds
Started Apr 25 12:35:59 PM PDT 24
Finished Apr 25 12:36:04 PM PDT 24
Peak memory 200216 kb
Host smart-2de50cb2-b368-4522-821e-2e24616c6a1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452678785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3452678785
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.211948489
Short name T1303
Test name
Test status
Simulation time 61891586 ps
CPU time 0.67 seconds
Started Apr 25 12:36:13 PM PDT 24
Finished Apr 25 12:36:16 PM PDT 24
Peak memory 197768 kb
Host smart-360439f5-24f6-4f62-a44f-c86c14c716c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211948489 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.211948489
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.2445481773
Short name T1277
Test name
Test status
Simulation time 162968816 ps
CPU time 0.6 seconds
Started Apr 25 12:36:12 PM PDT 24
Finished Apr 25 12:36:15 PM PDT 24
Peak memory 195552 kb
Host smart-bb91e5cb-891f-4480-b4ef-7f4a22b7bf12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445481773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2445481773
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.2307588377
Short name T1188
Test name
Test status
Simulation time 43719568 ps
CPU time 0.6 seconds
Started Apr 25 12:36:14 PM PDT 24
Finished Apr 25 12:36:17 PM PDT 24
Peak memory 194520 kb
Host smart-a919337b-ba5a-4386-a042-597a3dacdff1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307588377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2307588377
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2789341268
Short name T1217
Test name
Test status
Simulation time 91020261 ps
CPU time 0.84 seconds
Started Apr 25 12:36:12 PM PDT 24
Finished Apr 25 12:36:15 PM PDT 24
Peak memory 196744 kb
Host smart-6423f0dc-e494-466c-9b56-020fd54816f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789341268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.2789341268
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.4011288747
Short name T1225
Test name
Test status
Simulation time 462698968 ps
CPU time 2.34 seconds
Started Apr 25 12:37:24 PM PDT 24
Finished Apr 25 12:37:29 PM PDT 24
Peak memory 199808 kb
Host smart-41e863a2-1113-468f-a1b4-78cfd4f2fe94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011288747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.4011288747
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3681071257
Short name T1238
Test name
Test status
Simulation time 187090817 ps
CPU time 0.91 seconds
Started Apr 25 12:36:13 PM PDT 24
Finished Apr 25 12:36:16 PM PDT 24
Peak memory 198816 kb
Host smart-5278664c-21d9-431e-a2fb-2b316b8251dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681071257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3681071257
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.523952713
Short name T1264
Test name
Test status
Simulation time 92271586 ps
CPU time 0.89 seconds
Started Apr 25 12:36:24 PM PDT 24
Finished Apr 25 12:36:25 PM PDT 24
Peak memory 200028 kb
Host smart-8d7db0e2-f1e6-4ece-bcee-104c4fb173db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523952713 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.523952713
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.4176789444
Short name T68
Test name
Test status
Simulation time 43116803 ps
CPU time 0.59 seconds
Started Apr 25 12:36:19 PM PDT 24
Finished Apr 25 12:36:20 PM PDT 24
Peak memory 195468 kb
Host smart-d6b1b660-4fdd-4c8e-b64a-e71c372a6985
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176789444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.4176789444
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.314568934
Short name T1270
Test name
Test status
Simulation time 91199983 ps
CPU time 0.55 seconds
Started Apr 25 12:36:15 PM PDT 24
Finished Apr 25 12:36:17 PM PDT 24
Peak memory 194496 kb
Host smart-a53cb834-fafe-450d-a29a-5dfa83c7910c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314568934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.314568934
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.765946582
Short name T1241
Test name
Test status
Simulation time 14660513 ps
CPU time 0.63 seconds
Started Apr 25 12:36:03 PM PDT 24
Finished Apr 25 12:36:07 PM PDT 24
Peak memory 195676 kb
Host smart-e67ba6a5-da90-4a36-b140-e09e713e3141
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765946582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr
_outstanding.765946582
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.3128905006
Short name T1265
Test name
Test status
Simulation time 43137117 ps
CPU time 1.99 seconds
Started Apr 25 12:37:42 PM PDT 24
Finished Apr 25 12:37:47 PM PDT 24
Peak memory 200036 kb
Host smart-563812b7-2ef1-4b2d-8394-b594549fc6a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128905006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3128905006
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.368828656
Short name T1267
Test name
Test status
Simulation time 156648207 ps
CPU time 0.92 seconds
Started Apr 25 12:36:24 PM PDT 24
Finished Apr 25 12:36:26 PM PDT 24
Peak memory 199072 kb
Host smart-8b9020c5-92cd-405d-b5bd-b1a954cb4548
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368828656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.368828656
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1905550328
Short name T1297
Test name
Test status
Simulation time 100820090 ps
CPU time 0.79 seconds
Started Apr 25 12:37:37 PM PDT 24
Finished Apr 25 12:37:39 PM PDT 24
Peak memory 199812 kb
Host smart-3dde7174-76e0-430a-9b43-0dd7329af77c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905550328 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.1905550328
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.3921239085
Short name T1304
Test name
Test status
Simulation time 16897261 ps
CPU time 0.58 seconds
Started Apr 25 12:36:05 PM PDT 24
Finished Apr 25 12:36:09 PM PDT 24
Peak memory 195544 kb
Host smart-5eb58514-9e3c-4be4-b705-149646c969f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921239085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.3921239085
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.3055759150
Short name T1210
Test name
Test status
Simulation time 16778315 ps
CPU time 0.61 seconds
Started Apr 25 12:36:10 PM PDT 24
Finished Apr 25 12:36:14 PM PDT 24
Peak memory 194576 kb
Host smart-c93cf707-c36d-4e8a-bd50-5e011b76490c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055759150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.3055759150
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2380683066
Short name T1318
Test name
Test status
Simulation time 30013690 ps
CPU time 0.73 seconds
Started Apr 25 12:36:09 PM PDT 24
Finished Apr 25 12:36:12 PM PDT 24
Peak memory 197940 kb
Host smart-54614993-74a3-438c-961c-28ebafec1cb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380683066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.2380683066
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.858448394
Short name T1291
Test name
Test status
Simulation time 298567240 ps
CPU time 1.16 seconds
Started Apr 25 12:36:08 PM PDT 24
Finished Apr 25 12:36:12 PM PDT 24
Peak memory 200188 kb
Host smart-716e3336-05fc-4413-8a73-d48821db9e8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858448394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.858448394
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.673045828
Short name T102
Test name
Test status
Simulation time 43585134 ps
CPU time 0.92 seconds
Started Apr 25 12:36:07 PM PDT 24
Finished Apr 25 12:36:11 PM PDT 24
Peak memory 198820 kb
Host smart-a72cf202-4eae-4e12-9a77-9504c2d2b85d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673045828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.673045828
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2802234496
Short name T1240
Test name
Test status
Simulation time 26521358 ps
CPU time 0.77 seconds
Started Apr 25 12:36:14 PM PDT 24
Finished Apr 25 12:36:17 PM PDT 24
Peak memory 199816 kb
Host smart-cbbd4863-3278-43ad-825b-d0e9ac0e25dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802234496 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.2802234496
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.1133309513
Short name T1205
Test name
Test status
Simulation time 44780596 ps
CPU time 0.54 seconds
Started Apr 25 12:37:42 PM PDT 24
Finished Apr 25 12:37:46 PM PDT 24
Peak memory 195372 kb
Host smart-c55214ea-8ca3-4a63-8946-fd77ae409839
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133309513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1133309513
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.2817974175
Short name T1309
Test name
Test status
Simulation time 12102927 ps
CPU time 0.57 seconds
Started Apr 25 12:36:13 PM PDT 24
Finished Apr 25 12:36:16 PM PDT 24
Peak memory 194516 kb
Host smart-585d9e95-5e27-4149-8cbf-65c9d1d4a88d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817974175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.2817974175
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1398972271
Short name T1233
Test name
Test status
Simulation time 136294491 ps
CPU time 0.76 seconds
Started Apr 25 12:36:22 PM PDT 24
Finished Apr 25 12:36:24 PM PDT 24
Peak memory 197820 kb
Host smart-95aa0491-2811-4b64-a486-d85d899e6d5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398972271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.1398972271
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.1617822131
Short name T1230
Test name
Test status
Simulation time 70206669 ps
CPU time 1.86 seconds
Started Apr 25 12:36:33 PM PDT 24
Finished Apr 25 12:36:36 PM PDT 24
Peak memory 200200 kb
Host smart-4aa7c39b-dd28-4781-ac50-70b8c96aea28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617822131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.1617822131
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1996047571
Short name T76
Test name
Test status
Simulation time 78723900 ps
CPU time 1.3 seconds
Started Apr 25 12:36:01 PM PDT 24
Finished Apr 25 12:36:05 PM PDT 24
Peak memory 199720 kb
Host smart-4d169e4f-7ef8-43f4-baab-d77afb112baa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996047571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1996047571
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.4260321479
Short name T1272
Test name
Test status
Simulation time 22573098 ps
CPU time 0.7 seconds
Started Apr 25 12:36:05 PM PDT 24
Finished Apr 25 12:36:09 PM PDT 24
Peak memory 198664 kb
Host smart-381084bd-efee-47b2-b2f2-57b37e83f2c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260321479 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.4260321479
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.4128179439
Short name T59
Test name
Test status
Simulation time 44331140 ps
CPU time 0.55 seconds
Started Apr 25 12:36:09 PM PDT 24
Finished Apr 25 12:36:12 PM PDT 24
Peak memory 195524 kb
Host smart-b7ca70c0-a846-4b98-bcd0-16310a21053b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128179439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.4128179439
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.1252295724
Short name T1232
Test name
Test status
Simulation time 12476456 ps
CPU time 0.56 seconds
Started Apr 25 12:36:17 PM PDT 24
Finished Apr 25 12:36:19 PM PDT 24
Peak memory 194536 kb
Host smart-0a9177f2-f48a-4e35-8b24-cefded1c38ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252295724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.1252295724
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1491976589
Short name T1261
Test name
Test status
Simulation time 22830119 ps
CPU time 0.67 seconds
Started Apr 25 12:36:20 PM PDT 24
Finished Apr 25 12:36:22 PM PDT 24
Peak memory 195828 kb
Host smart-514cec25-12f2-4b80-8df7-acfe5e8e7e3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491976589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.1491976589
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.947391952
Short name T1308
Test name
Test status
Simulation time 216537843 ps
CPU time 1.24 seconds
Started Apr 25 12:36:23 PM PDT 24
Finished Apr 25 12:36:25 PM PDT 24
Peak memory 200160 kb
Host smart-5b4e089d-93d0-4b9f-91f5-a5e228371a41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947391952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.947391952
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3435832982
Short name T1216
Test name
Test status
Simulation time 25405321 ps
CPU time 0.77 seconds
Started Apr 25 12:36:09 PM PDT 24
Finished Apr 25 12:36:12 PM PDT 24
Peak memory 199556 kb
Host smart-4ef29c03-4247-46f8-994f-a1dc315a0bed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435832982 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.3435832982
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.315831733
Short name T58
Test name
Test status
Simulation time 82099655 ps
CPU time 0.53 seconds
Started Apr 25 12:37:43 PM PDT 24
Finished Apr 25 12:37:46 PM PDT 24
Peak memory 195392 kb
Host smart-608ac196-0fb7-45d8-93d9-010c4e8aacdb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315831733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.315831733
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.959898537
Short name T1293
Test name
Test status
Simulation time 30946917 ps
CPU time 0.55 seconds
Started Apr 25 12:36:05 PM PDT 24
Finished Apr 25 12:36:09 PM PDT 24
Peak memory 194508 kb
Host smart-85bb324f-d3f2-4c2d-9065-fca07239a498
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959898537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.959898537
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.1047842229
Short name T62
Test name
Test status
Simulation time 77283687 ps
CPU time 0.73 seconds
Started Apr 25 12:36:20 PM PDT 24
Finished Apr 25 12:36:22 PM PDT 24
Peak memory 196660 kb
Host smart-43f05296-08fc-44fb-ab51-fbe4cc5cb899
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047842229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.1047842229
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.4153965396
Short name T1281
Test name
Test status
Simulation time 196824477 ps
CPU time 1.68 seconds
Started Apr 25 12:36:01 PM PDT 24
Finished Apr 25 12:36:06 PM PDT 24
Peak memory 200224 kb
Host smart-7b895106-2978-40b2-86e4-931b4c175eb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153965396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.4153965396
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.547941861
Short name T81
Test name
Test status
Simulation time 100085186 ps
CPU time 1 seconds
Started Apr 25 12:36:11 PM PDT 24
Finished Apr 25 12:36:14 PM PDT 24
Peak memory 199164 kb
Host smart-60c8fdf5-69bc-4818-8890-b8e7991b5b8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547941861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.547941861
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2469295901
Short name T1228
Test name
Test status
Simulation time 37135567 ps
CPU time 1.11 seconds
Started Apr 25 12:36:18 PM PDT 24
Finished Apr 25 12:36:20 PM PDT 24
Peak memory 200048 kb
Host smart-2685f45c-a435-4c05-9d87-c0198b57a0de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469295901 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.2469295901
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.3888885276
Short name T1301
Test name
Test status
Simulation time 51331365 ps
CPU time 0.64 seconds
Started Apr 25 12:36:02 PM PDT 24
Finished Apr 25 12:36:06 PM PDT 24
Peak memory 195576 kb
Host smart-2b2f92e1-a259-40a7-88dd-aa091356a43b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888885276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3888885276
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.4247698795
Short name T1314
Test name
Test status
Simulation time 15218100 ps
CPU time 0.57 seconds
Started Apr 25 12:37:24 PM PDT 24
Finished Apr 25 12:37:26 PM PDT 24
Peak memory 193956 kb
Host smart-30aa765a-325d-4b72-8e0b-f4cb2917d165
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247698795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.4247698795
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.237863695
Short name T1222
Test name
Test status
Simulation time 27002881 ps
CPU time 0.74 seconds
Started Apr 25 12:36:23 PM PDT 24
Finished Apr 25 12:36:25 PM PDT 24
Peak memory 196996 kb
Host smart-7ea771b7-f44a-4bdd-a88f-97b95c2dbf99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237863695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr
_outstanding.237863695
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.3516436124
Short name T1282
Test name
Test status
Simulation time 272321530 ps
CPU time 1.41 seconds
Started Apr 25 12:36:14 PM PDT 24
Finished Apr 25 12:36:17 PM PDT 24
Peak memory 200276 kb
Host smart-aad5b3e3-c498-4cd0-bb89-597659f5f465
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516436124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.3516436124
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.353617297
Short name T1295
Test name
Test status
Simulation time 151298817 ps
CPU time 0.91 seconds
Started Apr 25 12:36:19 PM PDT 24
Finished Apr 25 12:36:20 PM PDT 24
Peak memory 198856 kb
Host smart-ae0dd846-bac3-491b-9047-fb4eb0bbc4c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353617297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.353617297
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3699433697
Short name T1287
Test name
Test status
Simulation time 60794603 ps
CPU time 0.85 seconds
Started Apr 25 12:36:13 PM PDT 24
Finished Apr 25 12:36:16 PM PDT 24
Peak memory 200020 kb
Host smart-87c75538-98fc-4175-91b1-2f37648e7d27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699433697 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.3699433697
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.1597622482
Short name T1259
Test name
Test status
Simulation time 46068172 ps
CPU time 0.56 seconds
Started Apr 25 12:36:19 PM PDT 24
Finished Apr 25 12:36:21 PM PDT 24
Peak memory 195488 kb
Host smart-45bc15e4-05b2-498d-83d3-c62836057253
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597622482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.1597622482
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.3487333651
Short name T1285
Test name
Test status
Simulation time 16150657 ps
CPU time 0.57 seconds
Started Apr 25 12:37:24 PM PDT 24
Finished Apr 25 12:37:26 PM PDT 24
Peak memory 193660 kb
Host smart-b41f826c-0e5a-4860-9a41-088d61232cbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487333651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.3487333651
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2846884982
Short name T64
Test name
Test status
Simulation time 21652996 ps
CPU time 0.66 seconds
Started Apr 25 12:36:32 PM PDT 24
Finished Apr 25 12:36:34 PM PDT 24
Peak memory 195884 kb
Host smart-da7bb358-b7dd-43ab-b0a4-72ef1d633ef1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846884982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.2846884982
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.1241349800
Short name T1306
Test name
Test status
Simulation time 112356405 ps
CPU time 1.66 seconds
Started Apr 25 12:36:12 PM PDT 24
Finished Apr 25 12:36:17 PM PDT 24
Peak memory 200260 kb
Host smart-a487ed41-4526-49da-bcd4-1bad4557e6e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241349800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.1241349800
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2722952855
Short name T101
Test name
Test status
Simulation time 111601971 ps
CPU time 0.94 seconds
Started Apr 25 12:36:13 PM PDT 24
Finished Apr 25 12:36:16 PM PDT 24
Peak memory 199108 kb
Host smart-92113014-9702-4f15-85b4-d34775336c20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722952855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.2722952855
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2991366504
Short name T55
Test name
Test status
Simulation time 60176330 ps
CPU time 0.74 seconds
Started Apr 25 12:35:54 PM PDT 24
Finished Apr 25 12:35:58 PM PDT 24
Peak memory 196368 kb
Host smart-a2590b32-2d75-45f1-a1d2-646b84b90aaf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991366504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.2991366504
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.119302056
Short name T1190
Test name
Test status
Simulation time 1038968842 ps
CPU time 2.62 seconds
Started Apr 25 12:35:57 PM PDT 24
Finished Apr 25 12:36:02 PM PDT 24
Peak memory 198140 kb
Host smart-d1046355-c9f3-4ee8-bbe8-c18c6fc33105
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119302056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.119302056
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2134226878
Short name T57
Test name
Test status
Simulation time 112979504 ps
CPU time 0.61 seconds
Started Apr 25 12:36:01 PM PDT 24
Finished Apr 25 12:36:04 PM PDT 24
Peak memory 195544 kb
Host smart-4c9d060e-9f18-42c0-800b-30b5d9a64d13
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134226878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.2134226878
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1756270617
Short name T1278
Test name
Test status
Simulation time 56983082 ps
CPU time 0.81 seconds
Started Apr 25 12:35:52 PM PDT 24
Finished Apr 25 12:35:55 PM PDT 24
Peak memory 199972 kb
Host smart-060654d1-a065-4fbe-bf62-49cd79866302
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756270617 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.1756270617
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.1464409086
Short name T60
Test name
Test status
Simulation time 12472545 ps
CPU time 0.57 seconds
Started Apr 25 12:35:57 PM PDT 24
Finished Apr 25 12:36:00 PM PDT 24
Peak memory 195516 kb
Host smart-e37b0e30-b252-4c30-a2ea-0025ef7aa8fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464409086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.1464409086
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.3251774976
Short name T1292
Test name
Test status
Simulation time 45730047 ps
CPU time 0.57 seconds
Started Apr 25 12:35:50 PM PDT 24
Finished Apr 25 12:35:52 PM PDT 24
Peak memory 194508 kb
Host smart-60a3e5f3-179b-4c94-9ff8-baae5fe74497
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251774976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3251774976
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.1132199793
Short name T1258
Test name
Test status
Simulation time 39378485 ps
CPU time 0.64 seconds
Started Apr 25 12:35:57 PM PDT 24
Finished Apr 25 12:36:01 PM PDT 24
Peak memory 196040 kb
Host smart-aa559a87-9a73-427c-882f-1e40bedaed3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132199793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.1132199793
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.468835377
Short name T1221
Test name
Test status
Simulation time 92866787 ps
CPU time 1.09 seconds
Started Apr 25 12:36:00 PM PDT 24
Finished Apr 25 12:36:04 PM PDT 24
Peak memory 199948 kb
Host smart-d54c172d-6932-42d8-ad01-ad5eab8e0134
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468835377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.468835377
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2307744375
Short name T73
Test name
Test status
Simulation time 193982521 ps
CPU time 0.93 seconds
Started Apr 25 12:36:00 PM PDT 24
Finished Apr 25 12:36:04 PM PDT 24
Peak memory 199072 kb
Host smart-a0f1313d-16ce-4c23-8c4c-90eadcaebc27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307744375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.2307744375
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.2266251089
Short name T1302
Test name
Test status
Simulation time 12165657 ps
CPU time 0.55 seconds
Started Apr 25 12:36:27 PM PDT 24
Finished Apr 25 12:36:28 PM PDT 24
Peak memory 194520 kb
Host smart-7e97b96f-8c27-42a4-99ff-a3e2edc42883
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266251089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2266251089
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.1225493694
Short name T1223
Test name
Test status
Simulation time 46966822 ps
CPU time 0.62 seconds
Started Apr 25 12:36:11 PM PDT 24
Finished Apr 25 12:36:14 PM PDT 24
Peak memory 194572 kb
Host smart-191bcaaf-32c0-4b70-8573-47e54e9feec1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225493694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.1225493694
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.317122165
Short name T1187
Test name
Test status
Simulation time 29103509 ps
CPU time 0.61 seconds
Started Apr 25 12:36:16 PM PDT 24
Finished Apr 25 12:36:18 PM PDT 24
Peak memory 194552 kb
Host smart-479004d3-4841-4e3b-834f-84320ea89fb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317122165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.317122165
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.4049491520
Short name T1191
Test name
Test status
Simulation time 11094021 ps
CPU time 0.58 seconds
Started Apr 25 12:36:04 PM PDT 24
Finished Apr 25 12:36:08 PM PDT 24
Peak memory 194508 kb
Host smart-d23691a7-59ee-493d-b9c8-a88726c122b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049491520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.4049491520
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.3627901823
Short name T1273
Test name
Test status
Simulation time 59135845 ps
CPU time 0.7 seconds
Started Apr 25 12:37:23 PM PDT 24
Finished Apr 25 12:37:26 PM PDT 24
Peak memory 191876 kb
Host smart-b2be5347-3e95-43f6-bad6-0d31e2afec78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627901823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.3627901823
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.1707091552
Short name T1193
Test name
Test status
Simulation time 37172758 ps
CPU time 0.57 seconds
Started Apr 25 12:36:23 PM PDT 24
Finished Apr 25 12:36:24 PM PDT 24
Peak memory 194576 kb
Host smart-90938c52-d874-45b1-9cc0-c589123faad5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707091552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.1707091552
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.2895483411
Short name T1207
Test name
Test status
Simulation time 31755754 ps
CPU time 0.56 seconds
Started Apr 25 12:36:17 PM PDT 24
Finished Apr 25 12:36:24 PM PDT 24
Peak memory 194452 kb
Host smart-1c8d8a83-d995-4fb2-9025-5749c31ff2e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895483411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.2895483411
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.2773172166
Short name T1311
Test name
Test status
Simulation time 12834663 ps
CPU time 0.56 seconds
Started Apr 25 12:36:23 PM PDT 24
Finished Apr 25 12:36:25 PM PDT 24
Peak memory 194696 kb
Host smart-3404616f-e081-493f-9cb2-371dbbdc87b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773172166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.2773172166
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.940278536
Short name T1214
Test name
Test status
Simulation time 12679176 ps
CPU time 0.59 seconds
Started Apr 25 12:36:12 PM PDT 24
Finished Apr 25 12:36:16 PM PDT 24
Peak memory 194692 kb
Host smart-1233b438-74c0-44ab-a32d-a784c9f18150
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940278536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.940278536
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.3238331019
Short name T1212
Test name
Test status
Simulation time 44493158 ps
CPU time 0.54 seconds
Started Apr 25 12:36:22 PM PDT 24
Finished Apr 25 12:36:24 PM PDT 24
Peak memory 194528 kb
Host smart-effe6ba7-a9d7-4339-a703-d4e6b4b08f91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238331019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.3238331019
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1567377820
Short name T1307
Test name
Test status
Simulation time 70365474 ps
CPU time 0.71 seconds
Started Apr 25 12:35:54 PM PDT 24
Finished Apr 25 12:35:57 PM PDT 24
Peak memory 195040 kb
Host smart-6795bf23-f59c-4990-a2f6-60ec5c4b1837
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567377820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1567377820
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1473271191
Short name T1249
Test name
Test status
Simulation time 213295277 ps
CPU time 2.31 seconds
Started Apr 25 12:36:11 PM PDT 24
Finished Apr 25 12:36:16 PM PDT 24
Peak memory 198140 kb
Host smart-d838e2a3-7135-4c8a-bcd0-55ae5240b481
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473271191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.1473271191
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1448547647
Short name T1254
Test name
Test status
Simulation time 54050142 ps
CPU time 0.58 seconds
Started Apr 25 12:35:55 PM PDT 24
Finished Apr 25 12:35:59 PM PDT 24
Peak memory 195544 kb
Host smart-1d02138f-dd48-460d-83ed-d678a5e2486c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448547647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.1448547647
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1904640627
Short name T1189
Test name
Test status
Simulation time 153462352 ps
CPU time 1.24 seconds
Started Apr 25 12:36:02 PM PDT 24
Finished Apr 25 12:36:06 PM PDT 24
Peak memory 200116 kb
Host smart-ab913c07-1011-4cda-b4db-bf2169359023
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904640627 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.1904640627
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.4289291336
Short name T1235
Test name
Test status
Simulation time 33339486 ps
CPU time 0.55 seconds
Started Apr 25 12:35:59 PM PDT 24
Finished Apr 25 12:36:03 PM PDT 24
Peak memory 195536 kb
Host smart-e60ddde4-f518-46b9-9915-71fae17bc348
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289291336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.4289291336
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.2591755788
Short name T1300
Test name
Test status
Simulation time 13463902 ps
CPU time 0.56 seconds
Started Apr 25 12:35:57 PM PDT 24
Finished Apr 25 12:36:00 PM PDT 24
Peak memory 194592 kb
Host smart-e0f6a864-3f32-46d7-a918-b3d373dbd88d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591755788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.2591755788
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2893124613
Short name T66
Test name
Test status
Simulation time 20729213 ps
CPU time 0.63 seconds
Started Apr 25 12:36:00 PM PDT 24
Finished Apr 25 12:36:03 PM PDT 24
Peak memory 194584 kb
Host smart-7f804e31-ce91-434b-a1c2-484145cacd33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893124613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.2893124613
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.3692950345
Short name T1209
Test name
Test status
Simulation time 348769941 ps
CPU time 2.04 seconds
Started Apr 25 12:35:58 PM PDT 24
Finished Apr 25 12:36:04 PM PDT 24
Peak memory 200144 kb
Host smart-3d934911-8d7c-4d87-828a-1ec50ba8b42e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692950345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.3692950345
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.100467075
Short name T74
Test name
Test status
Simulation time 461921421 ps
CPU time 1.27 seconds
Started Apr 25 12:36:03 PM PDT 24
Finished Apr 25 12:36:08 PM PDT 24
Peak memory 199592 kb
Host smart-374c810a-0864-46b5-82e5-113438283504
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100467075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.100467075
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.2950986145
Short name T1298
Test name
Test status
Simulation time 53141612 ps
CPU time 0.56 seconds
Started Apr 25 12:36:16 PM PDT 24
Finished Apr 25 12:36:18 PM PDT 24
Peak memory 194572 kb
Host smart-4a537597-e2e5-4495-a34e-c98cc64110e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950986145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.2950986145
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.2811849105
Short name T1197
Test name
Test status
Simulation time 14080194 ps
CPU time 0.59 seconds
Started Apr 25 12:36:16 PM PDT 24
Finished Apr 25 12:36:18 PM PDT 24
Peak memory 194612 kb
Host smart-638a3324-1bc7-4458-b6ba-d05444060428
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811849105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.2811849105
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.1027451109
Short name T1305
Test name
Test status
Simulation time 12838158 ps
CPU time 0.62 seconds
Started Apr 25 12:37:23 PM PDT 24
Finished Apr 25 12:37:26 PM PDT 24
Peak memory 192436 kb
Host smart-95ac1ee0-b82b-4833-aed2-07cea1d31870
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027451109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.1027451109
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.2875824079
Short name T1243
Test name
Test status
Simulation time 38178983 ps
CPU time 0.53 seconds
Started Apr 25 12:36:02 PM PDT 24
Finished Apr 25 12:36:06 PM PDT 24
Peak memory 194512 kb
Host smart-618c2bbe-71a5-45d0-926b-b9f99b0a6545
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875824079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.2875824079
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.3772827734
Short name T1213
Test name
Test status
Simulation time 43220511 ps
CPU time 0.55 seconds
Started Apr 25 12:36:06 PM PDT 24
Finished Apr 25 12:36:09 PM PDT 24
Peak memory 194456 kb
Host smart-cf38b0b5-c513-4ae9-b196-85bbca520cec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772827734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.3772827734
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.3497404571
Short name T1200
Test name
Test status
Simulation time 11477724 ps
CPU time 0.55 seconds
Started Apr 25 12:36:13 PM PDT 24
Finished Apr 25 12:36:16 PM PDT 24
Peak memory 194452 kb
Host smart-c8963914-c88d-462a-993f-f740f076ab54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497404571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.3497404571
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.603479569
Short name T1201
Test name
Test status
Simulation time 14199734 ps
CPU time 0.58 seconds
Started Apr 25 12:36:09 PM PDT 24
Finished Apr 25 12:36:12 PM PDT 24
Peak memory 194512 kb
Host smart-82f8d364-f4d4-47c9-808d-5570868c9605
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603479569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.603479569
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.57091928
Short name T1288
Test name
Test status
Simulation time 14033962 ps
CPU time 0.63 seconds
Started Apr 25 12:37:24 PM PDT 24
Finished Apr 25 12:37:26 PM PDT 24
Peak memory 192836 kb
Host smart-a0cc0d9f-b244-4322-bb58-ec73fbd35620
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57091928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.57091928
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.3695805636
Short name T1274
Test name
Test status
Simulation time 22714924 ps
CPU time 0.58 seconds
Started Apr 25 12:36:14 PM PDT 24
Finished Apr 25 12:36:17 PM PDT 24
Peak memory 194548 kb
Host smart-99b0142b-a6c1-4a00-84d1-cb17c3fdbc7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695805636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.3695805636
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.1792557835
Short name T1246
Test name
Test status
Simulation time 235242256 ps
CPU time 0.56 seconds
Started Apr 25 12:36:11 PM PDT 24
Finished Apr 25 12:36:14 PM PDT 24
Peak memory 194508 kb
Host smart-345498d8-2456-4807-b0c3-2e8278278a47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792557835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.1792557835
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3751732362
Short name T1194
Test name
Test status
Simulation time 29101160 ps
CPU time 0.75 seconds
Started Apr 25 12:36:12 PM PDT 24
Finished Apr 25 12:36:15 PM PDT 24
Peak memory 196496 kb
Host smart-3686b752-38f8-498f-9715-1e8a9fb6ebe2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751732362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.3751732362
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1664317560
Short name T1242
Test name
Test status
Simulation time 58367011 ps
CPU time 2.17 seconds
Started Apr 25 12:36:21 PM PDT 24
Finished Apr 25 12:36:25 PM PDT 24
Peak memory 197648 kb
Host smart-e9e014b5-8cf4-407b-af40-cd36f7de2952
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664317560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.1664317560
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.4017036380
Short name T1185
Test name
Test status
Simulation time 16182492 ps
CPU time 0.59 seconds
Started Apr 25 12:35:59 PM PDT 24
Finished Apr 25 12:36:03 PM PDT 24
Peak memory 195600 kb
Host smart-d09c9a84-0c2a-4a6d-b878-b6fc70ee3606
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017036380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.4017036380
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3304863849
Short name T1239
Test name
Test status
Simulation time 42439796 ps
CPU time 0.68 seconds
Started Apr 25 12:36:08 PM PDT 24
Finished Apr 25 12:36:11 PM PDT 24
Peak memory 198968 kb
Host smart-10350b3c-145d-44f5-aef4-f4bf9265cd53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304863849 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.3304863849
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.1285347374
Short name T65
Test name
Test status
Simulation time 12511546 ps
CPU time 0.57 seconds
Started Apr 25 12:36:12 PM PDT 24
Finished Apr 25 12:36:15 PM PDT 24
Peak memory 195592 kb
Host smart-c62a3c31-2878-4293-a1f0-91d0f8260a29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285347374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.1285347374
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.1829402101
Short name T1251
Test name
Test status
Simulation time 12909281 ps
CPU time 0.62 seconds
Started Apr 25 12:36:01 PM PDT 24
Finished Apr 25 12:36:04 PM PDT 24
Peak memory 194504 kb
Host smart-8718b940-134c-496b-87ef-7d29be04247e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829402101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.1829402101
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.1764189201
Short name T1290
Test name
Test status
Simulation time 33337434 ps
CPU time 0.79 seconds
Started Apr 25 12:35:58 PM PDT 24
Finished Apr 25 12:36:02 PM PDT 24
Peak memory 196220 kb
Host smart-c1ec4c1a-6225-4b85-8586-3991a5e21740
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764189201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.1764189201
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.4079109336
Short name T1236
Test name
Test status
Simulation time 19704096 ps
CPU time 1.02 seconds
Started Apr 25 12:36:07 PM PDT 24
Finished Apr 25 12:36:11 PM PDT 24
Peak memory 200028 kb
Host smart-1a153b5d-f39a-4891-ab07-304ab9a4f72c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079109336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.4079109336
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.856331045
Short name T1263
Test name
Test status
Simulation time 373189123 ps
CPU time 1.4 seconds
Started Apr 25 12:36:05 PM PDT 24
Finished Apr 25 12:36:10 PM PDT 24
Peak memory 199492 kb
Host smart-a2403cd5-c3b5-428e-ad17-68a024f2b9ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856331045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.856331045
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.184210459
Short name T1250
Test name
Test status
Simulation time 23796749 ps
CPU time 0.58 seconds
Started Apr 25 12:36:19 PM PDT 24
Finished Apr 25 12:36:21 PM PDT 24
Peak memory 194548 kb
Host smart-150cff29-3992-4673-9fc0-6959988636af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184210459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.184210459
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.1214301114
Short name T1198
Test name
Test status
Simulation time 94152236 ps
CPU time 0.57 seconds
Started Apr 25 12:36:22 PM PDT 24
Finished Apr 25 12:36:24 PM PDT 24
Peak memory 194588 kb
Host smart-e7162fef-e60d-4b83-9a78-89279a57be97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214301114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.1214301114
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.4071213469
Short name T1199
Test name
Test status
Simulation time 14917243 ps
CPU time 0.69 seconds
Started Apr 25 12:37:24 PM PDT 24
Finished Apr 25 12:37:26 PM PDT 24
Peak memory 192344 kb
Host smart-d5b632ab-f690-4afb-a7a5-e987bd4f667e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071213469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.4071213469
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.1044420456
Short name T1245
Test name
Test status
Simulation time 35046354 ps
CPU time 0.57 seconds
Started Apr 25 12:36:27 PM PDT 24
Finished Apr 25 12:36:28 PM PDT 24
Peak memory 194484 kb
Host smart-0540044b-169d-44a0-93d9-2d8be7249ee2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044420456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.1044420456
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.779867580
Short name T1312
Test name
Test status
Simulation time 21320183 ps
CPU time 0.57 seconds
Started Apr 25 12:36:25 PM PDT 24
Finished Apr 25 12:36:26 PM PDT 24
Peak memory 194532 kb
Host smart-223dd295-391a-4eef-a5c1-0ca4a9ad32c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779867580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.779867580
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.1496985177
Short name T1283
Test name
Test status
Simulation time 13212655 ps
CPU time 0.6 seconds
Started Apr 25 12:36:26 PM PDT 24
Finished Apr 25 12:36:28 PM PDT 24
Peak memory 194456 kb
Host smart-6ef73f2c-c6b1-4f07-a5a9-6c5c052f3274
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496985177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.1496985177
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.3372578684
Short name T1204
Test name
Test status
Simulation time 12198748 ps
CPU time 0.57 seconds
Started Apr 25 12:36:20 PM PDT 24
Finished Apr 25 12:36:22 PM PDT 24
Peak memory 194532 kb
Host smart-121edae9-0bcf-4e58-ac72-2cbdfefad367
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372578684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.3372578684
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.3762767909
Short name T1296
Test name
Test status
Simulation time 13185647 ps
CPU time 0.56 seconds
Started Apr 25 12:36:24 PM PDT 24
Finished Apr 25 12:36:26 PM PDT 24
Peak memory 194532 kb
Host smart-9146c218-0e7c-433a-a88a-fde621ab8330
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762767909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.3762767909
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.914636825
Short name T1195
Test name
Test status
Simulation time 14316750 ps
CPU time 0.55 seconds
Started Apr 25 12:36:19 PM PDT 24
Finished Apr 25 12:36:20 PM PDT 24
Peak memory 194532 kb
Host smart-b86238dd-3335-438d-931f-b2725c0879d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914636825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.914636825
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.1297788757
Short name T1310
Test name
Test status
Simulation time 57221412 ps
CPU time 0.58 seconds
Started Apr 25 12:36:21 PM PDT 24
Finished Apr 25 12:36:23 PM PDT 24
Peak memory 194488 kb
Host smart-f08f77b8-862f-4c69-88c0-5cc6d1332d0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297788757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.1297788757
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1833428700
Short name T1206
Test name
Test status
Simulation time 44338264 ps
CPU time 1.08 seconds
Started Apr 25 12:36:08 PM PDT 24
Finished Apr 25 12:36:11 PM PDT 24
Peak memory 200280 kb
Host smart-5e0b41eb-c6e6-460f-80a3-cf1e7f2f9b33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833428700 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.1833428700
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.4246498500
Short name T1226
Test name
Test status
Simulation time 12063413 ps
CPU time 0.63 seconds
Started Apr 25 12:35:55 PM PDT 24
Finished Apr 25 12:35:59 PM PDT 24
Peak memory 195620 kb
Host smart-419fc0d9-5bf4-4970-b09c-eef4cbbae1fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246498500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.4246498500
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.2643084642
Short name T1248
Test name
Test status
Simulation time 14220566 ps
CPU time 0.59 seconds
Started Apr 25 12:36:09 PM PDT 24
Finished Apr 25 12:36:12 PM PDT 24
Peak memory 194548 kb
Host smart-ac77ac33-8cb7-4e0e-9069-0e4937fbd902
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643084642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.2643084642
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.317962694
Short name T1299
Test name
Test status
Simulation time 35426917 ps
CPU time 0.74 seconds
Started Apr 25 12:36:01 PM PDT 24
Finished Apr 25 12:36:05 PM PDT 24
Peak memory 197076 kb
Host smart-3e972f55-fef3-4308-a77b-b9adfa055815
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317962694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_
outstanding.317962694
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.3569323714
Short name T1186
Test name
Test status
Simulation time 37269321 ps
CPU time 1.86 seconds
Started Apr 25 12:36:04 PM PDT 24
Finished Apr 25 12:36:09 PM PDT 24
Peak memory 200184 kb
Host smart-7e4fa6ca-5a01-4da6-b201-1a093f92a5c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569323714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.3569323714
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1528600557
Short name T78
Test name
Test status
Simulation time 48304973 ps
CPU time 0.92 seconds
Started Apr 25 12:36:00 PM PDT 24
Finished Apr 25 12:36:04 PM PDT 24
Peak memory 198988 kb
Host smart-644fccd1-5586-464d-ac5a-32a0a15d3f70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528600557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.1528600557
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1347581929
Short name T1252
Test name
Test status
Simulation time 19589291 ps
CPU time 0.74 seconds
Started Apr 25 12:36:18 PM PDT 24
Finished Apr 25 12:36:19 PM PDT 24
Peak memory 200008 kb
Host smart-62082b7e-f202-43e4-a229-f8cb84eac1a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347581929 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.1347581929
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.910469024
Short name T1286
Test name
Test status
Simulation time 20001496 ps
CPU time 0.57 seconds
Started Apr 25 12:36:04 PM PDT 24
Finished Apr 25 12:36:07 PM PDT 24
Peak memory 195496 kb
Host smart-0158f6c4-f534-4b12-895d-31ff123cbd08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910469024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.910469024
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.1869608270
Short name T1218
Test name
Test status
Simulation time 17381831 ps
CPU time 0.59 seconds
Started Apr 25 12:36:04 PM PDT 24
Finished Apr 25 12:36:07 PM PDT 24
Peak memory 194576 kb
Host smart-0328cb9c-2923-4e2e-9a21-d70bf18a1d4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869608270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.1869608270
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.3138952993
Short name T1279
Test name
Test status
Simulation time 18039561 ps
CPU time 0.77 seconds
Started Apr 25 12:36:11 PM PDT 24
Finished Apr 25 12:36:15 PM PDT 24
Peak memory 197188 kb
Host smart-fd46afab-b4a3-4a9a-8e9f-7e70e10d6bac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138952993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.3138952993
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.2512685471
Short name T1294
Test name
Test status
Simulation time 30221399 ps
CPU time 1.56 seconds
Started Apr 25 12:36:05 PM PDT 24
Finished Apr 25 12:36:09 PM PDT 24
Peak memory 200204 kb
Host smart-5ddfa4f2-4bd9-4df1-a144-03804cebfb03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512685471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.2512685471
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2219160069
Short name T75
Test name
Test status
Simulation time 99479378 ps
CPU time 1.35 seconds
Started Apr 25 12:36:00 PM PDT 24
Finished Apr 25 12:36:04 PM PDT 24
Peak memory 199440 kb
Host smart-257633d5-1d59-4088-a547-55e7b4dbbfcf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219160069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.2219160069
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.486541975
Short name T1208
Test name
Test status
Simulation time 18042422 ps
CPU time 0.84 seconds
Started Apr 25 12:36:03 PM PDT 24
Finished Apr 25 12:36:07 PM PDT 24
Peak memory 200016 kb
Host smart-bf5b66f8-dbc7-4d51-8557-2f44cca80866
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486541975 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.486541975
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.685908998
Short name T1284
Test name
Test status
Simulation time 12337747 ps
CPU time 0.59 seconds
Started Apr 25 12:36:11 PM PDT 24
Finished Apr 25 12:36:14 PM PDT 24
Peak memory 195488 kb
Host smart-a6c2ce4c-576b-464a-911b-01454c1ce69b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685908998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.685908998
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.1283503151
Short name T1256
Test name
Test status
Simulation time 15768014 ps
CPU time 0.55 seconds
Started Apr 25 12:35:59 PM PDT 24
Finished Apr 25 12:36:02 PM PDT 24
Peak memory 194524 kb
Host smart-16acdb6d-68fc-46c0-a55e-c0ef69a332ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283503151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.1283503151
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1797825989
Short name T1220
Test name
Test status
Simulation time 62468345 ps
CPU time 0.73 seconds
Started Apr 25 12:35:58 PM PDT 24
Finished Apr 25 12:36:02 PM PDT 24
Peak memory 197240 kb
Host smart-c2f3d8cd-3aaa-4deb-90d3-6066dfb1eeac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797825989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.1797825989
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.334920707
Short name T1196
Test name
Test status
Simulation time 98829268 ps
CPU time 2.07 seconds
Started Apr 25 12:36:04 PM PDT 24
Finished Apr 25 12:36:09 PM PDT 24
Peak memory 200200 kb
Host smart-34d482ca-cd56-443c-91e8-6d38e4fadfbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334920707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.334920707
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1389546000
Short name T1271
Test name
Test status
Simulation time 335659721 ps
CPU time 0.99 seconds
Started Apr 25 12:36:20 PM PDT 24
Finished Apr 25 12:36:23 PM PDT 24
Peak memory 199188 kb
Host smart-bacda0b7-eed1-47fd-ab8b-4e552a3182c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389546000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1389546000
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1066159569
Short name T1229
Test name
Test status
Simulation time 164848145 ps
CPU time 1.37 seconds
Started Apr 25 12:36:10 PM PDT 24
Finished Apr 25 12:36:14 PM PDT 24
Peak memory 200204 kb
Host smart-ffcc2bb7-78e0-4565-94a1-6cbb11b380de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066159569 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1066159569
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.1526914793
Short name T1262
Test name
Test status
Simulation time 18755471 ps
CPU time 0.62 seconds
Started Apr 25 12:36:19 PM PDT 24
Finished Apr 25 12:36:20 PM PDT 24
Peak memory 195848 kb
Host smart-f407c849-a7b7-45f3-8912-274c3fff9917
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526914793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.1526914793
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.1733351784
Short name T1319
Test name
Test status
Simulation time 71769548 ps
CPU time 0.58 seconds
Started Apr 25 12:36:03 PM PDT 24
Finished Apr 25 12:36:06 PM PDT 24
Peak memory 194524 kb
Host smart-8db3cdc0-5b43-4254-8925-6b37ad67a7ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733351784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.1733351784
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.4038474330
Short name T1289
Test name
Test status
Simulation time 76768446 ps
CPU time 0.66 seconds
Started Apr 25 12:36:07 PM PDT 24
Finished Apr 25 12:36:10 PM PDT 24
Peak memory 195900 kb
Host smart-7a97c342-b9f0-4144-857a-3a666267b4e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038474330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.4038474330
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.984201861
Short name T1320
Test name
Test status
Simulation time 101514826 ps
CPU time 1.91 seconds
Started Apr 25 12:36:10 PM PDT 24
Finished Apr 25 12:36:15 PM PDT 24
Peak memory 200200 kb
Host smart-5029c65b-b9f3-40a8-9f0a-73d1d7da7a6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984201861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.984201861
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1649205235
Short name T1211
Test name
Test status
Simulation time 188550912 ps
CPU time 0.92 seconds
Started Apr 25 12:36:04 PM PDT 24
Finished Apr 25 12:36:08 PM PDT 24
Peak memory 199196 kb
Host smart-594e04dd-ffe9-4dc5-8181-16325f342b23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649205235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.1649205235
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1642140643
Short name T1224
Test name
Test status
Simulation time 60533725 ps
CPU time 0.89 seconds
Started Apr 25 12:36:09 PM PDT 24
Finished Apr 25 12:36:13 PM PDT 24
Peak memory 200028 kb
Host smart-6c078c9c-e8e3-48c3-a8e6-435e2a4fb9aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642140643 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.1642140643
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.2367760241
Short name T1280
Test name
Test status
Simulation time 12257423 ps
CPU time 0.64 seconds
Started Apr 25 12:36:05 PM PDT 24
Finished Apr 25 12:36:08 PM PDT 24
Peak memory 195840 kb
Host smart-3eec772d-722a-442f-97c9-b13cb19d808e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367760241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.2367760241
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.3059307011
Short name T1316
Test name
Test status
Simulation time 12827513 ps
CPU time 0.55 seconds
Started Apr 25 12:36:07 PM PDT 24
Finished Apr 25 12:36:10 PM PDT 24
Peak memory 194496 kb
Host smart-29a04908-481d-4476-a3e8-d6a5e0e8408b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059307011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.3059307011
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.3704483943
Short name T63
Test name
Test status
Simulation time 13018031 ps
CPU time 0.62 seconds
Started Apr 25 12:35:57 PM PDT 24
Finished Apr 25 12:36:01 PM PDT 24
Peak memory 195680 kb
Host smart-dd8d29fa-2d70-43cd-a19b-461f426dac1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704483943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.3704483943
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.1233597674
Short name T1275
Test name
Test status
Simulation time 31361162 ps
CPU time 1.58 seconds
Started Apr 25 12:36:09 PM PDT 24
Finished Apr 25 12:36:13 PM PDT 24
Peak memory 200200 kb
Host smart-dee0d7dc-7560-49f9-95db-8d021c929eec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233597674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1233597674
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2307064281
Short name T79
Test name
Test status
Simulation time 189150033 ps
CPU time 1.35 seconds
Started Apr 25 12:36:06 PM PDT 24
Finished Apr 25 12:36:10 PM PDT 24
Peak memory 199536 kb
Host smart-d9761a5c-2d5b-4561-8584-4e16a4802d6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307064281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.2307064281
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.3685761151
Short name T1126
Test name
Test status
Simulation time 14568860 ps
CPU time 0.54 seconds
Started Apr 25 01:32:37 PM PDT 24
Finished Apr 25 01:32:39 PM PDT 24
Peak memory 195800 kb
Host smart-f943828c-43f6-4a9b-8721-0afe2ae8dfa7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685761151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.3685761151
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.2679973937
Short name T387
Test name
Test status
Simulation time 47391861863 ps
CPU time 77.07 seconds
Started Apr 25 01:32:26 PM PDT 24
Finished Apr 25 01:33:44 PM PDT 24
Peak memory 200288 kb
Host smart-f45e8bb0-c8b8-4c40-878b-0ae48bcb6030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679973937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.2679973937
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.3239669083
Short name T110
Test name
Test status
Simulation time 50810986379 ps
CPU time 90.65 seconds
Started Apr 25 01:32:27 PM PDT 24
Finished Apr 25 01:33:58 PM PDT 24
Peak memory 200440 kb
Host smart-9dae020d-5947-405c-baeb-929a33981b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239669083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.3239669083
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.3429981317
Short name T399
Test name
Test status
Simulation time 110369635346 ps
CPU time 187.9 seconds
Started Apr 25 01:32:27 PM PDT 24
Finished Apr 25 01:35:35 PM PDT 24
Peak memory 200400 kb
Host smart-4d43b55e-86bb-4371-8707-5f208ddde6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429981317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.3429981317
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.3826667513
Short name T408
Test name
Test status
Simulation time 59095307740 ps
CPU time 86.16 seconds
Started Apr 25 01:32:32 PM PDT 24
Finished Apr 25 01:33:59 PM PDT 24
Peak memory 200372 kb
Host smart-11c22c95-82bb-4540-bf7d-b0ad624f2490
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826667513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.3826667513
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_loopback.566087289
Short name T329
Test name
Test status
Simulation time 7613235276 ps
CPU time 7.45 seconds
Started Apr 25 01:32:33 PM PDT 24
Finished Apr 25 01:32:41 PM PDT 24
Peak memory 198712 kb
Host smart-c5b70da2-b3b3-4da7-a3ab-4bef4eecea18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566087289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.566087289
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.2167500087
Short name T404
Test name
Test status
Simulation time 106251214786 ps
CPU time 47.11 seconds
Started Apr 25 01:32:30 PM PDT 24
Finished Apr 25 01:33:18 PM PDT 24
Peak memory 200024 kb
Host smart-fa07e69d-6882-4a22-aa30-73270dfa68be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167500087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.2167500087
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.4085229996
Short name T294
Test name
Test status
Simulation time 20844412254 ps
CPU time 212.03 seconds
Started Apr 25 01:32:31 PM PDT 24
Finished Apr 25 01:36:04 PM PDT 24
Peak memory 200384 kb
Host smart-bf12c1c9-956f-4ac4-b151-8df13538db98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4085229996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.4085229996
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.1670762524
Short name T502
Test name
Test status
Simulation time 7530704845 ps
CPU time 66.84 seconds
Started Apr 25 01:32:31 PM PDT 24
Finished Apr 25 01:33:38 PM PDT 24
Peak memory 198596 kb
Host smart-8f4b79ea-6109-49aa-9c69-3fa2ca1b8247
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1670762524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.1670762524
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.1109280102
Short name T772
Test name
Test status
Simulation time 36035997850 ps
CPU time 32.11 seconds
Started Apr 25 01:32:32 PM PDT 24
Finished Apr 25 01:33:04 PM PDT 24
Peak memory 200384 kb
Host smart-ae4f2ac4-f798-4f88-a868-8501ef06cfbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109280102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.1109280102
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.1756596034
Short name T921
Test name
Test status
Simulation time 3921822912 ps
CPU time 7.06 seconds
Started Apr 25 01:32:31 PM PDT 24
Finished Apr 25 01:32:39 PM PDT 24
Peak memory 196408 kb
Host smart-84d39f50-9543-42df-bd1d-697a255d395e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756596034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.1756596034
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.3856943402
Short name T987
Test name
Test status
Simulation time 500775777 ps
CPU time 2.62 seconds
Started Apr 25 01:32:26 PM PDT 24
Finished Apr 25 01:32:29 PM PDT 24
Peak memory 199892 kb
Host smart-51abbadb-53e6-4970-a92f-951d2a09a777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856943402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.3856943402
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.3562029225
Short name T414
Test name
Test status
Simulation time 10837708224 ps
CPU time 8.31 seconds
Started Apr 25 01:32:31 PM PDT 24
Finished Apr 25 01:32:40 PM PDT 24
Peak memory 200360 kb
Host smart-15ea509c-a2ed-440b-beb9-77b7578ada82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562029225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.3562029225
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.3813378785
Short name T679
Test name
Test status
Simulation time 63363510767 ps
CPU time 45.25 seconds
Started Apr 25 01:32:24 PM PDT 24
Finished Apr 25 01:33:10 PM PDT 24
Peak memory 200412 kb
Host smart-fdfd1057-7441-4f1a-a106-cc39bd312102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813378785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.3813378785
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.1285290289
Short name T947
Test name
Test status
Simulation time 68116715 ps
CPU time 0.55 seconds
Started Apr 25 01:32:53 PM PDT 24
Finished Apr 25 01:32:55 PM PDT 24
Peak memory 195836 kb
Host smart-a2f6d3c2-4ad1-4241-803e-5910577972ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285290289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.1285290289
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.2840760901
Short name T244
Test name
Test status
Simulation time 117901229172 ps
CPU time 53.82 seconds
Started Apr 25 01:32:37 PM PDT 24
Finished Apr 25 01:33:32 PM PDT 24
Peak memory 200520 kb
Host smart-fcb6fed8-9340-49c8-87ef-7ed999b2abfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840760901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.2840760901
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.2117955019
Short name T314
Test name
Test status
Simulation time 108563966367 ps
CPU time 203.33 seconds
Started Apr 25 01:32:37 PM PDT 24
Finished Apr 25 01:36:02 PM PDT 24
Peak memory 200320 kb
Host smart-ab591c4c-e9db-4026-89ce-6765cd5c4292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117955019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.2117955019
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_intr.2278763519
Short name T1132
Test name
Test status
Simulation time 15216639278 ps
CPU time 19.06 seconds
Started Apr 25 01:32:42 PM PDT 24
Finished Apr 25 01:33:01 PM PDT 24
Peak memory 200388 kb
Host smart-59c3fe9e-5d59-43dd-b5f1-c70f3cd40f5a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278763519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.2278763519
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.4131991601
Short name T495
Test name
Test status
Simulation time 167414948523 ps
CPU time 315.64 seconds
Started Apr 25 01:32:52 PM PDT 24
Finished Apr 25 01:38:09 PM PDT 24
Peak memory 200388 kb
Host smart-5ee39836-7488-4617-a00b-cd724badab23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4131991601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.4131991601
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.543196825
Short name T95
Test name
Test status
Simulation time 12426693536 ps
CPU time 10.31 seconds
Started Apr 25 01:32:44 PM PDT 24
Finished Apr 25 01:32:54 PM PDT 24
Peak memory 200436 kb
Host smart-7a7f6e63-c978-40bb-8406-a7ccc321a6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543196825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.543196825
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.1976732861
Short name T318
Test name
Test status
Simulation time 52019395514 ps
CPU time 89.21 seconds
Started Apr 25 01:32:43 PM PDT 24
Finished Apr 25 01:34:12 PM PDT 24
Peak memory 200628 kb
Host smart-78a75463-5636-498f-acf3-756cc3c636c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976732861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.1976732861
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.1642218502
Short name T416
Test name
Test status
Simulation time 3938087019 ps
CPU time 109.94 seconds
Started Apr 25 01:32:54 PM PDT 24
Finished Apr 25 01:34:45 PM PDT 24
Peak memory 200368 kb
Host smart-66061c45-1094-41b7-8e4b-ecdba657a93f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1642218502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.1642218502
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.4177934114
Short name T15
Test name
Test status
Simulation time 5343934228 ps
CPU time 42.83 seconds
Started Apr 25 01:32:43 PM PDT 24
Finished Apr 25 01:33:27 PM PDT 24
Peak memory 200388 kb
Host smart-83a272b8-e6c3-4d96-a7e5-778b3971b7b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4177934114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.4177934114
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.725304489
Short name T752
Test name
Test status
Simulation time 33851222436 ps
CPU time 13.8 seconds
Started Apr 25 01:32:42 PM PDT 24
Finished Apr 25 01:32:56 PM PDT 24
Peak memory 199996 kb
Host smart-8cecdad9-03a4-4dc1-86f9-1d196b2d2c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725304489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.725304489
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.159673810
Short name T557
Test name
Test status
Simulation time 2153506111 ps
CPU time 4.3 seconds
Started Apr 25 01:32:42 PM PDT 24
Finished Apr 25 01:32:47 PM PDT 24
Peak memory 195832 kb
Host smart-4a8aedac-57fb-4399-bc31-61413a396e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159673810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.159673810
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.1217250619
Short name T23
Test name
Test status
Simulation time 39280351 ps
CPU time 0.76 seconds
Started Apr 25 01:32:50 PM PDT 24
Finished Apr 25 01:32:51 PM PDT 24
Peak memory 218436 kb
Host smart-38f2ed10-4817-4563-9482-1befe5968f1a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217250619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.1217250619
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.2091754714
Short name T683
Test name
Test status
Simulation time 105906781 ps
CPU time 0.93 seconds
Started Apr 25 01:32:37 PM PDT 24
Finished Apr 25 01:32:39 PM PDT 24
Peak memory 198312 kb
Host smart-e782e2db-0bb8-446c-bbb9-7686ae6941a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091754714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.2091754714
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.2850066631
Short name T840
Test name
Test status
Simulation time 14791775710 ps
CPU time 511.08 seconds
Started Apr 25 01:32:52 PM PDT 24
Finished Apr 25 01:41:24 PM PDT 24
Peak memory 200364 kb
Host smart-c3946e6e-69ee-4d7f-84dd-43d81326db24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850066631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.2850066631
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.14534228
Short name T392
Test name
Test status
Simulation time 741184211 ps
CPU time 3.37 seconds
Started Apr 25 01:32:44 PM PDT 24
Finished Apr 25 01:32:48 PM PDT 24
Peak memory 199228 kb
Host smart-0cb349b8-d0fe-4084-b7ea-f4dbcd8e194d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14534228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.14534228
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.4142387990
Short name T829
Test name
Test status
Simulation time 31998530176 ps
CPU time 25.73 seconds
Started Apr 25 01:32:37 PM PDT 24
Finished Apr 25 01:33:03 PM PDT 24
Peak memory 200408 kb
Host smart-512b0650-ae11-4871-b7d0-d263552afe46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142387990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.4142387990
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.4243190203
Short name T666
Test name
Test status
Simulation time 33996661 ps
CPU time 0.56 seconds
Started Apr 25 01:34:35 PM PDT 24
Finished Apr 25 01:34:36 PM PDT 24
Peak memory 195808 kb
Host smart-c2434b6d-4792-4a75-bf10-9aebfa872b1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243190203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.4243190203
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.2908005065
Short name T934
Test name
Test status
Simulation time 21215247006 ps
CPU time 19.01 seconds
Started Apr 25 01:34:22 PM PDT 24
Finished Apr 25 01:34:42 PM PDT 24
Peak memory 199548 kb
Host smart-1942ef65-25a3-4bc4-af11-3f7822b88b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908005065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.2908005065
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.4075187077
Short name T608
Test name
Test status
Simulation time 89828857359 ps
CPU time 65.36 seconds
Started Apr 25 01:34:21 PM PDT 24
Finished Apr 25 01:35:27 PM PDT 24
Peak memory 200412 kb
Host smart-cef81528-6f10-4464-99d4-190662f233ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075187077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.4075187077
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.1326355981
Short name T184
Test name
Test status
Simulation time 154366701704 ps
CPU time 240.85 seconds
Started Apr 25 01:34:28 PM PDT 24
Finished Apr 25 01:38:29 PM PDT 24
Peak memory 200420 kb
Host smart-00b24c58-8030-4eb0-a8f4-9537c466147f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326355981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.1326355981
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.2820725393
Short name T874
Test name
Test status
Simulation time 8245059684 ps
CPU time 11.09 seconds
Started Apr 25 01:34:31 PM PDT 24
Finished Apr 25 01:34:42 PM PDT 24
Peak memory 197064 kb
Host smart-8d6d6309-9218-48b0-b0c8-f143af977d59
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820725393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.2820725393
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.79554171
Short name T886
Test name
Test status
Simulation time 106457713015 ps
CPU time 260.56 seconds
Started Apr 25 01:34:27 PM PDT 24
Finished Apr 25 01:38:48 PM PDT 24
Peak memory 200440 kb
Host smart-0a2aad91-5534-4426-9725-997da4a18821
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=79554171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.79554171
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.4200956035
Short name T680
Test name
Test status
Simulation time 2007253325 ps
CPU time 4.55 seconds
Started Apr 25 01:34:29 PM PDT 24
Finished Apr 25 01:34:34 PM PDT 24
Peak memory 199048 kb
Host smart-36d9e08a-c25a-4889-9417-457069fe9671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200956035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.4200956035
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.971647664
Short name T1090
Test name
Test status
Simulation time 47993000933 ps
CPU time 48.1 seconds
Started Apr 25 01:34:26 PM PDT 24
Finished Apr 25 01:35:15 PM PDT 24
Peak memory 200396 kb
Host smart-df6e051e-796e-4423-98ee-2ad8d6212f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971647664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.971647664
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.396716421
Short name T312
Test name
Test status
Simulation time 20594267810 ps
CPU time 520.29 seconds
Started Apr 25 01:34:26 PM PDT 24
Finished Apr 25 01:43:07 PM PDT 24
Peak memory 200436 kb
Host smart-263adfbe-9cb9-4dfc-969c-ded3b70a8814
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=396716421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.396716421
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.2382303740
Short name T330
Test name
Test status
Simulation time 4767384348 ps
CPU time 24.13 seconds
Started Apr 25 01:34:28 PM PDT 24
Finished Apr 25 01:34:53 PM PDT 24
Peak memory 199820 kb
Host smart-1ec9abbe-ae95-4ca8-aa9c-4d06e938bf4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2382303740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.2382303740
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.3241658655
Short name T31
Test name
Test status
Simulation time 202524740934 ps
CPU time 54.56 seconds
Started Apr 25 01:34:28 PM PDT 24
Finished Apr 25 01:35:22 PM PDT 24
Peak memory 200368 kb
Host smart-57b12886-c68f-4532-a1d8-be12fa1657c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241658655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.3241658655
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.1367920893
Short name T1016
Test name
Test status
Simulation time 27466164457 ps
CPU time 10.53 seconds
Started Apr 25 01:34:28 PM PDT 24
Finished Apr 25 01:34:39 PM PDT 24
Peak memory 196720 kb
Host smart-d72d0912-5df4-4781-9d11-9aae2c372169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367920893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.1367920893
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.1383338346
Short name T667
Test name
Test status
Simulation time 5373825119 ps
CPU time 24.89 seconds
Started Apr 25 01:34:22 PM PDT 24
Finished Apr 25 01:34:48 PM PDT 24
Peak memory 199760 kb
Host smart-7cffa2aa-64d7-46bc-8a13-29044a83c253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383338346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.1383338346
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.794493011
Short name T832
Test name
Test status
Simulation time 245679695055 ps
CPU time 241.06 seconds
Started Apr 25 01:34:27 PM PDT 24
Finished Apr 25 01:38:28 PM PDT 24
Peak memory 200328 kb
Host smart-468378f3-ed3e-4ee4-9ec2-b0bd48f6e978
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794493011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.794493011
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.1097430366
Short name T1133
Test name
Test status
Simulation time 24299089703 ps
CPU time 161.07 seconds
Started Apr 25 01:34:27 PM PDT 24
Finished Apr 25 01:37:09 PM PDT 24
Peak memory 216288 kb
Host smart-2ad04fae-e86f-4b7f-959d-26c3d18ce42b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097430366 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.1097430366
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.934426911
Short name T528
Test name
Test status
Simulation time 917133923 ps
CPU time 3.92 seconds
Started Apr 25 01:34:27 PM PDT 24
Finished Apr 25 01:34:31 PM PDT 24
Peak memory 199284 kb
Host smart-f2fdaf47-b72f-4769-9708-cccdb6f8b327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934426911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.934426911
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.4233975049
Short name T954
Test name
Test status
Simulation time 36669831924 ps
CPU time 61.29 seconds
Started Apr 25 01:34:20 PM PDT 24
Finished Apr 25 01:35:22 PM PDT 24
Peak memory 200348 kb
Host smart-50b9b63e-8b2e-42f9-8254-1d8110a17f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233975049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.4233975049
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.2354577665
Short name T1051
Test name
Test status
Simulation time 227383061781 ps
CPU time 91.67 seconds
Started Apr 25 01:40:37 PM PDT 24
Finished Apr 25 01:42:10 PM PDT 24
Peak memory 200316 kb
Host smart-04771bdd-3843-4720-b03d-43d2ec014872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354577665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.2354577665
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.1034665285
Short name T92
Test name
Test status
Simulation time 104638263287 ps
CPU time 92.1 seconds
Started Apr 25 01:40:39 PM PDT 24
Finished Apr 25 01:42:11 PM PDT 24
Peak memory 200340 kb
Host smart-8d188f1b-5347-436a-a29a-2c2d8a65d604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034665285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.1034665285
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.1748898378
Short name T575
Test name
Test status
Simulation time 102045946360 ps
CPU time 37.67 seconds
Started Apr 25 01:40:39 PM PDT 24
Finished Apr 25 01:41:17 PM PDT 24
Peak memory 200452 kb
Host smart-a32d70dc-ddad-4058-b1d4-035e4f7f8cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748898378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.1748898378
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.2921856382
Short name T1177
Test name
Test status
Simulation time 27303281897 ps
CPU time 56.49 seconds
Started Apr 25 01:40:40 PM PDT 24
Finished Apr 25 01:41:37 PM PDT 24
Peak memory 200368 kb
Host smart-0140c189-129f-4066-9bdd-9049353ff9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921856382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.2921856382
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.2798983693
Short name T660
Test name
Test status
Simulation time 115145693983 ps
CPU time 52.86 seconds
Started Apr 25 01:40:38 PM PDT 24
Finished Apr 25 01:41:32 PM PDT 24
Peak memory 200208 kb
Host smart-3c968bc4-da09-468b-af18-b859144362ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798983693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.2798983693
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.1494450290
Short name T1155
Test name
Test status
Simulation time 28962170918 ps
CPU time 42.99 seconds
Started Apr 25 01:40:39 PM PDT 24
Finished Apr 25 01:41:23 PM PDT 24
Peak memory 200300 kb
Host smart-013f42c3-0c96-4c31-99af-9f22c0f1a3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494450290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.1494450290
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.1483521162
Short name T598
Test name
Test status
Simulation time 141114037767 ps
CPU time 106 seconds
Started Apr 25 01:40:45 PM PDT 24
Finished Apr 25 01:42:32 PM PDT 24
Peak memory 200196 kb
Host smart-6bd31c5b-30d1-49d3-a3c3-eb314dfb3da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483521162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1483521162
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.1506698449
Short name T451
Test name
Test status
Simulation time 14840613 ps
CPU time 0.55 seconds
Started Apr 25 01:34:43 PM PDT 24
Finished Apr 25 01:34:45 PM PDT 24
Peak memory 195784 kb
Host smart-89c5fbd4-38a0-412c-9e09-6e9e299b95f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506698449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.1506698449
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.3191927346
Short name T483
Test name
Test status
Simulation time 115267232869 ps
CPU time 51.06 seconds
Started Apr 25 01:34:36 PM PDT 24
Finished Apr 25 01:35:28 PM PDT 24
Peak memory 200460 kb
Host smart-acf2e741-0f8d-4e18-beef-b9a64e37c29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191927346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.3191927346
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.2187747372
Short name T706
Test name
Test status
Simulation time 176133927044 ps
CPU time 321.5 seconds
Started Apr 25 01:34:34 PM PDT 24
Finished Apr 25 01:39:56 PM PDT 24
Peak memory 200396 kb
Host smart-804acb3f-9ff0-4f06-ba0e-f0c42f4369e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187747372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.2187747372
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.3548734601
Short name T34
Test name
Test status
Simulation time 70348100719 ps
CPU time 63.17 seconds
Started Apr 25 01:34:36 PM PDT 24
Finished Apr 25 01:35:40 PM PDT 24
Peak memory 200432 kb
Host smart-783b60aa-128f-4d61-985b-343a76f6b594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548734601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.3548734601
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.3636710458
Short name T893
Test name
Test status
Simulation time 94462397022 ps
CPU time 49.94 seconds
Started Apr 25 01:34:34 PM PDT 24
Finished Apr 25 01:35:25 PM PDT 24
Peak memory 200452 kb
Host smart-9f9fe8b9-f4d7-4a75-820c-cb5f4e2072c5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636710458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.3636710458
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.3294903931
Short name T88
Test name
Test status
Simulation time 306741909258 ps
CPU time 253.8 seconds
Started Apr 25 01:34:34 PM PDT 24
Finished Apr 25 01:38:48 PM PDT 24
Peak memory 200452 kb
Host smart-9a7af4b3-b4f1-4e17-b2f8-69b62324bb4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3294903931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.3294903931
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.4157366513
Short name T534
Test name
Test status
Simulation time 2058499176 ps
CPU time 4.89 seconds
Started Apr 25 01:34:34 PM PDT 24
Finished Apr 25 01:34:40 PM PDT 24
Peak memory 197588 kb
Host smart-cc6805ce-472f-49ef-bb95-a8c44503012b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157366513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.4157366513
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.1310392234
Short name T750
Test name
Test status
Simulation time 23935471012 ps
CPU time 38.36 seconds
Started Apr 25 01:34:32 PM PDT 24
Finished Apr 25 01:35:11 PM PDT 24
Peak memory 199296 kb
Host smart-0daa9a62-d9ce-456b-850f-a742585e205f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310392234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.1310392234
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.2635198824
Short name T435
Test name
Test status
Simulation time 11740104514 ps
CPU time 685.55 seconds
Started Apr 25 01:34:35 PM PDT 24
Finished Apr 25 01:46:01 PM PDT 24
Peak memory 200448 kb
Host smart-d6ba0a08-b4b0-4478-970b-5a942f023fc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2635198824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.2635198824
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.3980736579
Short name T5
Test name
Test status
Simulation time 3667898861 ps
CPU time 13.37 seconds
Started Apr 25 01:34:35 PM PDT 24
Finished Apr 25 01:34:49 PM PDT 24
Peak memory 200312 kb
Host smart-c281eff3-d7cd-4885-bb17-d3c7eb63e9c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3980736579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.3980736579
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.1482205198
Short name T664
Test name
Test status
Simulation time 27435159755 ps
CPU time 31.4 seconds
Started Apr 25 01:34:35 PM PDT 24
Finished Apr 25 01:35:07 PM PDT 24
Peak memory 200396 kb
Host smart-65213022-41af-47ef-a867-63f83c4c3ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482205198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.1482205198
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.4281380879
Short name T849
Test name
Test status
Simulation time 691483437 ps
CPU time 0.86 seconds
Started Apr 25 01:34:40 PM PDT 24
Finished Apr 25 01:34:42 PM PDT 24
Peak memory 195796 kb
Host smart-7648d963-ead2-4ee6-9271-eb9623779fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281380879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.4281380879
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.94479785
Short name T760
Test name
Test status
Simulation time 686609086 ps
CPU time 2.59 seconds
Started Apr 25 01:34:43 PM PDT 24
Finished Apr 25 01:34:46 PM PDT 24
Peak memory 199484 kb
Host smart-e7504b3f-2a08-4093-895a-a26d0b795efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94479785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.94479785
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.1153562216
Short name T14
Test name
Test status
Simulation time 12931461934 ps
CPU time 65.15 seconds
Started Apr 25 01:34:36 PM PDT 24
Finished Apr 25 01:35:42 PM PDT 24
Peak memory 208692 kb
Host smart-6e5fff69-ae3d-4fb3-9bd1-60de76de19b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153562216 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.1153562216
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.3024863666
Short name T335
Test name
Test status
Simulation time 2604600939 ps
CPU time 2.67 seconds
Started Apr 25 01:34:34 PM PDT 24
Finished Apr 25 01:34:38 PM PDT 24
Peak memory 198956 kb
Host smart-db782004-2103-449b-9c72-b3ded9ca7610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024863666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.3024863666
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.3869704782
Short name T1054
Test name
Test status
Simulation time 67363319305 ps
CPU time 94.95 seconds
Started Apr 25 01:34:34 PM PDT 24
Finished Apr 25 01:36:10 PM PDT 24
Peak memory 200412 kb
Host smart-0beda395-9b71-440d-b302-bd65b69d7a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869704782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.3869704782
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.1867574318
Short name T364
Test name
Test status
Simulation time 105064916157 ps
CPU time 89.67 seconds
Started Apr 25 01:40:45 PM PDT 24
Finished Apr 25 01:42:16 PM PDT 24
Peak memory 200332 kb
Host smart-d97a970e-6309-4374-8e78-73bd77b20690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867574318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1867574318
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.1603483312
Short name T266
Test name
Test status
Simulation time 19046109359 ps
CPU time 12.77 seconds
Started Apr 25 01:40:51 PM PDT 24
Finished Apr 25 01:41:05 PM PDT 24
Peak memory 200372 kb
Host smart-0250383d-b0b4-4124-9699-f7797f7a4e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603483312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.1603483312
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.971538563
Short name T735
Test name
Test status
Simulation time 25078990955 ps
CPU time 43.72 seconds
Started Apr 25 01:40:53 PM PDT 24
Finished Apr 25 01:41:38 PM PDT 24
Peak memory 200452 kb
Host smart-49fd5627-b6cb-4d01-beaf-8cb0b44e051f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971538563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.971538563
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.1302520790
Short name T1127
Test name
Test status
Simulation time 14404731937 ps
CPU time 17.41 seconds
Started Apr 25 01:40:51 PM PDT 24
Finished Apr 25 01:41:09 PM PDT 24
Peak memory 200420 kb
Host smart-dbce5b43-fdd6-49bd-aace-fa18b8da9284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302520790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.1302520790
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.719032657
Short name T503
Test name
Test status
Simulation time 245683146824 ps
CPU time 42.28 seconds
Started Apr 25 01:40:51 PM PDT 24
Finished Apr 25 01:41:34 PM PDT 24
Peak memory 200420 kb
Host smart-6cdae6d5-aba3-476a-a70f-6b1f63a39475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719032657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.719032657
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.3492149819
Short name T315
Test name
Test status
Simulation time 21939693646 ps
CPU time 16.96 seconds
Started Apr 25 01:40:52 PM PDT 24
Finished Apr 25 01:41:10 PM PDT 24
Peak memory 200360 kb
Host smart-eb3739a8-a3fe-4e78-aca5-aca91dd71da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492149819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.3492149819
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.259594289
Short name T30
Test name
Test status
Simulation time 107600020165 ps
CPU time 121.9 seconds
Started Apr 25 01:40:52 PM PDT 24
Finished Apr 25 01:42:55 PM PDT 24
Peak memory 200416 kb
Host smart-50257717-0077-472b-be2c-4f8bae3074ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259594289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.259594289
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.1981885829
Short name T325
Test name
Test status
Simulation time 53693502452 ps
CPU time 91.4 seconds
Started Apr 25 01:40:51 PM PDT 24
Finished Apr 25 01:42:23 PM PDT 24
Peak memory 200368 kb
Host smart-80c401be-57e1-4e35-94d3-bec6dac2a662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981885829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.1981885829
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.3099953043
Short name T1061
Test name
Test status
Simulation time 13615851 ps
CPU time 0.56 seconds
Started Apr 25 01:34:47 PM PDT 24
Finished Apr 25 01:34:49 PM PDT 24
Peak memory 195788 kb
Host smart-2b6a0ded-c16b-498e-8941-f158ed59d6ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099953043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.3099953043
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.1130965661
Short name T618
Test name
Test status
Simulation time 82509752022 ps
CPU time 130.95 seconds
Started Apr 25 01:34:43 PM PDT 24
Finished Apr 25 01:36:55 PM PDT 24
Peak memory 200336 kb
Host smart-514f96c5-8b23-4229-840a-e46201418430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130965661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.1130965661
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.3250238187
Short name T970
Test name
Test status
Simulation time 67029762882 ps
CPU time 99.94 seconds
Started Apr 25 01:34:41 PM PDT 24
Finished Apr 25 01:36:21 PM PDT 24
Peak memory 199976 kb
Host smart-1a8a685d-2fac-4aa0-9b25-2a057cd2b584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250238187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.3250238187
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.3423553310
Short name T848
Test name
Test status
Simulation time 14527726619 ps
CPU time 32.77 seconds
Started Apr 25 01:34:40 PM PDT 24
Finished Apr 25 01:35:14 PM PDT 24
Peak memory 200428 kb
Host smart-ccf1afe0-3bd4-440b-8923-aa6b9bedc804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423553310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.3423553310
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.1011580198
Short name T36
Test name
Test status
Simulation time 26593125523 ps
CPU time 5.36 seconds
Started Apr 25 01:34:41 PM PDT 24
Finished Apr 25 01:34:48 PM PDT 24
Peak memory 198828 kb
Host smart-6e9016be-26f0-4b8d-b856-0b2296217223
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011580198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.1011580198
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.2279686054
Short name T436
Test name
Test status
Simulation time 116667424550 ps
CPU time 257.82 seconds
Started Apr 25 01:34:45 PM PDT 24
Finished Apr 25 01:39:04 PM PDT 24
Peak memory 200476 kb
Host smart-20cd8915-80c1-49ec-8413-8020c0fe6131
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2279686054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.2279686054
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.4147580711
Short name T488
Test name
Test status
Simulation time 10336695963 ps
CPU time 6.97 seconds
Started Apr 25 01:34:42 PM PDT 24
Finished Apr 25 01:34:50 PM PDT 24
Peak memory 199624 kb
Host smart-25da03b9-15c1-4e60-aa14-bb994d42b266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147580711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.4147580711
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.3578973658
Short name T412
Test name
Test status
Simulation time 5301075069 ps
CPU time 9.55 seconds
Started Apr 25 01:34:48 PM PDT 24
Finished Apr 25 01:34:59 PM PDT 24
Peak memory 198632 kb
Host smart-40e1d4da-c1e3-42ca-9670-2b8303cdc977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578973658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.3578973658
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.1831777995
Short name T433
Test name
Test status
Simulation time 8303060896 ps
CPU time 27.45 seconds
Started Apr 25 01:34:48 PM PDT 24
Finished Apr 25 01:35:17 PM PDT 24
Peak memory 200352 kb
Host smart-27be1a37-2dfd-43f5-9828-209bb73cdb0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1831777995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.1831777995
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.1149536948
Short name T824
Test name
Test status
Simulation time 4326800385 ps
CPU time 9.53 seconds
Started Apr 25 01:34:42 PM PDT 24
Finished Apr 25 01:34:52 PM PDT 24
Peak memory 199220 kb
Host smart-50096352-973e-4d61-ad08-ee6346e985ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1149536948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.1149536948
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.1994258009
Short name T577
Test name
Test status
Simulation time 25280774495 ps
CPU time 36.76 seconds
Started Apr 25 01:34:41 PM PDT 24
Finished Apr 25 01:35:19 PM PDT 24
Peak memory 199916 kb
Host smart-9ec4aee5-7305-4d89-b6a7-59e4271e74f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994258009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.1994258009
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.369836732
Short name T403
Test name
Test status
Simulation time 34605640641 ps
CPU time 13.99 seconds
Started Apr 25 01:34:44 PM PDT 24
Finished Apr 25 01:34:58 PM PDT 24
Peak memory 196152 kb
Host smart-9223ae3e-9a86-46d8-8eae-f10f31e74ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369836732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.369836732
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.4196280294
Short name T512
Test name
Test status
Simulation time 5587370201 ps
CPU time 7.92 seconds
Started Apr 25 01:34:40 PM PDT 24
Finished Apr 25 01:34:49 PM PDT 24
Peak memory 200228 kb
Host smart-968df495-33da-4412-9cc2-4316caa59379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196280294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.4196280294
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.2582082960
Short name T187
Test name
Test status
Simulation time 295588292413 ps
CPU time 88.76 seconds
Started Apr 25 01:34:49 PM PDT 24
Finished Apr 25 01:36:19 PM PDT 24
Peak memory 200412 kb
Host smart-64ce4540-710a-4148-a442-14172f26dca9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582082960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.2582082960
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.2638974943
Short name T917
Test name
Test status
Simulation time 148044798706 ps
CPU time 930.66 seconds
Started Apr 25 01:34:47 PM PDT 24
Finished Apr 25 01:50:19 PM PDT 24
Peak memory 217096 kb
Host smart-a6d95d61-8022-4d23-b7d3-dd65c81e57ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638974943 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.2638974943
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.2329637119
Short name T373
Test name
Test status
Simulation time 2558805626 ps
CPU time 2.41 seconds
Started Apr 25 01:34:42 PM PDT 24
Finished Apr 25 01:34:45 PM PDT 24
Peak memory 198924 kb
Host smart-1a4bc539-f6f8-45e2-99f0-022a5263d07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329637119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.2329637119
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.1891344599
Short name T958
Test name
Test status
Simulation time 17990522112 ps
CPU time 33.29 seconds
Started Apr 25 01:34:41 PM PDT 24
Finished Apr 25 01:35:16 PM PDT 24
Peak memory 200436 kb
Host smart-f27bf3a6-9695-4617-8879-57e4b5c5876c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891344599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.1891344599
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.3847596879
Short name T378
Test name
Test status
Simulation time 14072543748 ps
CPU time 23.7 seconds
Started Apr 25 01:40:52 PM PDT 24
Finished Apr 25 01:41:16 PM PDT 24
Peak memory 199972 kb
Host smart-f5251374-6b1d-4b28-b898-30641d7a6889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847596879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.3847596879
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.2495958054
Short name T994
Test name
Test status
Simulation time 115326073434 ps
CPU time 56.87 seconds
Started Apr 25 01:40:58 PM PDT 24
Finished Apr 25 01:41:56 PM PDT 24
Peak memory 200404 kb
Host smart-5fc5c86c-5d19-4157-baf7-80dfdaae1c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495958054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.2495958054
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.3545211036
Short name T119
Test name
Test status
Simulation time 71709179566 ps
CPU time 102.24 seconds
Started Apr 25 01:40:52 PM PDT 24
Finished Apr 25 01:42:35 PM PDT 24
Peak memory 200428 kb
Host smart-fb3481c2-804b-4798-b0ce-4427ace8cc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545211036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.3545211036
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.361732896
Short name T568
Test name
Test status
Simulation time 105949485054 ps
CPU time 157.81 seconds
Started Apr 25 01:40:50 PM PDT 24
Finished Apr 25 01:43:28 PM PDT 24
Peak memory 200364 kb
Host smart-1a21b0b9-d72b-410e-9d36-9a0112c68f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361732896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.361732896
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.212863262
Short name T1112
Test name
Test status
Simulation time 63211995337 ps
CPU time 132.47 seconds
Started Apr 25 01:40:51 PM PDT 24
Finished Apr 25 01:43:05 PM PDT 24
Peak memory 200440 kb
Host smart-af46f685-260a-4799-a830-3027155e8745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212863262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.212863262
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.1382325343
Short name T176
Test name
Test status
Simulation time 95979692611 ps
CPU time 141.09 seconds
Started Apr 25 01:41:00 PM PDT 24
Finished Apr 25 01:43:22 PM PDT 24
Peak memory 200340 kb
Host smart-e63b39f6-096d-45b2-8dfa-ca6b8b0599d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382325343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.1382325343
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.4086385923
Short name T603
Test name
Test status
Simulation time 8807241379 ps
CPU time 16.53 seconds
Started Apr 25 01:40:57 PM PDT 24
Finished Apr 25 01:41:14 PM PDT 24
Peak memory 200200 kb
Host smart-697dfa05-f171-4609-a2b1-d44a241c12ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086385923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.4086385923
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.1420904318
Short name T1019
Test name
Test status
Simulation time 165623289176 ps
CPU time 153.74 seconds
Started Apr 25 01:40:58 PM PDT 24
Finished Apr 25 01:43:32 PM PDT 24
Peak memory 200424 kb
Host smart-c05ede35-18d4-4ff2-9a33-737827025487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420904318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.1420904318
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.3854864991
Short name T522
Test name
Test status
Simulation time 104605010820 ps
CPU time 196.4 seconds
Started Apr 25 01:40:58 PM PDT 24
Finished Apr 25 01:44:15 PM PDT 24
Peak memory 200428 kb
Host smart-9272d7a8-1aaf-4ad4-8501-3f83b27db1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854864991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3854864991
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.2520521413
Short name T453
Test name
Test status
Simulation time 55843884092 ps
CPU time 102.72 seconds
Started Apr 25 01:40:59 PM PDT 24
Finished Apr 25 01:42:43 PM PDT 24
Peak memory 200368 kb
Host smart-bc0c97d9-4e34-4599-8556-db0f909f65c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520521413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2520521413
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.1287315215
Short name T624
Test name
Test status
Simulation time 15879732 ps
CPU time 0.56 seconds
Started Apr 25 01:34:56 PM PDT 24
Finished Apr 25 01:34:57 PM PDT 24
Peak memory 195792 kb
Host smart-a877fd12-7fcf-4c59-8aeb-84b09e2032ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287315215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.1287315215
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.846324617
Short name T247
Test name
Test status
Simulation time 244854539046 ps
CPU time 70.06 seconds
Started Apr 25 01:34:48 PM PDT 24
Finished Apr 25 01:35:59 PM PDT 24
Peak memory 200456 kb
Host smart-0268d5ad-de1c-4161-b731-e1279231389a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846324617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.846324617
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.2932336936
Short name T400
Test name
Test status
Simulation time 69304298396 ps
CPU time 32.2 seconds
Started Apr 25 01:34:46 PM PDT 24
Finished Apr 25 01:35:19 PM PDT 24
Peak memory 200332 kb
Host smart-3ad060c9-45ad-41e5-bda0-747bcc075718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932336936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2932336936
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.1554035024
Short name T165
Test name
Test status
Simulation time 71314930068 ps
CPU time 68.72 seconds
Started Apr 25 01:34:49 PM PDT 24
Finished Apr 25 01:35:59 PM PDT 24
Peak memory 200368 kb
Host smart-15cce140-b368-4e25-8bf8-31f1748c1179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554035024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.1554035024
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.2233708244
Short name T933
Test name
Test status
Simulation time 31557850324 ps
CPU time 59.58 seconds
Started Apr 25 01:34:48 PM PDT 24
Finished Apr 25 01:35:48 PM PDT 24
Peak memory 200288 kb
Host smart-e29f442a-c463-4c15-b9b3-446250160251
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233708244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2233708244
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.286083830
Short name T510
Test name
Test status
Simulation time 131720439747 ps
CPU time 440.51 seconds
Started Apr 25 01:34:56 PM PDT 24
Finished Apr 25 01:42:17 PM PDT 24
Peak memory 200424 kb
Host smart-7d370ef2-84f3-4222-b16b-7e2b8c2aac76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=286083830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.286083830
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.19279137
Short name T607
Test name
Test status
Simulation time 14344623653 ps
CPU time 7.29 seconds
Started Apr 25 01:34:54 PM PDT 24
Finished Apr 25 01:35:03 PM PDT 24
Peak memory 200312 kb
Host smart-91bcb8e8-2eb5-491e-b23f-ee607da805d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19279137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.19279137
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.1434843236
Short name T803
Test name
Test status
Simulation time 92974543089 ps
CPU time 157.51 seconds
Started Apr 25 01:34:56 PM PDT 24
Finished Apr 25 01:37:34 PM PDT 24
Peak memory 200568 kb
Host smart-742d0919-48ac-47fa-92e4-ac1326281089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434843236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.1434843236
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.100377750
Short name T1096
Test name
Test status
Simulation time 9214540275 ps
CPU time 580.69 seconds
Started Apr 25 01:34:56 PM PDT 24
Finished Apr 25 01:44:37 PM PDT 24
Peak memory 200460 kb
Host smart-28209bdc-6018-44f3-8618-4384071a5e16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=100377750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.100377750
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.833592962
Short name T668
Test name
Test status
Simulation time 1584629754 ps
CPU time 6.2 seconds
Started Apr 25 01:34:46 PM PDT 24
Finished Apr 25 01:34:53 PM PDT 24
Peak memory 197196 kb
Host smart-3b32322d-1aff-4f0d-a83c-6a1fb11a3e7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=833592962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.833592962
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.3810967089
Short name T708
Test name
Test status
Simulation time 86117258282 ps
CPU time 55.29 seconds
Started Apr 25 01:34:55 PM PDT 24
Finished Apr 25 01:35:52 PM PDT 24
Peak memory 200404 kb
Host smart-19bf454b-a1c4-4e1e-9a39-6fd2a90e3224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810967089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.3810967089
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.3028700556
Short name T780
Test name
Test status
Simulation time 35284968257 ps
CPU time 13.49 seconds
Started Apr 25 01:34:55 PM PDT 24
Finished Apr 25 01:35:09 PM PDT 24
Peak memory 196404 kb
Host smart-c2519d49-fedc-4db3-b313-fdd609083e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028700556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.3028700556
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.1796048294
Short name T395
Test name
Test status
Simulation time 939763237 ps
CPU time 2.64 seconds
Started Apr 25 01:34:47 PM PDT 24
Finished Apr 25 01:34:51 PM PDT 24
Peak memory 200140 kb
Host smart-4f2e4536-0c4b-43e3-beda-8865ab43c4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796048294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.1796048294
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.2892178692
Short name T738
Test name
Test status
Simulation time 356906553958 ps
CPU time 1011.78 seconds
Started Apr 25 01:34:56 PM PDT 24
Finished Apr 25 01:51:49 PM PDT 24
Peak memory 200380 kb
Host smart-25db48c4-d03f-4c82-9893-293b451045bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892178692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.2892178692
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.1854434473
Short name T960
Test name
Test status
Simulation time 104953533905 ps
CPU time 325.74 seconds
Started Apr 25 01:34:54 PM PDT 24
Finished Apr 25 01:40:21 PM PDT 24
Peak memory 217024 kb
Host smart-0658a8dc-b5fd-46c4-9880-82f854afdf6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854434473 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.1854434473
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.2408792988
Short name T1149
Test name
Test status
Simulation time 486808318 ps
CPU time 1.18 seconds
Started Apr 25 01:34:55 PM PDT 24
Finished Apr 25 01:34:57 PM PDT 24
Peak memory 197340 kb
Host smart-5ee966fb-d70a-4475-a29d-16dd730385f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408792988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.2408792988
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.1094218888
Short name T368
Test name
Test status
Simulation time 41619670709 ps
CPU time 67.81 seconds
Started Apr 25 01:34:48 PM PDT 24
Finished Apr 25 01:35:57 PM PDT 24
Peak memory 200448 kb
Host smart-352aebfa-2de3-47d4-9026-251f776a0aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094218888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.1094218888
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.119967300
Short name T622
Test name
Test status
Simulation time 62912296281 ps
CPU time 52.11 seconds
Started Apr 25 01:40:56 PM PDT 24
Finished Apr 25 01:41:48 PM PDT 24
Peak memory 200372 kb
Host smart-093f4875-b6bf-4661-bef6-ac549b6674e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119967300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.119967300
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.3404033826
Short name T644
Test name
Test status
Simulation time 13090343980 ps
CPU time 22.54 seconds
Started Apr 25 01:40:57 PM PDT 24
Finished Apr 25 01:41:20 PM PDT 24
Peak memory 200200 kb
Host smart-cbb51aa1-6c56-488e-a9ae-314c37970c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404033826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.3404033826
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.1223767922
Short name T112
Test name
Test status
Simulation time 25073907616 ps
CPU time 45.3 seconds
Started Apr 25 01:41:07 PM PDT 24
Finished Apr 25 01:41:53 PM PDT 24
Peak memory 200392 kb
Host smart-1d33a76c-ced2-4497-bb33-f7d3d54706a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223767922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.1223767922
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.3183667800
Short name T563
Test name
Test status
Simulation time 207502078822 ps
CPU time 105.41 seconds
Started Apr 25 01:41:04 PM PDT 24
Finished Apr 25 01:42:50 PM PDT 24
Peak memory 200428 kb
Host smart-2833cfb6-92c0-4de3-80ce-e6ccd43762ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183667800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.3183667800
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.4108503137
Short name T716
Test name
Test status
Simulation time 173730933640 ps
CPU time 142.1 seconds
Started Apr 25 01:41:04 PM PDT 24
Finished Apr 25 01:43:27 PM PDT 24
Peak memory 200420 kb
Host smart-a3ae9ba2-1b25-43ed-85aa-f843e16e0d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108503137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.4108503137
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.38879816
Short name T1036
Test name
Test status
Simulation time 60518039553 ps
CPU time 28.69 seconds
Started Apr 25 01:41:05 PM PDT 24
Finished Apr 25 01:41:34 PM PDT 24
Peak memory 200348 kb
Host smart-6adee126-d67c-41c4-a763-abe9a453b604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38879816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.38879816
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.4251304019
Short name T925
Test name
Test status
Simulation time 177519637788 ps
CPU time 124.93 seconds
Started Apr 25 01:41:03 PM PDT 24
Finished Apr 25 01:43:09 PM PDT 24
Peak memory 200420 kb
Host smart-8343da3a-7f0b-400d-b3c3-020b5fa82749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251304019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.4251304019
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.2360933297
Short name T33
Test name
Test status
Simulation time 22045081337 ps
CPU time 23.28 seconds
Started Apr 25 01:41:02 PM PDT 24
Finished Apr 25 01:41:26 PM PDT 24
Peak memory 200456 kb
Host smart-3a9cc7a1-9998-4f99-987e-acadcf1bceca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360933297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.2360933297
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.1396197256
Short name T190
Test name
Test status
Simulation time 122967724564 ps
CPU time 213.62 seconds
Started Apr 25 01:41:05 PM PDT 24
Finished Apr 25 01:44:40 PM PDT 24
Peak memory 200368 kb
Host smart-1805520e-dc6b-454d-9f44-3ff52756cce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396197256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.1396197256
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.4137431075
Short name T429
Test name
Test status
Simulation time 14294601 ps
CPU time 0.57 seconds
Started Apr 25 01:35:06 PM PDT 24
Finished Apr 25 01:35:07 PM PDT 24
Peak memory 195816 kb
Host smart-d1d33b83-fa0f-4e3e-a7af-49dd4946fe1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137431075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.4137431075
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.2142860933
Short name T847
Test name
Test status
Simulation time 41155185807 ps
CPU time 68.11 seconds
Started Apr 25 01:35:01 PM PDT 24
Finished Apr 25 01:36:10 PM PDT 24
Peak memory 200408 kb
Host smart-5450a07a-0594-4f1f-ab5e-eb0676521f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142860933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.2142860933
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.1337545926
Short name T1154
Test name
Test status
Simulation time 151503429506 ps
CPU time 147.96 seconds
Started Apr 25 01:35:01 PM PDT 24
Finished Apr 25 01:37:30 PM PDT 24
Peak memory 200324 kb
Host smart-ee86bc57-4789-484c-90be-d77877f007c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337545926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.1337545926
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.7792658
Short name T977
Test name
Test status
Simulation time 93605141763 ps
CPU time 39.37 seconds
Started Apr 25 01:34:59 PM PDT 24
Finished Apr 25 01:35:39 PM PDT 24
Peak memory 200332 kb
Host smart-d8ae8cc9-6b98-4762-8971-28b4a988cd54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7792658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.7792658
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.3998065761
Short name T1027
Test name
Test status
Simulation time 70963971117 ps
CPU time 128.45 seconds
Started Apr 25 01:35:01 PM PDT 24
Finished Apr 25 01:37:09 PM PDT 24
Peak memory 200332 kb
Host smart-852dbf64-f4f4-4161-9ae1-ee49254e9c29
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998065761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.3998065761
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.705098676
Short name T471
Test name
Test status
Simulation time 55972368786 ps
CPU time 395.28 seconds
Started Apr 25 01:35:07 PM PDT 24
Finished Apr 25 01:41:43 PM PDT 24
Peak memory 200388 kb
Host smart-35a24739-8ec0-4d3f-8f80-ccf82eaa7175
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=705098676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.705098676
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.1584904607
Short name T332
Test name
Test status
Simulation time 7458140360 ps
CPU time 14.45 seconds
Started Apr 25 01:35:01 PM PDT 24
Finished Apr 25 01:35:16 PM PDT 24
Peak memory 199960 kb
Host smart-ac518eed-2a3f-4867-b76f-956d139931bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584904607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.1584904607
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.3111195835
Short name T1026
Test name
Test status
Simulation time 17131499736 ps
CPU time 33.17 seconds
Started Apr 25 01:35:02 PM PDT 24
Finished Apr 25 01:35:36 PM PDT 24
Peak memory 199344 kb
Host smart-334d97f7-1916-45d1-b8a5-ecd78a38e909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111195835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.3111195835
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.1553408990
Short name T914
Test name
Test status
Simulation time 15880316948 ps
CPU time 232.66 seconds
Started Apr 25 01:35:02 PM PDT 24
Finished Apr 25 01:38:55 PM PDT 24
Peak memory 200372 kb
Host smart-c1de190a-8ce2-4bfa-b4c0-99124aa41f35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1553408990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.1553408990
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.4226632974
Short name T1157
Test name
Test status
Simulation time 6219801771 ps
CPU time 59.92 seconds
Started Apr 25 01:35:02 PM PDT 24
Finished Apr 25 01:36:02 PM PDT 24
Peak memory 199600 kb
Host smart-e33ae513-757d-4ebe-bd60-e5028cf95929
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4226632974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.4226632974
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.699421616
Short name T774
Test name
Test status
Simulation time 14769003523 ps
CPU time 10.97 seconds
Started Apr 25 01:35:01 PM PDT 24
Finished Apr 25 01:35:12 PM PDT 24
Peak memory 200388 kb
Host smart-7a507ed9-5ef9-4fcb-9ac2-99ec6258bffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699421616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.699421616
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.3962896188
Short name T1097
Test name
Test status
Simulation time 4774738392 ps
CPU time 2.39 seconds
Started Apr 25 01:35:02 PM PDT 24
Finished Apr 25 01:35:05 PM PDT 24
Peak memory 196444 kb
Host smart-342b104d-e65b-4770-9150-db43aa8a0d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962896188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.3962896188
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.4074825379
Short name T853
Test name
Test status
Simulation time 273224036 ps
CPU time 1.43 seconds
Started Apr 25 01:34:55 PM PDT 24
Finished Apr 25 01:34:57 PM PDT 24
Peak memory 198644 kb
Host smart-a0061c62-3128-479b-a151-7e62df014122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074825379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.4074825379
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.1854272417
Short name T654
Test name
Test status
Simulation time 13998998521 ps
CPU time 291.27 seconds
Started Apr 25 01:35:08 PM PDT 24
Finished Apr 25 01:40:00 PM PDT 24
Peak memory 200432 kb
Host smart-84566ca9-ad7e-431f-be1b-191bf43089a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854272417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.1854272417
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.1857949265
Short name T799
Test name
Test status
Simulation time 296599244035 ps
CPU time 938.99 seconds
Started Apr 25 01:35:11 PM PDT 24
Finished Apr 25 01:50:50 PM PDT 24
Peak memory 224992 kb
Host smart-1151e847-c9e4-4f4c-9219-d7a779be2cf5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857949265 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.1857949265
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.1806550798
Short name T347
Test name
Test status
Simulation time 975821421 ps
CPU time 3 seconds
Started Apr 25 01:35:02 PM PDT 24
Finished Apr 25 01:35:06 PM PDT 24
Peak memory 198844 kb
Host smart-637d0ab7-4d03-4d75-84e7-65a400095394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806550798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.1806550798
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.2798155434
Short name T263
Test name
Test status
Simulation time 68295679567 ps
CPU time 188.04 seconds
Started Apr 25 01:35:02 PM PDT 24
Finished Apr 25 01:38:11 PM PDT 24
Peak memory 200372 kb
Host smart-71478baf-b88d-425e-b664-a0b2e609d0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798155434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.2798155434
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.3302469533
Short name T425
Test name
Test status
Simulation time 191316305421 ps
CPU time 34.28 seconds
Started Apr 25 01:41:07 PM PDT 24
Finished Apr 25 01:41:42 PM PDT 24
Peak memory 200368 kb
Host smart-5658a616-70f9-4ded-8663-a215af7df8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302469533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.3302469533
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.965121158
Short name T782
Test name
Test status
Simulation time 102343196404 ps
CPU time 182.1 seconds
Started Apr 25 01:41:03 PM PDT 24
Finished Apr 25 01:44:06 PM PDT 24
Peak memory 200348 kb
Host smart-6dcab6d7-08a4-471d-98fb-55c2a4ad335c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965121158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.965121158
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.3992099853
Short name T844
Test name
Test status
Simulation time 182042099018 ps
CPU time 74.41 seconds
Started Apr 25 01:41:06 PM PDT 24
Finished Apr 25 01:42:21 PM PDT 24
Peak memory 200364 kb
Host smart-f99d2177-e974-4290-870e-6bc9207f743b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992099853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3992099853
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.3829978426
Short name T717
Test name
Test status
Simulation time 52477653838 ps
CPU time 31.43 seconds
Started Apr 25 01:41:10 PM PDT 24
Finished Apr 25 01:41:42 PM PDT 24
Peak memory 200404 kb
Host smart-c43e9cc0-517f-4a34-9994-dfc1c9ed798b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829978426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.3829978426
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.1076378889
Short name T195
Test name
Test status
Simulation time 20246153220 ps
CPU time 37.22 seconds
Started Apr 25 01:41:09 PM PDT 24
Finished Apr 25 01:41:47 PM PDT 24
Peak memory 200300 kb
Host smart-8072e37d-4600-473c-8ddd-c322b98a510a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076378889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.1076378889
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.3693626423
Short name T817
Test name
Test status
Simulation time 61860116548 ps
CPU time 26.04 seconds
Started Apr 25 01:41:09 PM PDT 24
Finished Apr 25 01:41:35 PM PDT 24
Peak memory 200444 kb
Host smart-91a01032-6ce7-4e9f-afbb-156735649732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693626423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.3693626423
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.2688647589
Short name T612
Test name
Test status
Simulation time 126743168642 ps
CPU time 39.29 seconds
Started Apr 25 01:41:10 PM PDT 24
Finished Apr 25 01:41:50 PM PDT 24
Peak memory 200388 kb
Host smart-25f4a587-d27c-4793-8854-c8b6cad9a3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688647589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.2688647589
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_fifo_full.4097502799
Short name T407
Test name
Test status
Simulation time 121006007082 ps
CPU time 98.43 seconds
Started Apr 25 01:35:14 PM PDT 24
Finished Apr 25 01:36:54 PM PDT 24
Peak memory 200384 kb
Host smart-2af14f1a-e484-40e3-abee-3647e1d97020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097502799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.4097502799
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.2671094715
Short name T777
Test name
Test status
Simulation time 20484743924 ps
CPU time 39.03 seconds
Started Apr 25 01:35:13 PM PDT 24
Finished Apr 25 01:35:53 PM PDT 24
Peak memory 200240 kb
Host smart-5bcad392-eb73-413b-a318-c40443e9d084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671094715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.2671094715
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.261956283
Short name T582
Test name
Test status
Simulation time 39675333988 ps
CPU time 45.34 seconds
Started Apr 25 01:35:12 PM PDT 24
Finished Apr 25 01:35:58 PM PDT 24
Peak memory 200468 kb
Host smart-c0a1e89f-f871-433a-9338-b0a54cc7de78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261956283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.261956283
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.2071769863
Short name T719
Test name
Test status
Simulation time 40537738284 ps
CPU time 65.96 seconds
Started Apr 25 01:35:14 PM PDT 24
Finished Apr 25 01:36:21 PM PDT 24
Peak memory 200420 kb
Host smart-de54839f-6811-4f00-bacc-659c380e5ae9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071769863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.2071769863
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.3696588834
Short name T1184
Test name
Test status
Simulation time 79865150178 ps
CPU time 540.14 seconds
Started Apr 25 01:35:16 PM PDT 24
Finished Apr 25 01:44:16 PM PDT 24
Peak memory 200384 kb
Host smart-5ee03133-6a26-4ff3-8d6c-050534706727
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3696588834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.3696588834
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.2544430474
Short name T1006
Test name
Test status
Simulation time 2231648003 ps
CPU time 6.36 seconds
Started Apr 25 01:35:14 PM PDT 24
Finished Apr 25 01:35:21 PM PDT 24
Peak memory 199232 kb
Host smart-c8f05590-4604-4732-93b4-e174224e6a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544430474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.2544430474
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.1573197539
Short name T1032
Test name
Test status
Simulation time 9210898017 ps
CPU time 14.91 seconds
Started Apr 25 01:35:14 PM PDT 24
Finished Apr 25 01:35:30 PM PDT 24
Peak memory 197904 kb
Host smart-2bdd2ee7-8c96-4c34-b430-ecc6e9561ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573197539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.1573197539
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.2074125522
Short name T442
Test name
Test status
Simulation time 25479867743 ps
CPU time 149.39 seconds
Started Apr 25 01:35:15 PM PDT 24
Finished Apr 25 01:37:45 PM PDT 24
Peak memory 200428 kb
Host smart-47dced4e-40f2-460a-8689-b4852f236243
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2074125522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.2074125522
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.3930657204
Short name T588
Test name
Test status
Simulation time 3170240280 ps
CPU time 4.98 seconds
Started Apr 25 01:35:13 PM PDT 24
Finished Apr 25 01:35:18 PM PDT 24
Peak memory 198348 kb
Host smart-b3fd1aa5-2912-40ce-8679-7c0679f516d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3930657204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3930657204
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.3690279575
Short name T685
Test name
Test status
Simulation time 93619874770 ps
CPU time 146.12 seconds
Started Apr 25 01:35:14 PM PDT 24
Finished Apr 25 01:37:41 PM PDT 24
Peak memory 200420 kb
Host smart-e75bfc01-5821-411b-b6d3-ca9208b430d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690279575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.3690279575
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.306791843
Short name T343
Test name
Test status
Simulation time 1489123555 ps
CPU time 3.16 seconds
Started Apr 25 01:35:15 PM PDT 24
Finished Apr 25 01:35:19 PM PDT 24
Peak memory 195776 kb
Host smart-4391d2c7-7698-4289-96a0-5ab7e8cfa5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306791843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.306791843
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.4149800335
Short name T258
Test name
Test status
Simulation time 530626535 ps
CPU time 2.36 seconds
Started Apr 25 01:35:08 PM PDT 24
Finished Apr 25 01:35:10 PM PDT 24
Peak memory 200344 kb
Host smart-33e9103c-a095-464e-9021-fe9a954f2cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149800335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.4149800335
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.3813636645
Short name T166
Test name
Test status
Simulation time 47778104859 ps
CPU time 113.42 seconds
Started Apr 25 01:35:15 PM PDT 24
Finished Apr 25 01:37:10 PM PDT 24
Peak memory 200240 kb
Host smart-41dd9e1c-cbe9-414a-815a-d197b3d8c183
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813636645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.3813636645
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.1528015821
Short name T519
Test name
Test status
Simulation time 6691275552 ps
CPU time 12.25 seconds
Started Apr 25 01:35:14 PM PDT 24
Finished Apr 25 01:35:27 PM PDT 24
Peak memory 200256 kb
Host smart-4ba9e4ad-1bc4-4808-9125-43c8b9dd8f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528015821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.1528015821
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.2877469661
Short name T89
Test name
Test status
Simulation time 34583604040 ps
CPU time 33.6 seconds
Started Apr 25 01:35:14 PM PDT 24
Finished Apr 25 01:35:48 PM PDT 24
Peak memory 200388 kb
Host smart-e8bc94bf-bd01-4435-aa8d-0fcbab593823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877469661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.2877469661
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.2740320571
Short name T320
Test name
Test status
Simulation time 55572211450 ps
CPU time 97.07 seconds
Started Apr 25 01:41:16 PM PDT 24
Finished Apr 25 01:42:53 PM PDT 24
Peak memory 200388 kb
Host smart-bd0446c8-9c3c-48cd-a310-ae7a996b2cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740320571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2740320571
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.2807566355
Short name T542
Test name
Test status
Simulation time 24017241268 ps
CPU time 50.78 seconds
Started Apr 25 01:41:16 PM PDT 24
Finished Apr 25 01:42:07 PM PDT 24
Peak memory 200424 kb
Host smart-4eaa2119-f786-4b19-b445-3a12b12f6846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807566355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.2807566355
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.2162543984
Short name T201
Test name
Test status
Simulation time 45592152792 ps
CPU time 80.44 seconds
Started Apr 25 01:41:18 PM PDT 24
Finished Apr 25 01:42:39 PM PDT 24
Peak memory 200460 kb
Host smart-0b38c754-3c63-4557-b3f3-521f9abe931c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162543984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.2162543984
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.819074835
Short name T386
Test name
Test status
Simulation time 115601239314 ps
CPU time 93.27 seconds
Started Apr 25 01:41:17 PM PDT 24
Finished Apr 25 01:42:50 PM PDT 24
Peak memory 200348 kb
Host smart-a9d2b7c7-bb34-486b-835f-96450d20e547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819074835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.819074835
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.1792689429
Short name T159
Test name
Test status
Simulation time 173813861591 ps
CPU time 132.79 seconds
Started Apr 25 01:41:16 PM PDT 24
Finished Apr 25 01:43:29 PM PDT 24
Peak memory 200356 kb
Host smart-8e642337-c517-468e-8697-8461e98f1e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792689429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.1792689429
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.2687808689
Short name T985
Test name
Test status
Simulation time 12985591019 ps
CPU time 18.31 seconds
Started Apr 25 01:41:16 PM PDT 24
Finished Apr 25 01:41:35 PM PDT 24
Peak memory 199968 kb
Host smart-989ba46e-d2cf-4990-ba33-69dc6d064bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687808689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.2687808689
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.3710690603
Short name T111
Test name
Test status
Simulation time 118662427201 ps
CPU time 42.97 seconds
Started Apr 25 01:41:18 PM PDT 24
Finished Apr 25 01:42:01 PM PDT 24
Peak memory 200308 kb
Host smart-bef4f54d-44f2-4aeb-bd9e-b74e7b330bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710690603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.3710690603
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.2129897850
Short name T814
Test name
Test status
Simulation time 21292302256 ps
CPU time 31.31 seconds
Started Apr 25 01:41:27 PM PDT 24
Finished Apr 25 01:41:59 PM PDT 24
Peak memory 200248 kb
Host smart-71de5ebe-c128-4946-8333-4ef0c54ab654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129897850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2129897850
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.2810242230
Short name T477
Test name
Test status
Simulation time 12272038 ps
CPU time 0.53 seconds
Started Apr 25 01:35:27 PM PDT 24
Finished Apr 25 01:35:29 PM PDT 24
Peak memory 195812 kb
Host smart-6d9685ec-2b7c-4c8d-a24d-2de5721d4f3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810242230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.2810242230
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.937703895
Short name T138
Test name
Test status
Simulation time 34628063520 ps
CPU time 54.86 seconds
Started Apr 25 01:35:20 PM PDT 24
Finished Apr 25 01:36:15 PM PDT 24
Peak memory 200452 kb
Host smart-50ff1e3a-ca34-4c17-a066-799a09633032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937703895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.937703895
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.2650045151
Short name T967
Test name
Test status
Simulation time 18092066518 ps
CPU time 28.52 seconds
Started Apr 25 01:35:20 PM PDT 24
Finished Apr 25 01:35:50 PM PDT 24
Peak memory 200356 kb
Host smart-54f3e53d-8524-4ada-8ee7-fc479ddaa11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650045151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2650045151
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.533806417
Short name T718
Test name
Test status
Simulation time 51090106968 ps
CPU time 19.19 seconds
Started Apr 25 01:35:24 PM PDT 24
Finished Apr 25 01:35:44 PM PDT 24
Peak memory 200152 kb
Host smart-2c8b6fa4-8e3c-40f0-9326-5d853bc3f01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533806417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.533806417
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.3024197718
Short name T839
Test name
Test status
Simulation time 82777419197 ps
CPU time 453.18 seconds
Started Apr 25 01:35:21 PM PDT 24
Finished Apr 25 01:42:56 PM PDT 24
Peak memory 200428 kb
Host smart-83f74d6a-86c1-46b0-b13f-c7491efef1b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3024197718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.3024197718
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.112974184
Short name T345
Test name
Test status
Simulation time 11377929188 ps
CPU time 18.63 seconds
Started Apr 25 01:35:20 PM PDT 24
Finished Apr 25 01:35:40 PM PDT 24
Peak memory 199260 kb
Host smart-8f77abc3-9f19-4962-9916-c87780e2aea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112974184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.112974184
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.2312018860
Short name T722
Test name
Test status
Simulation time 11648741162 ps
CPU time 13.94 seconds
Started Apr 25 01:35:20 PM PDT 24
Finished Apr 25 01:35:35 PM PDT 24
Peak memory 200376 kb
Host smart-5160f496-1eda-4530-ad60-8aae13bf5aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312018860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.2312018860
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.102520282
Short name T29
Test name
Test status
Simulation time 23775218448 ps
CPU time 1163.16 seconds
Started Apr 25 01:35:21 PM PDT 24
Finished Apr 25 01:54:45 PM PDT 24
Peak memory 200372 kb
Host smart-f3320fb6-50ef-49aa-8423-31e5c225003f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=102520282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.102520282
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.1455864445
Short name T42
Test name
Test status
Simulation time 5009657728 ps
CPU time 47.38 seconds
Started Apr 25 01:35:20 PM PDT 24
Finished Apr 25 01:36:09 PM PDT 24
Peak memory 199568 kb
Host smart-3cfba4e6-aaf3-4957-baaa-b07c30943225
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1455864445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.1455864445
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.3312854071
Short name T647
Test name
Test status
Simulation time 47771235118 ps
CPU time 17.4 seconds
Started Apr 25 01:35:21 PM PDT 24
Finished Apr 25 01:35:40 PM PDT 24
Peak memory 200448 kb
Host smart-033dc50f-ff92-4749-9457-e06bbdab1b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312854071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.3312854071
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.1334623826
Short name T687
Test name
Test status
Simulation time 5878659957 ps
CPU time 5.43 seconds
Started Apr 25 01:35:21 PM PDT 24
Finished Apr 25 01:35:28 PM PDT 24
Peak memory 196392 kb
Host smart-78611e63-ae5e-425d-b7e6-cf3b65f657b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334623826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.1334623826
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.2847342675
Short name T1150
Test name
Test status
Simulation time 263414384 ps
CPU time 1.49 seconds
Started Apr 25 01:35:15 PM PDT 24
Finished Apr 25 01:35:18 PM PDT 24
Peak memory 199176 kb
Host smart-d22e9931-2471-43ba-9739-b146149fb166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847342675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.2847342675
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.2172339586
Short name T513
Test name
Test status
Simulation time 109042408604 ps
CPU time 255.29 seconds
Started Apr 25 01:35:21 PM PDT 24
Finished Apr 25 01:39:37 PM PDT 24
Peak memory 208672 kb
Host smart-50dbcc96-9edd-471f-8505-2dcd8005469f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172339586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.2172339586
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.1562233627
Short name T108
Test name
Test status
Simulation time 98911014151 ps
CPU time 711 seconds
Started Apr 25 01:35:21 PM PDT 24
Finished Apr 25 01:47:13 PM PDT 24
Peak memory 216972 kb
Host smart-599af656-cdf1-4cce-b5d1-557581fa95f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562233627 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.1562233627
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.2503984536
Short name T594
Test name
Test status
Simulation time 1861881557 ps
CPU time 1.99 seconds
Started Apr 25 01:35:20 PM PDT 24
Finished Apr 25 01:35:23 PM PDT 24
Peak memory 198696 kb
Host smart-d65a0225-65b1-4595-8105-4bf073e83baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503984536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.2503984536
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.1340409358
Short name T786
Test name
Test status
Simulation time 42751156528 ps
CPU time 77.98 seconds
Started Apr 25 01:35:23 PM PDT 24
Finished Apr 25 01:36:42 PM PDT 24
Peak memory 200428 kb
Host smart-0b4da93d-9bf0-49fb-9e1a-a8c4b4db16b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340409358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.1340409358
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.1360381461
Short name T705
Test name
Test status
Simulation time 26143261660 ps
CPU time 22.1 seconds
Started Apr 25 01:41:16 PM PDT 24
Finished Apr 25 01:41:38 PM PDT 24
Peak memory 200424 kb
Host smart-8795fe5c-d4f7-4e0d-a8cf-8c6f35db0c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360381461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.1360381461
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.3596767139
Short name T173
Test name
Test status
Simulation time 101972499246 ps
CPU time 75.61 seconds
Started Apr 25 01:41:17 PM PDT 24
Finished Apr 25 01:42:33 PM PDT 24
Peak memory 200276 kb
Host smart-8a82a6e3-40cc-47b0-b4bc-066e26693c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596767139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.3596767139
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.1304228187
Short name T118
Test name
Test status
Simulation time 27172922426 ps
CPU time 44.47 seconds
Started Apr 25 01:41:19 PM PDT 24
Finished Apr 25 01:42:04 PM PDT 24
Peak memory 200408 kb
Host smart-8e97330f-b6e2-460f-a8d3-b2bdf59cf44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304228187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.1304228187
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.1830309941
Short name T942
Test name
Test status
Simulation time 71446201347 ps
CPU time 106.32 seconds
Started Apr 25 01:41:24 PM PDT 24
Finished Apr 25 01:43:11 PM PDT 24
Peak memory 200424 kb
Host smart-dd9ab5a7-f09c-4f5f-939d-70ada3c4d26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830309941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.1830309941
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.3372796851
Short name T571
Test name
Test status
Simulation time 101143512252 ps
CPU time 80.22 seconds
Started Apr 25 01:41:25 PM PDT 24
Finished Apr 25 01:42:46 PM PDT 24
Peak memory 200340 kb
Host smart-2e9ea3a7-e19c-43e6-bad7-93fac477d88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372796851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3372796851
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.1227800602
Short name T746
Test name
Test status
Simulation time 14236746779 ps
CPU time 24.27 seconds
Started Apr 25 01:41:21 PM PDT 24
Finished Apr 25 01:41:45 PM PDT 24
Peak memory 200340 kb
Host smart-52dc40ef-b2ef-4481-befd-199011564413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227800602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1227800602
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.3845883721
Short name T857
Test name
Test status
Simulation time 106553830481 ps
CPU time 92.06 seconds
Started Apr 25 01:41:24 PM PDT 24
Finished Apr 25 01:42:56 PM PDT 24
Peak memory 200424 kb
Host smart-9b761635-944d-46bc-8f88-314c81d661ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845883721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.3845883721
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.1847558057
Short name T785
Test name
Test status
Simulation time 38624896 ps
CPU time 0.54 seconds
Started Apr 25 01:35:36 PM PDT 24
Finished Apr 25 01:35:37 PM PDT 24
Peak memory 195784 kb
Host smart-e06f2682-e6c2-4a10-86b1-22a4f49afd44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847558057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.1847558057
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.1260488658
Short name T1092
Test name
Test status
Simulation time 34860198607 ps
CPU time 28.95 seconds
Started Apr 25 01:35:26 PM PDT 24
Finished Apr 25 01:35:55 PM PDT 24
Peak memory 200292 kb
Host smart-da5646b3-71dd-43b9-b9b3-e7c6c1ad5e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260488658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1260488658
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.102541217
Short name T739
Test name
Test status
Simulation time 18811403311 ps
CPU time 33.81 seconds
Started Apr 25 01:35:27 PM PDT 24
Finished Apr 25 01:36:02 PM PDT 24
Peak memory 200460 kb
Host smart-cec552bf-313c-463e-a52a-292a56441960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102541217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.102541217
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.1917727496
Short name T712
Test name
Test status
Simulation time 98981560779 ps
CPU time 88.37 seconds
Started Apr 25 01:35:27 PM PDT 24
Finished Apr 25 01:36:57 PM PDT 24
Peak memory 200384 kb
Host smart-0987f312-c634-4809-bfa7-f27445521644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917727496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.1917727496
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.3175582346
Short name T562
Test name
Test status
Simulation time 16491246488 ps
CPU time 25.83 seconds
Started Apr 25 01:35:29 PM PDT 24
Finished Apr 25 01:35:55 PM PDT 24
Peak memory 199116 kb
Host smart-3718aae5-9333-440a-974c-7f6ca6c31f39
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175582346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.3175582346
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.370455925
Short name T727
Test name
Test status
Simulation time 347139288529 ps
CPU time 136 seconds
Started Apr 25 01:35:27 PM PDT 24
Finished Apr 25 01:37:44 PM PDT 24
Peak memory 200388 kb
Host smart-55c242c3-a0f0-4166-bdc2-7b8cc5e47397
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=370455925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.370455925
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.2385014697
Short name T737
Test name
Test status
Simulation time 1336522435 ps
CPU time 1.92 seconds
Started Apr 25 01:35:26 PM PDT 24
Finished Apr 25 01:35:29 PM PDT 24
Peak memory 197876 kb
Host smart-8f0b923b-2d12-449d-9846-547e9aee5963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385014697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.2385014697
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.3928725359
Short name T865
Test name
Test status
Simulation time 66504794950 ps
CPU time 111.63 seconds
Started Apr 25 01:35:48 PM PDT 24
Finished Apr 25 01:37:40 PM PDT 24
Peak memory 208848 kb
Host smart-2ddba0fa-38d8-4ba1-a182-4f31cb7f5cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928725359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.3928725359
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.818024596
Short name T463
Test name
Test status
Simulation time 15519939705 ps
CPU time 756.63 seconds
Started Apr 25 01:35:26 PM PDT 24
Finished Apr 25 01:48:04 PM PDT 24
Peak memory 200432 kb
Host smart-f047aa1d-5438-4b7d-93d5-930fc2fb8f82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=818024596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.818024596
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.1496541472
Short name T726
Test name
Test status
Simulation time 3391751536 ps
CPU time 3.91 seconds
Started Apr 25 01:35:26 PM PDT 24
Finished Apr 25 01:35:30 PM PDT 24
Peak memory 198936 kb
Host smart-b6e8f5e7-abeb-4512-b3be-71aaaa376680
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1496541472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.1496541472
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.491657453
Short name T365
Test name
Test status
Simulation time 89300483224 ps
CPU time 37.32 seconds
Started Apr 25 01:35:25 PM PDT 24
Finished Apr 25 01:36:03 PM PDT 24
Peak memory 199400 kb
Host smart-30c9f67a-4973-4b04-9476-0345cb3d29cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491657453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.491657453
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.441560151
Short name T1080
Test name
Test status
Simulation time 527248446 ps
CPU time 1.47 seconds
Started Apr 25 01:35:27 PM PDT 24
Finished Apr 25 01:35:30 PM PDT 24
Peak memory 196000 kb
Host smart-efcc4e62-0414-404a-a2a6-b57fdc1ef415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441560151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.441560151
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.2822304262
Short name T527
Test name
Test status
Simulation time 691339241 ps
CPU time 1.69 seconds
Started Apr 25 01:35:29 PM PDT 24
Finished Apr 25 01:35:31 PM PDT 24
Peak memory 199896 kb
Host smart-008c153d-ebd9-4de8-a1ed-008e0db4edc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822304262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.2822304262
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.1037199868
Short name T550
Test name
Test status
Simulation time 244607308530 ps
CPU time 284.59 seconds
Started Apr 25 01:35:33 PM PDT 24
Finished Apr 25 01:40:18 PM PDT 24
Peak memory 208800 kb
Host smart-0ef5f0cc-cdfd-41d8-9b33-94b060285039
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037199868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.1037199868
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.315665149
Short name T46
Test name
Test status
Simulation time 95873162258 ps
CPU time 154.43 seconds
Started Apr 25 01:35:29 PM PDT 24
Finished Apr 25 01:38:04 PM PDT 24
Peak memory 213812 kb
Host smart-5ae730b2-2f5c-4b8d-83ec-cf12f00c3676
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315665149 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.315665149
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.244288067
Short name T710
Test name
Test status
Simulation time 2003895287 ps
CPU time 1.75 seconds
Started Apr 25 01:35:31 PM PDT 24
Finished Apr 25 01:35:33 PM PDT 24
Peak memory 198584 kb
Host smart-11881ba9-2d1c-425e-8c8e-4c43773601ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244288067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.244288067
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.1116306828
Short name T674
Test name
Test status
Simulation time 41589750390 ps
CPU time 65.45 seconds
Started Apr 25 01:35:27 PM PDT 24
Finished Apr 25 01:36:33 PM PDT 24
Peak memory 200464 kb
Host smart-f3cfe14e-bd25-45a3-9374-22cc52be5fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116306828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.1116306828
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.3812000392
Short name T191
Test name
Test status
Simulation time 120730021641 ps
CPU time 176.8 seconds
Started Apr 25 01:41:22 PM PDT 24
Finished Apr 25 01:44:19 PM PDT 24
Peak memory 200420 kb
Host smart-433a2abf-c52c-4361-b3c8-6a406b9e3904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812000392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.3812000392
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.173968181
Short name T873
Test name
Test status
Simulation time 97935407123 ps
CPU time 9.84 seconds
Started Apr 25 01:41:25 PM PDT 24
Finished Apr 25 01:41:35 PM PDT 24
Peak memory 200340 kb
Host smart-c81b5669-6fa1-48bc-b092-b4781b53ae95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173968181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.173968181
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.988457281
Short name T547
Test name
Test status
Simulation time 1928086694 ps
CPU time 3.64 seconds
Started Apr 25 01:41:23 PM PDT 24
Finished Apr 25 01:41:27 PM PDT 24
Peak memory 199108 kb
Host smart-ee2013f4-7386-43d1-9364-f38b30a3c0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988457281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.988457281
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.3429047485
Short name T604
Test name
Test status
Simulation time 17013484760 ps
CPU time 8.86 seconds
Started Apr 25 01:41:22 PM PDT 24
Finished Apr 25 01:41:32 PM PDT 24
Peak memory 200056 kb
Host smart-7428332e-4b80-4ffe-a231-42bcbfa5644b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429047485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.3429047485
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.4029678455
Short name T307
Test name
Test status
Simulation time 61239366769 ps
CPU time 103.93 seconds
Started Apr 25 01:41:27 PM PDT 24
Finished Apr 25 01:43:11 PM PDT 24
Peak memory 200260 kb
Host smart-7485ccc2-c5b5-4ce9-9c7e-6d1034584135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029678455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.4029678455
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.144108490
Short name T580
Test name
Test status
Simulation time 146053151641 ps
CPU time 192.37 seconds
Started Apr 25 01:41:28 PM PDT 24
Finished Apr 25 01:44:41 PM PDT 24
Peak memory 200412 kb
Host smart-40e3eb34-46aa-4072-b70e-d1a1bc7b292d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144108490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.144108490
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.3203428608
Short name T945
Test name
Test status
Simulation time 206011028395 ps
CPU time 32.66 seconds
Started Apr 25 01:41:28 PM PDT 24
Finished Apr 25 01:42:01 PM PDT 24
Peak memory 200420 kb
Host smart-023e4ad7-6ddd-4b84-ab40-479c2c5f2cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203428608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.3203428608
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.1868877241
Short name T936
Test name
Test status
Simulation time 66106429388 ps
CPU time 18.91 seconds
Started Apr 25 01:41:27 PM PDT 24
Finished Apr 25 01:41:46 PM PDT 24
Peak memory 200384 kb
Host smart-0acd2d06-9456-45f4-b407-a8ec98e00bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868877241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.1868877241
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.4094448270
Short name T275
Test name
Test status
Simulation time 240396911980 ps
CPU time 120.81 seconds
Started Apr 25 01:41:29 PM PDT 24
Finished Apr 25 01:43:30 PM PDT 24
Peak memory 200376 kb
Host smart-876b47c1-aa22-4bcb-9cff-6f9eed7b72cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094448270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.4094448270
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.1939947917
Short name T326
Test name
Test status
Simulation time 121798650006 ps
CPU time 33.62 seconds
Started Apr 25 01:41:28 PM PDT 24
Finished Apr 25 01:42:02 PM PDT 24
Peak memory 200372 kb
Host smart-975a5228-0f98-4984-b14b-bae49b472e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939947917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.1939947917
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.1229298103
Short name T1122
Test name
Test status
Simulation time 42848016 ps
CPU time 0.54 seconds
Started Apr 25 01:35:40 PM PDT 24
Finished Apr 25 01:35:41 PM PDT 24
Peak memory 195788 kb
Host smart-6fcdf746-8022-4d8a-8c13-32827bc3c1fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229298103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.1229298103
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.571979788
Short name T460
Test name
Test status
Simulation time 59768884587 ps
CPU time 46.3 seconds
Started Apr 25 01:35:34 PM PDT 24
Finished Apr 25 01:36:21 PM PDT 24
Peak memory 200420 kb
Host smart-6d5fd5c0-4646-4ffd-a754-993ec3d2c708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571979788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.571979788
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.2448771686
Short name T695
Test name
Test status
Simulation time 174768860959 ps
CPU time 69.35 seconds
Started Apr 25 01:35:33 PM PDT 24
Finished Apr 25 01:36:43 PM PDT 24
Peak memory 200340 kb
Host smart-bb352e6f-de3e-4544-aaba-ba89156dde33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448771686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.2448771686
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.282161251
Short name T256
Test name
Test status
Simulation time 115503490149 ps
CPU time 98.62 seconds
Started Apr 25 01:35:34 PM PDT 24
Finished Apr 25 01:37:14 PM PDT 24
Peak memory 200376 kb
Host smart-f8cdd828-2900-4a08-ad98-f77e9d6243a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282161251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.282161251
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.355327373
Short name T930
Test name
Test status
Simulation time 26528494702 ps
CPU time 23.05 seconds
Started Apr 25 01:35:35 PM PDT 24
Finished Apr 25 01:35:59 PM PDT 24
Peak memory 199816 kb
Host smart-2829bf66-fda2-48da-8b4f-e7603d1d3294
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355327373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.355327373
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.2806571806
Short name T1130
Test name
Test status
Simulation time 77672135128 ps
CPU time 329.16 seconds
Started Apr 25 01:35:38 PM PDT 24
Finished Apr 25 01:41:08 PM PDT 24
Peak memory 200388 kb
Host smart-9ddaa211-8267-42a6-a980-1da14069d8df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2806571806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.2806571806
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.3341357356
Short name T920
Test name
Test status
Simulation time 12023749632 ps
CPU time 32.31 seconds
Started Apr 25 01:35:37 PM PDT 24
Finished Apr 25 01:36:10 PM PDT 24
Peak memory 200384 kb
Host smart-7ec84cc7-5acb-4c3e-a570-6a7d2a99c671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341357356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.3341357356
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.2741208881
Short name T494
Test name
Test status
Simulation time 84922467632 ps
CPU time 35.89 seconds
Started Apr 25 01:35:34 PM PDT 24
Finished Apr 25 01:36:10 PM PDT 24
Peak memory 200008 kb
Host smart-9d29e4cf-cf6a-41cd-838d-2433ff9bcce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741208881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.2741208881
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.3699656096
Short name T298
Test name
Test status
Simulation time 9444688451 ps
CPU time 144.41 seconds
Started Apr 25 01:35:39 PM PDT 24
Finished Apr 25 01:38:04 PM PDT 24
Peak memory 200484 kb
Host smart-90ddf506-f62d-4916-92ce-65901fc5fa4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3699656096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.3699656096
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.1839885835
Short name T820
Test name
Test status
Simulation time 5545405337 ps
CPU time 50.91 seconds
Started Apr 25 01:35:34 PM PDT 24
Finished Apr 25 01:36:26 PM PDT 24
Peak memory 198592 kb
Host smart-9645b152-03d0-438c-87e4-018ce22b110d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1839885835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.1839885835
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.2612495907
Short name T353
Test name
Test status
Simulation time 25470761316 ps
CPU time 37.27 seconds
Started Apr 25 01:35:34 PM PDT 24
Finished Apr 25 01:36:12 PM PDT 24
Peak memory 200208 kb
Host smart-d0e3beab-faba-48a4-b727-bd58027795c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612495907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.2612495907
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.2238189459
Short name T628
Test name
Test status
Simulation time 3047799086 ps
CPU time 3.22 seconds
Started Apr 25 01:35:34 PM PDT 24
Finished Apr 25 01:35:37 PM PDT 24
Peak memory 196444 kb
Host smart-659092e4-2710-445a-b0fd-ed7ab911fb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238189459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.2238189459
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.1355977098
Short name T1001
Test name
Test status
Simulation time 6095577421 ps
CPU time 5.73 seconds
Started Apr 25 01:35:34 PM PDT 24
Finished Apr 25 01:35:40 PM PDT 24
Peak memory 200144 kb
Host smart-0c048838-c741-4c1c-9dc3-e1e4fd9323f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355977098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.1355977098
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.470296848
Short name T1052
Test name
Test status
Simulation time 535838349672 ps
CPU time 366 seconds
Started Apr 25 01:35:39 PM PDT 24
Finished Apr 25 01:41:46 PM PDT 24
Peak memory 200400 kb
Host smart-9c78d521-d5a5-4197-a698-da496d77e326
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470296848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.470296848
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.2015583300
Short name T1168
Test name
Test status
Simulation time 497505276142 ps
CPU time 1469.14 seconds
Started Apr 25 01:35:41 PM PDT 24
Finished Apr 25 02:00:11 PM PDT 24
Peak memory 229052 kb
Host smart-39111638-07eb-4513-a019-ad386d66e69b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015583300 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.2015583300
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.1248029899
Short name T487
Test name
Test status
Simulation time 2027602547 ps
CPU time 1.48 seconds
Started Apr 25 01:35:33 PM PDT 24
Finished Apr 25 01:35:35 PM PDT 24
Peak memory 199080 kb
Host smart-b4e45bf2-c130-47ee-ae40-f4a87977f1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248029899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.1248029899
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.2243062484
Short name T590
Test name
Test status
Simulation time 11419188311 ps
CPU time 19.1 seconds
Started Apr 25 01:35:33 PM PDT 24
Finished Apr 25 01:35:53 PM PDT 24
Peak memory 200392 kb
Host smart-52be460b-7c50-49a5-b403-1262daa954d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243062484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.2243062484
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.521143253
Short name T1082
Test name
Test status
Simulation time 81404936983 ps
CPU time 70.51 seconds
Started Apr 25 01:41:28 PM PDT 24
Finished Apr 25 01:42:39 PM PDT 24
Peak memory 200144 kb
Host smart-b2ea3fe2-6c93-4321-819b-3c18224acc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521143253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.521143253
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.130100792
Short name T973
Test name
Test status
Simulation time 104438455839 ps
CPU time 87.5 seconds
Started Apr 25 01:41:28 PM PDT 24
Finished Apr 25 01:42:56 PM PDT 24
Peak memory 200348 kb
Host smart-16e3989a-53ac-4387-afee-e6995ff6bcb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130100792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.130100792
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.2020297425
Short name T205
Test name
Test status
Simulation time 142556934012 ps
CPU time 63.85 seconds
Started Apr 25 01:41:28 PM PDT 24
Finished Apr 25 01:42:32 PM PDT 24
Peak memory 200272 kb
Host smart-3c1226de-9d00-45b8-a102-6db1e2841bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020297425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.2020297425
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.3763114105
Short name T464
Test name
Test status
Simulation time 8613324684 ps
CPU time 14.32 seconds
Started Apr 25 01:41:29 PM PDT 24
Finished Apr 25 01:41:44 PM PDT 24
Peak memory 200428 kb
Host smart-03805ffa-5d4a-4676-85d9-8b8443f9b268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763114105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.3763114105
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.826691730
Short name T1142
Test name
Test status
Simulation time 99774558304 ps
CPU time 104.29 seconds
Started Apr 25 01:41:29 PM PDT 24
Finished Apr 25 01:43:14 PM PDT 24
Peak memory 200448 kb
Host smart-cce8010b-1a3d-4885-9795-91c0a519dc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826691730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.826691730
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.2917846242
Short name T725
Test name
Test status
Simulation time 40500637395 ps
CPU time 16.53 seconds
Started Apr 25 01:41:35 PM PDT 24
Finished Apr 25 01:41:52 PM PDT 24
Peak memory 200412 kb
Host smart-0d5fddd9-999b-48fb-91af-da523f814de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917846242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.2917846242
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.3135565125
Short name T595
Test name
Test status
Simulation time 444937301433 ps
CPU time 40.35 seconds
Started Apr 25 01:41:35 PM PDT 24
Finished Apr 25 01:42:16 PM PDT 24
Peak memory 200548 kb
Host smart-d9f7ec63-69cc-4dd8-ab65-7d6a44bae87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135565125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.3135565125
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.714257744
Short name T1002
Test name
Test status
Simulation time 17676163072 ps
CPU time 30.56 seconds
Started Apr 25 01:41:34 PM PDT 24
Finished Apr 25 01:42:06 PM PDT 24
Peak memory 200392 kb
Host smart-51d80bcc-414c-4b41-be1b-4248fc773851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714257744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.714257744
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.4047029802
Short name T171
Test name
Test status
Simulation time 17187215193 ps
CPU time 26.97 seconds
Started Apr 25 01:41:34 PM PDT 24
Finished Apr 25 01:42:01 PM PDT 24
Peak memory 200096 kb
Host smart-20769de2-38d4-45a4-b31f-27dea04a04b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047029802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.4047029802
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.3436657250
Short name T397
Test name
Test status
Simulation time 29131186 ps
CPU time 0.56 seconds
Started Apr 25 01:35:52 PM PDT 24
Finished Apr 25 01:35:54 PM PDT 24
Peak memory 194768 kb
Host smart-3fe7c1ef-83c0-4b9c-9b80-9f1b2bdf4e62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436657250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.3436657250
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.2940588899
Short name T129
Test name
Test status
Simulation time 122684112978 ps
CPU time 110.25 seconds
Started Apr 25 01:35:46 PM PDT 24
Finished Apr 25 01:37:36 PM PDT 24
Peak memory 200396 kb
Host smart-ac44212c-ce90-4796-bca2-5b18af0d815b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940588899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.2940588899
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.1485941179
Short name T1101
Test name
Test status
Simulation time 322655659988 ps
CPU time 138.79 seconds
Started Apr 25 01:35:46 PM PDT 24
Finished Apr 25 01:38:05 PM PDT 24
Peak memory 199612 kb
Host smart-2a8eeecf-ef30-43a5-8071-58266e48d82f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485941179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.1485941179
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.145192331
Short name T907
Test name
Test status
Simulation time 68373499916 ps
CPU time 607.94 seconds
Started Apr 25 01:35:44 PM PDT 24
Finished Apr 25 01:45:53 PM PDT 24
Peak memory 200388 kb
Host smart-11223b3b-1a12-4587-8332-727ffa340399
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=145192331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.145192331
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.4155919655
Short name T467
Test name
Test status
Simulation time 11005857904 ps
CPU time 9.02 seconds
Started Apr 25 01:35:46 PM PDT 24
Finished Apr 25 01:35:55 PM PDT 24
Peak memory 200148 kb
Host smart-1ee6184a-74f7-4e72-b0f6-f2e46d1c703d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155919655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.4155919655
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.142912373
Short name T402
Test name
Test status
Simulation time 96004005450 ps
CPU time 86.6 seconds
Started Apr 25 01:35:45 PM PDT 24
Finished Apr 25 01:37:12 PM PDT 24
Peak memory 200596 kb
Host smart-1445395e-d8c7-418c-a799-1fd3f66a7b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142912373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.142912373
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.3745851168
Short name T296
Test name
Test status
Simulation time 21463883027 ps
CPU time 473.01 seconds
Started Apr 25 01:35:45 PM PDT 24
Finished Apr 25 01:43:38 PM PDT 24
Peak memory 200392 kb
Host smart-4f8dc246-3051-4b04-b796-64483a6ab89a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3745851168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3745851168
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.3588669131
Short name T858
Test name
Test status
Simulation time 7634295232 ps
CPU time 67.15 seconds
Started Apr 25 01:35:44 PM PDT 24
Finished Apr 25 01:36:51 PM PDT 24
Peak memory 199596 kb
Host smart-00f2187d-9a8c-434f-9b2c-734b5387d88d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3588669131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.3588669131
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.3937665833
Short name T1125
Test name
Test status
Simulation time 137398154612 ps
CPU time 20.46 seconds
Started Apr 25 01:35:48 PM PDT 24
Finished Apr 25 01:36:09 PM PDT 24
Peak memory 200428 kb
Host smart-df821479-1eec-444e-9814-f93ba2ad4a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937665833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.3937665833
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.2433399562
Short name T1153
Test name
Test status
Simulation time 43317971027 ps
CPU time 69.12 seconds
Started Apr 25 01:35:45 PM PDT 24
Finished Apr 25 01:36:54 PM PDT 24
Peak memory 196316 kb
Host smart-4bac293f-6c6e-4810-9c5f-ec9a28402a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433399562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.2433399562
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.318159639
Short name T1067
Test name
Test status
Simulation time 762418734 ps
CPU time 1.83 seconds
Started Apr 25 01:35:38 PM PDT 24
Finished Apr 25 01:35:40 PM PDT 24
Peak memory 200272 kb
Host smart-a51e3928-9677-4b02-8bb1-1b4bd99812fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318159639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.318159639
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.1103105898
Short name T783
Test name
Test status
Simulation time 57990621724 ps
CPU time 306.3 seconds
Started Apr 25 01:35:53 PM PDT 24
Finished Apr 25 01:41:00 PM PDT 24
Peak memory 216868 kb
Host smart-5a6ba570-cb99-42f7-977d-5634a4b87b54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103105898 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.1103105898
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.1171031525
Short name T1065
Test name
Test status
Simulation time 1157292628 ps
CPU time 1.82 seconds
Started Apr 25 01:35:46 PM PDT 24
Finished Apr 25 01:35:48 PM PDT 24
Peak memory 200292 kb
Host smart-bd59a0f0-66c9-4ec3-8ec1-75acc806e1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171031525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.1171031525
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.2899281806
Short name T868
Test name
Test status
Simulation time 98771670575 ps
CPU time 26.26 seconds
Started Apr 25 01:35:39 PM PDT 24
Finished Apr 25 01:36:06 PM PDT 24
Peak memory 200396 kb
Host smart-bf9aec66-74de-4686-aac8-1dd456fedaa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899281806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.2899281806
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.4028534603
Short name T553
Test name
Test status
Simulation time 147122360688 ps
CPU time 62.93 seconds
Started Apr 25 01:41:34 PM PDT 24
Finished Apr 25 01:42:38 PM PDT 24
Peak memory 200056 kb
Host smart-5422e7f8-e750-4bdb-90c0-b63433125e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028534603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.4028534603
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.2834184253
Short name T140
Test name
Test status
Simulation time 72444124660 ps
CPU time 160.56 seconds
Started Apr 25 01:41:35 PM PDT 24
Finished Apr 25 01:44:17 PM PDT 24
Peak memory 200252 kb
Host smart-f772b01c-9ab1-4826-9de7-51f3652171ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834184253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.2834184253
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.643723402
Short name T192
Test name
Test status
Simulation time 17675167803 ps
CPU time 29.42 seconds
Started Apr 25 01:41:33 PM PDT 24
Finished Apr 25 01:42:04 PM PDT 24
Peak memory 200460 kb
Host smart-ad826054-c9f0-4a25-8eb3-f3ed8fdc31e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643723402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.643723402
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.1349252812
Short name T241
Test name
Test status
Simulation time 57762640853 ps
CPU time 23.31 seconds
Started Apr 25 01:41:34 PM PDT 24
Finished Apr 25 01:41:58 PM PDT 24
Peak memory 200320 kb
Host smart-1c526d16-e633-4ead-9f7a-eba57d5485eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349252812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.1349252812
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.667128198
Short name T223
Test name
Test status
Simulation time 28798405216 ps
CPU time 25.77 seconds
Started Apr 25 01:41:33 PM PDT 24
Finished Apr 25 01:42:00 PM PDT 24
Peak memory 200276 kb
Host smart-b4edf5f0-a069-4cdf-a85f-189a742b86f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667128198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.667128198
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.526249035
Short name T321
Test name
Test status
Simulation time 115581381756 ps
CPU time 200.82 seconds
Started Apr 25 01:41:41 PM PDT 24
Finished Apr 25 01:45:03 PM PDT 24
Peak memory 200388 kb
Host smart-ca6b7053-4db3-4f6c-adc6-366255d827a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526249035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.526249035
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.3270868539
Short name T470
Test name
Test status
Simulation time 35771455 ps
CPU time 0.56 seconds
Started Apr 25 01:33:04 PM PDT 24
Finished Apr 25 01:33:05 PM PDT 24
Peak memory 195788 kb
Host smart-e2a88fc3-d13a-4349-9c85-2e848c8a4609
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270868539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.3270868539
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.3300804379
Short name T328
Test name
Test status
Simulation time 128939167902 ps
CPU time 199.12 seconds
Started Apr 25 01:32:52 PM PDT 24
Finished Apr 25 01:36:13 PM PDT 24
Peak memory 200376 kb
Host smart-60a5fc24-9a79-4780-80f8-bb3b357324a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300804379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.3300804379
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.4189666218
Short name T570
Test name
Test status
Simulation time 113170862713 ps
CPU time 240.22 seconds
Started Apr 25 01:32:51 PM PDT 24
Finished Apr 25 01:36:53 PM PDT 24
Peak memory 200456 kb
Host smart-dc552a18-db33-4c7a-bec6-b3f98d383695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189666218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.4189666218
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.1526719374
Short name T1009
Test name
Test status
Simulation time 22489153505 ps
CPU time 28.09 seconds
Started Apr 25 01:32:55 PM PDT 24
Finished Apr 25 01:33:24 PM PDT 24
Peak memory 200432 kb
Host smart-ec137b54-1308-4496-823f-d7384fc0ca8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526719374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.1526719374
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.1768112298
Short name T617
Test name
Test status
Simulation time 41514505545 ps
CPU time 16.35 seconds
Started Apr 25 01:32:55 PM PDT 24
Finished Apr 25 01:33:12 PM PDT 24
Peak memory 200396 kb
Host smart-1b66ab6c-0d10-4171-a7f0-2afe77639097
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768112298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.1768112298
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.493839959
Short name T352
Test name
Test status
Simulation time 117819606166 ps
CPU time 410.64 seconds
Started Apr 25 01:33:03 PM PDT 24
Finished Apr 25 01:39:54 PM PDT 24
Peak memory 200380 kb
Host smart-03f4b333-6e0e-4202-bdc5-6abadeb59713
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=493839959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.493839959
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.3937508803
Short name T906
Test name
Test status
Simulation time 7369008044 ps
CPU time 12.94 seconds
Started Apr 25 01:32:55 PM PDT 24
Finished Apr 25 01:33:09 PM PDT 24
Peak memory 200068 kb
Host smart-9a3ae879-ab9b-4726-b86b-bb8de0d8e884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937508803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.3937508803
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.2617901000
Short name T475
Test name
Test status
Simulation time 3825242213 ps
CPU time 6.29 seconds
Started Apr 25 01:33:00 PM PDT 24
Finished Apr 25 01:33:07 PM PDT 24
Peak memory 195016 kb
Host smart-90e41765-269a-4a2d-9193-4afe8bb5f592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617901000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.2617901000
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.1500750067
Short name T969
Test name
Test status
Simulation time 9438653608 ps
CPU time 516.57 seconds
Started Apr 25 01:33:05 PM PDT 24
Finished Apr 25 01:41:42 PM PDT 24
Peak memory 200472 kb
Host smart-872aee41-33b6-4fcf-808f-6e60cdf42c9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1500750067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.1500750067
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.3589940802
Short name T530
Test name
Test status
Simulation time 5334885225 ps
CPU time 53.24 seconds
Started Apr 25 01:32:56 PM PDT 24
Finished Apr 25 01:33:50 PM PDT 24
Peak memory 198512 kb
Host smart-f2df24e3-ac49-41cb-80b1-4294e10e94cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3589940802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.3589940802
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.1133095615
Short name T465
Test name
Test status
Simulation time 37715209891 ps
CPU time 64.85 seconds
Started Apr 25 01:32:56 PM PDT 24
Finished Apr 25 01:34:02 PM PDT 24
Peak memory 200216 kb
Host smart-b20bb813-c2c8-47ef-bbf4-c9fb65a46472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133095615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1133095615
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.3431593943
Short name T292
Test name
Test status
Simulation time 3080630573 ps
CPU time 2.03 seconds
Started Apr 25 01:32:59 PM PDT 24
Finished Apr 25 01:33:01 PM PDT 24
Peak memory 196416 kb
Host smart-ccb5e283-7eeb-45ca-b69d-cf6f40b63a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431593943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.3431593943
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.2487370243
Short name T82
Test name
Test status
Simulation time 450915818 ps
CPU time 0.82 seconds
Started Apr 25 01:33:06 PM PDT 24
Finished Apr 25 01:33:07 PM PDT 24
Peak memory 218676 kb
Host smart-3ffaa793-f24e-47e3-b85a-8d33e3798ad7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487370243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.2487370243
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.1834843504
Short name T655
Test name
Test status
Simulation time 675466123 ps
CPU time 1.94 seconds
Started Apr 25 01:32:53 PM PDT 24
Finished Apr 25 01:32:56 PM PDT 24
Peak memory 198784 kb
Host smart-6bd93821-6e03-4177-bba6-cc33c5c1e538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834843504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.1834843504
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.526869844
Short name T798
Test name
Test status
Simulation time 1089983825470 ps
CPU time 134.56 seconds
Started Apr 25 01:33:03 PM PDT 24
Finished Apr 25 01:35:18 PM PDT 24
Peak memory 217004 kb
Host smart-1c2ce187-9768-45c9-8114-fe1625216d37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526869844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.526869844
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.850059176
Short name T597
Test name
Test status
Simulation time 81492706813 ps
CPU time 1371.06 seconds
Started Apr 25 01:33:06 PM PDT 24
Finished Apr 25 01:55:57 PM PDT 24
Peak memory 216936 kb
Host smart-b2ab52f9-7e41-48a5-8fe3-4a21062baa7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850059176 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.850059176
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.453336459
Short name T882
Test name
Test status
Simulation time 7050514217 ps
CPU time 37.18 seconds
Started Apr 25 01:32:56 PM PDT 24
Finished Apr 25 01:33:34 PM PDT 24
Peak memory 199636 kb
Host smart-079e5599-db06-440a-ba77-5930aae0c48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453336459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.453336459
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.156897906
Short name T821
Test name
Test status
Simulation time 94374043057 ps
CPU time 209.25 seconds
Started Apr 25 01:32:52 PM PDT 24
Finished Apr 25 01:36:23 PM PDT 24
Peak memory 200372 kb
Host smart-dcbc8399-7285-495a-8fb5-852732b5ed37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156897906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.156897906
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.4090210932
Short name T18
Test name
Test status
Simulation time 14948258 ps
CPU time 0.58 seconds
Started Apr 25 01:35:58 PM PDT 24
Finished Apr 25 01:35:59 PM PDT 24
Peak memory 195800 kb
Host smart-6adfe522-6253-4073-b0ca-b78aadee3e89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090210932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.4090210932
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.554021812
Short name T148
Test name
Test status
Simulation time 52685279736 ps
CPU time 54.91 seconds
Started Apr 25 01:35:51 PM PDT 24
Finished Apr 25 01:36:46 PM PDT 24
Peak memory 200432 kb
Host smart-9bf93845-cf0e-47f5-8f80-448ddbb495da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554021812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.554021812
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.1676489989
Short name T943
Test name
Test status
Simulation time 131099129918 ps
CPU time 55.38 seconds
Started Apr 25 01:35:52 PM PDT 24
Finished Apr 25 01:36:49 PM PDT 24
Peak memory 200376 kb
Host smart-913ed4af-6042-45cd-9782-334d9803f95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676489989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.1676489989
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.2018198322
Short name T1043
Test name
Test status
Simulation time 172306553267 ps
CPU time 273.79 seconds
Started Apr 25 01:35:52 PM PDT 24
Finished Apr 25 01:40:26 PM PDT 24
Peak memory 200452 kb
Host smart-888397c5-8fef-4d28-8806-63944acd1e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018198322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.2018198322
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.3045865996
Short name T7
Test name
Test status
Simulation time 48549589750 ps
CPU time 31.53 seconds
Started Apr 25 01:35:52 PM PDT 24
Finished Apr 25 01:36:24 PM PDT 24
Peak memory 200408 kb
Host smart-f0e3e113-af19-487b-94f6-f009e74fe1d1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045865996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.3045865996
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.2282977564
Short name T458
Test name
Test status
Simulation time 171832732421 ps
CPU time 483.03 seconds
Started Apr 25 01:35:54 PM PDT 24
Finished Apr 25 01:43:57 PM PDT 24
Peak memory 200396 kb
Host smart-c0c3e398-fced-4a9b-bf93-a4c3729699ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2282977564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.2282977564
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.1731032598
Short name T1083
Test name
Test status
Simulation time 141820548 ps
CPU time 0.67 seconds
Started Apr 25 01:35:51 PM PDT 24
Finished Apr 25 01:35:52 PM PDT 24
Peak memory 196380 kb
Host smart-67172a6e-708f-467a-9c02-70389ad91787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731032598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.1731032598
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.273788610
Short name T480
Test name
Test status
Simulation time 153290807908 ps
CPU time 84.63 seconds
Started Apr 25 01:35:52 PM PDT 24
Finished Apr 25 01:37:18 PM PDT 24
Peak memory 200600 kb
Host smart-1031124d-cd33-468a-8850-3abffd6db4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273788610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.273788610
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.3308245101
Short name T398
Test name
Test status
Simulation time 7316351936 ps
CPU time 305.49 seconds
Started Apr 25 01:35:53 PM PDT 24
Finished Apr 25 01:40:59 PM PDT 24
Peak memory 200444 kb
Host smart-297fb198-b6ba-41c2-95c5-939456e38e0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3308245101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.3308245101
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.3968055109
Short name T634
Test name
Test status
Simulation time 1380285946 ps
CPU time 3.05 seconds
Started Apr 25 01:35:52 PM PDT 24
Finished Apr 25 01:35:56 PM PDT 24
Peak memory 198704 kb
Host smart-0458fd4a-23d7-4ac6-9e33-6c4d2fea7396
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3968055109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.3968055109
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.3458029447
Short name T350
Test name
Test status
Simulation time 41192454087 ps
CPU time 18.16 seconds
Started Apr 25 01:35:55 PM PDT 24
Finished Apr 25 01:36:13 PM PDT 24
Peak memory 200320 kb
Host smart-959fdee3-1ea2-422b-9935-fc4b4ef0b51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458029447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.3458029447
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.2189594880
Short name T277
Test name
Test status
Simulation time 1562729533 ps
CPU time 1.26 seconds
Started Apr 25 01:35:51 PM PDT 24
Finished Apr 25 01:35:53 PM PDT 24
Peak memory 195800 kb
Host smart-ac0b71f7-6362-4d63-ade9-356d95a28dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189594880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.2189594880
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.2873290859
Short name T295
Test name
Test status
Simulation time 855670229 ps
CPU time 2.42 seconds
Started Apr 25 01:35:50 PM PDT 24
Finished Apr 25 01:35:53 PM PDT 24
Peak memory 198652 kb
Host smart-2a9a7370-f6b6-4469-85a9-3726d6f40f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873290859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.2873290859
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.238884430
Short name T525
Test name
Test status
Simulation time 251309001365 ps
CPU time 896.76 seconds
Started Apr 25 01:35:58 PM PDT 24
Finished Apr 25 01:50:56 PM PDT 24
Peak memory 200416 kb
Host smart-67c6a7db-026e-4d8c-8469-598689ccb806
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238884430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.238884430
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.1837639164
Short name T1022
Test name
Test status
Simulation time 1705367820 ps
CPU time 2.46 seconds
Started Apr 25 01:35:53 PM PDT 24
Finished Apr 25 01:35:56 PM PDT 24
Peak memory 198676 kb
Host smart-9cb9018d-2c0f-472d-8f71-d339ebe5d091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837639164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.1837639164
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.2880702798
Short name T900
Test name
Test status
Simulation time 238135006539 ps
CPU time 96.66 seconds
Started Apr 25 01:35:50 PM PDT 24
Finished Apr 25 01:37:27 PM PDT 24
Peak memory 200428 kb
Host smart-938647ff-1072-4415-abba-b5af063a0bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880702798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.2880702798
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.1401496510
Short name T230
Test name
Test status
Simulation time 19320167579 ps
CPU time 11.05 seconds
Started Apr 25 01:41:40 PM PDT 24
Finished Apr 25 01:41:51 PM PDT 24
Peak memory 200424 kb
Host smart-81ec4adb-3635-423a-952d-0f4d860d03d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401496510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.1401496510
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.3597795820
Short name T541
Test name
Test status
Simulation time 96258782964 ps
CPU time 82.05 seconds
Started Apr 25 01:41:39 PM PDT 24
Finished Apr 25 01:43:01 PM PDT 24
Peak memory 200408 kb
Host smart-8693a021-7666-4781-b64c-15cc854b7fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597795820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3597795820
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.1824048507
Short name T485
Test name
Test status
Simulation time 103347020879 ps
CPU time 49.34 seconds
Started Apr 25 01:41:40 PM PDT 24
Finished Apr 25 01:42:30 PM PDT 24
Peak memory 200408 kb
Host smart-c3eb86b4-d682-42b5-be83-ba6de07d8304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824048507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.1824048507
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.4211938206
Short name T170
Test name
Test status
Simulation time 77667467590 ps
CPU time 35.73 seconds
Started Apr 25 01:41:46 PM PDT 24
Finished Apr 25 01:42:23 PM PDT 24
Peak memory 200360 kb
Host smart-0b8fdf03-c31a-4bf4-a32a-6405a4796e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211938206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.4211938206
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.1367424939
Short name T709
Test name
Test status
Simulation time 145210334537 ps
CPU time 246.58 seconds
Started Apr 25 01:41:45 PM PDT 24
Finished Apr 25 01:45:53 PM PDT 24
Peak memory 200352 kb
Host smart-5e9dcf7b-ddd3-46ee-be70-a9a88af77146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367424939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.1367424939
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.3331968812
Short name T620
Test name
Test status
Simulation time 5539032147 ps
CPU time 10.15 seconds
Started Apr 25 01:41:45 PM PDT 24
Finished Apr 25 01:41:56 PM PDT 24
Peak memory 200424 kb
Host smart-a5a2ddee-9235-46fc-9d31-6b593431c27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331968812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.3331968812
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.2562148256
Short name T455
Test name
Test status
Simulation time 94840120761 ps
CPU time 155.55 seconds
Started Apr 25 01:41:46 PM PDT 24
Finished Apr 25 01:44:22 PM PDT 24
Peak memory 200312 kb
Host smart-7305ff92-2178-4cba-9733-22e67f3330f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562148256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2562148256
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.3345376630
Short name T186
Test name
Test status
Simulation time 194726971415 ps
CPU time 260.95 seconds
Started Apr 25 01:41:45 PM PDT 24
Finished Apr 25 01:46:06 PM PDT 24
Peak memory 200448 kb
Host smart-ef7e82c3-f80b-4ee4-9677-9e78f931a48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345376630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.3345376630
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.1971132871
Short name T869
Test name
Test status
Simulation time 27164726252 ps
CPU time 11.27 seconds
Started Apr 25 01:41:46 PM PDT 24
Finished Apr 25 01:41:58 PM PDT 24
Peak memory 200372 kb
Host smart-6ffa22f4-0748-4423-b098-1dd8c633aa5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971132871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.1971132871
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.2713282615
Short name T804
Test name
Test status
Simulation time 20927095 ps
CPU time 0.56 seconds
Started Apr 25 01:36:07 PM PDT 24
Finished Apr 25 01:36:08 PM PDT 24
Peak memory 195856 kb
Host smart-a75b163c-68ee-4cf7-9454-faddc2bcef56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713282615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.2713282615
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.6545601
Short name T309
Test name
Test status
Simulation time 178778526667 ps
CPU time 32.35 seconds
Started Apr 25 01:35:59 PM PDT 24
Finished Apr 25 01:36:32 PM PDT 24
Peak memory 200368 kb
Host smart-8c764126-b08b-4cac-8d74-e04384170f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6545601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.6545601
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.2667018892
Short name T912
Test name
Test status
Simulation time 29661587405 ps
CPU time 52.17 seconds
Started Apr 25 01:36:00 PM PDT 24
Finished Apr 25 01:36:53 PM PDT 24
Peak memory 200432 kb
Host smart-18e0380b-eab8-4b93-bac3-3ad933778422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667018892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.2667018892
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.1999840071
Short name T856
Test name
Test status
Simulation time 146784850297 ps
CPU time 60.07 seconds
Started Apr 25 01:35:58 PM PDT 24
Finished Apr 25 01:36:59 PM PDT 24
Peak memory 200424 kb
Host smart-1cd6606b-0fb2-478c-ac0f-5cd5aa38f94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999840071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.1999840071
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.3371420675
Short name T576
Test name
Test status
Simulation time 112173746505 ps
CPU time 54.91 seconds
Started Apr 25 01:35:59 PM PDT 24
Finished Apr 25 01:36:54 PM PDT 24
Peak memory 200400 kb
Host smart-5b7b62a7-69ad-4ef0-a2f3-c33ba8b061b7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371420675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.3371420675
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.1146373076
Short name T635
Test name
Test status
Simulation time 143741446233 ps
CPU time 462.58 seconds
Started Apr 25 01:36:07 PM PDT 24
Finished Apr 25 01:43:50 PM PDT 24
Peak memory 200376 kb
Host smart-0b3f1852-4bfe-4173-b8c7-30a97f22f55c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1146373076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.1146373076
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.685510200
Short name T711
Test name
Test status
Simulation time 6965184941 ps
CPU time 3.59 seconds
Started Apr 25 01:35:59 PM PDT 24
Finished Apr 25 01:36:03 PM PDT 24
Peak memory 199864 kb
Host smart-bf7d5ab7-4bba-4919-a1ae-f5352a0bd180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685510200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.685510200
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.1347333849
Short name T889
Test name
Test status
Simulation time 32865366000 ps
CPU time 60.55 seconds
Started Apr 25 01:35:58 PM PDT 24
Finished Apr 25 01:36:59 PM PDT 24
Peak memory 199940 kb
Host smart-cea6df77-1bfe-400b-bada-11680a1a51e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347333849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.1347333849
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.3697623008
Short name T946
Test name
Test status
Simulation time 6615001227 ps
CPU time 206.11 seconds
Started Apr 25 01:36:05 PM PDT 24
Finished Apr 25 01:39:32 PM PDT 24
Peak memory 200428 kb
Host smart-c8830c35-5a2c-44c8-87d9-131784783734
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3697623008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.3697623008
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.3530611307
Short name T549
Test name
Test status
Simulation time 7139145794 ps
CPU time 62.29 seconds
Started Apr 25 01:35:59 PM PDT 24
Finished Apr 25 01:37:02 PM PDT 24
Peak memory 199888 kb
Host smart-94a781fd-70e8-4aef-9430-2c3fa70549f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3530611307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.3530611307
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.3663757787
Short name T3
Test name
Test status
Simulation time 16024826830 ps
CPU time 26.66 seconds
Started Apr 25 01:35:59 PM PDT 24
Finished Apr 25 01:36:26 PM PDT 24
Peak memory 200408 kb
Host smart-5893bb50-0ff7-46ad-b187-49268318d4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663757787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.3663757787
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.1855483310
Short name T1120
Test name
Test status
Simulation time 40388680395 ps
CPU time 16.11 seconds
Started Apr 25 01:36:00 PM PDT 24
Finished Apr 25 01:36:16 PM PDT 24
Peak memory 196444 kb
Host smart-829a52f7-3ae9-4bcf-8a7a-486fd5eaa9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855483310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.1855483310
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.163327013
Short name T468
Test name
Test status
Simulation time 951206425 ps
CPU time 1.59 seconds
Started Apr 25 01:35:57 PM PDT 24
Finished Apr 25 01:35:59 PM PDT 24
Peak memory 199716 kb
Host smart-1b8df7d1-13cc-43d8-8136-233034a6abc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163327013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.163327013
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.2833131273
Short name T143
Test name
Test status
Simulation time 324406752816 ps
CPU time 256.86 seconds
Started Apr 25 01:36:09 PM PDT 24
Finished Apr 25 01:40:26 PM PDT 24
Peak memory 200332 kb
Host smart-09b62aad-1371-449d-be77-1f8c67ad44d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833131273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2833131273
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.4216385080
Short name T346
Test name
Test status
Simulation time 1065670438 ps
CPU time 2.23 seconds
Started Apr 25 01:36:00 PM PDT 24
Finished Apr 25 01:36:02 PM PDT 24
Peak memory 199252 kb
Host smart-38fb432c-596b-4068-8f75-e975e7176435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216385080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.4216385080
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.2331204376
Short name T537
Test name
Test status
Simulation time 193885574946 ps
CPU time 63.32 seconds
Started Apr 25 01:35:59 PM PDT 24
Finished Apr 25 01:37:03 PM PDT 24
Peak memory 200404 kb
Host smart-9dfaa247-16db-42c5-8383-f7b138937f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331204376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.2331204376
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.591033241
Short name T961
Test name
Test status
Simulation time 13999884825 ps
CPU time 25.21 seconds
Started Apr 25 01:41:46 PM PDT 24
Finished Apr 25 01:42:12 PM PDT 24
Peak memory 200344 kb
Host smart-1011cdca-b7c0-424e-a1e0-b880a0caee5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591033241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.591033241
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.3946609996
Short name T1004
Test name
Test status
Simulation time 17438049313 ps
CPU time 27.3 seconds
Started Apr 25 01:41:46 PM PDT 24
Finished Apr 25 01:42:14 PM PDT 24
Peak memory 200380 kb
Host smart-4041406a-ff6a-4943-8f6a-be2c9137095c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946609996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.3946609996
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.4021257674
Short name T113
Test name
Test status
Simulation time 50666092793 ps
CPU time 97.24 seconds
Started Apr 25 01:41:46 PM PDT 24
Finished Apr 25 01:43:24 PM PDT 24
Peak memory 200460 kb
Host smart-53931e82-fa36-45ad-9142-159feff826e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021257674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.4021257674
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.3634207914
Short name T301
Test name
Test status
Simulation time 19652048500 ps
CPU time 8.92 seconds
Started Apr 25 01:41:47 PM PDT 24
Finished Apr 25 01:41:56 PM PDT 24
Peak memory 200420 kb
Host smart-13850186-8adf-44cd-b111-6472412ac631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634207914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.3634207914
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.407768086
Short name T663
Test name
Test status
Simulation time 140470583124 ps
CPU time 272.51 seconds
Started Apr 25 01:41:53 PM PDT 24
Finished Apr 25 01:46:26 PM PDT 24
Peak memory 200392 kb
Host smart-077b644f-57b9-4bff-bfaf-fbb472cbc0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407768086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.407768086
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.2940324757
Short name T124
Test name
Test status
Simulation time 40342114006 ps
CPU time 20.84 seconds
Started Apr 25 01:41:51 PM PDT 24
Finished Apr 25 01:42:13 PM PDT 24
Peak memory 200456 kb
Host smart-7a963aa2-ba3e-4239-af7c-b4cd499f3c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940324757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.2940324757
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.2436436004
Short name T1058
Test name
Test status
Simulation time 151319988514 ps
CPU time 249.24 seconds
Started Apr 25 01:41:51 PM PDT 24
Finished Apr 25 01:46:01 PM PDT 24
Peak memory 200424 kb
Host smart-7f6f8582-5d69-433b-a64d-6220698fab2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436436004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.2436436004
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.959766205
Short name T981
Test name
Test status
Simulation time 14999108 ps
CPU time 0.61 seconds
Started Apr 25 01:36:12 PM PDT 24
Finished Apr 25 01:36:14 PM PDT 24
Peak memory 195788 kb
Host smart-ea6f70ee-89e6-4bfd-8548-b1915af406ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959766205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.959766205
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.4049429505
Short name T1179
Test name
Test status
Simulation time 21697602650 ps
CPU time 12.38 seconds
Started Apr 25 01:36:05 PM PDT 24
Finished Apr 25 01:36:18 PM PDT 24
Peak memory 200340 kb
Host smart-2dca555f-3c5b-45cb-aa4e-169e38ee6246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049429505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.4049429505
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.1877323363
Short name T116
Test name
Test status
Simulation time 126117150099 ps
CPU time 61.05 seconds
Started Apr 25 01:36:06 PM PDT 24
Finished Apr 25 01:37:08 PM PDT 24
Peak memory 200404 kb
Host smart-453c42c0-c1fa-404a-bda7-52a5e0e341e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877323363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.1877323363
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.2663300
Short name T745
Test name
Test status
Simulation time 27794689154 ps
CPU time 40.1 seconds
Started Apr 25 01:36:07 PM PDT 24
Finished Apr 25 01:36:48 PM PDT 24
Peak memory 200388 kb
Host smart-1d93560f-fec1-4d2b-a862-b96e117dc4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.2663300
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.3123143219
Short name T452
Test name
Test status
Simulation time 11865819624 ps
CPU time 12.14 seconds
Started Apr 25 01:36:06 PM PDT 24
Finished Apr 25 01:36:19 PM PDT 24
Peak memory 200376 kb
Host smart-9eb9dbb3-50b3-461b-ab1c-2a08815a11a5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123143219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.3123143219
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.2054321012
Short name T1010
Test name
Test status
Simulation time 127502938716 ps
CPU time 905.48 seconds
Started Apr 25 01:36:13 PM PDT 24
Finished Apr 25 01:51:19 PM PDT 24
Peak memory 200408 kb
Host smart-c3d99078-ef14-431a-bb6e-6c9e284151d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2054321012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.2054321012
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.4023371917
Short name T1050
Test name
Test status
Simulation time 10922637150 ps
CPU time 12.84 seconds
Started Apr 25 01:36:14 PM PDT 24
Finished Apr 25 01:36:27 PM PDT 24
Peak memory 200080 kb
Host smart-c0606b63-518a-4297-8ded-86d87821b1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023371917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.4023371917
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.2101744064
Short name T466
Test name
Test status
Simulation time 21101165098 ps
CPU time 38.19 seconds
Started Apr 25 01:36:05 PM PDT 24
Finished Apr 25 01:36:44 PM PDT 24
Peak memory 199508 kb
Host smart-6020f922-96af-4bfd-8117-206ff7d8f2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101744064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.2101744064
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.2845729869
Short name T338
Test name
Test status
Simulation time 5212323331 ps
CPU time 265.13 seconds
Started Apr 25 01:36:14 PM PDT 24
Finished Apr 25 01:40:39 PM PDT 24
Peak memory 200352 kb
Host smart-d94e334a-f792-4c5c-ba19-87ba22cb3947
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2845729869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.2845729869
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.1643039281
Short name T1110
Test name
Test status
Simulation time 3623762754 ps
CPU time 6.96 seconds
Started Apr 25 01:36:08 PM PDT 24
Finished Apr 25 01:36:16 PM PDT 24
Peak memory 199264 kb
Host smart-2f24cc66-41f2-4801-b75b-ef0f3ae3dea4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1643039281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.1643039281
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.4236036714
Short name T1025
Test name
Test status
Simulation time 14579711075 ps
CPU time 23.62 seconds
Started Apr 25 01:36:09 PM PDT 24
Finished Apr 25 01:36:33 PM PDT 24
Peak memory 198664 kb
Host smart-aabdcc50-1c1a-4000-81b2-506c3ad647f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236036714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.4236036714
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.4013790594
Short name T1078
Test name
Test status
Simulation time 4964469284 ps
CPU time 4.57 seconds
Started Apr 25 01:36:05 PM PDT 24
Finished Apr 25 01:36:11 PM PDT 24
Peak memory 196416 kb
Host smart-e5709bbb-d03c-42d8-83e7-c6176e436e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013790594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.4013790594
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.1341585710
Short name T697
Test name
Test status
Simulation time 954250552 ps
CPU time 1.81 seconds
Started Apr 25 01:36:08 PM PDT 24
Finished Apr 25 01:36:10 PM PDT 24
Peak memory 199852 kb
Host smart-9b921b39-5216-4132-9195-7d17e4f7010e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341585710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.1341585710
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.3376452810
Short name T147
Test name
Test status
Simulation time 120094746307 ps
CPU time 2085.72 seconds
Started Apr 25 01:36:14 PM PDT 24
Finished Apr 25 02:11:00 PM PDT 24
Peak memory 200388 kb
Host smart-641622e1-eac6-4cf5-9f2e-e42c799478f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376452810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.3376452810
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.2167394773
Short name T891
Test name
Test status
Simulation time 452836957835 ps
CPU time 1103.8 seconds
Started Apr 25 01:36:11 PM PDT 24
Finished Apr 25 01:54:35 PM PDT 24
Peak memory 227772 kb
Host smart-075aaff4-6894-40ef-95e7-0fb95a3f4f4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167394773 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.2167394773
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.1335034885
Short name T999
Test name
Test status
Simulation time 7623665261 ps
CPU time 9.32 seconds
Started Apr 25 01:36:12 PM PDT 24
Finished Apr 25 01:36:23 PM PDT 24
Peak memory 200332 kb
Host smart-47f3b093-f37e-4ff7-9244-c5eb02e95859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335034885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.1335034885
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.724768412
Short name T303
Test name
Test status
Simulation time 97758428211 ps
CPU time 138.26 seconds
Started Apr 25 01:36:07 PM PDT 24
Finished Apr 25 01:38:26 PM PDT 24
Peak memory 200464 kb
Host smart-7e13b2a3-c957-428d-9b5c-1e0a47685020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724768412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.724768412
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.540729411
Short name T163
Test name
Test status
Simulation time 55576637217 ps
CPU time 27.22 seconds
Started Apr 25 01:41:50 PM PDT 24
Finished Apr 25 01:42:18 PM PDT 24
Peak memory 200416 kb
Host smart-dbe8a7fd-ebf7-4e6d-a489-93b98279c336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540729411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.540729411
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.1726245589
Short name T872
Test name
Test status
Simulation time 101957008116 ps
CPU time 155.43 seconds
Started Apr 25 01:41:53 PM PDT 24
Finished Apr 25 01:44:29 PM PDT 24
Peak memory 200464 kb
Host smart-7c6a6e3c-47af-45d1-be05-dd19f50e4187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726245589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.1726245589
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.2669815905
Short name T12
Test name
Test status
Simulation time 133277212777 ps
CPU time 32.52 seconds
Started Apr 25 01:41:53 PM PDT 24
Finished Apr 25 01:42:26 PM PDT 24
Peak memory 200364 kb
Host smart-344fcc26-a997-45fe-9c86-a7e5f35fc796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669815905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.2669815905
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.3552209742
Short name T220
Test name
Test status
Simulation time 16641841165 ps
CPU time 11.39 seconds
Started Apr 25 01:41:53 PM PDT 24
Finished Apr 25 01:42:05 PM PDT 24
Peak memory 200432 kb
Host smart-cd5ab122-212a-40a0-9e2f-b20a77f3f8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552209742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.3552209742
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.1120508662
Short name T826
Test name
Test status
Simulation time 17497576603 ps
CPU time 30.49 seconds
Started Apr 25 01:41:52 PM PDT 24
Finished Apr 25 01:42:23 PM PDT 24
Peak memory 200240 kb
Host smart-953bab18-6cb6-4b0b-b6bb-602f53b02b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120508662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1120508662
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.2089908551
Short name T543
Test name
Test status
Simulation time 92301416900 ps
CPU time 82.26 seconds
Started Apr 25 01:41:50 PM PDT 24
Finished Apr 25 01:43:13 PM PDT 24
Peak memory 200412 kb
Host smart-40e4967f-0780-48af-8795-7c778816cda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089908551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.2089908551
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.3620636550
Short name T899
Test name
Test status
Simulation time 77783848382 ps
CPU time 221.29 seconds
Started Apr 25 01:41:51 PM PDT 24
Finished Apr 25 01:45:33 PM PDT 24
Peak memory 200372 kb
Host smart-47163455-0300-4f3b-9598-0f075132e4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620636550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.3620636550
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.694138056
Short name T1042
Test name
Test status
Simulation time 19778497245 ps
CPU time 39.85 seconds
Started Apr 25 01:41:51 PM PDT 24
Finished Apr 25 01:42:32 PM PDT 24
Peak memory 200172 kb
Host smart-71cd3e80-708f-4c93-b4a2-c1016bcab3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694138056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.694138056
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.3200308354
Short name T478
Test name
Test status
Simulation time 215290829535 ps
CPU time 53.95 seconds
Started Apr 25 01:41:53 PM PDT 24
Finished Apr 25 01:42:47 PM PDT 24
Peak memory 200440 kb
Host smart-5b779ae0-af27-41dc-85e8-e20dbfe273f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200308354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.3200308354
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.3284854030
Short name T669
Test name
Test status
Simulation time 4499517302 ps
CPU time 9.72 seconds
Started Apr 25 01:41:56 PM PDT 24
Finished Apr 25 01:42:06 PM PDT 24
Peak memory 200416 kb
Host smart-35508c1b-95f4-43e6-8b8e-22fcc7f62408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284854030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.3284854030
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.1762863790
Short name T331
Test name
Test status
Simulation time 21042305 ps
CPU time 0.55 seconds
Started Apr 25 01:36:25 PM PDT 24
Finished Apr 25 01:36:26 PM PDT 24
Peak memory 195800 kb
Host smart-b7a7d5f8-c796-48e5-8dc3-5f18c84f167e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762863790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.1762863790
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.709167063
Short name T929
Test name
Test status
Simulation time 123557703893 ps
CPU time 49.51 seconds
Started Apr 25 01:36:13 PM PDT 24
Finished Apr 25 01:37:03 PM PDT 24
Peak memory 200340 kb
Host smart-514ce2b0-3e10-4d64-b5f6-69e69c8ce2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709167063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.709167063
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.3341182828
Short name T587
Test name
Test status
Simulation time 207292812594 ps
CPU time 305.25 seconds
Started Apr 25 01:36:11 PM PDT 24
Finished Apr 25 01:41:17 PM PDT 24
Peak memory 200400 kb
Host smart-749e84c2-6e16-49e9-91ee-df057546d81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341182828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.3341182828
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.2201702117
Short name T1134
Test name
Test status
Simulation time 36436801548 ps
CPU time 66.61 seconds
Started Apr 25 01:36:19 PM PDT 24
Finished Apr 25 01:37:26 PM PDT 24
Peak memory 200432 kb
Host smart-3b399d7d-9553-4a7b-9fc5-d64217bb4336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201702117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.2201702117
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.396500096
Short name T807
Test name
Test status
Simulation time 105008392968 ps
CPU time 195.83 seconds
Started Apr 25 01:36:21 PM PDT 24
Finished Apr 25 01:39:37 PM PDT 24
Peak memory 200404 kb
Host smart-a6bc0682-a11c-46c9-b721-5bc109e73834
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396500096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.396500096
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.1329493223
Short name T372
Test name
Test status
Simulation time 30539792917 ps
CPU time 106.44 seconds
Started Apr 25 01:36:25 PM PDT 24
Finished Apr 25 01:38:12 PM PDT 24
Peak memory 200468 kb
Host smart-85000844-0df0-4da0-9b6b-430436af96e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1329493223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1329493223
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.2107815041
Short name T713
Test name
Test status
Simulation time 1008263366 ps
CPU time 1.07 seconds
Started Apr 25 01:36:18 PM PDT 24
Finished Apr 25 01:36:20 PM PDT 24
Peak memory 196412 kb
Host smart-030bb711-e42a-4eb1-9ac0-d89fbfcf77b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107815041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.2107815041
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.2701285883
Short name T291
Test name
Test status
Simulation time 111581018227 ps
CPU time 249.43 seconds
Started Apr 25 01:36:19 PM PDT 24
Finished Apr 25 01:40:29 PM PDT 24
Peak memory 199684 kb
Host smart-a1f077cd-a590-4e60-805c-1aa1810f12c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701285883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.2701285883
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.703587402
Short name T791
Test name
Test status
Simulation time 19420225774 ps
CPU time 984.54 seconds
Started Apr 25 01:36:25 PM PDT 24
Finished Apr 25 01:52:50 PM PDT 24
Peak memory 200348 kb
Host smart-f9178bfc-a77c-41d4-832e-4be713a460b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=703587402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.703587402
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.169239937
Short name T430
Test name
Test status
Simulation time 1487842952 ps
CPU time 6.05 seconds
Started Apr 25 01:36:18 PM PDT 24
Finished Apr 25 01:36:25 PM PDT 24
Peak memory 198228 kb
Host smart-31855bf0-4298-49f5-886c-6c1087282f9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=169239937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.169239937
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.4151058613
Short name T506
Test name
Test status
Simulation time 46657142734 ps
CPU time 33.64 seconds
Started Apr 25 01:36:21 PM PDT 24
Finished Apr 25 01:36:55 PM PDT 24
Peak memory 199780 kb
Host smart-6a18ec90-0508-435c-b463-f228099b78ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151058613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.4151058613
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.895141835
Short name T823
Test name
Test status
Simulation time 3280545301 ps
CPU time 2.1 seconds
Started Apr 25 01:36:22 PM PDT 24
Finished Apr 25 01:36:24 PM PDT 24
Peak memory 196400 kb
Host smart-635d1992-6ccc-44ed-87bd-0b6bae253adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895141835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.895141835
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.1027263395
Short name T1021
Test name
Test status
Simulation time 278759888 ps
CPU time 1 seconds
Started Apr 25 01:36:12 PM PDT 24
Finished Apr 25 01:36:13 PM PDT 24
Peak memory 198932 kb
Host smart-72d47b5b-29bf-459d-ba93-391ff9df18ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027263395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.1027263395
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.970806299
Short name T153
Test name
Test status
Simulation time 191599875394 ps
CPU time 309.38 seconds
Started Apr 25 01:36:25 PM PDT 24
Finished Apr 25 01:41:35 PM PDT 24
Peak memory 200420 kb
Host smart-a39bf21b-f05e-40bb-a7d0-fa9abc8509bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970806299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.970806299
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.2576291586
Short name T621
Test name
Test status
Simulation time 98502064446 ps
CPU time 600.25 seconds
Started Apr 25 01:36:26 PM PDT 24
Finished Apr 25 01:46:27 PM PDT 24
Peak memory 216884 kb
Host smart-95e17af8-ada6-46a3-bb76-a73c009c8573
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576291586 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.2576291586
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.314617425
Short name T833
Test name
Test status
Simulation time 721353820 ps
CPU time 2.16 seconds
Started Apr 25 01:36:19 PM PDT 24
Finished Apr 25 01:36:22 PM PDT 24
Peak memory 199488 kb
Host smart-f23e1e89-c111-4d8c-8b45-bd4ae102115d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314617425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.314617425
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.767442154
Short name T949
Test name
Test status
Simulation time 111613398025 ps
CPU time 243.8 seconds
Started Apr 25 01:36:10 PM PDT 24
Finished Apr 25 01:40:15 PM PDT 24
Peak memory 200440 kb
Host smart-58f1767f-de58-447c-b775-2f0dc6fe23d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767442154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.767442154
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.896825774
Short name T1055
Test name
Test status
Simulation time 152859403638 ps
CPU time 121.87 seconds
Started Apr 25 01:41:58 PM PDT 24
Finished Apr 25 01:44:01 PM PDT 24
Peak memory 200392 kb
Host smart-cb7ec207-143d-4c1d-b57c-b09a0a7b0693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896825774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.896825774
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3013882363
Short name T185
Test name
Test status
Simulation time 132385034731 ps
CPU time 237.86 seconds
Started Apr 25 01:41:58 PM PDT 24
Finished Apr 25 01:45:56 PM PDT 24
Peak memory 200428 kb
Host smart-be2ac730-94f1-45d4-83ec-dec971f3f28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013882363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3013882363
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.1964020259
Short name T729
Test name
Test status
Simulation time 146755435183 ps
CPU time 31.37 seconds
Started Apr 25 01:41:59 PM PDT 24
Finished Apr 25 01:42:31 PM PDT 24
Peak memory 198788 kb
Host smart-183d3c48-b62d-4254-b3d4-b76e87d10c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964020259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.1964020259
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.2818339968
Short name T149
Test name
Test status
Simulation time 52134430912 ps
CPU time 83.89 seconds
Started Apr 25 01:41:58 PM PDT 24
Finished Apr 25 01:43:22 PM PDT 24
Peak memory 200416 kb
Host smart-735b9921-307d-413e-818e-475ef791e812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818339968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2818339968
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.661121109
Short name T989
Test name
Test status
Simulation time 23835276817 ps
CPU time 11.6 seconds
Started Apr 25 01:41:59 PM PDT 24
Finished Apr 25 01:42:11 PM PDT 24
Peak memory 200372 kb
Host smart-98552d43-48cb-4c58-ac61-47ca3874929e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661121109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.661121109
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.998226896
Short name T661
Test name
Test status
Simulation time 35246216516 ps
CPU time 54.59 seconds
Started Apr 25 01:41:58 PM PDT 24
Finished Apr 25 01:42:53 PM PDT 24
Peak memory 200412 kb
Host smart-210ec763-cf4e-433a-a0c1-3d90a8f6c46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998226896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.998226896
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.2522512938
Short name T730
Test name
Test status
Simulation time 12591615426 ps
CPU time 9.91 seconds
Started Apr 25 01:41:59 PM PDT 24
Finished Apr 25 01:42:09 PM PDT 24
Peak memory 200436 kb
Host smart-d5e89ecf-cc47-4a53-a73b-5f987d1a55b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522512938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.2522512938
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.3851584879
Short name T394
Test name
Test status
Simulation time 17718686715 ps
CPU time 8.35 seconds
Started Apr 25 01:41:58 PM PDT 24
Finished Apr 25 01:42:07 PM PDT 24
Peak memory 200076 kb
Host smart-792564bf-08bb-4670-945b-8dc29f3e22b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851584879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3851584879
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.3673653140
Short name T866
Test name
Test status
Simulation time 48478066518 ps
CPU time 72.35 seconds
Started Apr 25 01:41:59 PM PDT 24
Finished Apr 25 01:43:12 PM PDT 24
Peak memory 200356 kb
Host smart-c6ce3e50-0ff8-497c-b1b5-9a37a2d3bcb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673653140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.3673653140
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.1854303091
Short name T20
Test name
Test status
Simulation time 137419669 ps
CPU time 0.57 seconds
Started Apr 25 01:36:32 PM PDT 24
Finished Apr 25 01:36:33 PM PDT 24
Peak memory 195792 kb
Host smart-8e1ccf2c-2665-4b26-985b-6648136a20bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854303091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.1854303091
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.2246819484
Short name T690
Test name
Test status
Simulation time 54277302546 ps
CPU time 38.75 seconds
Started Apr 25 01:36:33 PM PDT 24
Finished Apr 25 01:37:12 PM PDT 24
Peak memory 200400 kb
Host smart-6ffd108a-aa92-4d14-a822-5dd220f51553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246819484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.2246819484
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.399167774
Short name T85
Test name
Test status
Simulation time 76848694899 ps
CPU time 29.32 seconds
Started Apr 25 01:36:35 PM PDT 24
Finished Apr 25 01:37:05 PM PDT 24
Peak memory 200424 kb
Host smart-815db527-d18a-461f-b49c-937da2bcf9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399167774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.399167774
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.2947448651
Short name T388
Test name
Test status
Simulation time 40855285167 ps
CPU time 18.98 seconds
Started Apr 25 01:36:25 PM PDT 24
Finished Apr 25 01:36:45 PM PDT 24
Peak memory 200076 kb
Host smart-a3297277-99f6-40f2-862d-6b1d9877d515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947448651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.2947448651
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.1418315144
Short name T625
Test name
Test status
Simulation time 19123330098 ps
CPU time 19.75 seconds
Started Apr 25 01:36:24 PM PDT 24
Finished Apr 25 01:36:44 PM PDT 24
Peak memory 199672 kb
Host smart-ca0d33f7-dbd6-44fc-9fa6-46d857556542
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418315144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.1418315144
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.4036532943
Short name T673
Test name
Test status
Simulation time 91378911833 ps
CPU time 659.96 seconds
Started Apr 25 01:36:31 PM PDT 24
Finished Apr 25 01:47:32 PM PDT 24
Peak memory 200404 kb
Host smart-2ffc3b3a-12f3-4e8b-b919-30173fec032e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4036532943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.4036532943
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.2108656992
Short name T349
Test name
Test status
Simulation time 7514248773 ps
CPU time 4.96 seconds
Started Apr 25 01:36:32 PM PDT 24
Finished Apr 25 01:36:38 PM PDT 24
Peak memory 200196 kb
Host smart-22c7c78e-630f-4fc4-bdc7-924c14007500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108656992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.2108656992
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.2057298517
Short name T431
Test name
Test status
Simulation time 72911603434 ps
CPU time 59.44 seconds
Started Apr 25 01:36:24 PM PDT 24
Finished Apr 25 01:37:24 PM PDT 24
Peak memory 200624 kb
Host smart-ffdbbc3f-a23b-4cb0-87f4-36b76fa20b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057298517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.2057298517
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.174794437
Short name T901
Test name
Test status
Simulation time 37056464497 ps
CPU time 1985.01 seconds
Started Apr 25 01:36:33 PM PDT 24
Finished Apr 25 02:09:39 PM PDT 24
Peak memory 200416 kb
Host smart-2b142f60-7b34-4307-a1b7-6fde769309a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=174794437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.174794437
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.4061908216
Short name T556
Test name
Test status
Simulation time 1937549849 ps
CPU time 2.2 seconds
Started Apr 25 01:36:24 PM PDT 24
Finished Apr 25 01:36:27 PM PDT 24
Peak memory 198876 kb
Host smart-88bd179d-34b0-4f95-9e99-f6c657cbd6e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4061908216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.4061908216
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.2108100635
Short name T426
Test name
Test status
Simulation time 32520568125 ps
CPU time 14.53 seconds
Started Apr 25 01:36:35 PM PDT 24
Finished Apr 25 01:36:50 PM PDT 24
Peak memory 200428 kb
Host smart-50d41eed-e314-4035-8414-db623179debe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108100635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.2108100635
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.163542901
Short name T1074
Test name
Test status
Simulation time 2256509665 ps
CPU time 1.08 seconds
Started Apr 25 01:36:31 PM PDT 24
Finished Apr 25 01:36:33 PM PDT 24
Peak memory 195852 kb
Host smart-87549fda-58c8-459b-8282-417a62cc0068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163542901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.163542901
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.3780869983
Short name T646
Test name
Test status
Simulation time 284816655 ps
CPU time 1.04 seconds
Started Apr 25 01:36:24 PM PDT 24
Finished Apr 25 01:36:25 PM PDT 24
Peak memory 198604 kb
Host smart-61a47dfa-837c-4b3e-8fe2-b3734e2f1fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780869983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.3780869983
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.1457611457
Short name T100
Test name
Test status
Simulation time 504900452603 ps
CPU time 959.12 seconds
Started Apr 25 01:36:31 PM PDT 24
Finished Apr 25 01:52:30 PM PDT 24
Peak memory 216972 kb
Host smart-5abc3fe2-00d1-4cf4-b578-ec96172786c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457611457 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.1457611457
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.3860590037
Short name T474
Test name
Test status
Simulation time 6252038960 ps
CPU time 25.55 seconds
Started Apr 25 01:36:31 PM PDT 24
Finished Apr 25 01:36:57 PM PDT 24
Peak memory 199696 kb
Host smart-c41fb1f1-0880-48d4-b86c-803087f92d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860590037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.3860590037
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.3369780151
Short name T1144
Test name
Test status
Simulation time 21374768117 ps
CPU time 20.43 seconds
Started Apr 25 01:36:26 PM PDT 24
Finished Apr 25 01:36:47 PM PDT 24
Peak memory 200332 kb
Host smart-eed4bca3-3fe0-4046-8107-993a02e2d95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369780151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.3369780151
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.2097764707
Short name T322
Test name
Test status
Simulation time 152359155511 ps
CPU time 64.43 seconds
Started Apr 25 01:41:59 PM PDT 24
Finished Apr 25 01:43:04 PM PDT 24
Peak memory 200420 kb
Host smart-d13a7fda-802f-49c9-a6b0-26f19ed35491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097764707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.2097764707
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.1260642897
Short name T707
Test name
Test status
Simulation time 160671789664 ps
CPU time 247.84 seconds
Started Apr 25 01:42:05 PM PDT 24
Finished Apr 25 01:46:14 PM PDT 24
Peak memory 200392 kb
Host smart-15ebfea4-6c0d-4c0b-a322-ad9491695676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260642897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.1260642897
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.2673436309
Short name T835
Test name
Test status
Simulation time 381236184218 ps
CPU time 56.35 seconds
Started Apr 25 01:42:05 PM PDT 24
Finished Apr 25 01:43:02 PM PDT 24
Peak memory 200276 kb
Host smart-8b9328f7-83b1-42ab-b38f-9d396aa95fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673436309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.2673436309
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.784473168
Short name T194
Test name
Test status
Simulation time 126200078120 ps
CPU time 246.94 seconds
Started Apr 25 01:42:06 PM PDT 24
Finished Apr 25 01:46:13 PM PDT 24
Peak memory 200396 kb
Host smart-c00dd4be-9f00-4347-abbb-3f0d7d8113d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784473168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.784473168
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.2591714847
Short name T509
Test name
Test status
Simulation time 24617578252 ps
CPU time 41.13 seconds
Started Apr 25 01:42:06 PM PDT 24
Finished Apr 25 01:42:48 PM PDT 24
Peak memory 200424 kb
Host smart-1baa67d0-f040-4158-ba5a-3f49ccecee05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591714847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.2591714847
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.3792773264
Short name T531
Test name
Test status
Simulation time 50675164802 ps
CPU time 11.52 seconds
Started Apr 25 01:42:04 PM PDT 24
Finished Apr 25 01:42:16 PM PDT 24
Peak memory 200364 kb
Host smart-162224b1-5cd8-41c6-9f48-382c243d076d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792773264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.3792773264
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.2827983543
Short name T160
Test name
Test status
Simulation time 62441514117 ps
CPU time 27.62 seconds
Started Apr 25 01:42:06 PM PDT 24
Finished Apr 25 01:42:34 PM PDT 24
Peak memory 199932 kb
Host smart-ec4a4a00-c0ec-4b79-a977-2de76eb050d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827983543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.2827983543
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.2804360268
Short name T748
Test name
Test status
Simulation time 59384213297 ps
CPU time 23.76 seconds
Started Apr 25 01:42:06 PM PDT 24
Finished Apr 25 01:42:30 PM PDT 24
Peak memory 200264 kb
Host smart-bf30f627-4f5d-4dad-be14-905960cb0dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804360268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.2804360268
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.506611265
Short name T40
Test name
Test status
Simulation time 206372684993 ps
CPU time 151.97 seconds
Started Apr 25 01:42:13 PM PDT 24
Finished Apr 25 01:44:46 PM PDT 24
Peak memory 200388 kb
Host smart-9ff607d1-956d-409f-8591-c92ca01486a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506611265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.506611265
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.2745138089
Short name T765
Test name
Test status
Simulation time 12932630 ps
CPU time 0.55 seconds
Started Apr 25 01:36:37 PM PDT 24
Finished Apr 25 01:36:38 PM PDT 24
Peak memory 195196 kb
Host smart-fa3a6539-545e-4d03-b73a-c8d69bb111fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745138089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.2745138089
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.873079131
Short name T648
Test name
Test status
Simulation time 52062713523 ps
CPU time 11.83 seconds
Started Apr 25 01:36:35 PM PDT 24
Finished Apr 25 01:36:48 PM PDT 24
Peak memory 200432 kb
Host smart-c176cec0-1083-48aa-a9ac-bba8e3566a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873079131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.873079131
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.278178174
Short name T992
Test name
Test status
Simulation time 92370589405 ps
CPU time 41.03 seconds
Started Apr 25 01:36:31 PM PDT 24
Finished Apr 25 01:37:13 PM PDT 24
Peak memory 200432 kb
Host smart-0268f207-4018-4d96-abf7-01a4bca31456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278178174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.278178174
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.3018802969
Short name T440
Test name
Test status
Simulation time 47862997855 ps
CPU time 20.82 seconds
Started Apr 25 01:36:30 PM PDT 24
Finished Apr 25 01:36:52 PM PDT 24
Peak memory 200404 kb
Host smart-dc6c33c1-0508-4f34-b27e-b3f3568b33d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018802969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.3018802969
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.2260756894
Short name T1000
Test name
Test status
Simulation time 109421838533 ps
CPU time 40.84 seconds
Started Apr 25 01:36:30 PM PDT 24
Finished Apr 25 01:37:11 PM PDT 24
Peak memory 196492 kb
Host smart-4648812f-ea1e-488b-8dbd-bc9d1d7af87a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260756894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.2260756894
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.2435184397
Short name T861
Test name
Test status
Simulation time 85165094609 ps
CPU time 742.64 seconds
Started Apr 25 01:36:38 PM PDT 24
Finished Apr 25 01:49:02 PM PDT 24
Peak memory 200436 kb
Host smart-661290b7-2133-4198-af3b-83167388659c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2435184397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.2435184397
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.2692491035
Short name T689
Test name
Test status
Simulation time 190338825 ps
CPU time 1.26 seconds
Started Apr 25 01:36:36 PM PDT 24
Finished Apr 25 01:36:38 PM PDT 24
Peak memory 197636 kb
Host smart-3ecb2fd1-c012-4e51-856f-398e428dc44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692491035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.2692491035
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.2727188314
Short name T69
Test name
Test status
Simulation time 125333008460 ps
CPU time 123.13 seconds
Started Apr 25 01:36:38 PM PDT 24
Finished Apr 25 01:38:42 PM PDT 24
Peak memory 200284 kb
Host smart-cc4c86f9-9cb7-496c-8dd5-a50c25b9b128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727188314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.2727188314
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.3534097484
Short name T8
Test name
Test status
Simulation time 13579485280 ps
CPU time 781.95 seconds
Started Apr 25 01:36:36 PM PDT 24
Finished Apr 25 01:49:39 PM PDT 24
Peak memory 200352 kb
Host smart-57d10451-de64-4879-bf0c-4560c1635436
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3534097484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.3534097484
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.2888564620
Short name T554
Test name
Test status
Simulation time 3572978737 ps
CPU time 26.55 seconds
Started Apr 25 01:36:33 PM PDT 24
Finished Apr 25 01:37:00 PM PDT 24
Peak memory 199540 kb
Host smart-f3d61258-f3f5-4c3d-b36b-10f3940e1f0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2888564620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.2888564620
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.1492706374
Short name T573
Test name
Test status
Simulation time 218553548039 ps
CPU time 440.76 seconds
Started Apr 25 01:36:37 PM PDT 24
Finished Apr 25 01:43:59 PM PDT 24
Peak memory 200368 kb
Host smart-1f068789-868a-4a2f-aea0-3ed0a5fbdf97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492706374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.1492706374
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.624430978
Short name T1115
Test name
Test status
Simulation time 39174606814 ps
CPU time 65.65 seconds
Started Apr 25 01:36:38 PM PDT 24
Finished Apr 25 01:37:44 PM PDT 24
Peak memory 196728 kb
Host smart-c6ef7f5d-19b4-4c0d-82b3-97cac71b19e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624430978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.624430978
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.3541544147
Short name T336
Test name
Test status
Simulation time 474796317 ps
CPU time 1.85 seconds
Started Apr 25 01:36:32 PM PDT 24
Finished Apr 25 01:36:34 PM PDT 24
Peak memory 199276 kb
Host smart-0a02ecea-7225-46e4-870f-f40860cda771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541544147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.3541544147
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.1372616546
Short name T174
Test name
Test status
Simulation time 199483181330 ps
CPU time 274.73 seconds
Started Apr 25 01:36:39 PM PDT 24
Finished Apr 25 01:41:14 PM PDT 24
Peak memory 200584 kb
Host smart-a9f9d336-3926-4a4b-be2e-6e251b947acc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372616546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.1372616546
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.3521175125
Short name T715
Test name
Test status
Simulation time 113860769163 ps
CPU time 639.14 seconds
Started Apr 25 01:36:38 PM PDT 24
Finished Apr 25 01:47:18 PM PDT 24
Peak memory 216896 kb
Host smart-c6ab6c89-8095-446d-be64-8b5e4f8e1e94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521175125 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.3521175125
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.440677876
Short name T377
Test name
Test status
Simulation time 1015604513 ps
CPU time 1.99 seconds
Started Apr 25 01:36:37 PM PDT 24
Finished Apr 25 01:36:39 PM PDT 24
Peak memory 199252 kb
Host smart-173fed6f-b69e-405d-9070-c6bd36f80adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440677876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.440677876
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.3964158687
Short name T761
Test name
Test status
Simulation time 159614347957 ps
CPU time 73.33 seconds
Started Apr 25 01:36:33 PM PDT 24
Finished Apr 25 01:37:47 PM PDT 24
Peak memory 200432 kb
Host smart-1104ba82-0bba-482f-807a-5e83e944be8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964158687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.3964158687
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.3026818869
Short name T1087
Test name
Test status
Simulation time 16493286161 ps
CPU time 26.25 seconds
Started Apr 25 01:42:16 PM PDT 24
Finished Apr 25 01:42:43 PM PDT 24
Peak memory 200332 kb
Host smart-c17de871-e026-480f-af99-e3a1f53f1646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026818869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.3026818869
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.4097478562
Short name T881
Test name
Test status
Simulation time 30115739081 ps
CPU time 48.65 seconds
Started Apr 25 01:42:13 PM PDT 24
Finished Apr 25 01:43:02 PM PDT 24
Peak memory 200400 kb
Host smart-75e05a45-fd65-40b9-95b8-24299b7c89c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097478562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.4097478562
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.2092427715
Short name T581
Test name
Test status
Simulation time 139100224889 ps
CPU time 63.52 seconds
Started Apr 25 01:42:14 PM PDT 24
Finished Apr 25 01:43:18 PM PDT 24
Peak memory 200180 kb
Host smart-9f227b98-0254-4b6f-ac7c-a2846019a593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092427715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.2092427715
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.969462740
Short name T515
Test name
Test status
Simulation time 274673459218 ps
CPU time 85.92 seconds
Started Apr 25 01:42:13 PM PDT 24
Finished Apr 25 01:43:40 PM PDT 24
Peak memory 200384 kb
Host smart-543b2e0c-86ae-4cf5-95df-6e6e374758b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969462740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.969462740
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.1340604382
Short name T271
Test name
Test status
Simulation time 152858057978 ps
CPU time 61.49 seconds
Started Apr 25 01:42:16 PM PDT 24
Finished Apr 25 01:43:19 PM PDT 24
Peak memory 200172 kb
Host smart-bb09d997-369c-46a4-890b-1e5c2531efc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340604382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.1340604382
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.2864211543
Short name T308
Test name
Test status
Simulation time 161734805527 ps
CPU time 147.61 seconds
Started Apr 25 01:42:14 PM PDT 24
Finished Apr 25 01:44:42 PM PDT 24
Peak memory 200284 kb
Host smart-3451536e-a9ca-4158-af2f-b712f468a0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864211543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.2864211543
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.3128217564
Short name T895
Test name
Test status
Simulation time 342950642447 ps
CPU time 54.55 seconds
Started Apr 25 01:42:13 PM PDT 24
Finished Apr 25 01:43:08 PM PDT 24
Peak memory 200348 kb
Host smart-aeb67435-f148-42e8-971e-f8a4ccc5e22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128217564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.3128217564
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.3222311053
Short name T855
Test name
Test status
Simulation time 23025726281 ps
CPU time 15.95 seconds
Started Apr 25 01:42:13 PM PDT 24
Finished Apr 25 01:42:30 PM PDT 24
Peak memory 200424 kb
Host smart-2be2b334-cfcc-4124-ad6a-3a99d877f075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222311053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.3222311053
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.1954174055
Short name T492
Test name
Test status
Simulation time 49852822660 ps
CPU time 126.93 seconds
Started Apr 25 01:42:12 PM PDT 24
Finished Apr 25 01:44:20 PM PDT 24
Peak memory 200352 kb
Host smart-592e5503-8b57-48fa-ae16-e427c605e6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954174055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.1954174055
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.2105442472
Short name T978
Test name
Test status
Simulation time 17114517 ps
CPU time 0.56 seconds
Started Apr 25 01:36:44 PM PDT 24
Finished Apr 25 01:36:46 PM PDT 24
Peak memory 195788 kb
Host smart-8cc7d941-12eb-42a1-8411-0ae2e64f293c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105442472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.2105442472
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.49916142
Short name T482
Test name
Test status
Simulation time 255262036153 ps
CPU time 89.18 seconds
Started Apr 25 01:36:38 PM PDT 24
Finished Apr 25 01:38:08 PM PDT 24
Peak memory 200328 kb
Host smart-6e009ee9-358e-4471-9702-05eff1891852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49916142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.49916142
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.1975899833
Short name T546
Test name
Test status
Simulation time 134515386669 ps
CPU time 125.12 seconds
Started Apr 25 01:36:37 PM PDT 24
Finished Apr 25 01:38:43 PM PDT 24
Peak memory 200308 kb
Host smart-e45d1131-2f94-467a-a04d-9402fcac65d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975899833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.1975899833
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.3073739138
Short name T1079
Test name
Test status
Simulation time 20931380798 ps
CPU time 39.43 seconds
Started Apr 25 01:36:44 PM PDT 24
Finished Apr 25 01:37:24 PM PDT 24
Peak memory 200344 kb
Host smart-c2081cb7-9202-4119-9d7d-a0b87c83799b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073739138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.3073739138
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.706761398
Short name T867
Test name
Test status
Simulation time 108742524552 ps
CPU time 437.39 seconds
Started Apr 25 01:36:44 PM PDT 24
Finished Apr 25 01:44:02 PM PDT 24
Peak memory 200464 kb
Host smart-12e12084-3ee3-4f20-9a35-ea9044045701
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=706761398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.706761398
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.1245504195
Short name T880
Test name
Test status
Simulation time 2236004320 ps
CPU time 4.81 seconds
Started Apr 25 01:36:50 PM PDT 24
Finished Apr 25 01:36:56 PM PDT 24
Peak memory 198284 kb
Host smart-ef864dde-2693-4219-83a4-b7d9bacf6177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245504195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.1245504195
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.1096383006
Short name T841
Test name
Test status
Simulation time 68326562953 ps
CPU time 38.42 seconds
Started Apr 25 01:36:43 PM PDT 24
Finished Apr 25 01:37:22 PM PDT 24
Peak memory 200600 kb
Host smart-4b85d99e-c450-41ee-8bd4-5c9f5ef4f760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096383006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.1096383006
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.4235016898
Short name T1138
Test name
Test status
Simulation time 17596908645 ps
CPU time 738.53 seconds
Started Apr 25 01:36:45 PM PDT 24
Finished Apr 25 01:49:04 PM PDT 24
Peak memory 200408 kb
Host smart-19da9744-d5d1-4e4f-b68d-2ceb5a562d89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4235016898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.4235016898
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.4190593221
Short name T812
Test name
Test status
Simulation time 7454959677 ps
CPU time 4.56 seconds
Started Apr 25 01:36:45 PM PDT 24
Finished Apr 25 01:36:50 PM PDT 24
Peak memory 198620 kb
Host smart-aa5dc0c0-a085-495d-85a3-a0c8da2690d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4190593221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.4190593221
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.4042691390
Short name T72
Test name
Test status
Simulation time 44624026647 ps
CPU time 26.96 seconds
Started Apr 25 01:36:43 PM PDT 24
Finished Apr 25 01:37:10 PM PDT 24
Peak memory 200436 kb
Host smart-366c05e5-9cc4-42e5-9b6f-dd54967e8ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042691390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.4042691390
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.2636812190
Short name T285
Test name
Test status
Simulation time 75642521797 ps
CPU time 33.36 seconds
Started Apr 25 01:36:49 PM PDT 24
Finished Apr 25 01:37:22 PM PDT 24
Peak memory 196432 kb
Host smart-b4dc2b17-b4e7-4bc9-ae0d-906cdb011422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636812190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.2636812190
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.3648584540
Short name T1018
Test name
Test status
Simulation time 947374555 ps
CPU time 1.15 seconds
Started Apr 25 01:36:38 PM PDT 24
Finished Apr 25 01:36:40 PM PDT 24
Peak memory 199052 kb
Host smart-60b0549d-9f6e-4267-b663-8284dc334e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648584540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.3648584540
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.3147984363
Short name T526
Test name
Test status
Simulation time 145916306018 ps
CPU time 222.86 seconds
Started Apr 25 01:36:45 PM PDT 24
Finished Apr 25 01:40:28 PM PDT 24
Peak memory 200456 kb
Host smart-33e88763-19a0-418f-a1eb-f9bdaeb53376
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147984363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.3147984363
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.1579719944
Short name T49
Test name
Test status
Simulation time 112912802683 ps
CPU time 589.98 seconds
Started Apr 25 01:36:44 PM PDT 24
Finished Apr 25 01:46:35 PM PDT 24
Peak memory 225172 kb
Host smart-7c442c79-2cfe-4e19-96e0-f76fca3565ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579719944 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.1579719944
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.242812133
Short name T913
Test name
Test status
Simulation time 6751623358 ps
CPU time 47.82 seconds
Started Apr 25 01:36:44 PM PDT 24
Finished Apr 25 01:37:32 PM PDT 24
Peak memory 199848 kb
Host smart-48cf7068-48ca-4d80-b081-92385df728a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242812133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.242812133
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.1673496704
Short name T1174
Test name
Test status
Simulation time 105500137603 ps
CPU time 23.87 seconds
Started Apr 25 01:36:38 PM PDT 24
Finished Apr 25 01:37:02 PM PDT 24
Peak memory 200436 kb
Host smart-11f72d20-1d41-4379-afb9-6f8f5772092e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673496704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1673496704
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.2946415544
Short name T862
Test name
Test status
Simulation time 162596554076 ps
CPU time 21.63 seconds
Started Apr 25 01:42:21 PM PDT 24
Finished Apr 25 01:42:43 PM PDT 24
Peak memory 200336 kb
Host smart-ea6c9eff-2110-44f8-9ea1-bef572f9a48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946415544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2946415544
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.2712512763
Short name T928
Test name
Test status
Simulation time 16288299247 ps
CPU time 19.24 seconds
Started Apr 25 01:42:20 PM PDT 24
Finished Apr 25 01:42:40 PM PDT 24
Peak memory 200404 kb
Host smart-745ea2ae-4095-49f9-823f-09f20efb2729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712512763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.2712512763
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.2434992594
Short name T203
Test name
Test status
Simulation time 15688610280 ps
CPU time 25.7 seconds
Started Apr 25 01:42:20 PM PDT 24
Finished Apr 25 01:42:47 PM PDT 24
Peak memory 200252 kb
Host smart-b6272c1a-aa05-4193-8217-bd01ac1c032b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434992594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.2434992594
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.1325292299
Short name T181
Test name
Test status
Simulation time 28131934724 ps
CPU time 45.53 seconds
Started Apr 25 01:42:21 PM PDT 24
Finished Apr 25 01:43:07 PM PDT 24
Peak memory 200376 kb
Host smart-cd9ff268-0f67-4dd7-ab1f-bad86bd515a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325292299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.1325292299
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.3627982584
Short name T504
Test name
Test status
Simulation time 73045835852 ps
CPU time 100.69 seconds
Started Apr 25 01:42:19 PM PDT 24
Finished Apr 25 01:44:00 PM PDT 24
Peak memory 200432 kb
Host smart-0fa60dd2-ec47-420d-85a0-6d005ef153b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627982584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.3627982584
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.3686554081
Short name T317
Test name
Test status
Simulation time 55820915033 ps
CPU time 51.33 seconds
Started Apr 25 01:42:21 PM PDT 24
Finished Apr 25 01:43:13 PM PDT 24
Peak memory 200404 kb
Host smart-b9d1960b-1c2e-4e82-866c-61199c912e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686554081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3686554081
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.3888497597
Short name T993
Test name
Test status
Simulation time 204394153067 ps
CPU time 36.75 seconds
Started Apr 25 01:42:24 PM PDT 24
Finished Apr 25 01:43:01 PM PDT 24
Peak memory 200256 kb
Host smart-49e00768-e815-49c8-884b-94410df95030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888497597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.3888497597
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.933202286
Short name T802
Test name
Test status
Simulation time 28167377606 ps
CPU time 19.43 seconds
Started Apr 25 01:42:19 PM PDT 24
Finished Apr 25 01:42:39 PM PDT 24
Peak memory 200200 kb
Host smart-5634e0c6-409e-45e1-8276-1191f77b83e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933202286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.933202286
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.991478089
Short name T224
Test name
Test status
Simulation time 12851632387 ps
CPU time 24.54 seconds
Started Apr 25 01:42:20 PM PDT 24
Finished Apr 25 01:42:45 PM PDT 24
Peak memory 200412 kb
Host smart-72cd6a68-ccfe-4a34-a664-f82376da5358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991478089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.991478089
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.245609295
Short name T358
Test name
Test status
Simulation time 11628465 ps
CPU time 0.54 seconds
Started Apr 25 01:36:50 PM PDT 24
Finished Apr 25 01:36:52 PM PDT 24
Peak memory 194776 kb
Host smart-f2c20a3b-f571-428e-987b-1ce9050fe8f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245609295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.245609295
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.3416325411
Short name T806
Test name
Test status
Simulation time 131339305563 ps
CPU time 212.62 seconds
Started Apr 25 01:36:51 PM PDT 24
Finished Apr 25 01:40:25 PM PDT 24
Peak memory 200468 kb
Host smart-22edbd1e-fb3f-4e6c-9e66-42279616ecf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416325411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.3416325411
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.4100774133
Short name T741
Test name
Test status
Simulation time 37135278631 ps
CPU time 34.75 seconds
Started Apr 25 01:36:51 PM PDT 24
Finished Apr 25 01:37:27 PM PDT 24
Peak memory 200412 kb
Host smart-4abe364f-692d-4f21-a668-4dc46f9e4b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100774133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.4100774133
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.3094696625
Short name T505
Test name
Test status
Simulation time 41513170595 ps
CPU time 23.89 seconds
Started Apr 25 01:36:51 PM PDT 24
Finished Apr 25 01:37:16 PM PDT 24
Peak memory 200444 kb
Host smart-41a1fa3c-e08c-4437-9e02-e9744bea4fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094696625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.3094696625
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.809962925
Short name T951
Test name
Test status
Simulation time 5597366286 ps
CPU time 3.87 seconds
Started Apr 25 01:36:50 PM PDT 24
Finished Apr 25 01:36:55 PM PDT 24
Peak memory 199924 kb
Host smart-b37b237c-a6df-4e8b-a02a-b717062b6522
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809962925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.809962925
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.3619800574
Short name T753
Test name
Test status
Simulation time 121767933734 ps
CPU time 364.62 seconds
Started Apr 25 01:36:50 PM PDT 24
Finished Apr 25 01:42:56 PM PDT 24
Peak memory 200368 kb
Host smart-205d2632-2c06-44c2-bf7a-6904d00595a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3619800574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.3619800574
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.2693098659
Short name T311
Test name
Test status
Simulation time 5359355659 ps
CPU time 7.52 seconds
Started Apr 25 01:36:52 PM PDT 24
Finished Apr 25 01:37:00 PM PDT 24
Peak memory 200052 kb
Host smart-6aad31aa-13a6-4bca-8b9d-bb2198fde86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693098659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.2693098659
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.804019402
Short name T432
Test name
Test status
Simulation time 100292534920 ps
CPU time 94.09 seconds
Started Apr 25 01:36:51 PM PDT 24
Finished Apr 25 01:38:26 PM PDT 24
Peak memory 208668 kb
Host smart-e7e6a951-f1a5-4d10-a7e5-0967f00cbb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804019402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.804019402
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.2467442123
Short name T486
Test name
Test status
Simulation time 7324939567 ps
CPU time 221.1 seconds
Started Apr 25 01:36:51 PM PDT 24
Finished Apr 25 01:40:34 PM PDT 24
Peak memory 200364 kb
Host smart-2a5c7f2d-c89c-4c09-82e6-1cef55c85c59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2467442123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2467442123
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.3736947228
Short name T517
Test name
Test status
Simulation time 5258474805 ps
CPU time 12.49 seconds
Started Apr 25 01:36:50 PM PDT 24
Finished Apr 25 01:37:03 PM PDT 24
Peak memory 199624 kb
Host smart-fc441992-24bf-409a-aadf-38cdcd8b4f49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3736947228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.3736947228
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.610866466
Short name T656
Test name
Test status
Simulation time 33150546500 ps
CPU time 71.97 seconds
Started Apr 25 01:36:51 PM PDT 24
Finished Apr 25 01:38:04 PM PDT 24
Peak memory 200344 kb
Host smart-a2d5f7c6-7e94-4f42-9b87-afe833a5d691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610866466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.610866466
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.3493982259
Short name T1049
Test name
Test status
Simulation time 629605845 ps
CPU time 1.15 seconds
Started Apr 25 01:36:49 PM PDT 24
Finished Apr 25 01:36:51 PM PDT 24
Peak memory 196076 kb
Host smart-7bf8dea1-89c6-4cb1-af4c-3e084f168331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493982259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.3493982259
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.2797717507
Short name T972
Test name
Test status
Simulation time 530982136 ps
CPU time 1.2 seconds
Started Apr 25 01:36:52 PM PDT 24
Finished Apr 25 01:36:54 PM PDT 24
Peak memory 198912 kb
Host smart-5a7bc638-9e6e-45cc-8c6b-442806b700d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797717507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.2797717507
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.1229160116
Short name T974
Test name
Test status
Simulation time 74655912102 ps
CPU time 820.53 seconds
Started Apr 25 01:36:55 PM PDT 24
Finished Apr 25 01:50:36 PM PDT 24
Peak memory 200396 kb
Host smart-2410c534-10dd-4554-b96e-a0cf27117437
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229160116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.1229160116
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.4197856724
Short name T539
Test name
Test status
Simulation time 61569029482 ps
CPU time 369.68 seconds
Started Apr 25 01:36:55 PM PDT 24
Finished Apr 25 01:43:05 PM PDT 24
Peak memory 212544 kb
Host smart-dc1c803d-a586-4cd4-92c3-4866cd52652e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197856724 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.4197856724
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.2380676519
Short name T491
Test name
Test status
Simulation time 2112282138 ps
CPU time 2.41 seconds
Started Apr 25 01:36:50 PM PDT 24
Finished Apr 25 01:36:54 PM PDT 24
Peak memory 199188 kb
Host smart-36d76a77-25d6-4dd6-94d3-d40adda380e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380676519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.2380676519
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.4194487475
Short name T810
Test name
Test status
Simulation time 23207372309 ps
CPU time 14.34 seconds
Started Apr 25 01:36:50 PM PDT 24
Finished Apr 25 01:37:04 PM PDT 24
Peak memory 200460 kb
Host smart-443cbaa4-5a48-4a9e-8240-e93ecd5ca6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194487475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.4194487475
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.2535949611
Short name T421
Test name
Test status
Simulation time 130399860241 ps
CPU time 207.92 seconds
Started Apr 25 01:42:19 PM PDT 24
Finished Apr 25 01:45:48 PM PDT 24
Peak memory 200380 kb
Host smart-d052f996-af06-47a4-81ee-4feffbc1f7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535949611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.2535949611
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.1545983325
Short name T270
Test name
Test status
Simulation time 99300079844 ps
CPU time 71.48 seconds
Started Apr 25 01:42:24 PM PDT 24
Finished Apr 25 01:43:36 PM PDT 24
Peak memory 200440 kb
Host smart-5b6c13c7-2ce9-4594-9704-d734926df0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545983325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.1545983325
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.2063540097
Short name T538
Test name
Test status
Simulation time 36379608286 ps
CPU time 17.22 seconds
Started Apr 25 01:42:19 PM PDT 24
Finished Apr 25 01:42:37 PM PDT 24
Peak memory 200396 kb
Host smart-2ca49c7b-0e0f-49a6-8074-381de07e5a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063540097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.2063540097
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.2072930907
Short name T179
Test name
Test status
Simulation time 39825448101 ps
CPU time 67.36 seconds
Started Apr 25 01:42:19 PM PDT 24
Finished Apr 25 01:43:26 PM PDT 24
Peak memory 200440 kb
Host smart-cf502acf-c454-45f1-9ca2-b4dab34b7bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072930907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.2072930907
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.3522821904
Short name T813
Test name
Test status
Simulation time 217792136660 ps
CPU time 199.34 seconds
Started Apr 25 01:42:20 PM PDT 24
Finished Apr 25 01:45:40 PM PDT 24
Peak memory 200376 kb
Host smart-27076f20-c847-4235-a06f-9631a25bda97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522821904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.3522821904
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.619399623
Short name T918
Test name
Test status
Simulation time 19231716077 ps
CPU time 15.81 seconds
Started Apr 25 01:42:28 PM PDT 24
Finished Apr 25 01:42:44 PM PDT 24
Peak memory 200436 kb
Host smart-da684c05-fc2a-4dd2-91a9-d84846286513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619399623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.619399623
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.26740176
Short name T1046
Test name
Test status
Simulation time 128954834776 ps
CPU time 93.45 seconds
Started Apr 25 01:42:25 PM PDT 24
Finished Apr 25 01:43:59 PM PDT 24
Peak memory 200400 kb
Host smart-9cd19ee4-17ed-495c-b75f-b44d57d81655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26740176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.26740176
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.383893095
Short name T177
Test name
Test status
Simulation time 40597291739 ps
CPU time 32.34 seconds
Started Apr 25 01:42:24 PM PDT 24
Finished Apr 25 01:42:57 PM PDT 24
Peak memory 200368 kb
Host smart-1ed8295d-7057-4daf-8e25-e4668bf674d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383893095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.383893095
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.44851800
Short name T499
Test name
Test status
Simulation time 12484586 ps
CPU time 0.54 seconds
Started Apr 25 01:37:03 PM PDT 24
Finished Apr 25 01:37:04 PM PDT 24
Peak memory 195764 kb
Host smart-9c35f9d5-039f-412a-9a6d-bbbce34340c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44851800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.44851800
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.2185262936
Short name T641
Test name
Test status
Simulation time 60584320103 ps
CPU time 31.67 seconds
Started Apr 25 01:36:51 PM PDT 24
Finished Apr 25 01:37:24 PM PDT 24
Peak memory 200444 kb
Host smart-31298b14-2646-4ba7-a15f-bb26797ee481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185262936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.2185262936
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.818627804
Short name T146
Test name
Test status
Simulation time 24063161126 ps
CPU time 42.71 seconds
Started Apr 25 01:36:58 PM PDT 24
Finished Apr 25 01:37:42 PM PDT 24
Peak memory 200340 kb
Host smart-13ffe35a-1698-4aef-ba0f-cfb711968c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818627804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.818627804
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_intr.3780509445
Short name T614
Test name
Test status
Simulation time 31771739196 ps
CPU time 52.52 seconds
Started Apr 25 01:36:58 PM PDT 24
Finished Apr 25 01:37:50 PM PDT 24
Peak memory 200420 kb
Host smart-301dfe74-fa09-4bb4-93f2-305ae2ac0471
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780509445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.3780509445
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.1003257116
Short name T919
Test name
Test status
Simulation time 207932467010 ps
CPU time 2016.49 seconds
Started Apr 25 01:36:56 PM PDT 24
Finished Apr 25 02:10:33 PM PDT 24
Peak memory 200384 kb
Host smart-09d2c6aa-4887-4a6b-8781-832f2999e8e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1003257116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.1003257116
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.83120433
Short name T489
Test name
Test status
Simulation time 9026949282 ps
CPU time 2.68 seconds
Started Apr 25 01:36:56 PM PDT 24
Finished Apr 25 01:36:59 PM PDT 24
Peak memory 200408 kb
Host smart-dc930f1d-acfb-4f44-b302-075e9768f54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83120433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.83120433
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.1289521885
Short name T734
Test name
Test status
Simulation time 72506086694 ps
CPU time 40.93 seconds
Started Apr 25 01:36:56 PM PDT 24
Finished Apr 25 01:37:37 PM PDT 24
Peak memory 200580 kb
Host smart-36ebeeec-b7f9-4ba1-b8eb-f4440ea4dfa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289521885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.1289521885
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.50061526
Short name T523
Test name
Test status
Simulation time 6245370807 ps
CPU time 86.02 seconds
Started Apr 25 01:36:58 PM PDT 24
Finished Apr 25 01:38:25 PM PDT 24
Peak memory 200460 kb
Host smart-5c53cfc4-218e-42df-8190-70c46b0188ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=50061526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.50061526
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.753927476
Short name T815
Test name
Test status
Simulation time 6836909450 ps
CPU time 58.52 seconds
Started Apr 25 01:36:56 PM PDT 24
Finished Apr 25 01:37:55 PM PDT 24
Peak memory 200372 kb
Host smart-c9205288-7cf6-4643-a8ea-99c77449e740
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=753927476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.753927476
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.495515856
Short name T447
Test name
Test status
Simulation time 52707892845 ps
CPU time 93.8 seconds
Started Apr 25 01:36:56 PM PDT 24
Finished Apr 25 01:38:31 PM PDT 24
Peak memory 200392 kb
Host smart-7e8f1121-f9b5-4757-8452-a09e525f5c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495515856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.495515856
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.585413825
Short name T645
Test name
Test status
Simulation time 6436523911 ps
CPU time 3.27 seconds
Started Apr 25 01:36:55 PM PDT 24
Finished Apr 25 01:36:59 PM PDT 24
Peak memory 196440 kb
Host smart-da218904-2b22-4a71-9866-30eb09e3dda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585413825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.585413825
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.3886190963
Short name T290
Test name
Test status
Simulation time 748024344 ps
CPU time 1.07 seconds
Started Apr 25 01:36:50 PM PDT 24
Finished Apr 25 01:36:52 PM PDT 24
Peak memory 198864 kb
Host smart-ed634ba9-a47b-4aba-9982-44460c037179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886190963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.3886190963
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.2323043846
Short name T44
Test name
Test status
Simulation time 37393385906 ps
CPU time 294.83 seconds
Started Apr 25 01:36:56 PM PDT 24
Finished Apr 25 01:41:52 PM PDT 24
Peak memory 216136 kb
Host smart-fabf097e-957a-4586-ad61-107d48432ebf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323043846 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.2323043846
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.69445410
Short name T615
Test name
Test status
Simulation time 850760594 ps
CPU time 3.87 seconds
Started Apr 25 01:36:57 PM PDT 24
Finished Apr 25 01:37:02 PM PDT 24
Peak memory 199996 kb
Host smart-9df920c2-595f-47f4-9e60-24dfea496f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69445410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.69445410
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.2625444875
Short name T367
Test name
Test status
Simulation time 41628945448 ps
CPU time 11.84 seconds
Started Apr 25 01:36:52 PM PDT 24
Finished Apr 25 01:37:04 PM PDT 24
Peak memory 200492 kb
Host smart-974fa235-976f-4e8e-b642-d75b29de7221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625444875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.2625444875
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.4228562786
Short name T120
Test name
Test status
Simulation time 105574179793 ps
CPU time 244.41 seconds
Started Apr 25 01:42:26 PM PDT 24
Finished Apr 25 01:46:31 PM PDT 24
Peak memory 200424 kb
Host smart-b98be1e4-6f1f-49d5-bf65-4ac8b832b613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228562786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.4228562786
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.4239890179
Short name T995
Test name
Test status
Simulation time 40635837476 ps
CPU time 19.03 seconds
Started Apr 25 01:42:28 PM PDT 24
Finished Apr 25 01:42:48 PM PDT 24
Peak memory 200420 kb
Host smart-d1f9f266-0cd4-40a7-80d2-051b57d4804d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239890179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.4239890179
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.1466199468
Short name T721
Test name
Test status
Simulation time 134650737832 ps
CPU time 131.21 seconds
Started Apr 25 01:42:24 PM PDT 24
Finished Apr 25 01:44:35 PM PDT 24
Peak memory 200440 kb
Host smart-5829be09-1aea-48b3-9e84-c363c75b6260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466199468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.1466199468
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.3083654547
Short name T130
Test name
Test status
Simulation time 33297938737 ps
CPU time 21.47 seconds
Started Apr 25 01:42:26 PM PDT 24
Finished Apr 25 01:42:47 PM PDT 24
Peak memory 200408 kb
Host smart-9a7e3f7e-2d21-4ec5-bff5-dc84a617842f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083654547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.3083654547
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.454582112
Short name T965
Test name
Test status
Simulation time 35643957201 ps
CPU time 13.06 seconds
Started Apr 25 01:42:24 PM PDT 24
Finished Apr 25 01:42:38 PM PDT 24
Peak memory 199088 kb
Host smart-57cda6ca-fbb0-4d23-9e6f-a91d10525158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454582112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.454582112
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.3727927067
Short name T225
Test name
Test status
Simulation time 140100712405 ps
CPU time 27.71 seconds
Started Apr 25 01:42:28 PM PDT 24
Finished Apr 25 01:42:56 PM PDT 24
Peak memory 200416 kb
Host smart-32c80c05-f70b-4f26-8c7c-29fd45d74a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727927067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.3727927067
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.1124988564
Short name T434
Test name
Test status
Simulation time 72960953692 ps
CPU time 20.19 seconds
Started Apr 25 01:42:52 PM PDT 24
Finished Apr 25 01:43:13 PM PDT 24
Peak memory 200428 kb
Host smart-4c8f022c-6e22-4073-805b-ea5d7c033bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124988564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.1124988564
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.1315518980
Short name T606
Test name
Test status
Simulation time 77638120056 ps
CPU time 114.12 seconds
Started Apr 25 01:42:26 PM PDT 24
Finished Apr 25 01:44:21 PM PDT 24
Peak memory 200436 kb
Host smart-61155f15-cd46-4e9d-845e-41e92f531cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315518980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.1315518980
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.3210125564
Short name T883
Test name
Test status
Simulation time 14394486842 ps
CPU time 25.42 seconds
Started Apr 25 01:42:25 PM PDT 24
Finished Apr 25 01:42:51 PM PDT 24
Peak memory 200408 kb
Host smart-ff1e0eb8-33b1-4ac3-bba1-b22fa859abcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210125564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.3210125564
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.1051223784
Short name T437
Test name
Test status
Simulation time 13932726783 ps
CPU time 24.58 seconds
Started Apr 25 01:42:31 PM PDT 24
Finished Apr 25 01:42:56 PM PDT 24
Peak memory 200432 kb
Host smart-42aa44b8-99c6-468d-a602-5005718f1320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051223784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.1051223784
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.2079951342
Short name T473
Test name
Test status
Simulation time 22091840 ps
CPU time 0.58 seconds
Started Apr 25 01:37:11 PM PDT 24
Finished Apr 25 01:37:12 PM PDT 24
Peak memory 195796 kb
Host smart-c00fa243-7d89-497e-b7be-003f8b5a9de4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079951342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2079951342
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.3768543169
Short name T703
Test name
Test status
Simulation time 45893477180 ps
CPU time 81.57 seconds
Started Apr 25 01:37:03 PM PDT 24
Finished Apr 25 01:38:25 PM PDT 24
Peak memory 200400 kb
Host smart-d51ef3a7-a8b9-4bb3-852a-b7a0ebd8a13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768543169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.3768543169
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.1630776205
Short name T1140
Test name
Test status
Simulation time 14148981177 ps
CPU time 22.79 seconds
Started Apr 25 01:37:05 PM PDT 24
Finished Apr 25 01:37:28 PM PDT 24
Peak memory 200328 kb
Host smart-71e869ba-a31a-4119-bbee-d9e4674982b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630776205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.1630776205
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.3011900336
Short name T200
Test name
Test status
Simulation time 48510378982 ps
CPU time 119.05 seconds
Started Apr 25 01:37:04 PM PDT 24
Finished Apr 25 01:39:04 PM PDT 24
Peak memory 200432 kb
Host smart-feaf8998-d22f-4254-8b37-509351bd5225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011900336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.3011900336
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.1126180270
Short name T793
Test name
Test status
Simulation time 184208349134 ps
CPU time 50.4 seconds
Started Apr 25 01:37:03 PM PDT 24
Finished Apr 25 01:37:54 PM PDT 24
Peak memory 196552 kb
Host smart-b45f9b09-29d2-478b-9442-107af9791847
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126180270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1126180270
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.3143408946
Short name T351
Test name
Test status
Simulation time 121722784755 ps
CPU time 196.39 seconds
Started Apr 25 01:37:10 PM PDT 24
Finished Apr 25 01:40:27 PM PDT 24
Peak memory 200404 kb
Host smart-f0232207-7a6f-4bac-baa4-d6f28ff3f68e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3143408946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.3143408946
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.291701205
Short name T948
Test name
Test status
Simulation time 5231054731 ps
CPU time 4.26 seconds
Started Apr 25 01:37:10 PM PDT 24
Finished Apr 25 01:37:15 PM PDT 24
Peak memory 200372 kb
Host smart-b4004e7a-28fc-4abb-a98b-9bc184480cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291701205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.291701205
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_perf.525770321
Short name T1044
Test name
Test status
Simulation time 16114048193 ps
CPU time 376.46 seconds
Started Apr 25 01:37:11 PM PDT 24
Finished Apr 25 01:43:28 PM PDT 24
Peak memory 200380 kb
Host smart-19b9b12e-465a-44b9-8a44-39a2bd98e4f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=525770321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.525770321
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.3918627853
Short name T827
Test name
Test status
Simulation time 4147435156 ps
CPU time 33.21 seconds
Started Apr 25 01:37:03 PM PDT 24
Finished Apr 25 01:37:37 PM PDT 24
Peak memory 198784 kb
Host smart-8864ec0f-5928-43bf-b20f-7d3ba91addc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3918627853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.3918627853
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.2709940488
Short name T310
Test name
Test status
Simulation time 92669814742 ps
CPU time 144.96 seconds
Started Apr 25 01:37:04 PM PDT 24
Finished Apr 25 01:39:29 PM PDT 24
Peak memory 200448 kb
Host smart-241d4a82-67cc-4618-9ec1-b73da3089cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709940488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.2709940488
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.3799475029
Short name T443
Test name
Test status
Simulation time 43284239523 ps
CPU time 33.44 seconds
Started Apr 25 01:37:03 PM PDT 24
Finished Apr 25 01:37:37 PM PDT 24
Peak memory 196444 kb
Host smart-484f3529-0936-479c-a43e-5812e33ad6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799475029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.3799475029
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.3685122210
Short name T363
Test name
Test status
Simulation time 308164188 ps
CPU time 1.03 seconds
Started Apr 25 01:37:03 PM PDT 24
Finished Apr 25 01:37:05 PM PDT 24
Peak memory 199132 kb
Host smart-46240d89-10cc-4903-9a87-034953674440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685122210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.3685122210
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.2006785336
Short name T1105
Test name
Test status
Simulation time 245678108521 ps
CPU time 386.47 seconds
Started Apr 25 01:37:10 PM PDT 24
Finished Apr 25 01:43:37 PM PDT 24
Peak memory 200400 kb
Host smart-e451a033-87d0-4305-8920-bc8fd120d5bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006785336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.2006785336
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.1531751098
Short name T26
Test name
Test status
Simulation time 80155750777 ps
CPU time 331.33 seconds
Started Apr 25 01:37:12 PM PDT 24
Finished Apr 25 01:42:45 PM PDT 24
Peak memory 216800 kb
Host smart-42f1312f-5b54-4f50-902a-85eecf79d2b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531751098 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.1531751098
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.781905795
Short name T300
Test name
Test status
Simulation time 7009676236 ps
CPU time 1.66 seconds
Started Apr 25 01:37:12 PM PDT 24
Finished Apr 25 01:37:15 PM PDT 24
Peak memory 199668 kb
Host smart-ae7f90db-c48f-4b2a-8af7-b628b4417cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781905795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.781905795
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.528822390
Short name T778
Test name
Test status
Simulation time 58284286087 ps
CPU time 51.91 seconds
Started Apr 25 01:37:04 PM PDT 24
Finished Apr 25 01:37:56 PM PDT 24
Peak memory 200412 kb
Host smart-fca3854f-6727-441d-af11-79778318f749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528822390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.528822390
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.2506868629
Short name T922
Test name
Test status
Simulation time 75014656520 ps
CPU time 32.76 seconds
Started Apr 25 01:42:30 PM PDT 24
Finished Apr 25 01:43:04 PM PDT 24
Peak memory 200400 kb
Host smart-c8c9c9cc-d4ff-481c-bef3-613471b9242e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506868629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.2506868629
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1196896524
Short name T1013
Test name
Test status
Simulation time 43718704429 ps
CPU time 50.79 seconds
Started Apr 25 01:42:30 PM PDT 24
Finished Apr 25 01:43:22 PM PDT 24
Peak memory 200336 kb
Host smart-7e18098c-6e1c-4557-b6bf-263dc5ada2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196896524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1196896524
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.2042639878
Short name T896
Test name
Test status
Simulation time 108266578076 ps
CPU time 215.74 seconds
Started Apr 25 01:42:40 PM PDT 24
Finished Apr 25 01:46:16 PM PDT 24
Peak memory 200176 kb
Host smart-6f9e01c3-7249-4832-9b56-629d0cce05e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042639878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.2042639878
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.3168138432
Short name T1034
Test name
Test status
Simulation time 29891100428 ps
CPU time 55.02 seconds
Started Apr 25 01:42:30 PM PDT 24
Finished Apr 25 01:43:26 PM PDT 24
Peak memory 200208 kb
Host smart-29f660ad-eba2-498d-8df5-46ad418b4e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168138432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.3168138432
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.1955415178
Short name T32
Test name
Test status
Simulation time 41287846636 ps
CPU time 38.03 seconds
Started Apr 25 01:42:40 PM PDT 24
Finished Apr 25 01:43:18 PM PDT 24
Peak memory 200148 kb
Host smart-4e0c9b57-ff9c-4b53-a32e-56ee9a3caec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955415178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.1955415178
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.2526393119
Short name T1175
Test name
Test status
Simulation time 220142093365 ps
CPU time 45.42 seconds
Started Apr 25 01:42:30 PM PDT 24
Finished Apr 25 01:43:16 PM PDT 24
Peak memory 199680 kb
Host smart-087b6cc5-2c5f-4207-bbea-d6ed752ded0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526393119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2526393119
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.1416929665
Short name T1106
Test name
Test status
Simulation time 32998323170 ps
CPU time 28.5 seconds
Started Apr 25 01:42:32 PM PDT 24
Finished Apr 25 01:43:01 PM PDT 24
Peak memory 199216 kb
Host smart-defd970e-f497-4573-b925-750cf8c31cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416929665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.1416929665
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.1959030227
Short name T749
Test name
Test status
Simulation time 131608350826 ps
CPU time 193.94 seconds
Started Apr 25 01:42:40 PM PDT 24
Finished Apr 25 01:45:54 PM PDT 24
Peak memory 200260 kb
Host smart-4f62a22d-a02e-4bfa-9e0a-ce4037a6ce89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959030227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.1959030227
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.514924927
Short name T1015
Test name
Test status
Simulation time 37902515892 ps
CPU time 63.08 seconds
Started Apr 25 01:42:40 PM PDT 24
Finished Apr 25 01:43:43 PM PDT 24
Peak memory 200280 kb
Host smart-46de5ea9-fb51-4ff4-b8d0-10437bb358dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514924927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.514924927
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.766266963
Short name T700
Test name
Test status
Simulation time 42721765500 ps
CPU time 17.65 seconds
Started Apr 25 01:42:29 PM PDT 24
Finished Apr 25 01:42:47 PM PDT 24
Peak memory 200348 kb
Host smart-3b8ecd25-a7ba-4fe1-bc6e-08a24dd589ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766266963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.766266963
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.2774123038
Short name T490
Test name
Test status
Simulation time 39805708 ps
CPU time 0.55 seconds
Started Apr 25 01:33:17 PM PDT 24
Finished Apr 25 01:33:18 PM PDT 24
Peak memory 195768 kb
Host smart-22e8e23a-e1e0-49ee-bfb0-4dd01bfc44ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774123038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.2774123038
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.1153699412
Short name T574
Test name
Test status
Simulation time 58281717027 ps
CPU time 115.28 seconds
Started Apr 25 01:33:11 PM PDT 24
Finished Apr 25 01:35:07 PM PDT 24
Peak memory 200260 kb
Host smart-6ca3da1c-042d-45de-b0f2-0719b1dc9e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153699412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.1153699412
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.3819645538
Short name T584
Test name
Test status
Simulation time 39696944398 ps
CPU time 66.91 seconds
Started Apr 25 01:33:10 PM PDT 24
Finished Apr 25 01:34:17 PM PDT 24
Peak memory 200440 kb
Host smart-4defb793-4ad5-4ee8-9447-fd6bbe67e7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819645538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.3819645538
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.1271723206
Short name T212
Test name
Test status
Simulation time 33764034556 ps
CPU time 48.36 seconds
Started Apr 25 01:33:11 PM PDT 24
Finished Apr 25 01:34:00 PM PDT 24
Peak memory 200372 kb
Host smart-c02f7fe7-7fca-48c0-9440-bae40e0bede7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271723206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.1271723206
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.1391088571
Short name T479
Test name
Test status
Simulation time 10722031989 ps
CPU time 4.12 seconds
Started Apr 25 01:33:11 PM PDT 24
Finished Apr 25 01:33:15 PM PDT 24
Peak memory 196472 kb
Host smart-09478e48-1f81-4707-beb0-3102c7e11304
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391088571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.1391088571
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.3498489993
Short name T356
Test name
Test status
Simulation time 156969367989 ps
CPU time 307 seconds
Started Apr 25 01:33:19 PM PDT 24
Finished Apr 25 01:38:27 PM PDT 24
Peak memory 200456 kb
Host smart-a4f80a4a-f694-4cb9-ac77-e44ca6ac493e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3498489993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.3498489993
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.3808564373
Short name T851
Test name
Test status
Simulation time 2239042087 ps
CPU time 4 seconds
Started Apr 25 01:33:17 PM PDT 24
Finished Apr 25 01:33:22 PM PDT 24
Peak memory 199936 kb
Host smart-90d184cc-62dc-4ba1-839f-05ff08a2d143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808564373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.3808564373
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.1577364161
Short name T253
Test name
Test status
Simulation time 84294653249 ps
CPU time 74.04 seconds
Started Apr 25 01:33:10 PM PDT 24
Finished Apr 25 01:34:25 PM PDT 24
Peak memory 200700 kb
Host smart-80e136ea-e68b-4b41-8260-e69bd9134116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577364161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.1577364161
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.1269157307
Short name T850
Test name
Test status
Simulation time 15109169753 ps
CPU time 113.69 seconds
Started Apr 25 01:33:16 PM PDT 24
Finished Apr 25 01:35:10 PM PDT 24
Peak memory 200372 kb
Host smart-3da441c6-922d-45b8-8bc5-ff303ceeb824
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1269157307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.1269157307
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.298164974
Short name T544
Test name
Test status
Simulation time 3893374249 ps
CPU time 34.97 seconds
Started Apr 25 01:33:10 PM PDT 24
Finished Apr 25 01:33:46 PM PDT 24
Peak memory 198508 kb
Host smart-ae0d914e-6073-45ff-8d35-670b13f5a845
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=298164974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.298164974
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.683589259
Short name T1048
Test name
Test status
Simulation time 156383929213 ps
CPU time 394.67 seconds
Started Apr 25 01:33:10 PM PDT 24
Finished Apr 25 01:39:46 PM PDT 24
Peak memory 200268 kb
Host smart-11050f59-1961-4dd3-9962-38283ae131c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683589259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.683589259
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.2579704079
Short name T875
Test name
Test status
Simulation time 70925318226 ps
CPU time 16.47 seconds
Started Apr 25 01:33:10 PM PDT 24
Finished Apr 25 01:33:27 PM PDT 24
Peak memory 196688 kb
Host smart-72c945ce-cfe7-481c-98a5-c0becbe5a228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579704079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.2579704079
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.3170092035
Short name T22
Test name
Test status
Simulation time 2121018067 ps
CPU time 0.95 seconds
Started Apr 25 01:33:17 PM PDT 24
Finished Apr 25 01:33:19 PM PDT 24
Peak memory 218684 kb
Host smart-8ea0a462-7c41-4cfe-aaf3-47fe46c52892
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170092035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3170092035
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.3239686865
Short name T268
Test name
Test status
Simulation time 6253315771 ps
CPU time 7.72 seconds
Started Apr 25 01:33:05 PM PDT 24
Finished Apr 25 01:33:13 PM PDT 24
Peak memory 199648 kb
Host smart-b5f05444-eb18-4b01-9649-d6c75a44a9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239686865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.3239686865
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.1394064306
Short name T599
Test name
Test status
Simulation time 89823261299 ps
CPU time 99.9 seconds
Started Apr 25 01:33:17 PM PDT 24
Finished Apr 25 01:34:58 PM PDT 24
Peak memory 200348 kb
Host smart-3164bfd3-6aef-4a2b-86e5-f2194bfe12e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394064306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.1394064306
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.840979738
Short name T1148
Test name
Test status
Simulation time 69154389862 ps
CPU time 927.76 seconds
Started Apr 25 01:33:18 PM PDT 24
Finished Apr 25 01:48:46 PM PDT 24
Peak memory 216936 kb
Host smart-1927a2a1-14de-4023-90a9-573a6269bdfe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840979738 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.840979738
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.2681732752
Short name T444
Test name
Test status
Simulation time 1730155627 ps
CPU time 1.67 seconds
Started Apr 25 01:33:17 PM PDT 24
Finished Apr 25 01:33:19 PM PDT 24
Peak memory 198932 kb
Host smart-07677af9-c9b1-437b-8f63-831de9eba90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681732752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2681732752
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.696031760
Short name T1059
Test name
Test status
Simulation time 12318356485 ps
CPU time 22.11 seconds
Started Apr 25 01:33:34 PM PDT 24
Finished Apr 25 01:33:57 PM PDT 24
Peak memory 200432 kb
Host smart-30f71bba-2695-4a8e-a48c-c745f5294d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696031760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.696031760
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.3136756631
Short name T686
Test name
Test status
Simulation time 44553735 ps
CPU time 0.55 seconds
Started Apr 25 01:37:28 PM PDT 24
Finished Apr 25 01:37:29 PM PDT 24
Peak memory 195776 kb
Host smart-ce72152f-5b50-45b1-a052-20ea279de85a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136756631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.3136756631
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.2514048629
Short name T743
Test name
Test status
Simulation time 31981111045 ps
CPU time 51.76 seconds
Started Apr 25 01:37:09 PM PDT 24
Finished Apr 25 01:38:01 PM PDT 24
Peak memory 200276 kb
Host smart-d8f9d322-7044-4277-86ea-91ed16bc8548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514048629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.2514048629
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.3282386940
Short name T501
Test name
Test status
Simulation time 58972917409 ps
CPU time 40.64 seconds
Started Apr 25 01:37:16 PM PDT 24
Finished Apr 25 01:37:57 PM PDT 24
Peak memory 200340 kb
Host smart-8c3f0145-c80b-4992-83b4-b7073185e67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282386940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.3282386940
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.1737908886
Short name T157
Test name
Test status
Simulation time 65136953765 ps
CPU time 11.89 seconds
Started Apr 25 01:37:16 PM PDT 24
Finished Apr 25 01:37:28 PM PDT 24
Peak memory 200420 kb
Host smart-9a525b00-a71f-451a-b5cf-ce20dca953e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737908886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.1737908886
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.2523836535
Short name T362
Test name
Test status
Simulation time 38383947664 ps
CPU time 11.62 seconds
Started Apr 25 01:37:25 PM PDT 24
Finished Apr 25 01:37:37 PM PDT 24
Peak memory 200380 kb
Host smart-2bee6cbb-667e-4a20-a100-421f19a19ad5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523836535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.2523836535
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.2239368306
Short name T1114
Test name
Test status
Simulation time 34712930182 ps
CPU time 92.3 seconds
Started Apr 25 01:37:26 PM PDT 24
Finished Apr 25 01:38:59 PM PDT 24
Peak memory 200424 kb
Host smart-8865360a-ac86-4b8f-8920-c580823b40c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2239368306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.2239368306
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.3825113481
Short name T909
Test name
Test status
Simulation time 3505140735 ps
CPU time 5.66 seconds
Started Apr 25 01:37:16 PM PDT 24
Finished Apr 25 01:37:22 PM PDT 24
Peak memory 200280 kb
Host smart-30d12e31-3f23-4632-b177-2155161ef70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825113481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.3825113481
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.2988336671
Short name T1143
Test name
Test status
Simulation time 83382655330 ps
CPU time 35.5 seconds
Started Apr 25 01:37:16 PM PDT 24
Finished Apr 25 01:37:52 PM PDT 24
Peak memory 208792 kb
Host smart-b4eda7f4-3d68-4bd0-afca-b7aa632c6eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988336671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.2988336671
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.1123711366
Short name T1162
Test name
Test status
Simulation time 21144536742 ps
CPU time 461.83 seconds
Started Apr 25 01:37:23 PM PDT 24
Finished Apr 25 01:45:06 PM PDT 24
Peak memory 200392 kb
Host smart-697262af-28d9-429e-a383-10de1386212a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1123711366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.1123711366
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.2179149695
Short name T70
Test name
Test status
Simulation time 8243769093 ps
CPU time 69.45 seconds
Started Apr 25 01:37:17 PM PDT 24
Finished Apr 25 01:38:27 PM PDT 24
Peak memory 198624 kb
Host smart-10922fb1-df15-4466-9799-a21c35b685de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2179149695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.2179149695
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.384541130
Short name T1095
Test name
Test status
Simulation time 170873028835 ps
CPU time 67.8 seconds
Started Apr 25 01:37:25 PM PDT 24
Finished Apr 25 01:38:33 PM PDT 24
Peak memory 200404 kb
Host smart-a50de070-8ce8-4bd4-8397-089d90bddf8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384541130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.384541130
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.831906714
Short name T273
Test name
Test status
Simulation time 2300985664 ps
CPU time 4.8 seconds
Started Apr 25 01:37:26 PM PDT 24
Finished Apr 25 01:37:32 PM PDT 24
Peak memory 195928 kb
Host smart-30467bcb-3fcf-4548-9812-5d01ef7116f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831906714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.831906714
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.1955574530
Short name T678
Test name
Test status
Simulation time 487933828 ps
CPU time 2.58 seconds
Started Apr 25 01:37:11 PM PDT 24
Finished Apr 25 01:37:14 PM PDT 24
Peak memory 199160 kb
Host smart-3ec21baa-c3b5-4733-bd98-dec545d3e762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955574530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.1955574530
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.2786301265
Short name T887
Test name
Test status
Simulation time 216492621159 ps
CPU time 731.13 seconds
Started Apr 25 01:37:23 PM PDT 24
Finished Apr 25 01:49:35 PM PDT 24
Peak memory 199952 kb
Host smart-d54b8503-eebc-4f3a-9470-00f4ac14da86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786301265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.2786301265
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.3663761963
Short name T1012
Test name
Test status
Simulation time 60417002566 ps
CPU time 1168.91 seconds
Started Apr 25 01:37:25 PM PDT 24
Finished Apr 25 01:56:54 PM PDT 24
Peak memory 216816 kb
Host smart-e46274ea-5d8a-4c3f-ab1c-7bc18d2460cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663761963 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.3663761963
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.3384494791
Short name T834
Test name
Test status
Simulation time 7784778056 ps
CPU time 10.9 seconds
Started Apr 25 01:37:16 PM PDT 24
Finished Apr 25 01:37:27 PM PDT 24
Peak memory 200284 kb
Host smart-253a12da-4bac-404a-ade0-0264a131bfd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384494791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.3384494791
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.3251370881
Short name T670
Test name
Test status
Simulation time 16566053511 ps
CPU time 13.41 seconds
Started Apr 25 01:37:12 PM PDT 24
Finished Apr 25 01:37:26 PM PDT 24
Peak memory 200280 kb
Host smart-22126a29-b88b-4fa3-baf0-b7a46deb4b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251370881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.3251370881
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.2299027228
Short name T953
Test name
Test status
Simulation time 26511617 ps
CPU time 0.54 seconds
Started Apr 25 01:37:28 PM PDT 24
Finished Apr 25 01:37:30 PM PDT 24
Peak memory 195812 kb
Host smart-5158b09b-2fba-4b9b-9b28-96157b49e0d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299027228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.2299027228
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.478431028
Short name T419
Test name
Test status
Simulation time 19020740622 ps
CPU time 38.75 seconds
Started Apr 25 01:37:23 PM PDT 24
Finished Apr 25 01:38:03 PM PDT 24
Peak memory 199732 kb
Host smart-0eaf6f29-082b-47ae-8ac9-8bd45efea891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478431028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.478431028
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.1281022104
Short name T871
Test name
Test status
Simulation time 93720818780 ps
CPU time 72.17 seconds
Started Apr 25 01:37:23 PM PDT 24
Finished Apr 25 01:38:36 PM PDT 24
Peak memory 200344 kb
Host smart-54529f86-8825-4d89-8cd1-fde6eff3616e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281022104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.1281022104
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.2306003418
Short name T11
Test name
Test status
Simulation time 11295907714 ps
CPU time 23.58 seconds
Started Apr 25 01:37:23 PM PDT 24
Finished Apr 25 01:37:48 PM PDT 24
Peak memory 200352 kb
Host smart-2c4e9d7e-721e-4413-805f-c54102efcdbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306003418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.2306003418
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.2467289832
Short name T1118
Test name
Test status
Simulation time 241832918745 ps
CPU time 270.2 seconds
Started Apr 25 01:37:26 PM PDT 24
Finished Apr 25 01:41:57 PM PDT 24
Peak memory 200400 kb
Host smart-d56d152a-2cc0-4f0a-ae96-3962014a91d8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467289832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.2467289832
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.3771024327
Short name T283
Test name
Test status
Simulation time 120042534154 ps
CPU time 560.01 seconds
Started Apr 25 01:37:29 PM PDT 24
Finished Apr 25 01:46:51 PM PDT 24
Peak memory 200456 kb
Host smart-74b33b94-f13f-407e-b0d2-ebbbfcae1787
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3771024327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.3771024327
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.1411404836
Short name T1117
Test name
Test status
Simulation time 7358210798 ps
CPU time 15.16 seconds
Started Apr 25 01:37:29 PM PDT 24
Finished Apr 25 01:37:45 PM PDT 24
Peak memory 200140 kb
Host smart-b367e99d-5312-4402-b78e-2cce1597dea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411404836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.1411404836
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.3539737498
Short name T996
Test name
Test status
Simulation time 35493244752 ps
CPU time 15.28 seconds
Started Apr 25 01:37:23 PM PDT 24
Finished Apr 25 01:37:38 PM PDT 24
Peak memory 200400 kb
Host smart-4677ac8d-1dd0-43dc-bfda-d3a1f7fe48aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539737498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3539737498
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.187982630
Short name T564
Test name
Test status
Simulation time 11982525920 ps
CPU time 131.83 seconds
Started Apr 25 01:37:28 PM PDT 24
Finished Apr 25 01:39:41 PM PDT 24
Peak memory 200164 kb
Host smart-b5d506f5-2cd0-40a0-9837-cf89d72dbc79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=187982630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.187982630
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.1638095266
Short name T704
Test name
Test status
Simulation time 6480490623 ps
CPU time 3.94 seconds
Started Apr 25 01:37:24 PM PDT 24
Finished Apr 25 01:37:28 PM PDT 24
Peak memory 200388 kb
Host smart-40b3eeb6-682a-4b01-bcc0-134c9c7a2bb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1638095266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.1638095266
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.1033526392
Short name T162
Test name
Test status
Simulation time 71282960623 ps
CPU time 12.84 seconds
Started Apr 25 01:37:30 PM PDT 24
Finished Apr 25 01:37:44 PM PDT 24
Peak memory 200428 kb
Host smart-c08bc8e4-992a-4835-a430-66ac802eb572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033526392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1033526392
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.3751443962
Short name T755
Test name
Test status
Simulation time 3635175402 ps
CPU time 5.91 seconds
Started Apr 25 01:37:28 PM PDT 24
Finished Apr 25 01:37:35 PM PDT 24
Peak memory 196144 kb
Host smart-319092e5-b040-42f9-a9ba-30eaf0f99ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751443962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.3751443962
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.2499619281
Short name T1131
Test name
Test status
Simulation time 6047348324 ps
CPU time 10.67 seconds
Started Apr 25 01:37:24 PM PDT 24
Finished Apr 25 01:37:35 PM PDT 24
Peak memory 200352 kb
Host smart-12d9aa30-13d4-4553-89a2-6134ac315f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499619281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.2499619281
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.909720509
Short name T997
Test name
Test status
Simulation time 2494791027 ps
CPU time 2.12 seconds
Started Apr 25 01:37:29 PM PDT 24
Finished Apr 25 01:37:32 PM PDT 24
Peak memory 200280 kb
Host smart-ba399abd-8070-4810-b453-1b51a6b36224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909720509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.909720509
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.2604611229
Short name T520
Test name
Test status
Simulation time 100451043264 ps
CPU time 156.44 seconds
Started Apr 25 01:37:24 PM PDT 24
Finished Apr 25 01:40:01 PM PDT 24
Peak memory 200456 kb
Host smart-e4b67ffc-6317-48e3-8ffd-ddaa3baadb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604611229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.2604611229
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.2402406361
Short name T532
Test name
Test status
Simulation time 39426446 ps
CPU time 0.55 seconds
Started Apr 25 01:37:35 PM PDT 24
Finished Apr 25 01:37:37 PM PDT 24
Peak memory 195776 kb
Host smart-83eac5b5-16c5-4722-a471-7ed86989b001
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402406361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2402406361
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.3558645727
Short name T789
Test name
Test status
Simulation time 80331302338 ps
CPU time 45.62 seconds
Started Apr 25 01:37:29 PM PDT 24
Finished Apr 25 01:38:15 PM PDT 24
Peak memory 200524 kb
Host smart-c6831936-f656-429d-85cf-a36c0d07b33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558645727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.3558645727
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.1184829563
Short name T567
Test name
Test status
Simulation time 78140008982 ps
CPU time 27.7 seconds
Started Apr 25 01:37:28 PM PDT 24
Finished Apr 25 01:37:57 PM PDT 24
Peak memory 200180 kb
Host smart-f2f19feb-8ec5-4d02-8d96-4591a58e435f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184829563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.1184829563
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_intr.313080772
Short name T561
Test name
Test status
Simulation time 33387262807 ps
CPU time 20.06 seconds
Started Apr 25 01:37:29 PM PDT 24
Finished Apr 25 01:37:50 PM PDT 24
Peak memory 200412 kb
Host smart-3de43204-fe8a-4412-9051-8457da11cdd9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313080772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.313080772
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.3720583145
Short name T976
Test name
Test status
Simulation time 122838435968 ps
CPU time 1061.15 seconds
Started Apr 25 01:37:35 PM PDT 24
Finished Apr 25 01:55:17 PM PDT 24
Peak memory 200432 kb
Host smart-5f9aac70-4b4c-4bc2-a291-11005ec9b227
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3720583145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.3720583145
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.3147196116
Short name T496
Test name
Test status
Simulation time 13095968216 ps
CPU time 7 seconds
Started Apr 25 01:37:36 PM PDT 24
Finished Apr 25 01:37:44 PM PDT 24
Peak memory 199180 kb
Host smart-fa2ae7b1-3375-4765-85b2-79287cdc66cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147196116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.3147196116
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.1427721004
Short name T651
Test name
Test status
Simulation time 60023655314 ps
CPU time 100.65 seconds
Started Apr 25 01:37:27 PM PDT 24
Finished Apr 25 01:39:09 PM PDT 24
Peak memory 199924 kb
Host smart-9ab153a7-145b-4f9a-8050-f6425cbf2d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427721004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.1427721004
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.569205705
Short name T484
Test name
Test status
Simulation time 20236805820 ps
CPU time 912.46 seconds
Started Apr 25 01:37:35 PM PDT 24
Finished Apr 25 01:52:48 PM PDT 24
Peak memory 200416 kb
Host smart-95849f22-386f-4c49-ae25-d6e4b657c321
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=569205705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.569205705
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.3337126969
Short name T1180
Test name
Test status
Simulation time 2031659633 ps
CPU time 2.57 seconds
Started Apr 25 01:37:27 PM PDT 24
Finished Apr 25 01:37:31 PM PDT 24
Peak memory 199636 kb
Host smart-29c125f2-a394-47cd-9f9c-7a83903044b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3337126969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3337126969
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.1617329934
Short name T518
Test name
Test status
Simulation time 76861152206 ps
CPU time 189.85 seconds
Started Apr 25 01:37:28 PM PDT 24
Finished Apr 25 01:40:39 PM PDT 24
Peak memory 200404 kb
Host smart-63ba43ed-efb1-4a2c-b499-643737f4d2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617329934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.1617329934
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.3858640304
Short name T355
Test name
Test status
Simulation time 35421498237 ps
CPU time 50.39 seconds
Started Apr 25 01:37:28 PM PDT 24
Finished Apr 25 01:38:19 PM PDT 24
Peak memory 196724 kb
Host smart-29594dba-20b3-46c5-bded-3c5d1100249d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858640304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.3858640304
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.1954545191
Short name T905
Test name
Test status
Simulation time 555667351 ps
CPU time 2.28 seconds
Started Apr 25 01:37:30 PM PDT 24
Finished Apr 25 01:37:33 PM PDT 24
Peak memory 198664 kb
Host smart-46d5761c-ffe7-44af-94a8-cc1d3196a932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954545191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.1954545191
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.2588561117
Short name T169
Test name
Test status
Simulation time 359819360766 ps
CPU time 765.72 seconds
Started Apr 25 01:37:36 PM PDT 24
Finished Apr 25 01:50:22 PM PDT 24
Peak memory 200428 kb
Host smart-b6611c7c-98f3-447b-87f8-6ad028041ab1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588561117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.2588561117
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.1749486351
Short name T676
Test name
Test status
Simulation time 189707332346 ps
CPU time 349.86 seconds
Started Apr 25 01:37:34 PM PDT 24
Finished Apr 25 01:43:24 PM PDT 24
Peak memory 216572 kb
Host smart-8cbc396a-51c7-4c6b-9fcb-cb7237f4dead
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749486351 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.1749486351
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.4007214204
Short name T731
Test name
Test status
Simulation time 12304347825 ps
CPU time 20.47 seconds
Started Apr 25 01:37:34 PM PDT 24
Finished Apr 25 01:37:55 PM PDT 24
Peak memory 200384 kb
Host smart-c13f4e7f-24f1-4523-9829-72fd5d6565f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007214204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.4007214204
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.1498927594
Short name T249
Test name
Test status
Simulation time 16929663918 ps
CPU time 47.97 seconds
Started Apr 25 01:37:31 PM PDT 24
Finished Apr 25 01:38:20 PM PDT 24
Peak memory 200440 kb
Host smart-3e4d9e71-833e-49bb-b04e-9a2161eb9d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498927594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.1498927594
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.1986512101
Short name T449
Test name
Test status
Simulation time 20899302 ps
CPU time 0.56 seconds
Started Apr 25 01:37:40 PM PDT 24
Finished Apr 25 01:37:41 PM PDT 24
Peak memory 195816 kb
Host smart-d0f4c668-e51a-45ba-8ddc-d0c91289bb4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986512101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.1986512101
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.816961483
Short name T1176
Test name
Test status
Simulation time 116977050784 ps
CPU time 159.15 seconds
Started Apr 25 01:37:34 PM PDT 24
Finished Apr 25 01:40:14 PM PDT 24
Peak memory 200424 kb
Host smart-204c5f04-c5d7-4211-9106-7f534d521c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816961483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.816961483
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.14204552
Short name T1159
Test name
Test status
Simulation time 98998766560 ps
CPU time 36 seconds
Started Apr 25 01:37:33 PM PDT 24
Finished Apr 25 01:38:09 PM PDT 24
Peak memory 200360 kb
Host smart-fb4dee10-3cf3-4cf2-a242-f21c09876151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14204552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.14204552
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.2249452877
Short name T213
Test name
Test status
Simulation time 42109374580 ps
CPU time 77.49 seconds
Started Apr 25 01:37:40 PM PDT 24
Finished Apr 25 01:38:57 PM PDT 24
Peak memory 200416 kb
Host smart-07a02693-ec0d-40e2-bbdb-ec25574b1885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249452877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.2249452877
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.1529464212
Short name T1171
Test name
Test status
Simulation time 38351483269 ps
CPU time 17.41 seconds
Started Apr 25 01:37:42 PM PDT 24
Finished Apr 25 01:38:00 PM PDT 24
Peak memory 199428 kb
Host smart-0e420700-36f6-4f22-92e7-d0db5b0f0ace
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529464212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.1529464212
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.3064983064
Short name T600
Test name
Test status
Simulation time 141676238757 ps
CPU time 638.56 seconds
Started Apr 25 01:37:42 PM PDT 24
Finished Apr 25 01:48:21 PM PDT 24
Peak memory 200352 kb
Host smart-ce4285e9-0e2f-4df2-abcc-c7f86e98365d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3064983064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.3064983064
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.2012714935
Short name T533
Test name
Test status
Simulation time 6009569415 ps
CPU time 13.62 seconds
Started Apr 25 01:37:43 PM PDT 24
Finished Apr 25 01:37:57 PM PDT 24
Peak memory 200360 kb
Host smart-6f125742-5d90-4476-8065-95ab9accd92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012714935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.2012714935
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.212069909
Short name T754
Test name
Test status
Simulation time 45372033746 ps
CPU time 94.19 seconds
Started Apr 25 01:37:39 PM PDT 24
Finished Apr 25 01:39:14 PM PDT 24
Peak memory 200000 kb
Host smart-df07e16a-e1dd-4085-a8fa-565de4811479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212069909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.212069909
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.3853105211
Short name T816
Test name
Test status
Simulation time 5831906399 ps
CPU time 131.1 seconds
Started Apr 25 01:37:41 PM PDT 24
Finished Apr 25 01:39:53 PM PDT 24
Peak memory 200420 kb
Host smart-1a06d50c-ae0c-45df-a3ec-cd07cf33d4f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3853105211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.3853105211
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.4089292421
Short name T1098
Test name
Test status
Simulation time 6971142014 ps
CPU time 64.95 seconds
Started Apr 25 01:37:35 PM PDT 24
Finished Apr 25 01:38:40 PM PDT 24
Peak memory 198588 kb
Host smart-57ee4d7d-bcd1-4cc6-95d7-f57f69e01af4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4089292421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.4089292421
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.549850891
Short name T306
Test name
Test status
Simulation time 111141019180 ps
CPU time 139.79 seconds
Started Apr 25 01:37:43 PM PDT 24
Finished Apr 25 01:40:03 PM PDT 24
Peak memory 200344 kb
Host smart-f6bcb74d-96e2-40b7-88a3-a6d149e84aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549850891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.549850891
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.325495686
Short name T406
Test name
Test status
Simulation time 660107544 ps
CPU time 0.91 seconds
Started Apr 25 01:37:41 PM PDT 24
Finished Apr 25 01:37:42 PM PDT 24
Peak memory 196144 kb
Host smart-dd5f6362-a87c-4b7f-a7df-8ac01e819117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325495686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.325495686
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.1380898262
Short name T1104
Test name
Test status
Simulation time 6300480565 ps
CPU time 8.8 seconds
Started Apr 25 01:37:35 PM PDT 24
Finished Apr 25 01:37:45 PM PDT 24
Peak memory 200204 kb
Host smart-22cb4574-9c3b-4eca-80c5-7c1ee4c374d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380898262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.1380898262
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.3184616042
Short name T1068
Test name
Test status
Simulation time 160251643951 ps
CPU time 310.12 seconds
Started Apr 25 01:37:40 PM PDT 24
Finished Apr 25 01:42:51 PM PDT 24
Peak memory 200448 kb
Host smart-1867055f-2ec7-4cb0-818e-2ee4c1315af6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184616042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.3184616042
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.3768124882
Short name T1008
Test name
Test status
Simulation time 78714550783 ps
CPU time 408.28 seconds
Started Apr 25 01:37:42 PM PDT 24
Finished Apr 25 01:44:31 PM PDT 24
Peak memory 216676 kb
Host smart-7584dd32-122d-402b-9d0b-4654e3d24997
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768124882 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.3768124882
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.2182277865
Short name T299
Test name
Test status
Simulation time 621506510 ps
CPU time 2.1 seconds
Started Apr 25 01:37:42 PM PDT 24
Finished Apr 25 01:37:44 PM PDT 24
Peak memory 199540 kb
Host smart-35c2c7b5-667e-4ff3-b654-be90edaa632a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182277865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.2182277865
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.3745743431
Short name T323
Test name
Test status
Simulation time 40058366226 ps
CPU time 82.92 seconds
Started Apr 25 01:37:35 PM PDT 24
Finished Apr 25 01:38:58 PM PDT 24
Peak memory 200408 kb
Host smart-c6b798be-f766-48c1-a825-0766f23986fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745743431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.3745743431
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.3137251624
Short name T462
Test name
Test status
Simulation time 31726970 ps
CPU time 0.55 seconds
Started Apr 25 01:37:49 PM PDT 24
Finished Apr 25 01:37:50 PM PDT 24
Peak memory 195776 kb
Host smart-ac528e00-0691-43e8-8832-011e8e59ba9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137251624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.3137251624
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.3808146272
Short name T360
Test name
Test status
Simulation time 116685350872 ps
CPU time 20.14 seconds
Started Apr 25 01:37:41 PM PDT 24
Finished Apr 25 01:38:02 PM PDT 24
Peak memory 200400 kb
Host smart-05162173-b4cb-4044-bad4-f6ce217c1d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808146272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.3808146272
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.4282657926
Short name T559
Test name
Test status
Simulation time 200831143147 ps
CPU time 46.71 seconds
Started Apr 25 01:37:43 PM PDT 24
Finished Apr 25 01:38:30 PM PDT 24
Peak memory 200332 kb
Host smart-ac55f5e7-4769-4704-8f4f-22cddc9d2fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282657926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.4282657926
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.2821824645
Short name T681
Test name
Test status
Simulation time 85042187313 ps
CPU time 136.96 seconds
Started Apr 25 01:37:48 PM PDT 24
Finished Apr 25 01:40:06 PM PDT 24
Peak memory 200448 kb
Host smart-0e3fed37-49f1-4299-919e-a052cc296602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821824645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.2821824645
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.1209490839
Short name T357
Test name
Test status
Simulation time 43134776476 ps
CPU time 77.33 seconds
Started Apr 25 01:37:48 PM PDT 24
Finished Apr 25 01:39:06 PM PDT 24
Peak memory 199340 kb
Host smart-a1db548f-b147-461c-8054-205a4989a580
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209490839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.1209490839
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.724555787
Short name T1041
Test name
Test status
Simulation time 35668219350 ps
CPU time 300.5 seconds
Started Apr 25 01:37:46 PM PDT 24
Finished Apr 25 01:42:47 PM PDT 24
Peak memory 200384 kb
Host smart-45f55001-c904-4215-9e2f-d1763cab780c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=724555787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.724555787
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.4111292486
Short name T991
Test name
Test status
Simulation time 2606674062 ps
CPU time 2.21 seconds
Started Apr 25 01:37:47 PM PDT 24
Finished Apr 25 01:37:51 PM PDT 24
Peak memory 199140 kb
Host smart-21c19656-fd2e-479a-a9a3-e4126d1618e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111292486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.4111292486
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.2036688963
Short name T959
Test name
Test status
Simulation time 185347210305 ps
CPU time 115.95 seconds
Started Apr 25 01:37:48 PM PDT 24
Finished Apr 25 01:39:45 PM PDT 24
Peak memory 200068 kb
Host smart-762511d7-1c8e-449d-81e0-507c9cff25b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036688963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.2036688963
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.4165929158
Short name T418
Test name
Test status
Simulation time 25652211887 ps
CPU time 215.26 seconds
Started Apr 25 01:37:48 PM PDT 24
Finished Apr 25 01:41:24 PM PDT 24
Peak memory 200384 kb
Host smart-de45be29-633c-4f42-b586-bcfcedf6048b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4165929158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.4165929158
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.2635961309
Short name T890
Test name
Test status
Simulation time 2565673170 ps
CPU time 1.89 seconds
Started Apr 25 01:37:48 PM PDT 24
Finished Apr 25 01:37:51 PM PDT 24
Peak memory 198480 kb
Host smart-7a004ae0-1b92-4e69-9641-5b9347e21c15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2635961309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.2635961309
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.1093055805
Short name T1
Test name
Test status
Simulation time 27262720852 ps
CPU time 62.42 seconds
Started Apr 25 01:37:51 PM PDT 24
Finished Apr 25 01:38:54 PM PDT 24
Peak memory 199688 kb
Host smart-9abdc963-46e4-442f-8e87-59e62f50e299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093055805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1093055805
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.2348360374
Short name T860
Test name
Test status
Simulation time 3288317464 ps
CPU time 5.43 seconds
Started Apr 25 01:37:47 PM PDT 24
Finished Apr 25 01:37:53 PM PDT 24
Peak memory 196244 kb
Host smart-ce591c6a-1983-41ed-b596-5b77b5b53334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348360374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.2348360374
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.2294601673
Short name T339
Test name
Test status
Simulation time 466224961 ps
CPU time 2.67 seconds
Started Apr 25 01:37:41 PM PDT 24
Finished Apr 25 01:37:44 PM PDT 24
Peak memory 198632 kb
Host smart-b43ca413-b93d-4094-8959-d3d8f740945f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294601673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.2294601673
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.3328319272
Short name T164
Test name
Test status
Simulation time 329446007716 ps
CPU time 2369.43 seconds
Started Apr 25 01:37:47 PM PDT 24
Finished Apr 25 02:17:17 PM PDT 24
Peak memory 200376 kb
Host smart-c04cc911-b37b-46ee-bd7c-8e5e249a7ea2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328319272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.3328319272
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.3377088714
Short name T287
Test name
Test status
Simulation time 207347785901 ps
CPU time 403.75 seconds
Started Apr 25 01:37:50 PM PDT 24
Finished Apr 25 01:44:34 PM PDT 24
Peak memory 216400 kb
Host smart-456054f8-8d27-418e-8a02-7acafd79970f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377088714 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.3377088714
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.3314073174
Short name T698
Test name
Test status
Simulation time 1303543992 ps
CPU time 1.67 seconds
Started Apr 25 01:37:47 PM PDT 24
Finished Apr 25 01:37:50 PM PDT 24
Peak memory 199472 kb
Host smart-36130102-3c94-4737-8a84-593f2e402584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314073174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.3314073174
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.1420975165
Short name T966
Test name
Test status
Simulation time 118682233158 ps
CPU time 124.12 seconds
Started Apr 25 01:37:42 PM PDT 24
Finished Apr 25 01:39:47 PM PDT 24
Peak memory 200372 kb
Host smart-4dd1d90b-f144-4237-bd25-6f61aa1a0f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420975165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.1420975165
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.317235639
Short name T1020
Test name
Test status
Simulation time 15368310 ps
CPU time 0.57 seconds
Started Apr 25 01:38:01 PM PDT 24
Finished Apr 25 01:38:02 PM PDT 24
Peak memory 195824 kb
Host smart-32c842b8-5066-43ab-8170-16bc84fece52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317235639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.317235639
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.1811246988
Short name T1071
Test name
Test status
Simulation time 94975073113 ps
CPU time 213.74 seconds
Started Apr 25 01:37:47 PM PDT 24
Finished Apr 25 01:41:22 PM PDT 24
Peak memory 200308 kb
Host smart-4a7aaf20-e029-4974-a428-e9a2df039633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811246988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.1811246988
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.1759292160
Short name T1040
Test name
Test status
Simulation time 116683155093 ps
CPU time 91.56 seconds
Started Apr 25 01:37:47 PM PDT 24
Finished Apr 25 01:39:19 PM PDT 24
Peak memory 199816 kb
Host smart-a1c9fa0d-fc44-4a11-9e80-56c941893786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759292160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.1759292160
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.3807523611
Short name T984
Test name
Test status
Simulation time 453235577939 ps
CPU time 69.77 seconds
Started Apr 25 01:37:53 PM PDT 24
Finished Apr 25 01:39:04 PM PDT 24
Peak memory 200360 kb
Host smart-2b284fb6-53e8-419d-bd43-4e84d83635df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807523611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.3807523611
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.48203015
Short name T1129
Test name
Test status
Simulation time 21566821501 ps
CPU time 5.51 seconds
Started Apr 25 01:38:01 PM PDT 24
Finished Apr 25 01:38:07 PM PDT 24
Peak memory 197600 kb
Host smart-89e02145-75ff-4aa5-b3c9-14993018241d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48203015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.48203015
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.3120871364
Short name T763
Test name
Test status
Simulation time 145358589543 ps
CPU time 783.29 seconds
Started Apr 25 01:38:00 PM PDT 24
Finished Apr 25 01:51:05 PM PDT 24
Peak memory 200440 kb
Host smart-92147374-4980-4707-b42d-a91fbc349755
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3120871364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.3120871364
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.3399021860
Short name T454
Test name
Test status
Simulation time 7016518186 ps
CPU time 14.36 seconds
Started Apr 25 01:38:02 PM PDT 24
Finished Apr 25 01:38:17 PM PDT 24
Peak memory 200384 kb
Host smart-c03cff79-90f5-4d1b-9b4b-22fae352ded3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399021860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3399021860
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.2464557133
Short name T319
Test name
Test status
Simulation time 18117654678 ps
CPU time 14.76 seconds
Started Apr 25 01:37:54 PM PDT 24
Finished Apr 25 01:38:09 PM PDT 24
Peak memory 197312 kb
Host smart-ffb9b5e2-1496-4e8a-b480-f945b5600b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464557133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.2464557133
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.2099364185
Short name T245
Test name
Test status
Simulation time 8955562850 ps
CPU time 528.92 seconds
Started Apr 25 01:38:01 PM PDT 24
Finished Apr 25 01:46:51 PM PDT 24
Peak memory 200336 kb
Host smart-e2354ab2-3642-4756-a923-6f3c0264877c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2099364185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.2099364185
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.2344766788
Short name T524
Test name
Test status
Simulation time 4506829465 ps
CPU time 38.01 seconds
Started Apr 25 01:38:00 PM PDT 24
Finished Apr 25 01:38:38 PM PDT 24
Peak memory 198568 kb
Host smart-8e0e4802-ff15-40f8-8875-6ac7b73678ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2344766788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.2344766788
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.439223603
Short name T609
Test name
Test status
Simulation time 99091310642 ps
CPU time 160.56 seconds
Started Apr 25 01:37:54 PM PDT 24
Finished Apr 25 01:40:35 PM PDT 24
Peak memory 199948 kb
Host smart-c6dae59c-c091-473c-90e3-2becaf174dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439223603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.439223603
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.1950776629
Short name T1089
Test name
Test status
Simulation time 5541676448 ps
CPU time 4.66 seconds
Started Apr 25 01:37:53 PM PDT 24
Finished Apr 25 01:37:59 PM PDT 24
Peak memory 196436 kb
Host smart-2e6155af-167d-49b5-9c74-ebb94c238c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950776629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.1950776629
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.211002243
Short name T37
Test name
Test status
Simulation time 961451080 ps
CPU time 2.25 seconds
Started Apr 25 01:37:49 PM PDT 24
Finished Apr 25 01:37:52 PM PDT 24
Peak memory 200244 kb
Host smart-08bedeba-c9f8-4cf9-991d-7ba394358141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211002243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.211002243
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.585840911
Short name T272
Test name
Test status
Simulation time 301693596399 ps
CPU time 339.89 seconds
Started Apr 25 01:37:59 PM PDT 24
Finished Apr 25 01:43:39 PM PDT 24
Peak memory 200416 kb
Host smart-4ff6f3ab-5941-47ee-85e6-36d10ff905dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585840911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.585840911
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.3156304215
Short name T1060
Test name
Test status
Simulation time 8374481598 ps
CPU time 10.28 seconds
Started Apr 25 01:37:54 PM PDT 24
Finished Apr 25 01:38:05 PM PDT 24
Peak memory 200188 kb
Host smart-1217441b-c2a4-4eff-90c4-b17d837f870b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156304215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.3156304215
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.559289744
Short name T508
Test name
Test status
Simulation time 35257531685 ps
CPU time 13.34 seconds
Started Apr 25 01:37:49 PM PDT 24
Finished Apr 25 01:38:03 PM PDT 24
Peak memory 197300 kb
Host smart-8cab2537-b858-477f-8c24-55c710449971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559289744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.559289744
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.674312592
Short name T1161
Test name
Test status
Simulation time 40700093 ps
CPU time 0.53 seconds
Started Apr 25 01:38:06 PM PDT 24
Finished Apr 25 01:38:07 PM PDT 24
Peak memory 195772 kb
Host smart-a392fa6c-2ea7-475d-a4e9-11ed777a969e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674312592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.674312592
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.2094976944
Short name T409
Test name
Test status
Simulation time 192895901677 ps
CPU time 149.81 seconds
Started Apr 25 01:38:04 PM PDT 24
Finished Apr 25 01:40:35 PM PDT 24
Peak memory 200408 kb
Host smart-174146cd-8a21-434f-9b3f-0226253b44c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094976944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2094976944
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.3247156761
Short name T904
Test name
Test status
Simulation time 19948264700 ps
CPU time 31.14 seconds
Started Apr 25 01:38:00 PM PDT 24
Finished Apr 25 01:38:32 PM PDT 24
Peak memory 200296 kb
Host smart-4e857dca-9559-4e71-8574-835852213ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247156761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.3247156761
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.1485772122
Short name T1064
Test name
Test status
Simulation time 153682076054 ps
CPU time 15.1 seconds
Started Apr 25 01:38:09 PM PDT 24
Finished Apr 25 01:38:24 PM PDT 24
Peak memory 200352 kb
Host smart-d3352089-4b16-47b0-8014-70c0a2d551fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485772122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.1485772122
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.1945583011
Short name T1069
Test name
Test status
Simulation time 27980210409 ps
CPU time 69.29 seconds
Started Apr 25 01:38:10 PM PDT 24
Finished Apr 25 01:39:19 PM PDT 24
Peak memory 200436 kb
Host smart-cc4b7113-a276-4ef0-96a2-ae626a635103
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945583011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.1945583011
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.276391821
Short name T38
Test name
Test status
Simulation time 131821200928 ps
CPU time 150.69 seconds
Started Apr 25 01:38:08 PM PDT 24
Finished Apr 25 01:40:39 PM PDT 24
Peak memory 200364 kb
Host smart-983a047a-5998-4b05-bf77-e0af123ddc96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=276391821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.276391821
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.2216984991
Short name T1007
Test name
Test status
Simulation time 4943932601 ps
CPU time 10.06 seconds
Started Apr 25 01:38:07 PM PDT 24
Finished Apr 25 01:38:18 PM PDT 24
Peak memory 200376 kb
Host smart-2a4b50c9-a29c-40c6-bf5d-e728c21c641f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216984991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.2216984991
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.1742084067
Short name T1158
Test name
Test status
Simulation time 43633324607 ps
CPU time 40.8 seconds
Started Apr 25 01:38:07 PM PDT 24
Finished Apr 25 01:38:49 PM PDT 24
Peak memory 198508 kb
Host smart-af67d2aa-144e-4478-a742-0c1a85e2f223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742084067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.1742084067
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.1771724656
Short name T348
Test name
Test status
Simulation time 27234362065 ps
CPU time 139.16 seconds
Started Apr 25 01:38:08 PM PDT 24
Finished Apr 25 01:40:28 PM PDT 24
Peak memory 200360 kb
Host smart-e5db7979-019c-4246-b5b2-d54888f96081
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1771724656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.1771724656
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.1955365541
Short name T762
Test name
Test status
Simulation time 1805103258 ps
CPU time 6.45 seconds
Started Apr 25 01:38:09 PM PDT 24
Finished Apr 25 01:38:16 PM PDT 24
Peak memory 198984 kb
Host smart-7529d6e7-cb48-4237-85c2-512aa0f4f77a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1955365541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.1955365541
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.607604282
Short name T583
Test name
Test status
Simulation time 134086849310 ps
CPU time 84.39 seconds
Started Apr 25 01:38:10 PM PDT 24
Finished Apr 25 01:39:35 PM PDT 24
Peak memory 200372 kb
Host smart-e7dac584-204c-4d8b-92f1-222e8d5812c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607604282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.607604282
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.2483260554
Short name T884
Test name
Test status
Simulation time 49590352095 ps
CPU time 20.79 seconds
Started Apr 25 01:38:07 PM PDT 24
Finished Apr 25 01:38:28 PM PDT 24
Peak memory 196160 kb
Host smart-1b5bd201-5cbe-4e01-a281-59e501b19747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483260554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.2483260554
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.3645936113
Short name T438
Test name
Test status
Simulation time 271544060 ps
CPU time 1.98 seconds
Started Apr 25 01:38:00 PM PDT 24
Finished Apr 25 01:38:03 PM PDT 24
Peak memory 199368 kb
Host smart-2e6bc822-e326-4be7-ba8e-6879239dce99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645936113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.3645936113
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.1987277800
Short name T1124
Test name
Test status
Simulation time 262511750599 ps
CPU time 363.24 seconds
Started Apr 25 01:38:07 PM PDT 24
Finished Apr 25 01:44:10 PM PDT 24
Peak memory 208884 kb
Host smart-48570c40-1a41-430b-9509-d38bd02b4b0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987277800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.1987277800
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.4114004255
Short name T469
Test name
Test status
Simulation time 35110046593 ps
CPU time 486.22 seconds
Started Apr 25 01:38:07 PM PDT 24
Finished Apr 25 01:46:14 PM PDT 24
Peak memory 208604 kb
Host smart-07e9eae4-99f4-4984-9e78-4f3c2191584a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114004255 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.4114004255
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.3943281531
Short name T337
Test name
Test status
Simulation time 4936986509 ps
CPU time 1.53 seconds
Started Apr 25 01:38:06 PM PDT 24
Finished Apr 25 01:38:08 PM PDT 24
Peak memory 200384 kb
Host smart-e05d778d-ccf3-41be-b8ad-58a0209bfb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943281531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3943281531
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.1598262092
Short name T4
Test name
Test status
Simulation time 169635815109 ps
CPU time 90.66 seconds
Started Apr 25 01:38:00 PM PDT 24
Finished Apr 25 01:39:32 PM PDT 24
Peak memory 200380 kb
Host smart-8e7f96a9-276f-4382-9b2d-f3fdce85b190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598262092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.1598262092
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.3166597181
Short name T417
Test name
Test status
Simulation time 52151624 ps
CPU time 0.55 seconds
Started Apr 25 01:38:20 PM PDT 24
Finished Apr 25 01:38:22 PM PDT 24
Peak memory 195536 kb
Host smart-62ae4ed8-e319-4f42-a427-cadc5124c4b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166597181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.3166597181
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.1831847008
Short name T133
Test name
Test status
Simulation time 93726739475 ps
CPU time 140.48 seconds
Started Apr 25 01:38:07 PM PDT 24
Finished Apr 25 01:40:28 PM PDT 24
Peak memory 200436 kb
Host smart-edb9c137-ae18-4a5f-b1fc-6bb45176ae7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831847008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.1831847008
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.258909014
Short name T126
Test name
Test status
Simulation time 139892709110 ps
CPU time 97.79 seconds
Started Apr 25 01:38:11 PM PDT 24
Finished Apr 25 01:39:49 PM PDT 24
Peak memory 200420 kb
Host smart-6e0b8492-dd3e-4a41-9ac8-08e024ced492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258909014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.258909014
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.2096951208
Short name T797
Test name
Test status
Simulation time 140155470717 ps
CPU time 59.6 seconds
Started Apr 25 01:38:13 PM PDT 24
Finished Apr 25 01:39:13 PM PDT 24
Peak memory 200256 kb
Host smart-14718d5a-b93a-486f-badf-b968d8f22571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096951208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.2096951208
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.2215204426
Short name T831
Test name
Test status
Simulation time 247936771962 ps
CPU time 147.51 seconds
Started Apr 25 01:38:14 PM PDT 24
Finished Apr 25 01:40:42 PM PDT 24
Peak memory 200260 kb
Host smart-411be425-f6d4-4835-ac4e-de13c29e1c10
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215204426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.2215204426
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.862471636
Short name T497
Test name
Test status
Simulation time 130933382416 ps
CPU time 348.63 seconds
Started Apr 25 01:38:14 PM PDT 24
Finished Apr 25 01:44:03 PM PDT 24
Peak memory 200404 kb
Host smart-f162f64d-ab59-489d-b93c-f4bddbd13f23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=862471636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.862471636
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.3561798688
Short name T422
Test name
Test status
Simulation time 67539481 ps
CPU time 0.6 seconds
Started Apr 25 01:38:13 PM PDT 24
Finished Apr 25 01:38:14 PM PDT 24
Peak memory 196160 kb
Host smart-0fb6bae5-553e-403e-9fa0-59a9b8b49bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561798688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.3561798688
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.2801520826
Short name T1063
Test name
Test status
Simulation time 13244748977 ps
CPU time 14.27 seconds
Started Apr 25 01:38:14 PM PDT 24
Finished Apr 25 01:38:28 PM PDT 24
Peak memory 198720 kb
Host smart-331315fd-af81-4f80-9a99-0bae327cb406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801520826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.2801520826
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.3351294541
Short name T775
Test name
Test status
Simulation time 20795291464 ps
CPU time 1038.86 seconds
Started Apr 25 01:38:12 PM PDT 24
Finished Apr 25 01:55:31 PM PDT 24
Peak memory 200452 kb
Host smart-15051ae5-9f6a-4fe2-bae1-3622b7bb17db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3351294541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.3351294541
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.1480500571
Short name T878
Test name
Test status
Simulation time 6556005844 ps
CPU time 59.37 seconds
Started Apr 25 01:38:13 PM PDT 24
Finished Apr 25 01:39:13 PM PDT 24
Peak memory 199608 kb
Host smart-ba42863a-535a-49d9-b6ae-12ea50e62e9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1480500571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.1480500571
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.3828999892
Short name T938
Test name
Test status
Simulation time 120518361890 ps
CPU time 233.22 seconds
Started Apr 25 01:38:13 PM PDT 24
Finished Apr 25 01:42:07 PM PDT 24
Peak memory 200368 kb
Host smart-58dfd305-bfe8-4641-beb0-200890bd6dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828999892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3828999892
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.3543516459
Short name T578
Test name
Test status
Simulation time 37280135246 ps
CPU time 64.33 seconds
Started Apr 25 01:38:12 PM PDT 24
Finished Apr 25 01:39:17 PM PDT 24
Peak memory 196132 kb
Host smart-eeacd2c2-48a9-44b6-930b-dae8dd3e153a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543516459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3543516459
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.1589834186
Short name T639
Test name
Test status
Simulation time 5799630411 ps
CPU time 9.2 seconds
Started Apr 25 01:38:08 PM PDT 24
Finished Apr 25 01:38:17 PM PDT 24
Peak memory 199548 kb
Host smart-b9e751db-513f-4b2c-b027-c2dd6f6174be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589834186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.1589834186
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.1611604645
Short name T764
Test name
Test status
Simulation time 126109223410 ps
CPU time 1772.84 seconds
Started Apr 25 01:38:20 PM PDT 24
Finished Apr 25 02:07:53 PM PDT 24
Peak memory 208828 kb
Host smart-e40f62f1-ea3b-46d6-aff1-cfb05207abb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611604645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.1611604645
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.2549354233
Short name T155
Test name
Test status
Simulation time 345164317331 ps
CPU time 736.55 seconds
Started Apr 25 01:38:14 PM PDT 24
Finished Apr 25 01:50:31 PM PDT 24
Peak memory 225220 kb
Host smart-97708390-3d80-4f8b-8a07-21fecde22b25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549354233 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.2549354233
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.2023717542
Short name T1119
Test name
Test status
Simulation time 7395149288 ps
CPU time 11.13 seconds
Started Apr 25 01:38:13 PM PDT 24
Finished Apr 25 01:38:25 PM PDT 24
Peak memory 200304 kb
Host smart-a128d704-6aa4-46d8-84ee-87419025adec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023717542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.2023717542
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.4160364528
Short name T1170
Test name
Test status
Simulation time 30265080261 ps
CPU time 13.9 seconds
Started Apr 25 01:38:05 PM PDT 24
Finished Apr 25 01:38:20 PM PDT 24
Peak memory 200332 kb
Host smart-e32881bd-6fcc-4140-8060-2c99f42d833f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160364528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.4160364528
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.4126691845
Short name T1011
Test name
Test status
Simulation time 75055988 ps
CPU time 0.51 seconds
Started Apr 25 01:38:22 PM PDT 24
Finished Apr 25 01:38:23 PM PDT 24
Peak memory 194656 kb
Host smart-2666f872-0f1c-44dc-838f-1c734abff385
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126691845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.4126691845
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.1666569513
Short name T1108
Test name
Test status
Simulation time 15727615196 ps
CPU time 26.61 seconds
Started Apr 25 01:38:19 PM PDT 24
Finished Apr 25 01:38:46 PM PDT 24
Peak memory 200416 kb
Host smart-9139432a-e95f-443b-aa27-76df2b8dea46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666569513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.1666569513
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.2901138780
Short name T1081
Test name
Test status
Simulation time 34875731649 ps
CPU time 51.54 seconds
Started Apr 25 01:38:20 PM PDT 24
Finished Apr 25 01:39:12 PM PDT 24
Peak memory 200020 kb
Host smart-dd330ad4-34de-437f-9fe7-8483d0eaf2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901138780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.2901138780
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.3294601243
Short name T610
Test name
Test status
Simulation time 108642281836 ps
CPU time 39.45 seconds
Started Apr 25 01:38:19 PM PDT 24
Finished Apr 25 01:39:00 PM PDT 24
Peak memory 199744 kb
Host smart-77cb37da-1959-4c64-a99c-79a6ac1eee99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294601243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3294601243
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.132791202
Short name T1033
Test name
Test status
Simulation time 39661945705 ps
CPU time 19.89 seconds
Started Apr 25 01:38:19 PM PDT 24
Finished Apr 25 01:38:40 PM PDT 24
Peak memory 200404 kb
Host smart-72fd25a7-8a8a-4689-8222-31537440c8fc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132791202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.132791202
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.3701266538
Short name T342
Test name
Test status
Simulation time 133377574812 ps
CPU time 309.58 seconds
Started Apr 25 01:38:20 PM PDT 24
Finished Apr 25 01:43:30 PM PDT 24
Peak memory 200432 kb
Host smart-fdc0ff43-15d6-42a6-a109-fe03a27e806b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3701266538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.3701266538
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.4242335457
Short name T988
Test name
Test status
Simulation time 11359322789 ps
CPU time 19.94 seconds
Started Apr 25 01:38:18 PM PDT 24
Finished Apr 25 01:38:39 PM PDT 24
Peak memory 200328 kb
Host smart-22c97163-99c5-4eea-a0c9-9945fe9ee338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242335457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.4242335457
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.2185434590
Short name T10
Test name
Test status
Simulation time 27219845757 ps
CPU time 53.17 seconds
Started Apr 25 01:38:19 PM PDT 24
Finished Apr 25 01:39:13 PM PDT 24
Peak memory 200632 kb
Host smart-2d782a4d-5cdf-4ee6-996a-3db26b4a56be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185434590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.2185434590
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.3475941371
Short name T327
Test name
Test status
Simulation time 25101422891 ps
CPU time 1368.32 seconds
Started Apr 25 01:38:18 PM PDT 24
Finished Apr 25 02:01:07 PM PDT 24
Peak memory 200460 kb
Host smart-a012ef6c-a593-4c72-ba12-94aa45b6222b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3475941371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.3475941371
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.4037484110
Short name T558
Test name
Test status
Simulation time 5924571995 ps
CPU time 53.31 seconds
Started Apr 25 01:38:19 PM PDT 24
Finished Apr 25 01:39:12 PM PDT 24
Peak memory 199520 kb
Host smart-aafb5286-6eaa-47b9-a535-3b2aed3405fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4037484110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.4037484110
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.2370229913
Short name T516
Test name
Test status
Simulation time 215111193950 ps
CPU time 75.43 seconds
Started Apr 25 01:38:20 PM PDT 24
Finished Apr 25 01:39:36 PM PDT 24
Peak memory 200112 kb
Host smart-dcf5f5e0-bf53-4783-bb28-5bb5e11afd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370229913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.2370229913
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.1314701085
Short name T250
Test name
Test status
Simulation time 47443119665 ps
CPU time 18.49 seconds
Started Apr 25 01:38:20 PM PDT 24
Finished Apr 25 01:38:39 PM PDT 24
Peak memory 196124 kb
Host smart-f41dca5c-e5d2-4538-8207-d369189589d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314701085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.1314701085
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.115221378
Short name T1085
Test name
Test status
Simulation time 927870768 ps
CPU time 3.21 seconds
Started Apr 25 01:38:19 PM PDT 24
Finished Apr 25 01:38:22 PM PDT 24
Peak memory 200156 kb
Host smart-86549910-29e5-46a1-acb1-fed9f0958fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115221378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.115221378
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.2710711943
Short name T254
Test name
Test status
Simulation time 133242014826 ps
CPU time 256.99 seconds
Started Apr 25 01:38:25 PM PDT 24
Finished Apr 25 01:42:42 PM PDT 24
Peak memory 200432 kb
Host smart-f625080d-7336-40eb-89c2-e2b434cc9963
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710711943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.2710711943
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.4087623059
Short name T1164
Test name
Test status
Simulation time 40144135920 ps
CPU time 538.91 seconds
Started Apr 25 01:38:23 PM PDT 24
Finished Apr 25 01:47:22 PM PDT 24
Peak memory 211948 kb
Host smart-b872cbd0-e316-44b1-9223-8ace759af2ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087623059 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.4087623059
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.180446205
Short name T720
Test name
Test status
Simulation time 1102770512 ps
CPU time 3.82 seconds
Started Apr 25 01:38:19 PM PDT 24
Finished Apr 25 01:38:23 PM PDT 24
Peak memory 199140 kb
Host smart-ef4e11bf-dff2-458c-95f6-94278c38da7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180446205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.180446205
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.292700405
Short name T96
Test name
Test status
Simulation time 41959985915 ps
CPU time 24.28 seconds
Started Apr 25 01:38:20 PM PDT 24
Finished Apr 25 01:38:45 PM PDT 24
Peak memory 200364 kb
Host smart-3f77620f-879f-4410-ad2b-2618f65eda2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292700405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.292700405
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.1930245731
Short name T500
Test name
Test status
Simulation time 28270494 ps
CPU time 0.57 seconds
Started Apr 25 01:38:33 PM PDT 24
Finished Apr 25 01:38:33 PM PDT 24
Peak memory 195804 kb
Host smart-5addfdbb-70aa-4338-8690-c23b00947aaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930245731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.1930245731
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.628747129
Short name T552
Test name
Test status
Simulation time 136462768854 ps
CPU time 16.85 seconds
Started Apr 25 01:38:24 PM PDT 24
Finished Apr 25 01:38:42 PM PDT 24
Peak memory 200196 kb
Host smart-0859f178-45be-47f9-b48c-66bb598ef300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628747129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.628747129
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.4182573471
Short name T1035
Test name
Test status
Simulation time 15896779969 ps
CPU time 50.52 seconds
Started Apr 25 01:38:25 PM PDT 24
Finished Apr 25 01:39:16 PM PDT 24
Peak memory 200428 kb
Host smart-39846404-8b19-44e8-a075-722de94b8a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182573471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.4182573471
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_intr.2754711215
Short name T1023
Test name
Test status
Simulation time 19738264858 ps
CPU time 7.74 seconds
Started Apr 25 01:38:30 PM PDT 24
Finished Apr 25 01:38:39 PM PDT 24
Peak memory 200316 kb
Host smart-36b61897-a9b6-46d6-b640-4042a1cd3507
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754711215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.2754711215
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.94115279
Short name T1070
Test name
Test status
Simulation time 164472007346 ps
CPU time 298.36 seconds
Started Apr 25 01:38:30 PM PDT 24
Finished Apr 25 01:43:29 PM PDT 24
Peak memory 200424 kb
Host smart-f35231a9-ca21-45f4-933b-b5954884b5f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=94115279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.94115279
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.2969809678
Short name T601
Test name
Test status
Simulation time 5999487038 ps
CPU time 16.45 seconds
Started Apr 25 01:38:31 PM PDT 24
Finished Apr 25 01:38:48 PM PDT 24
Peak memory 200392 kb
Host smart-658a3c86-5e62-4705-9e57-f7032da39a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969809678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.2969809678
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.1983053522
Short name T586
Test name
Test status
Simulation time 32470955929 ps
CPU time 25.86 seconds
Started Apr 25 01:38:35 PM PDT 24
Finished Apr 25 01:39:01 PM PDT 24
Peak memory 200560 kb
Host smart-381278e6-df04-4e73-8ad1-b4139fa4e8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983053522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.1983053522
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.2160235563
Short name T1103
Test name
Test status
Simulation time 9974243840 ps
CPU time 135.54 seconds
Started Apr 25 01:38:30 PM PDT 24
Finished Apr 25 01:40:46 PM PDT 24
Peak memory 200460 kb
Host smart-345bbc19-38c8-41b8-b69c-45f630583c25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2160235563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.2160235563
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.1508744219
Short name T35
Test name
Test status
Simulation time 5761512476 ps
CPU time 24.54 seconds
Started Apr 25 01:38:22 PM PDT 24
Finished Apr 25 01:38:48 PM PDT 24
Peak memory 198556 kb
Host smart-87e5e281-789f-4cb8-9f5a-2e46241dcc85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1508744219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.1508744219
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.3624730558
Short name T837
Test name
Test status
Simulation time 114545176186 ps
CPU time 183.39 seconds
Started Apr 25 01:38:29 PM PDT 24
Finished Apr 25 01:41:33 PM PDT 24
Peak memory 200376 kb
Host smart-e831d3f7-121a-4601-b81e-900d9e8380d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624730558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.3624730558
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.3301754072
Short name T892
Test name
Test status
Simulation time 4542657870 ps
CPU time 2.41 seconds
Started Apr 25 01:38:30 PM PDT 24
Finished Apr 25 01:38:33 PM PDT 24
Peak memory 196444 kb
Host smart-6cdbdcf9-c7da-464c-affb-b764cc12b35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301754072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.3301754072
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.3080587878
Short name T279
Test name
Test status
Simulation time 289194228 ps
CPU time 1.81 seconds
Started Apr 25 01:38:24 PM PDT 24
Finished Apr 25 01:38:27 PM PDT 24
Peak memory 198928 kb
Host smart-ecff3f8a-6e5f-4acf-b2ea-eb0fa7c7da8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080587878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.3080587878
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.2609018523
Short name T1072
Test name
Test status
Simulation time 200044821865 ps
CPU time 199.61 seconds
Started Apr 25 01:38:31 PM PDT 24
Finished Apr 25 01:41:51 PM PDT 24
Peak memory 208808 kb
Host smart-1c3a4a43-1688-4107-886e-5db0f8c4699b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609018523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.2609018523
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.292658545
Short name T982
Test name
Test status
Simulation time 162313246088 ps
CPU time 670.52 seconds
Started Apr 25 01:38:31 PM PDT 24
Finished Apr 25 01:49:42 PM PDT 24
Peak memory 216940 kb
Host smart-1ad60b1b-40cf-42fe-8ee3-fbc0b5159b7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292658545 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.292658545
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.2951635445
Short name T842
Test name
Test status
Simulation time 1557695813 ps
CPU time 2.35 seconds
Started Apr 25 01:38:31 PM PDT 24
Finished Apr 25 01:38:34 PM PDT 24
Peak memory 199240 kb
Host smart-03edcdce-5366-4c1e-acc9-6ca426074acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951635445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.2951635445
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.553688244
Short name T769
Test name
Test status
Simulation time 26741507603 ps
CPU time 40.98 seconds
Started Apr 25 01:38:24 PM PDT 24
Finished Apr 25 01:39:06 PM PDT 24
Peak memory 200400 kb
Host smart-8a2e5a48-195a-4d9b-ac6f-eed900982aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553688244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.553688244
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.3051676200
Short name T1107
Test name
Test status
Simulation time 33888765 ps
CPU time 0.53 seconds
Started Apr 25 01:33:30 PM PDT 24
Finished Apr 25 01:33:31 PM PDT 24
Peak memory 195796 kb
Host smart-5ad3c58a-f341-48b7-9383-6e24c5ccb9e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051676200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.3051676200
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.1726789271
Short name T838
Test name
Test status
Simulation time 76489475666 ps
CPU time 82.13 seconds
Started Apr 25 01:33:24 PM PDT 24
Finished Apr 25 01:34:47 PM PDT 24
Peak memory 200460 kb
Host smart-ce7f0138-c783-4ba5-80a8-0f5fb3ce43b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726789271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.1726789271
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.3107205186
Short name T990
Test name
Test status
Simulation time 63677165956 ps
CPU time 14.03 seconds
Started Apr 25 01:33:25 PM PDT 24
Finished Apr 25 01:33:40 PM PDT 24
Peak memory 200356 kb
Host smart-c61e95ff-312e-40de-9947-d973de01d303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107205186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.3107205186
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.1857582705
Short name T229
Test name
Test status
Simulation time 166911292489 ps
CPU time 30.6 seconds
Started Apr 25 01:33:25 PM PDT 24
Finished Apr 25 01:33:57 PM PDT 24
Peak memory 200248 kb
Host smart-a7168dc7-8000-4cf8-bd09-928b0abce45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857582705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.1857582705
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.3157485048
Short name T924
Test name
Test status
Simulation time 49068144757 ps
CPU time 21.51 seconds
Started Apr 25 01:33:26 PM PDT 24
Finished Apr 25 01:33:48 PM PDT 24
Peak memory 200240 kb
Host smart-86683129-d17b-45b7-a4b2-501c059193e9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157485048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.3157485048
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.2780838909
Short name T472
Test name
Test status
Simulation time 102343885940 ps
CPU time 529.86 seconds
Started Apr 25 01:33:25 PM PDT 24
Finished Apr 25 01:42:16 PM PDT 24
Peak memory 200460 kb
Host smart-b0807aab-e352-4ad3-9bef-e16be7363740
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2780838909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.2780838909
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.3087305109
Short name T391
Test name
Test status
Simulation time 2539941232 ps
CPU time 1.47 seconds
Started Apr 25 01:33:26 PM PDT 24
Finished Apr 25 01:33:28 PM PDT 24
Peak memory 198172 kb
Host smart-9c43165f-01c6-4f31-8b02-4de7e053d3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087305109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.3087305109
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.2431738231
Short name T1173
Test name
Test status
Simulation time 164832465777 ps
CPU time 144.5 seconds
Started Apr 25 01:33:25 PM PDT 24
Finished Apr 25 01:35:50 PM PDT 24
Peak memory 200772 kb
Host smart-b879f501-39c7-4f8c-8408-6b55e7029ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431738231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.2431738231
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.928055535
Short name T278
Test name
Test status
Simulation time 8146764274 ps
CPU time 473.63 seconds
Started Apr 25 01:33:25 PM PDT 24
Finished Apr 25 01:41:19 PM PDT 24
Peak memory 200432 kb
Host smart-3dacd4b8-bb30-4ff8-9346-39ae5a41fbef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=928055535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.928055535
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.4174153527
Short name T1172
Test name
Test status
Simulation time 2230102162 ps
CPU time 13.23 seconds
Started Apr 25 01:33:26 PM PDT 24
Finished Apr 25 01:33:40 PM PDT 24
Peak memory 199692 kb
Host smart-1df5cefd-9c4c-4da0-abe9-1fba206f4dad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4174153527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.4174153527
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.1200183336
Short name T423
Test name
Test status
Simulation time 24277307361 ps
CPU time 12.8 seconds
Started Apr 25 01:33:26 PM PDT 24
Finished Apr 25 01:33:39 PM PDT 24
Peak memory 200380 kb
Host smart-c6216eaf-5608-4bc7-99c8-fecdac83933c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200183336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.1200183336
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.384098914
Short name T1145
Test name
Test status
Simulation time 73301262259 ps
CPU time 125.08 seconds
Started Apr 25 01:33:25 PM PDT 24
Finished Apr 25 01:35:31 PM PDT 24
Peak memory 196688 kb
Host smart-2d959de1-c1f0-448c-89d0-6fb42503d064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384098914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.384098914
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.1368022518
Short name T83
Test name
Test status
Simulation time 232759636 ps
CPU time 0.85 seconds
Started Apr 25 01:33:31 PM PDT 24
Finished Apr 25 01:33:32 PM PDT 24
Peak memory 218444 kb
Host smart-2294e88a-190d-4220-929c-d8b7f6445ded
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368022518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.1368022518
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.2558829674
Short name T779
Test name
Test status
Simulation time 539397507 ps
CPU time 1.22 seconds
Started Apr 25 01:33:16 PM PDT 24
Finished Apr 25 01:33:18 PM PDT 24
Peak memory 199112 kb
Host smart-79713ca1-a012-4480-971e-6fefd98b7ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558829674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.2558829674
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.2387760269
Short name T107
Test name
Test status
Simulation time 145230071373 ps
CPU time 1113.56 seconds
Started Apr 25 01:33:31 PM PDT 24
Finished Apr 25 01:52:05 PM PDT 24
Peak memory 200368 kb
Host smart-334b48ae-a366-4e7e-9e23-47166f91dca7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387760269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2387760269
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.1799795565
Short name T45
Test name
Test status
Simulation time 118200793978 ps
CPU time 1313.84 seconds
Started Apr 25 01:33:31 PM PDT 24
Finished Apr 25 01:55:25 PM PDT 24
Peak memory 229324 kb
Host smart-1c7e1519-9685-45cf-81a7-5039f535193d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799795565 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.1799795565
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.1973346185
Short name T792
Test name
Test status
Simulation time 6941234504 ps
CPU time 31.45 seconds
Started Apr 25 01:33:24 PM PDT 24
Finished Apr 25 01:33:57 PM PDT 24
Peak memory 200348 kb
Host smart-bce28f73-aa6c-44f4-abf4-2c6b808edf73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973346185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.1973346185
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.1861417858
Short name T1183
Test name
Test status
Simulation time 15277051637 ps
CPU time 6.62 seconds
Started Apr 25 01:33:19 PM PDT 24
Finished Apr 25 01:33:26 PM PDT 24
Peak memory 200392 kb
Host smart-ef7e13f7-ae1d-47b4-a07a-407d85aa3cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861417858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.1861417858
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.422767726
Short name T396
Test name
Test status
Simulation time 37741889 ps
CPU time 0.58 seconds
Started Apr 25 01:38:42 PM PDT 24
Finished Apr 25 01:38:43 PM PDT 24
Peak memory 195792 kb
Host smart-86fb21b2-70b1-4491-9f12-cd386db1e709
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422767726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.422767726
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.1205992502
Short name T262
Test name
Test status
Simulation time 16386480675 ps
CPU time 26.2 seconds
Started Apr 25 01:38:35 PM PDT 24
Finished Apr 25 01:39:02 PM PDT 24
Peak memory 200436 kb
Host smart-2ba83eb1-7bf4-4d51-8a3b-3be8875544db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205992502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.1205992502
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.1161614991
Short name T1163
Test name
Test status
Simulation time 78321452291 ps
CPU time 122.94 seconds
Started Apr 25 01:38:35 PM PDT 24
Finished Apr 25 01:40:39 PM PDT 24
Peak memory 200340 kb
Host smart-4f24caa6-1b94-4d05-b8d0-fd0d3ff1d497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161614991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.1161614991
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.4232621884
Short name T183
Test name
Test status
Simulation time 134524056128 ps
CPU time 112.23 seconds
Started Apr 25 01:38:58 PM PDT 24
Finished Apr 25 01:40:51 PM PDT 24
Peak memory 200428 kb
Host smart-0ff7f97f-a70e-4421-92a2-a34a953df416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232621884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.4232621884
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.137151108
Short name T413
Test name
Test status
Simulation time 48577321246 ps
CPU time 37.84 seconds
Started Apr 25 01:38:36 PM PDT 24
Finished Apr 25 01:39:14 PM PDT 24
Peak memory 200420 kb
Host smart-13d825da-f970-422a-8170-225f284a680a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137151108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.137151108
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.614285047
Short name T1086
Test name
Test status
Simulation time 47753222389 ps
CPU time 245.2 seconds
Started Apr 25 01:38:35 PM PDT 24
Finished Apr 25 01:42:40 PM PDT 24
Peak memory 200352 kb
Host smart-fda959f1-e532-478d-a81a-8373cb0508ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=614285047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.614285047
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.3462163141
Short name T1024
Test name
Test status
Simulation time 5468844691 ps
CPU time 10.38 seconds
Started Apr 25 01:38:37 PM PDT 24
Finished Apr 25 01:38:48 PM PDT 24
Peak memory 197944 kb
Host smart-09f36b3e-c650-482c-a1eb-2229f1fa6639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462163141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.3462163141
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.672438850
Short name T768
Test name
Test status
Simulation time 72637454641 ps
CPU time 38.07 seconds
Started Apr 25 01:38:39 PM PDT 24
Finished Apr 25 01:39:18 PM PDT 24
Peak memory 200604 kb
Host smart-ffb11798-be31-4be6-8556-92a73ca1761c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672438850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.672438850
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.2929351569
Short name T980
Test name
Test status
Simulation time 14422912493 ps
CPU time 266.27 seconds
Started Apr 25 01:38:37 PM PDT 24
Finished Apr 25 01:43:03 PM PDT 24
Peak memory 200460 kb
Host smart-3ac3c869-9016-4d49-942c-37229b34b980
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2929351569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.2929351569
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.1547679614
Short name T940
Test name
Test status
Simulation time 6715767178 ps
CPU time 13.81 seconds
Started Apr 25 01:38:37 PM PDT 24
Finished Apr 25 01:38:51 PM PDT 24
Peak memory 199212 kb
Host smart-85aaf7b8-8b61-4962-a8b2-ddd09473f497
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1547679614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.1547679614
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.2785066998
Short name T286
Test name
Test status
Simulation time 15886604583 ps
CPU time 29.78 seconds
Started Apr 25 01:38:36 PM PDT 24
Finished Apr 25 01:39:07 PM PDT 24
Peak memory 200384 kb
Host smart-01e721a5-bd65-4998-b097-b35338dea938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785066998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.2785066998
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.3564739009
Short name T1146
Test name
Test status
Simulation time 6446251915 ps
CPU time 5.68 seconds
Started Apr 25 01:38:36 PM PDT 24
Finished Apr 25 01:38:43 PM PDT 24
Peak memory 196696 kb
Host smart-e99c704c-b126-485e-a360-7190a37453fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564739009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.3564739009
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.3528779993
Short name T1091
Test name
Test status
Simulation time 427543578 ps
CPU time 1.78 seconds
Started Apr 25 01:38:31 PM PDT 24
Finished Apr 25 01:38:33 PM PDT 24
Peak memory 199036 kb
Host smart-ba60868b-e723-45e8-a0d6-62ec15e29931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528779993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3528779993
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.2902573447
Short name T545
Test name
Test status
Simulation time 376713612498 ps
CPU time 522.96 seconds
Started Apr 25 01:38:42 PM PDT 24
Finished Apr 25 01:47:25 PM PDT 24
Peak memory 200400 kb
Host smart-65dbb385-c75c-43cf-bd5a-d8e749f6438a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902573447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.2902573447
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.827238083
Short name T293
Test name
Test status
Simulation time 47619178716 ps
CPU time 497.53 seconds
Started Apr 25 01:38:41 PM PDT 24
Finished Apr 25 01:46:59 PM PDT 24
Peak memory 216824 kb
Host smart-5ea11dbd-3d5c-4c6e-ae3e-15d2d6b6e59d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827238083 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.827238083
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.113922174
Short name T776
Test name
Test status
Simulation time 1195787491 ps
CPU time 2.84 seconds
Started Apr 25 01:38:38 PM PDT 24
Finished Apr 25 01:38:42 PM PDT 24
Peak memory 198732 kb
Host smart-003b01f0-9d27-474a-9fa6-c450e9606a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113922174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.113922174
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.1789990949
Short name T383
Test name
Test status
Simulation time 44207375202 ps
CPU time 21.2 seconds
Started Apr 25 01:38:29 PM PDT 24
Finished Apr 25 01:38:51 PM PDT 24
Peak memory 200436 kb
Host smart-4272543b-7c9f-49c4-9157-eee6115dd8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789990949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.1789990949
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.63807211
Short name T747
Test name
Test status
Simulation time 14670308 ps
CPU time 0.56 seconds
Started Apr 25 01:38:47 PM PDT 24
Finished Apr 25 01:38:48 PM PDT 24
Peak memory 195808 kb
Host smart-737845f7-c000-4238-80fd-a9362975b3e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63807211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.63807211
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.3539188849
Short name T771
Test name
Test status
Simulation time 179105590118 ps
CPU time 117.37 seconds
Started Apr 25 01:38:41 PM PDT 24
Finished Apr 25 01:40:39 PM PDT 24
Peak memory 200444 kb
Host smart-0675234d-1362-48f3-9af3-aab1c66d6a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539188849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3539188849
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.2930752568
Short name T86
Test name
Test status
Simulation time 37199659728 ps
CPU time 35.26 seconds
Started Apr 25 01:38:42 PM PDT 24
Finished Apr 25 01:39:18 PM PDT 24
Peak memory 200436 kb
Host smart-a1ca5771-ce1e-42bb-9021-f2ecbc0fb6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930752568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.2930752568
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.1668722186
Short name T389
Test name
Test status
Simulation time 17330608991 ps
CPU time 37.03 seconds
Started Apr 25 01:38:42 PM PDT 24
Finished Apr 25 01:39:19 PM PDT 24
Peak memory 200400 kb
Host smart-319b5b98-a66b-47c5-ad1b-75d71ee190e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668722186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.1668722186
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.2559286538
Short name T596
Test name
Test status
Simulation time 31514161222 ps
CPU time 6.52 seconds
Started Apr 25 01:38:40 PM PDT 24
Finished Apr 25 01:38:47 PM PDT 24
Peak memory 200380 kb
Host smart-2c79c5f7-e17b-4d2a-9c66-964079367a1c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559286538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.2559286538
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.2361029775
Short name T801
Test name
Test status
Simulation time 79197631502 ps
CPU time 473.89 seconds
Started Apr 25 01:38:48 PM PDT 24
Finished Apr 25 01:46:43 PM PDT 24
Peak memory 200444 kb
Host smart-a3e15b17-6c52-48db-8299-d1db8714643a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2361029775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.2361029775
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.339974349
Short name T1139
Test name
Test status
Simulation time 8380542834 ps
CPU time 6.59 seconds
Started Apr 25 01:38:49 PM PDT 24
Finished Apr 25 01:38:56 PM PDT 24
Peak memory 200312 kb
Host smart-e2fae7e1-2566-41d1-85aa-28989dc4766c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339974349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.339974349
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.2970746188
Short name T611
Test name
Test status
Simulation time 19490807321 ps
CPU time 53.63 seconds
Started Apr 25 01:38:42 PM PDT 24
Finished Apr 25 01:39:36 PM PDT 24
Peak memory 200248 kb
Host smart-196b2d5d-5770-42fb-82d7-ebbfeb36a7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970746188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.2970746188
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.912632954
Short name T427
Test name
Test status
Simulation time 30688409490 ps
CPU time 96.68 seconds
Started Apr 25 01:38:46 PM PDT 24
Finished Apr 25 01:40:23 PM PDT 24
Peak memory 200368 kb
Host smart-1a499833-9cc9-46b8-91b5-195debe11a44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=912632954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.912632954
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.3471130850
Short name T461
Test name
Test status
Simulation time 4948849862 ps
CPU time 20.74 seconds
Started Apr 25 01:38:42 PM PDT 24
Finished Apr 25 01:39:04 PM PDT 24
Peak memory 198468 kb
Host smart-13e769ec-11be-41e7-9727-d93e2be9ef13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3471130850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.3471130850
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.1402890708
Short name T410
Test name
Test status
Simulation time 48906800955 ps
CPU time 17.69 seconds
Started Apr 25 01:38:42 PM PDT 24
Finished Apr 25 01:39:00 PM PDT 24
Peak memory 200428 kb
Host smart-f746f826-ccba-4559-a7fc-d2cbeee83e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402890708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.1402890708
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.2965219184
Short name T758
Test name
Test status
Simulation time 4047775522 ps
CPU time 3.99 seconds
Started Apr 25 01:38:41 PM PDT 24
Finished Apr 25 01:38:46 PM PDT 24
Peak memory 196400 kb
Host smart-d20f13ef-c3b5-4b32-83ef-53a5c4e4c09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965219184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.2965219184
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.2803416786
Short name T903
Test name
Test status
Simulation time 5346701551 ps
CPU time 16.53 seconds
Started Apr 25 01:38:42 PM PDT 24
Finished Apr 25 01:38:59 PM PDT 24
Peak memory 200124 kb
Host smart-b9d090bb-8072-460b-90c3-42d118751f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803416786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2803416786
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.3841031008
Short name T926
Test name
Test status
Simulation time 165742126457 ps
CPU time 289.53 seconds
Started Apr 25 01:38:48 PM PDT 24
Finished Apr 25 01:43:38 PM PDT 24
Peak memory 200444 kb
Host smart-3eb04de6-da64-413a-9f99-bb8a8c41b42d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841031008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.3841031008
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.3971132639
Short name T825
Test name
Test status
Simulation time 62112213159 ps
CPU time 351.64 seconds
Started Apr 25 01:38:48 PM PDT 24
Finished Apr 25 01:44:40 PM PDT 24
Peak memory 208736 kb
Host smart-6e9e52d1-fa7c-4c02-a0a2-b693da4bab1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971132639 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.3971132639
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.2289823133
Short name T401
Test name
Test status
Simulation time 1137021244 ps
CPU time 3.88 seconds
Started Apr 25 01:38:43 PM PDT 24
Finished Apr 25 01:38:47 PM PDT 24
Peak memory 199204 kb
Host smart-88ca080e-54e8-452f-a3a7-915ab380f8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289823133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.2289823133
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.3454394739
Short name T1123
Test name
Test status
Simulation time 156522465179 ps
CPU time 30.2 seconds
Started Apr 25 01:38:42 PM PDT 24
Finished Apr 25 01:39:13 PM PDT 24
Peak memory 200372 kb
Host smart-9a25ba34-73b7-46fd-85a2-75b75832ea22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454394739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.3454394739
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.3334462461
Short name T795
Test name
Test status
Simulation time 12514175 ps
CPU time 0.57 seconds
Started Apr 25 01:38:59 PM PDT 24
Finished Apr 25 01:39:00 PM PDT 24
Peak memory 195816 kb
Host smart-2e26f6c0-ec89-4fdf-a3cf-f00e83931375
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334462461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.3334462461
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.1169797337
Short name T1147
Test name
Test status
Simulation time 63650429543 ps
CPU time 30.61 seconds
Started Apr 25 01:38:48 PM PDT 24
Finished Apr 25 01:39:19 PM PDT 24
Peak memory 200368 kb
Host smart-724e59be-3a62-44c7-b8fb-fa8e33acbb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169797337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.1169797337
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.507779945
Short name T1094
Test name
Test status
Simulation time 11595443972 ps
CPU time 4.03 seconds
Started Apr 25 01:38:48 PM PDT 24
Finished Apr 25 01:38:52 PM PDT 24
Peak memory 198964 kb
Host smart-a76cdc8a-a14b-4a0e-bdc9-79adcf209726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507779945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.507779945
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.1511886738
Short name T196
Test name
Test status
Simulation time 10895925150 ps
CPU time 5.03 seconds
Started Apr 25 01:38:47 PM PDT 24
Finished Apr 25 01:38:52 PM PDT 24
Peak memory 200124 kb
Host smart-dd024846-4a6c-45ad-9b57-465fe7b35df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511886738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.1511886738
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.765403358
Short name T756
Test name
Test status
Simulation time 19532883206 ps
CPU time 7.38 seconds
Started Apr 25 01:38:55 PM PDT 24
Finished Apr 25 01:39:03 PM PDT 24
Peak memory 200056 kb
Host smart-b5f20da3-dfcd-4c6c-84bf-5a54e28dd9a9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765403358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.765403358
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.38814326
Short name T248
Test name
Test status
Simulation time 77103607346 ps
CPU time 179.58 seconds
Started Apr 25 01:38:54 PM PDT 24
Finished Apr 25 01:41:54 PM PDT 24
Peak memory 200352 kb
Host smart-48abcd83-05f8-47f0-9b9e-8f1857dbac92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=38814326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.38814326
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.3080951742
Short name T809
Test name
Test status
Simulation time 3426013956 ps
CPU time 8.61 seconds
Started Apr 25 01:38:54 PM PDT 24
Finished Apr 25 01:39:03 PM PDT 24
Peak memory 199680 kb
Host smart-39935419-1621-4b74-ada1-1cea88562008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080951742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.3080951742
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.2852215658
Short name T1003
Test name
Test status
Simulation time 135146439276 ps
CPU time 33.49 seconds
Started Apr 25 01:38:54 PM PDT 24
Finished Apr 25 01:39:28 PM PDT 24
Peak memory 208612 kb
Host smart-63d932a3-976f-4d0b-b1f3-5fb30eba964f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852215658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.2852215658
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.1159515915
Short name T1165
Test name
Test status
Simulation time 12415060540 ps
CPU time 681.6 seconds
Started Apr 25 01:38:54 PM PDT 24
Finished Apr 25 01:50:16 PM PDT 24
Peak memory 200512 kb
Host smart-5c2ca8f2-1055-4d7e-bb4b-7e762ee20468
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1159515915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.1159515915
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.2595556608
Short name T333
Test name
Test status
Simulation time 5238668545 ps
CPU time 12.03 seconds
Started Apr 25 01:38:55 PM PDT 24
Finished Apr 25 01:39:08 PM PDT 24
Peak memory 199332 kb
Host smart-a03a2c2d-a27a-4b1b-8df7-18f3c60dac2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2595556608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.2595556608
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.2348179024
Short name T521
Test name
Test status
Simulation time 68759148240 ps
CPU time 56.62 seconds
Started Apr 25 01:38:54 PM PDT 24
Finished Apr 25 01:39:51 PM PDT 24
Peak memory 200384 kb
Host smart-a538359d-6c87-4815-afcb-ce5efd80583c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348179024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.2348179024
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.4016894945
Short name T269
Test name
Test status
Simulation time 4025782509 ps
CPU time 3.91 seconds
Started Apr 25 01:38:53 PM PDT 24
Finished Apr 25 01:38:57 PM PDT 24
Peak memory 196400 kb
Host smart-b6091fa8-86be-4c7d-99d8-613e27752e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016894945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.4016894945
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.3190406100
Short name T282
Test name
Test status
Simulation time 6106361195 ps
CPU time 8.16 seconds
Started Apr 25 01:38:49 PM PDT 24
Finished Apr 25 01:38:57 PM PDT 24
Peak memory 200260 kb
Host smart-a06edd8f-2c61-4c0f-bfef-8bcfc428734d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190406100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.3190406100
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.3349408125
Short name T154
Test name
Test status
Simulation time 152986175412 ps
CPU time 167.4 seconds
Started Apr 25 01:38:52 PM PDT 24
Finished Apr 25 01:41:40 PM PDT 24
Peak memory 200432 kb
Host smart-806cb01b-fedf-4644-8add-3032adb26073
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349408125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.3349408125
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.1388564073
Short name T773
Test name
Test status
Simulation time 10884115241 ps
CPU time 137.7 seconds
Started Apr 25 01:38:53 PM PDT 24
Finished Apr 25 01:41:11 PM PDT 24
Peak memory 208640 kb
Host smart-fa50cbba-e4ef-4d33-bb07-f61f838a6223
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388564073 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.1388564073
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.389935340
Short name T843
Test name
Test status
Simulation time 7462900098 ps
CPU time 8.06 seconds
Started Apr 25 01:39:02 PM PDT 24
Finished Apr 25 01:39:11 PM PDT 24
Peak memory 200032 kb
Host smart-e05bdad4-9560-4d6f-baa1-df4619a3ca54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389935340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.389935340
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.2271369869
Short name T677
Test name
Test status
Simulation time 24389881084 ps
CPU time 24.31 seconds
Started Apr 25 01:38:51 PM PDT 24
Finished Apr 25 01:39:15 PM PDT 24
Peak memory 200424 kb
Host smart-993928e6-acb4-485a-a588-4f8178558b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271369869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.2271369869
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.2977657250
Short name T692
Test name
Test status
Simulation time 14096438 ps
CPU time 0.55 seconds
Started Apr 25 01:39:00 PM PDT 24
Finished Apr 25 01:39:01 PM PDT 24
Peak memory 195776 kb
Host smart-941c4994-0bb8-49d0-96ba-66732546785b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977657250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.2977657250
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.4220735535
Short name T702
Test name
Test status
Simulation time 234142236784 ps
CPU time 82.29 seconds
Started Apr 25 01:39:02 PM PDT 24
Finished Apr 25 01:40:24 PM PDT 24
Peak memory 200452 kb
Host smart-84a71cdb-4b2c-4229-a24b-01254ecd147b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220735535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.4220735535
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.3435141683
Short name T1030
Test name
Test status
Simulation time 9168179103 ps
CPU time 16.88 seconds
Started Apr 25 01:38:59 PM PDT 24
Finished Apr 25 01:39:16 PM PDT 24
Peak memory 200108 kb
Host smart-7c48e634-a365-4d39-ad43-e9fe8b4482b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435141683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3435141683
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.1307971117
Short name T1062
Test name
Test status
Simulation time 106822618710 ps
CPU time 178.43 seconds
Started Apr 25 01:39:01 PM PDT 24
Finished Apr 25 01:42:00 PM PDT 24
Peak memory 200456 kb
Host smart-729e9a05-e36a-45b6-ab32-fed7435fd995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307971117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.1307971117
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.3928091026
Short name T535
Test name
Test status
Simulation time 6205928787 ps
CPU time 6.12 seconds
Started Apr 25 01:39:00 PM PDT 24
Finished Apr 25 01:39:06 PM PDT 24
Peak memory 196668 kb
Host smart-0ef777b6-9077-417b-b60b-ee6109a6ddbc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928091026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3928091026
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.1743004927
Short name T555
Test name
Test status
Simulation time 80758640199 ps
CPU time 231.21 seconds
Started Apr 25 01:38:58 PM PDT 24
Finished Apr 25 01:42:50 PM PDT 24
Peak memory 200396 kb
Host smart-4ba6ff58-2ac2-402b-99ba-982dff92e590
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1743004927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.1743004927
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.1001239183
Short name T340
Test name
Test status
Simulation time 7762999008 ps
CPU time 2.89 seconds
Started Apr 25 01:38:59 PM PDT 24
Finished Apr 25 01:39:03 PM PDT 24
Peak memory 200412 kb
Host smart-f940b59f-e102-4a47-904e-cbc17b391391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001239183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.1001239183
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.1167835570
Short name T671
Test name
Test status
Simulation time 113826233996 ps
CPU time 68.58 seconds
Started Apr 25 01:39:01 PM PDT 24
Finished Apr 25 01:40:10 PM PDT 24
Peak memory 200572 kb
Host smart-ce1b45c2-ffa9-42d7-886a-dbbbbcf37cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167835570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.1167835570
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.1487449339
Short name T379
Test name
Test status
Simulation time 5291692850 ps
CPU time 290.43 seconds
Started Apr 25 01:39:00 PM PDT 24
Finished Apr 25 01:43:52 PM PDT 24
Peak memory 200400 kb
Host smart-321e373b-e016-42f5-aa42-cc37848e93a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1487449339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1487449339
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.533564320
Short name T636
Test name
Test status
Simulation time 3146629223 ps
CPU time 6.23 seconds
Started Apr 25 01:39:01 PM PDT 24
Finished Apr 25 01:39:08 PM PDT 24
Peak memory 198744 kb
Host smart-0a2fab21-e8f1-4e5e-aff3-0518982191db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=533564320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.533564320
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.3966777190
Short name T459
Test name
Test status
Simulation time 1394348754 ps
CPU time 1.16 seconds
Started Apr 25 01:39:01 PM PDT 24
Finished Apr 25 01:39:03 PM PDT 24
Peak memory 196064 kb
Host smart-a1eba796-f8c0-4293-82ab-323b3b28d72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966777190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.3966777190
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.2033913392
Short name T274
Test name
Test status
Simulation time 470990842 ps
CPU time 2.45 seconds
Started Apr 25 01:38:58 PM PDT 24
Finished Apr 25 01:39:01 PM PDT 24
Peak memory 198676 kb
Host smart-aaaef7f4-bcca-4329-8f18-61ac761113ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033913392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.2033913392
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.352139238
Short name T1057
Test name
Test status
Simulation time 106941627289 ps
CPU time 62.19 seconds
Started Apr 25 01:39:00 PM PDT 24
Finished Apr 25 01:40:03 PM PDT 24
Peak memory 216960 kb
Host smart-53339633-41e7-4401-a293-13d28b14e572
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352139238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.352139238
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.179335397
Short name T106
Test name
Test status
Simulation time 145295067539 ps
CPU time 591.9 seconds
Started Apr 25 01:39:03 PM PDT 24
Finished Apr 25 01:48:55 PM PDT 24
Peak memory 216976 kb
Host smart-08594065-359f-46e7-a552-436675696c46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179335397 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.179335397
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.3668704787
Short name T1076
Test name
Test status
Simulation time 6845964881 ps
CPU time 47.36 seconds
Started Apr 25 01:39:00 PM PDT 24
Finished Apr 25 01:39:48 PM PDT 24
Peak memory 200396 kb
Host smart-bd994970-faaa-411e-adff-9bc2c15d8cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668704787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.3668704787
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.3299114090
Short name T1166
Test name
Test status
Simulation time 40136386395 ps
CPU time 18.37 seconds
Started Apr 25 01:39:01 PM PDT 24
Finished Apr 25 01:39:20 PM PDT 24
Peak memory 200460 kb
Host smart-b95baabb-6964-46d9-96c7-a194c3ce781b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299114090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.3299114090
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.3784184317
Short name T428
Test name
Test status
Simulation time 24656159 ps
CPU time 0.58 seconds
Started Apr 25 01:39:14 PM PDT 24
Finished Apr 25 01:39:15 PM PDT 24
Peak memory 195096 kb
Host smart-83b37d6a-3ef1-4392-a059-de39c492fefb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784184317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.3784184317
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.1783525112
Short name T854
Test name
Test status
Simulation time 402702750017 ps
CPU time 139.97 seconds
Started Apr 25 01:39:06 PM PDT 24
Finished Apr 25 01:41:26 PM PDT 24
Peak memory 200416 kb
Host smart-53658f4f-92de-43e0-8d03-84dfcb19aa05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783525112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.1783525112
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.2431965248
Short name T382
Test name
Test status
Simulation time 211756263467 ps
CPU time 40.63 seconds
Started Apr 25 01:39:07 PM PDT 24
Finished Apr 25 01:39:48 PM PDT 24
Peak memory 200460 kb
Host smart-45c83607-8555-4e50-b47c-f5c8c2df7d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431965248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.2431965248
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.2114125108
Short name T415
Test name
Test status
Simulation time 17499917430 ps
CPU time 31.23 seconds
Started Apr 25 01:39:07 PM PDT 24
Finished Apr 25 01:39:39 PM PDT 24
Peak memory 200340 kb
Host smart-75ed549c-5035-4061-8f85-5a52d49dd37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114125108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2114125108
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.1481845781
Short name T243
Test name
Test status
Simulation time 390034285772 ps
CPU time 682.65 seconds
Started Apr 25 01:39:09 PM PDT 24
Finished Apr 25 01:50:32 PM PDT 24
Peak memory 200464 kb
Host smart-391affa3-d200-4c06-adc7-caf296c2ad5e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481845781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.1481845781
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.2055474683
Short name T836
Test name
Test status
Simulation time 131144772926 ps
CPU time 347.93 seconds
Started Apr 25 01:39:16 PM PDT 24
Finished Apr 25 01:45:05 PM PDT 24
Peak memory 200432 kb
Host smart-456e15e1-33dc-499d-aae7-de184514235e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2055474683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.2055474683
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.1549994843
Short name T682
Test name
Test status
Simulation time 9949269812 ps
CPU time 6.21 seconds
Started Apr 25 01:39:06 PM PDT 24
Finished Apr 25 01:39:12 PM PDT 24
Peak memory 199344 kb
Host smart-60124c00-bb9a-4ffc-8a57-aeabc46e0464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549994843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.1549994843
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.1254927239
Short name T694
Test name
Test status
Simulation time 33541815190 ps
CPU time 82.77 seconds
Started Apr 25 01:39:05 PM PDT 24
Finished Apr 25 01:40:29 PM PDT 24
Peak memory 200620 kb
Host smart-c4f19d39-5506-4c3c-ae17-550ae5ba0edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254927239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.1254927239
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.3408548633
Short name T897
Test name
Test status
Simulation time 13216168220 ps
CPU time 188.77 seconds
Started Apr 25 01:39:06 PM PDT 24
Finished Apr 25 01:42:16 PM PDT 24
Peak memory 200312 kb
Host smart-3deaf615-2697-4e30-bc12-cb1b2f71e8fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3408548633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.3408548633
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.2781472302
Short name T932
Test name
Test status
Simulation time 1400739269 ps
CPU time 1.19 seconds
Started Apr 25 01:39:06 PM PDT 24
Finished Apr 25 01:39:08 PM PDT 24
Peak memory 196016 kb
Host smart-ab7210a7-d393-4769-9c43-58c6c4eccec5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2781472302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.2781472302
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.3475236438
Short name T267
Test name
Test status
Simulation time 33097140054 ps
CPU time 74.45 seconds
Started Apr 25 01:39:08 PM PDT 24
Finished Apr 25 01:40:23 PM PDT 24
Peak memory 200372 kb
Host smart-38415388-1025-40b8-b3d0-431f49161e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475236438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.3475236438
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.4187388702
Short name T540
Test name
Test status
Simulation time 1379474057 ps
CPU time 1.91 seconds
Started Apr 25 01:39:06 PM PDT 24
Finished Apr 25 01:39:09 PM PDT 24
Peak memory 195760 kb
Host smart-c160c424-0190-4c7e-8e76-63c7e0d58b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187388702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.4187388702
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.2499350191
Short name T952
Test name
Test status
Simulation time 584434666 ps
CPU time 1.4 seconds
Started Apr 25 01:39:07 PM PDT 24
Finished Apr 25 01:39:09 PM PDT 24
Peak memory 199988 kb
Host smart-f18c5fe2-1753-4d87-bcd4-be3a79a62868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499350191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.2499350191
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.134830135
Short name T551
Test name
Test status
Simulation time 184288648903 ps
CPU time 208.95 seconds
Started Apr 25 01:39:13 PM PDT 24
Finished Apr 25 01:42:43 PM PDT 24
Peak memory 200412 kb
Host smart-e36fd9b1-c1e5-44a3-8649-c33b5eee78be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134830135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.134830135
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.5514081
Short name T757
Test name
Test status
Simulation time 322088997113 ps
CPU time 1249.25 seconds
Started Apr 25 01:39:12 PM PDT 24
Finished Apr 25 02:00:03 PM PDT 24
Peak memory 216880 kb
Host smart-9ec1f402-2202-4a4d-911f-23a836be0575
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5514081 -assert nopostproc
+UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.5514081
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.1725259265
Short name T1073
Test name
Test status
Simulation time 1865205782 ps
CPU time 1.94 seconds
Started Apr 25 01:39:07 PM PDT 24
Finished Apr 25 01:39:09 PM PDT 24
Peak memory 198972 kb
Host smart-2bbea79c-72cc-4a06-aada-a7bc9a9c69a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725259265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.1725259265
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.748228220
Short name T1038
Test name
Test status
Simulation time 72267996532 ps
CPU time 107.05 seconds
Started Apr 25 01:39:07 PM PDT 24
Finished Apr 25 01:40:54 PM PDT 24
Peak memory 200456 kb
Host smart-6a46cc3b-77da-443a-a20d-74b2c56074a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748228220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.748228220
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.2658007947
Short name T405
Test name
Test status
Simulation time 37209033 ps
CPU time 0.54 seconds
Started Apr 25 01:39:20 PM PDT 24
Finished Apr 25 01:39:21 PM PDT 24
Peak memory 195800 kb
Host smart-2703edbb-f3af-4819-9c08-cd0488adcc72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658007947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.2658007947
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.1911723918
Short name T736
Test name
Test status
Simulation time 107670271030 ps
CPU time 42.82 seconds
Started Apr 25 01:39:13 PM PDT 24
Finished Apr 25 01:39:57 PM PDT 24
Peak memory 200392 kb
Host smart-8b9b952e-4db4-404a-a5cb-34cb914ce1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911723918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.1911723918
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.4012256344
Short name T637
Test name
Test status
Simulation time 197562192584 ps
CPU time 253.63 seconds
Started Apr 25 01:39:26 PM PDT 24
Finished Apr 25 01:43:41 PM PDT 24
Peak memory 200276 kb
Host smart-a0dca3a5-e32a-4c50-8932-8ce6b3038e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012256344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.4012256344
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.1952585244
Short name T879
Test name
Test status
Simulation time 61771437832 ps
CPU time 25.98 seconds
Started Apr 25 01:39:14 PM PDT 24
Finished Apr 25 01:39:40 PM PDT 24
Peak memory 199896 kb
Host smart-fd1e25f4-c282-4f19-a1af-b8e0e08ab9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952585244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.1952585244
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.501497396
Short name T493
Test name
Test status
Simulation time 24707117952 ps
CPU time 11.55 seconds
Started Apr 25 01:39:13 PM PDT 24
Finished Apr 25 01:39:25 PM PDT 24
Peak memory 200424 kb
Host smart-bf8482f2-051a-4594-90f3-99aaafa9fc0b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501497396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.501497396
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.3308681342
Short name T305
Test name
Test status
Simulation time 129519282093 ps
CPU time 388.87 seconds
Started Apr 25 01:39:19 PM PDT 24
Finished Apr 25 01:45:49 PM PDT 24
Peak memory 200328 kb
Host smart-b2f944b2-f4fc-4142-97d4-7ead1209d1bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3308681342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.3308681342
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.1097416187
Short name T1151
Test name
Test status
Simulation time 3470620295 ps
CPU time 3.36 seconds
Started Apr 25 01:39:19 PM PDT 24
Finished Apr 25 01:39:22 PM PDT 24
Peak memory 198332 kb
Host smart-e17c93d1-576f-42dd-9fea-d38660ef9872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097416187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.1097416187
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.2799951473
Short name T902
Test name
Test status
Simulation time 28984577314 ps
CPU time 46.58 seconds
Started Apr 25 01:39:13 PM PDT 24
Finished Apr 25 01:40:01 PM PDT 24
Peak memory 199352 kb
Host smart-79d19085-b80f-464c-bd70-36c8a70fc2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799951473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.2799951473
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.3148740543
Short name T380
Test name
Test status
Simulation time 9895160299 ps
CPU time 114.07 seconds
Started Apr 25 01:39:18 PM PDT 24
Finished Apr 25 01:41:12 PM PDT 24
Peak memory 200400 kb
Host smart-2be8b16f-bafa-41d0-9221-3ad6218958ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3148740543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.3148740543
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.4213916224
Short name T937
Test name
Test status
Simulation time 5632757888 ps
CPU time 54.25 seconds
Started Apr 25 01:39:21 PM PDT 24
Finished Apr 25 01:40:16 PM PDT 24
Peak memory 199476 kb
Host smart-eb6edf4d-d804-4ff5-a848-c2779a6f5abb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4213916224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.4213916224
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.3784300793
Short name T1136
Test name
Test status
Simulation time 67157778571 ps
CPU time 27.73 seconds
Started Apr 25 01:39:20 PM PDT 24
Finished Apr 25 01:39:48 PM PDT 24
Peak memory 200192 kb
Host smart-06a2f8ef-7e44-4345-a523-60d47102440e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784300793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3784300793
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.1660406478
Short name T354
Test name
Test status
Simulation time 5442104713 ps
CPU time 4.87 seconds
Started Apr 25 01:39:23 PM PDT 24
Finished Apr 25 01:39:28 PM PDT 24
Peak memory 196420 kb
Host smart-79d3a1e1-bf17-4253-a7cc-eddae79cff64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660406478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.1660406478
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.2593235854
Short name T939
Test name
Test status
Simulation time 289522385 ps
CPU time 1.28 seconds
Started Apr 25 01:39:13 PM PDT 24
Finished Apr 25 01:39:15 PM PDT 24
Peak memory 198988 kb
Host smart-74f07917-06f9-47c4-bd78-6f99b37ff966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593235854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.2593235854
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.2841345921
Short name T696
Test name
Test status
Simulation time 268933799674 ps
CPU time 440.18 seconds
Started Apr 25 01:39:20 PM PDT 24
Finished Apr 25 01:46:41 PM PDT 24
Peak memory 216876 kb
Host smart-9e0945f1-63e8-4c66-937b-5412d4b3d230
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841345921 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.2841345921
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.1627780960
Short name T481
Test name
Test status
Simulation time 988407989 ps
CPU time 2.79 seconds
Started Apr 25 01:39:20 PM PDT 24
Finished Apr 25 01:39:23 PM PDT 24
Peak memory 199192 kb
Host smart-a60830ac-a5a7-4d4f-8c3a-fd3dbe769383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627780960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.1627780960
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.2396838910
Short name T439
Test name
Test status
Simulation time 87040706364 ps
CPU time 127.91 seconds
Started Apr 25 01:39:13 PM PDT 24
Finished Apr 25 01:41:22 PM PDT 24
Peak memory 200440 kb
Host smart-78b063d7-62aa-4af5-8ad6-8630b115ea9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396838910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.2396838910
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.622451566
Short name T751
Test name
Test status
Simulation time 23160470 ps
CPU time 0.57 seconds
Started Apr 25 01:39:25 PM PDT 24
Finished Apr 25 01:39:26 PM PDT 24
Peak memory 195680 kb
Host smart-bb182217-70c8-4153-9e2b-ce05de61aa6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622451566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.622451566
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.961279841
Short name T589
Test name
Test status
Simulation time 65679152594 ps
CPU time 29.36 seconds
Started Apr 25 01:39:25 PM PDT 24
Finished Apr 25 01:39:55 PM PDT 24
Peak memory 200388 kb
Host smart-4c6c3b4d-058e-4bd9-a4e1-3fc3f8c1e5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961279841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.961279841
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.3075513601
Short name T923
Test name
Test status
Simulation time 55373308145 ps
CPU time 84.12 seconds
Started Apr 25 01:39:28 PM PDT 24
Finished Apr 25 01:40:53 PM PDT 24
Peak memory 200296 kb
Host smart-b75c5f56-6af7-4966-a164-6024eff28516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075513601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.3075513601
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.2937445133
Short name T688
Test name
Test status
Simulation time 63324649367 ps
CPU time 100.52 seconds
Started Apr 25 01:39:24 PM PDT 24
Finished Apr 25 01:41:06 PM PDT 24
Peak memory 200424 kb
Host smart-0cb2ab86-4994-4e24-a4fd-90f1ea955a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937445133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.2937445133
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.2935436814
Short name T633
Test name
Test status
Simulation time 41568275887 ps
CPU time 72.68 seconds
Started Apr 25 01:39:26 PM PDT 24
Finished Apr 25 01:40:40 PM PDT 24
Peak memory 199768 kb
Host smart-e587adfe-91f9-46e3-bf68-4f32d8bdf281
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935436814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.2935436814
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.958485250
Short name T252
Test name
Test status
Simulation time 145326359000 ps
CPU time 722.53 seconds
Started Apr 25 01:39:25 PM PDT 24
Finished Apr 25 01:51:29 PM PDT 24
Peak memory 200428 kb
Host smart-354f1ac5-a6f9-40aa-ad4f-8913fe940ce4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=958485250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.958485250
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.3108611524
Short name T1121
Test name
Test status
Simulation time 12685794085 ps
CPU time 8.84 seconds
Started Apr 25 01:39:26 PM PDT 24
Finished Apr 25 01:39:36 PM PDT 24
Peak memory 200424 kb
Host smart-02c3caf1-9390-43b5-bdcb-032cf543cbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108611524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.3108611524
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.3062941527
Short name T964
Test name
Test status
Simulation time 15008624356 ps
CPU time 29.58 seconds
Started Apr 25 01:39:25 PM PDT 24
Finished Apr 25 01:39:56 PM PDT 24
Peak memory 198732 kb
Host smart-2bd0346d-6d1c-4197-871a-efaa171a285f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062941527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.3062941527
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.1252287975
Short name T649
Test name
Test status
Simulation time 7546403106 ps
CPU time 431.28 seconds
Started Apr 25 01:39:26 PM PDT 24
Finished Apr 25 01:46:39 PM PDT 24
Peak memory 200312 kb
Host smart-f380e614-11a3-41a9-8620-7cb4190a790c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1252287975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.1252287975
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.3071243280
Short name T632
Test name
Test status
Simulation time 1422389095 ps
CPU time 0.86 seconds
Started Apr 25 01:39:25 PM PDT 24
Finished Apr 25 01:39:28 PM PDT 24
Peak memory 195916 kb
Host smart-428b629c-e38f-4a3a-af7e-9723ca233044
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3071243280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.3071243280
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.1293232890
Short name T1093
Test name
Test status
Simulation time 33759413789 ps
CPU time 27.54 seconds
Started Apr 25 01:39:27 PM PDT 24
Finished Apr 25 01:39:55 PM PDT 24
Peak memory 200408 kb
Host smart-ea9ebd4b-a003-407f-bd3e-5f668ce357ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293232890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.1293232890
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.3883682224
Short name T441
Test name
Test status
Simulation time 3193082604 ps
CPU time 2.56 seconds
Started Apr 25 01:39:26 PM PDT 24
Finished Apr 25 01:39:30 PM PDT 24
Peak memory 196168 kb
Host smart-e10b3181-1d56-45ec-9777-2d350b7aecd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883682224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3883682224
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.2306632095
Short name T723
Test name
Test status
Simulation time 1001274467 ps
CPU time 1.99 seconds
Started Apr 25 01:39:19 PM PDT 24
Finished Apr 25 01:39:21 PM PDT 24
Peak memory 198772 kb
Host smart-63100179-a479-4c34-9fab-31134bc79e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306632095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.2306632095
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.1811278757
Short name T957
Test name
Test status
Simulation time 97031220159 ps
CPU time 543.7 seconds
Started Apr 25 01:39:28 PM PDT 24
Finished Apr 25 01:48:33 PM PDT 24
Peak memory 200396 kb
Host smart-e4494f36-47ad-4a6b-b0ac-a99b19a82828
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811278757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.1811278757
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.959736170
Short name T658
Test name
Test status
Simulation time 940411985 ps
CPU time 2.3 seconds
Started Apr 25 01:39:25 PM PDT 24
Finished Apr 25 01:39:29 PM PDT 24
Peak memory 198752 kb
Host smart-9e840c5f-fee9-4851-8cac-e15528ad35f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959736170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.959736170
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.3008334634
Short name T280
Test name
Test status
Simulation time 121271197782 ps
CPU time 266.29 seconds
Started Apr 25 01:39:25 PM PDT 24
Finished Apr 25 01:43:52 PM PDT 24
Peak memory 200424 kb
Host smart-6001a7b3-7725-45ad-afe4-9d23da8e1945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008334634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.3008334634
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.2833706381
Short name T19
Test name
Test status
Simulation time 39306931 ps
CPU time 0.55 seconds
Started Apr 25 01:39:36 PM PDT 24
Finished Apr 25 01:39:38 PM PDT 24
Peak memory 195812 kb
Host smart-1bea7deb-2e50-41b5-a2d8-1f254204cd75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833706381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.2833706381
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.2568494693
Short name T260
Test name
Test status
Simulation time 70455554622 ps
CPU time 29.39 seconds
Started Apr 25 01:39:31 PM PDT 24
Finished Apr 25 01:40:02 PM PDT 24
Peak memory 200304 kb
Host smart-30ee47d5-0703-4947-910f-26570acac8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568494693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.2568494693
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.3818936452
Short name T650
Test name
Test status
Simulation time 74574118529 ps
CPU time 120.23 seconds
Started Apr 25 01:39:31 PM PDT 24
Finished Apr 25 01:41:32 PM PDT 24
Peak memory 200432 kb
Host smart-479afeb7-1df7-47a5-a122-8d65c865bbd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818936452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.3818936452
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.1696392268
Short name T822
Test name
Test status
Simulation time 17170193613 ps
CPU time 32.45 seconds
Started Apr 25 01:39:31 PM PDT 24
Finished Apr 25 01:40:05 PM PDT 24
Peak memory 200372 kb
Host smart-7cbdbf9a-af98-4787-b399-cb024c7bbffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696392268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.1696392268
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.2553858388
Short name T1066
Test name
Test status
Simulation time 38198331976 ps
CPU time 72.33 seconds
Started Apr 25 01:39:32 PM PDT 24
Finished Apr 25 01:40:45 PM PDT 24
Peak memory 200036 kb
Host smart-6d354ecc-1d46-4902-b772-e4f204dc9ab2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553858388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.2553858388
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.2373934117
Short name T657
Test name
Test status
Simulation time 203126834166 ps
CPU time 185.7 seconds
Started Apr 25 01:39:37 PM PDT 24
Finished Apr 25 01:42:44 PM PDT 24
Peak memory 200288 kb
Host smart-35b3b1a6-2cb3-4dec-afce-94fa4d19daaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2373934117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.2373934117
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.2296981758
Short name T684
Test name
Test status
Simulation time 6058677451 ps
CPU time 2.73 seconds
Started Apr 25 01:39:37 PM PDT 24
Finished Apr 25 01:39:41 PM PDT 24
Peak memory 200080 kb
Host smart-9174e13f-4612-493f-bb39-8402e080b923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296981758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.2296981758
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.2271526371
Short name T898
Test name
Test status
Simulation time 79465786819 ps
CPU time 115.52 seconds
Started Apr 25 01:39:31 PM PDT 24
Finished Apr 25 01:41:26 PM PDT 24
Peak memory 199416 kb
Host smart-25f64e4e-2f09-4c7b-a015-85f0ff7dec7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271526371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.2271526371
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.2805731684
Short name T962
Test name
Test status
Simulation time 14047926099 ps
CPU time 304.88 seconds
Started Apr 25 01:39:36 PM PDT 24
Finished Apr 25 01:44:41 PM PDT 24
Peak memory 200392 kb
Host smart-ed633754-7b08-49db-bd26-03d702cff7fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2805731684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.2805731684
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.3021186312
Short name T846
Test name
Test status
Simulation time 3332645079 ps
CPU time 15.22 seconds
Started Apr 25 01:39:33 PM PDT 24
Finished Apr 25 01:39:49 PM PDT 24
Peak memory 199388 kb
Host smart-f9135905-fdf2-4d62-a44c-84cdd5ea7bfe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3021186312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.3021186312
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.3532060064
Short name T983
Test name
Test status
Simulation time 198131737434 ps
CPU time 42.65 seconds
Started Apr 25 01:39:31 PM PDT 24
Finished Apr 25 01:40:15 PM PDT 24
Peak memory 200420 kb
Host smart-e1599d19-5289-4ed7-b0c8-1d7cf7bbc2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532060064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3532060064
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.33460445
Short name T638
Test name
Test status
Simulation time 3486370726 ps
CPU time 1.94 seconds
Started Apr 25 01:39:31 PM PDT 24
Finished Apr 25 01:39:34 PM PDT 24
Peak memory 196204 kb
Host smart-1d6596d5-113f-4dfe-8ce9-9fc07eb6d590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33460445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.33460445
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.3842211919
Short name T1029
Test name
Test status
Simulation time 910045227 ps
CPU time 1.84 seconds
Started Apr 25 01:39:26 PM PDT 24
Finished Apr 25 01:39:29 PM PDT 24
Peak memory 199220 kb
Host smart-3ede0e58-9ef6-4a2a-8a00-169cacd0c4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842211919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.3842211919
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.989860014
Short name T714
Test name
Test status
Simulation time 137567346916 ps
CPU time 113.28 seconds
Started Apr 25 01:39:37 PM PDT 24
Finished Apr 25 01:41:32 PM PDT 24
Peak memory 200356 kb
Host smart-f464cf02-d2f2-421d-91fb-cf475c9c17c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989860014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.989860014
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.122099483
Short name T276
Test name
Test status
Simulation time 597053328 ps
CPU time 2.24 seconds
Started Apr 25 01:39:32 PM PDT 24
Finished Apr 25 01:39:35 PM PDT 24
Peak memory 199264 kb
Host smart-11edc4f8-34f4-4037-bc8f-306b13678361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122099483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.122099483
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.3623166014
Short name T456
Test name
Test status
Simulation time 37397836300 ps
CPU time 16.12 seconds
Started Apr 25 01:39:29 PM PDT 24
Finished Apr 25 01:39:46 PM PDT 24
Peak memory 200340 kb
Host smart-e7e086db-89e1-4392-ba64-b98a583329c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623166014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.3623166014
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.2826171177
Short name T876
Test name
Test status
Simulation time 17533094 ps
CPU time 0.51 seconds
Started Apr 25 01:39:40 PM PDT 24
Finished Apr 25 01:39:41 PM PDT 24
Peak memory 194768 kb
Host smart-b7e29813-8d9d-4d2d-9e71-610848d7cc4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826171177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.2826171177
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.2476461092
Short name T818
Test name
Test status
Simulation time 38729350300 ps
CPU time 17.29 seconds
Started Apr 25 01:39:37 PM PDT 24
Finished Apr 25 01:39:55 PM PDT 24
Peak memory 200376 kb
Host smart-cf229692-6bb9-415a-8ffa-e8cb0e7103c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476461092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2476461092
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.1456652365
Short name T975
Test name
Test status
Simulation time 173978302341 ps
CPU time 81.57 seconds
Started Apr 25 01:39:36 PM PDT 24
Finished Apr 25 01:40:58 PM PDT 24
Peak memory 200408 kb
Host smart-543e7aba-04f7-416a-8904-5a6e150fc7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456652365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1456652365
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.1318875617
Short name T207
Test name
Test status
Simulation time 70128468607 ps
CPU time 545.07 seconds
Started Apr 25 01:39:37 PM PDT 24
Finished Apr 25 01:48:43 PM PDT 24
Peak memory 200280 kb
Host smart-c9c90595-1b56-4078-a28a-bcf1fbf58b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318875617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.1318875617
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.1874820983
Short name T908
Test name
Test status
Simulation time 28043229829 ps
CPU time 23.59 seconds
Started Apr 25 01:39:41 PM PDT 24
Finished Apr 25 01:40:06 PM PDT 24
Peak memory 198916 kb
Host smart-037c380c-175b-4e43-bb7b-a3dba1995ac6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874820983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.1874820983
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.2052343672
Short name T359
Test name
Test status
Simulation time 131962666436 ps
CPU time 280.67 seconds
Started Apr 25 01:39:42 PM PDT 24
Finished Apr 25 01:44:24 PM PDT 24
Peak memory 200456 kb
Host smart-c06b620c-0b16-4a47-a573-18798d1eaf89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2052343672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.2052343672
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.2625631689
Short name T910
Test name
Test status
Simulation time 13220388825 ps
CPU time 30.22 seconds
Started Apr 25 01:39:42 PM PDT 24
Finished Apr 25 01:40:13 PM PDT 24
Peak memory 200340 kb
Host smart-db436980-9dd1-40f9-a1c4-df6729e6bc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625631689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.2625631689
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.2542580235
Short name T830
Test name
Test status
Simulation time 34158048436 ps
CPU time 33.29 seconds
Started Apr 25 01:39:37 PM PDT 24
Finished Apr 25 01:40:11 PM PDT 24
Peak memory 199108 kb
Host smart-1a8b6b14-410d-458d-b683-c3e4092c7d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542580235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.2542580235
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.199786795
Short name T623
Test name
Test status
Simulation time 12768269832 ps
CPU time 143.72 seconds
Started Apr 25 01:39:41 PM PDT 24
Finished Apr 25 01:42:06 PM PDT 24
Peak memory 200384 kb
Host smart-489d37f1-01d0-46bc-ade5-b629b278824a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=199786795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.199786795
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.2525751522
Short name T450
Test name
Test status
Simulation time 5277284369 ps
CPU time 42.55 seconds
Started Apr 25 01:39:41 PM PDT 24
Finished Apr 25 01:40:25 PM PDT 24
Peak memory 199048 kb
Host smart-842eae89-9cb6-4e28-ae8b-16f95a2fa54e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2525751522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.2525751522
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.4127761592
Short name T591
Test name
Test status
Simulation time 221701016132 ps
CPU time 340.36 seconds
Started Apr 25 01:39:38 PM PDT 24
Finished Apr 25 01:45:19 PM PDT 24
Peak memory 200416 kb
Host smart-a6b7e936-19a9-46bc-bcb2-3fa39567936d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127761592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.4127761592
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.1870116681
Short name T420
Test name
Test status
Simulation time 6098160057 ps
CPU time 11.27 seconds
Started Apr 25 01:39:36 PM PDT 24
Finished Apr 25 01:39:48 PM PDT 24
Peak memory 196432 kb
Host smart-93aa5c17-6ec9-453c-8d26-ee570ae22554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870116681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1870116681
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.3247803847
Short name T1005
Test name
Test status
Simulation time 580409619 ps
CPU time 1.5 seconds
Started Apr 25 01:39:40 PM PDT 24
Finished Apr 25 01:39:42 PM PDT 24
Peak memory 199164 kb
Host smart-fb8ceff7-708d-4f84-950e-0ec7a1e68fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247803847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3247803847
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.907961425
Short name T151
Test name
Test status
Simulation time 278451812958 ps
CPU time 168.23 seconds
Started Apr 25 01:39:43 PM PDT 24
Finished Apr 25 01:42:32 PM PDT 24
Peak memory 216256 kb
Host smart-098725f1-41b5-43a6-8460-72682f41c6e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907961425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.907961425
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.1108711371
Short name T944
Test name
Test status
Simulation time 88715361229 ps
CPU time 1715.14 seconds
Started Apr 25 01:39:42 PM PDT 24
Finished Apr 25 02:08:18 PM PDT 24
Peak memory 226880 kb
Host smart-0f319863-2862-43cc-983a-a33a1c1e7882
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108711371 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.1108711371
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.3627742367
Short name T1084
Test name
Test status
Simulation time 6548010234 ps
CPU time 17.49 seconds
Started Apr 25 01:39:39 PM PDT 24
Finished Apr 25 01:39:57 PM PDT 24
Peak memory 199760 kb
Host smart-841ec640-8408-4eae-b79b-e29fd9c56fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627742367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.3627742367
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.3046636939
Short name T845
Test name
Test status
Simulation time 139944772982 ps
CPU time 73.37 seconds
Started Apr 25 01:39:38 PM PDT 24
Finished Apr 25 01:40:52 PM PDT 24
Peak memory 200404 kb
Host smart-bce5ab8e-425d-42b2-8175-d3c7383b4b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046636939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.3046636939
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.3998544343
Short name T1077
Test name
Test status
Simulation time 10719763 ps
CPU time 0.55 seconds
Started Apr 25 01:39:50 PM PDT 24
Finished Apr 25 01:39:51 PM PDT 24
Peak memory 194764 kb
Host smart-4cbdfe6e-b3c5-4341-ba48-3464f6250228
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998544343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.3998544343
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.1999752134
Short name T289
Test name
Test status
Simulation time 64199943682 ps
CPU time 30.65 seconds
Started Apr 25 01:39:41 PM PDT 24
Finished Apr 25 01:40:12 PM PDT 24
Peak memory 200424 kb
Host smart-aa249635-2f16-48de-b26a-1351ad26dd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999752134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.1999752134
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.892048618
Short name T740
Test name
Test status
Simulation time 16809279812 ps
CPU time 31.4 seconds
Started Apr 25 01:39:41 PM PDT 24
Finished Apr 25 01:40:13 PM PDT 24
Peak memory 200452 kb
Host smart-ea21c153-2448-46c3-8d51-152b10e0f58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892048618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.892048618
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.3178172532
Short name T659
Test name
Test status
Simulation time 137524959970 ps
CPU time 31.05 seconds
Started Apr 25 01:39:42 PM PDT 24
Finished Apr 25 01:40:14 PM PDT 24
Peak memory 200420 kb
Host smart-8084bc02-8e7b-414d-bb1b-415d0c3a7b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178172532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.3178172532
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.3593240069
Short name T808
Test name
Test status
Simulation time 3820001350 ps
CPU time 5.71 seconds
Started Apr 25 01:39:48 PM PDT 24
Finished Apr 25 01:39:54 PM PDT 24
Peak memory 197044 kb
Host smart-ce4f9952-38cb-4fa2-8d3a-c0eff6a92882
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593240069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.3593240069
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.1615035782
Short name T888
Test name
Test status
Simulation time 49033097111 ps
CPU time 251.05 seconds
Started Apr 25 01:39:49 PM PDT 24
Finished Apr 25 01:44:00 PM PDT 24
Peak memory 200460 kb
Host smart-6958b141-4b55-46bd-b10b-558768b8eb7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1615035782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.1615035782
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.3023185130
Short name T385
Test name
Test status
Simulation time 6154674169 ps
CPU time 6.06 seconds
Started Apr 25 01:39:48 PM PDT 24
Finished Apr 25 01:39:55 PM PDT 24
Peak memory 199520 kb
Host smart-2d358344-feaa-4cff-ab77-fe2ae1d20a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023185130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.3023185130
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.600884708
Short name T728
Test name
Test status
Simulation time 49557505044 ps
CPU time 88.76 seconds
Started Apr 25 01:39:47 PM PDT 24
Finished Apr 25 01:41:17 PM PDT 24
Peak memory 200604 kb
Host smart-b019d700-e1eb-4c93-9674-2bf82e0750b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600884708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.600884708
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.3313723011
Short name T631
Test name
Test status
Simulation time 25491264949 ps
CPU time 211.71 seconds
Started Apr 25 01:39:49 PM PDT 24
Finished Apr 25 01:43:21 PM PDT 24
Peak memory 200340 kb
Host smart-9839bffe-b832-421f-a56f-c58d52209c7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3313723011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.3313723011
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.3618238612
Short name T507
Test name
Test status
Simulation time 6320567904 ps
CPU time 13.86 seconds
Started Apr 25 01:39:42 PM PDT 24
Finished Apr 25 01:39:57 PM PDT 24
Peak memory 198664 kb
Host smart-a1bc70d0-b883-42a9-b727-ddb15da9fd2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3618238612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.3618238612
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.3526440208
Short name T1152
Test name
Test status
Simulation time 60557122166 ps
CPU time 96.61 seconds
Started Apr 25 01:39:49 PM PDT 24
Finished Apr 25 01:41:26 PM PDT 24
Peak memory 199664 kb
Host smart-d451a949-7099-4150-8170-f1bead0a9479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526440208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.3526440208
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.3322825971
Short name T811
Test name
Test status
Simulation time 6580001856 ps
CPU time 1.53 seconds
Started Apr 25 01:39:49 PM PDT 24
Finished Apr 25 01:39:51 PM PDT 24
Peak memory 196416 kb
Host smart-eee6d679-6547-449b-a348-92e1636ef304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322825971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.3322825971
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.1398891752
Short name T1137
Test name
Test status
Simulation time 5528534803 ps
CPU time 6.84 seconds
Started Apr 25 01:39:44 PM PDT 24
Finished Apr 25 01:39:51 PM PDT 24
Peak memory 200192 kb
Host smart-e90e98ec-8793-4929-9524-71a24bae44e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398891752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.1398891752
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.915926225
Short name T1182
Test name
Test status
Simulation time 142366264767 ps
CPU time 236.03 seconds
Started Apr 25 01:39:47 PM PDT 24
Finished Apr 25 01:43:44 PM PDT 24
Peak memory 200388 kb
Host smart-25df5ab4-3e23-4429-bd85-cf317a219bb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915926225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.915926225
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.2888989588
Short name T950
Test name
Test status
Simulation time 6734950890 ps
CPU time 28.81 seconds
Started Apr 25 01:39:48 PM PDT 24
Finished Apr 25 01:40:18 PM PDT 24
Peak memory 200368 kb
Host smart-99e6626a-ff1d-4000-9ee5-b7931384eb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888989588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2888989588
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.1817925473
Short name T675
Test name
Test status
Simulation time 68842456936 ps
CPU time 121.47 seconds
Started Apr 25 01:39:43 PM PDT 24
Finished Apr 25 01:41:45 PM PDT 24
Peak memory 200404 kb
Host smart-340a2bb0-9571-4662-a5ac-c25d42ea4e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817925473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.1817925473
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.3438378008
Short name T1056
Test name
Test status
Simulation time 13969241 ps
CPU time 0.56 seconds
Started Apr 25 01:33:47 PM PDT 24
Finished Apr 25 01:33:48 PM PDT 24
Peak memory 195808 kb
Host smart-255fe913-de0f-46c9-a563-870831b37059
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438378008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.3438378008
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.2454943895
Short name T393
Test name
Test status
Simulation time 22934408674 ps
CPU time 12.71 seconds
Started Apr 25 01:33:39 PM PDT 24
Finished Apr 25 01:33:52 PM PDT 24
Peak memory 200440 kb
Host smart-6f03e999-e860-46f3-974d-ec72ecb9ba1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454943895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.2454943895
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.2646209450
Short name T1014
Test name
Test status
Simulation time 36036694493 ps
CPU time 29.41 seconds
Started Apr 25 01:33:38 PM PDT 24
Finished Apr 25 01:34:09 PM PDT 24
Peak memory 200384 kb
Host smart-29f6184c-dc31-4c31-a230-5995db340e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646209450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.2646209450
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.2725513492
Short name T324
Test name
Test status
Simulation time 5886632840 ps
CPU time 2.92 seconds
Started Apr 25 01:33:38 PM PDT 24
Finished Apr 25 01:33:41 PM PDT 24
Peak memory 199372 kb
Host smart-3e2e83e5-51dd-47ab-ae0d-dca0b3530032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725513492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.2725513492
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.3255777913
Short name T17
Test name
Test status
Simulation time 41035159508 ps
CPU time 19.22 seconds
Started Apr 25 01:33:39 PM PDT 24
Finished Apr 25 01:33:59 PM PDT 24
Peak memory 200432 kb
Host smart-96fcba91-9228-4c8a-ae78-c12248ac55c1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255777913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.3255777913
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.2513017712
Short name T787
Test name
Test status
Simulation time 100728659514 ps
CPU time 455.82 seconds
Started Apr 25 01:33:46 PM PDT 24
Finished Apr 25 01:41:22 PM PDT 24
Peak memory 200356 kb
Host smart-1fb77e29-c7c4-41e2-a107-e784efa1f880
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2513017712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.2513017712
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.2234210280
Short name T916
Test name
Test status
Simulation time 59625173 ps
CPU time 0.67 seconds
Started Apr 25 01:33:38 PM PDT 24
Finished Apr 25 01:33:40 PM PDT 24
Peak memory 196212 kb
Host smart-05798997-ea3d-4d19-a245-2202bb6724f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234210280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.2234210280
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.3930823633
Short name T255
Test name
Test status
Simulation time 92021727316 ps
CPU time 45.36 seconds
Started Apr 25 01:33:36 PM PDT 24
Finished Apr 25 01:34:22 PM PDT 24
Peak memory 199924 kb
Host smart-1f9b7c20-264f-4535-a83e-9ff5a42e9b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930823633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.3930823633
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.3129096263
Short name T619
Test name
Test status
Simulation time 3274487731 ps
CPU time 77.14 seconds
Started Apr 25 01:33:38 PM PDT 24
Finished Apr 25 01:34:56 PM PDT 24
Peak memory 200392 kb
Host smart-28eb194e-f07a-4ff7-ba8a-31d08e2f6ec6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3129096263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.3129096263
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.1041616826
Short name T1156
Test name
Test status
Simulation time 6507105053 ps
CPU time 62.37 seconds
Started Apr 25 01:33:37 PM PDT 24
Finished Apr 25 01:34:40 PM PDT 24
Peak memory 198740 kb
Host smart-91dcc22f-407e-4a68-b486-6a926d3bbd48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1041616826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.1041616826
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.1522738018
Short name T652
Test name
Test status
Simulation time 63817801899 ps
CPU time 19.96 seconds
Started Apr 25 01:33:38 PM PDT 24
Finished Apr 25 01:33:59 PM PDT 24
Peak memory 199848 kb
Host smart-b4d672ae-f979-4e2e-a453-8253ef7a98ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522738018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.1522738018
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.720533686
Short name T514
Test name
Test status
Simulation time 58201110354 ps
CPU time 10.14 seconds
Started Apr 25 01:33:40 PM PDT 24
Finished Apr 25 01:33:50 PM PDT 24
Peak memory 196144 kb
Host smart-34ba3ac2-90c9-46d7-91bd-a46fec87a9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720533686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.720533686
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.2535343804
Short name T259
Test name
Test status
Simulation time 466068149 ps
CPU time 1.65 seconds
Started Apr 25 01:33:30 PM PDT 24
Finished Apr 25 01:33:32 PM PDT 24
Peak memory 200312 kb
Host smart-5c06c14a-71da-4227-928d-1af5b77dbc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535343804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.2535343804
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.3528858253
Short name T1167
Test name
Test status
Simulation time 140406107748 ps
CPU time 266.02 seconds
Started Apr 25 01:33:45 PM PDT 24
Finished Apr 25 01:38:12 PM PDT 24
Peak memory 208800 kb
Host smart-a3e96aeb-f279-4973-9970-1950668cb7d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528858253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3528858253
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.406859105
Short name T446
Test name
Test status
Simulation time 188321390317 ps
CPU time 912.79 seconds
Started Apr 25 01:33:46 PM PDT 24
Finished Apr 25 01:49:00 PM PDT 24
Peak memory 216896 kb
Host smart-987944b4-c770-4480-b3f5-39e212b0591c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406859105 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.406859105
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.3075414725
Short name T653
Test name
Test status
Simulation time 587520469 ps
CPU time 1.92 seconds
Started Apr 25 01:33:39 PM PDT 24
Finished Apr 25 01:33:41 PM PDT 24
Peak memory 200244 kb
Host smart-c25c3110-20e2-4e10-b973-cc9add282fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075414725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.3075414725
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.3383453756
Short name T334
Test name
Test status
Simulation time 9660280306 ps
CPU time 8.65 seconds
Started Apr 25 01:33:31 PM PDT 24
Finished Apr 25 01:33:40 PM PDT 24
Peak memory 198228 kb
Host smart-ae5fe947-5e8b-44bc-a204-e3baf3d62f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383453756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.3383453756
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.4225895274
Short name T593
Test name
Test status
Simulation time 46598715327 ps
CPU time 18.12 seconds
Started Apr 25 01:39:48 PM PDT 24
Finished Apr 25 01:40:06 PM PDT 24
Peak memory 200292 kb
Host smart-27624f03-67da-44ed-bde0-2d7b878647b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225895274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.4225895274
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.2602739384
Short name T27
Test name
Test status
Simulation time 204243956087 ps
CPU time 513.69 seconds
Started Apr 25 01:39:50 PM PDT 24
Finished Apr 25 01:48:24 PM PDT 24
Peak memory 216212 kb
Host smart-7ec92bcb-46a3-4e6a-aea6-f3e88be0d1f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602739384 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.2602739384
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.296809081
Short name T264
Test name
Test status
Simulation time 165063684303 ps
CPU time 71.42 seconds
Started Apr 25 01:39:48 PM PDT 24
Finished Apr 25 01:41:00 PM PDT 24
Peak memory 200440 kb
Host smart-223a9550-a820-49c2-af22-0ca726e7163f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296809081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.296809081
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.1000436568
Short name T941
Test name
Test status
Simulation time 52652714669 ps
CPU time 1411.82 seconds
Started Apr 25 01:39:48 PM PDT 24
Finished Apr 25 02:03:21 PM PDT 24
Peak memory 225264 kb
Host smart-c0cd11c3-9914-4886-b3bf-d4f56e397384
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000436568 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.1000436568
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.4211741291
Short name T370
Test name
Test status
Simulation time 49392487401 ps
CPU time 18.53 seconds
Started Apr 25 01:39:47 PM PDT 24
Finished Apr 25 01:40:06 PM PDT 24
Peak memory 200456 kb
Host smart-ff687139-3d75-4756-adb1-7fd00473506e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211741291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.4211741291
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.2482749403
Short name T1178
Test name
Test status
Simulation time 748993778522 ps
CPU time 570.89 seconds
Started Apr 25 01:39:54 PM PDT 24
Finished Apr 25 01:49:26 PM PDT 24
Peak memory 213744 kb
Host smart-1bc42513-ba8a-4e67-bd2d-9337465e0af3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482749403 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.2482749403
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.1370116531
Short name T759
Test name
Test status
Simulation time 23456544119 ps
CPU time 23.05 seconds
Started Apr 25 01:39:59 PM PDT 24
Finished Apr 25 01:40:22 PM PDT 24
Peak memory 200396 kb
Host smart-f2bfb9de-8f6e-4e84-8e51-264f356a4944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370116531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1370116531
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.3810379014
Short name T979
Test name
Test status
Simulation time 1467023417 ps
CPU time 19.96 seconds
Started Apr 25 01:39:57 PM PDT 24
Finished Apr 25 01:40:17 PM PDT 24
Peak memory 200452 kb
Host smart-594e4418-788c-4de2-a382-3927aea4d0b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810379014 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.3810379014
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.908002854
Short name T198
Test name
Test status
Simulation time 34970962752 ps
CPU time 30.3 seconds
Started Apr 25 01:39:56 PM PDT 24
Finished Apr 25 01:40:27 PM PDT 24
Peak memory 200460 kb
Host smart-cf534412-96bd-402a-bac8-6731ce693f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908002854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.908002854
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.975940210
Short name T448
Test name
Test status
Simulation time 53814854240 ps
CPU time 241.46 seconds
Started Apr 25 01:39:55 PM PDT 24
Finished Apr 25 01:43:57 PM PDT 24
Peak memory 215768 kb
Host smart-fa7f6b39-3650-4022-9fe6-aaff6defa0a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975940210 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.975940210
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.4260950813
Short name T927
Test name
Test status
Simulation time 97373037722 ps
CPU time 89.36 seconds
Started Apr 25 01:39:56 PM PDT 24
Finished Apr 25 01:41:26 PM PDT 24
Peak memory 200408 kb
Host smart-5ccf0822-c90c-43d5-974c-bdafd672148e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260950813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.4260950813
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.2948596559
Short name T90
Test name
Test status
Simulation time 95247164869 ps
CPU time 352.02 seconds
Started Apr 25 01:39:54 PM PDT 24
Finished Apr 25 01:45:46 PM PDT 24
Peak memory 216816 kb
Host smart-137833b6-167d-4b24-ae94-24ae9f95a3ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948596559 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.2948596559
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.1548157455
Short name T536
Test name
Test status
Simulation time 26814863528 ps
CPU time 40.17 seconds
Started Apr 25 01:39:54 PM PDT 24
Finished Apr 25 01:40:34 PM PDT 24
Peak memory 200112 kb
Host smart-785f41c9-8c80-4551-9e83-7fec1bca84e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548157455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1548157455
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.3024594564
Short name T968
Test name
Test status
Simulation time 60718326266 ps
CPU time 444.08 seconds
Started Apr 25 01:39:55 PM PDT 24
Finished Apr 25 01:47:20 PM PDT 24
Peak memory 216904 kb
Host smart-ececf5df-3b0a-427a-8f18-68e6e917bac1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024594564 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.3024594564
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.2323287958
Short name T114
Test name
Test status
Simulation time 65768200038 ps
CPU time 137.76 seconds
Started Apr 25 01:39:54 PM PDT 24
Finished Apr 25 01:42:12 PM PDT 24
Peak memory 200444 kb
Host smart-ed053e26-e19d-460c-8a56-a7b1a7911fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323287958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.2323287958
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.2989684358
Short name T99
Test name
Test status
Simulation time 99897914411 ps
CPU time 17.93 seconds
Started Apr 25 01:39:54 PM PDT 24
Finished Apr 25 01:40:12 PM PDT 24
Peak memory 200372 kb
Host smart-d85d877d-1e44-46da-856e-028084ddc203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989684358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.2989684358
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.955230397
Short name T240
Test name
Test status
Simulation time 38495019528 ps
CPU time 500.56 seconds
Started Apr 25 01:39:56 PM PDT 24
Finished Apr 25 01:48:17 PM PDT 24
Peak memory 217016 kb
Host smart-ccb8e04d-cfc8-4842-a9ef-be92ea463264
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955230397 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.955230397
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.503695694
Short name T91
Test name
Test status
Simulation time 221003569186 ps
CPU time 824.54 seconds
Started Apr 25 01:39:59 PM PDT 24
Finished Apr 25 01:53:45 PM PDT 24
Peak memory 225008 kb
Host smart-0c137e0d-40b4-40dc-ba6d-faf8a79902c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503695694 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.503695694
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.3278620461
Short name T662
Test name
Test status
Simulation time 81446137 ps
CPU time 0.53 seconds
Started Apr 25 01:33:53 PM PDT 24
Finished Apr 25 01:33:55 PM PDT 24
Peak memory 195800 kb
Host smart-ede26e41-fd81-4916-a7ad-78b4bc53c52b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278620461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3278620461
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.2906709981
Short name T257
Test name
Test status
Simulation time 143458941730 ps
CPU time 135.84 seconds
Started Apr 25 01:33:45 PM PDT 24
Finished Apr 25 01:36:01 PM PDT 24
Peak memory 200412 kb
Host smart-090ce020-686c-4545-9a67-ac23a03a0848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906709981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.2906709981
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.655263303
Short name T246
Test name
Test status
Simulation time 39929222431 ps
CPU time 34.79 seconds
Started Apr 25 01:33:44 PM PDT 24
Finished Apr 25 01:34:19 PM PDT 24
Peak memory 200416 kb
Host smart-7745b9ae-3c14-48ad-be15-f0b636afedfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655263303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.655263303
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.292078414
Short name T313
Test name
Test status
Simulation time 16799302539 ps
CPU time 14.18 seconds
Started Apr 25 01:33:43 PM PDT 24
Finished Apr 25 01:33:58 PM PDT 24
Peak memory 200388 kb
Host smart-c86009e5-3610-4559-8011-0827d5684cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292078414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.292078414
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.4240787835
Short name T744
Test name
Test status
Simulation time 39800534045 ps
CPU time 63.63 seconds
Started Apr 25 01:33:49 PM PDT 24
Finished Apr 25 01:34:53 PM PDT 24
Peak memory 199296 kb
Host smart-bade29d9-54bd-4538-9452-1b8db53a2e7f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240787835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.4240787835
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.1559134827
Short name T1135
Test name
Test status
Simulation time 66705587455 ps
CPU time 196.74 seconds
Started Apr 25 01:33:53 PM PDT 24
Finished Apr 25 01:37:11 PM PDT 24
Peak memory 200408 kb
Host smart-ef60613b-df86-43f2-b099-ba699c9207ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1559134827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.1559134827
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.2697834567
Short name T6
Test name
Test status
Simulation time 3421777246 ps
CPU time 9.39 seconds
Started Apr 25 01:33:55 PM PDT 24
Finished Apr 25 01:34:05 PM PDT 24
Peak memory 199200 kb
Host smart-6f8217e9-54b7-4661-b7e1-059bbdd8c931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697834567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.2697834567
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.3353541477
Short name T384
Test name
Test status
Simulation time 113124030989 ps
CPU time 50.85 seconds
Started Apr 25 01:33:46 PM PDT 24
Finished Apr 25 01:34:38 PM PDT 24
Peak memory 200600 kb
Host smart-458ee7d1-7da3-472c-8fa3-4325fcdca6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353541477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.3353541477
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.4179015413
Short name T297
Test name
Test status
Simulation time 16634949262 ps
CPU time 215.44 seconds
Started Apr 25 01:33:54 PM PDT 24
Finished Apr 25 01:37:30 PM PDT 24
Peak memory 200388 kb
Host smart-9aeb75bf-fbfd-43b3-958c-fe6acecebd60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4179015413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.4179015413
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.1452642443
Short name T877
Test name
Test status
Simulation time 4713286998 ps
CPU time 36.9 seconds
Started Apr 25 01:33:45 PM PDT 24
Finished Apr 25 01:34:23 PM PDT 24
Peak memory 199660 kb
Host smart-ff348b8f-65d5-48d4-be7a-051ec9c07903
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1452642443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.1452642443
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.839920197
Short name T643
Test name
Test status
Simulation time 128372592073 ps
CPU time 147.76 seconds
Started Apr 25 01:33:46 PM PDT 24
Finished Apr 25 01:36:15 PM PDT 24
Peak memory 200324 kb
Host smart-fc8cd55c-9f59-43a8-95a5-c5309443bcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839920197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.839920197
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.3140914508
Short name T371
Test name
Test status
Simulation time 2765970078 ps
CPU time 1.52 seconds
Started Apr 25 01:33:46 PM PDT 24
Finished Apr 25 01:33:48 PM PDT 24
Peak memory 196116 kb
Host smart-b9073eda-3eac-4b60-baac-858ed88d584e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140914508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.3140914508
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.4139884911
Short name T699
Test name
Test status
Simulation time 6036669635 ps
CPU time 6.76 seconds
Started Apr 25 01:33:44 PM PDT 24
Finished Apr 25 01:33:51 PM PDT 24
Peak memory 200428 kb
Host smart-03054d94-7c68-4061-a17b-483ce6dc4976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139884911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.4139884911
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.2460341283
Short name T1116
Test name
Test status
Simulation time 702904855358 ps
CPU time 591.44 seconds
Started Apr 25 01:33:53 PM PDT 24
Finished Apr 25 01:43:45 PM PDT 24
Peak memory 200368 kb
Host smart-4d004bcd-8fa0-47f1-99ed-a72dcffb0656
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460341283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.2460341283
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.1691833607
Short name T1039
Test name
Test status
Simulation time 19895086540 ps
CPU time 191.75 seconds
Started Apr 25 01:33:53 PM PDT 24
Finished Apr 25 01:37:05 PM PDT 24
Peak memory 216432 kb
Host smart-fee9c9cf-541d-4021-be9b-d96f69179a08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691833607 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.1691833607
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.3219510922
Short name T369
Test name
Test status
Simulation time 7361363308 ps
CPU time 7.93 seconds
Started Apr 25 01:33:46 PM PDT 24
Finished Apr 25 01:33:55 PM PDT 24
Peak memory 199656 kb
Host smart-cc9132b8-587e-4a72-8efb-116e959a5a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219510922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.3219510922
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.2899505412
Short name T1113
Test name
Test status
Simulation time 913416696 ps
CPU time 1.37 seconds
Started Apr 25 01:33:44 PM PDT 24
Finished Apr 25 01:33:46 PM PDT 24
Peak memory 197276 kb
Host smart-1a332f08-430f-4277-8847-67a2ca487470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899505412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.2899505412
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.2801763990
Short name T141
Test name
Test status
Simulation time 26998251318 ps
CPU time 39.44 seconds
Started Apr 25 01:40:02 PM PDT 24
Finished Apr 25 01:40:41 PM PDT 24
Peak memory 200280 kb
Host smart-92e95f73-acf5-43db-ba9a-c465b94253f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801763990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.2801763990
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.3216350296
Short name T193
Test name
Test status
Simulation time 92516458676 ps
CPU time 600.08 seconds
Started Apr 25 01:40:07 PM PDT 24
Finished Apr 25 01:50:07 PM PDT 24
Peak memory 216884 kb
Host smart-df12156b-50c6-45ea-a09f-780a35a1bfbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216350296 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.3216350296
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.964394708
Short name T172
Test name
Test status
Simulation time 248623164919 ps
CPU time 109.85 seconds
Started Apr 25 01:40:02 PM PDT 24
Finished Apr 25 01:41:52 PM PDT 24
Peak memory 200448 kb
Host smart-f45a2560-037e-4139-9493-36cdb848c3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964394708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.964394708
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.3146086891
Short name T955
Test name
Test status
Simulation time 158136687575 ps
CPU time 2237.39 seconds
Started Apr 25 01:40:02 PM PDT 24
Finished Apr 25 02:17:20 PM PDT 24
Peak memory 228220 kb
Host smart-fd361c39-2f8a-4739-9a9a-16814988bb4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146086891 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.3146086891
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.1569135000
Short name T592
Test name
Test status
Simulation time 27438224612 ps
CPU time 13.81 seconds
Started Apr 25 01:40:00 PM PDT 24
Finished Apr 25 01:40:14 PM PDT 24
Peak memory 200420 kb
Host smart-a3276935-7fd4-4a9b-972e-3c2431a63a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569135000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.1569135000
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.3312103139
Short name T84
Test name
Test status
Simulation time 151996275533 ps
CPU time 620.53 seconds
Started Apr 25 01:40:07 PM PDT 24
Finished Apr 25 01:50:28 PM PDT 24
Peak memory 225308 kb
Host smart-9c7d9d24-b18a-44a3-89b8-8d8d994628d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312103139 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.3312103139
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.4177252387
Short name T208
Test name
Test status
Simulation time 107760486641 ps
CPU time 57.14 seconds
Started Apr 25 01:40:01 PM PDT 24
Finished Apr 25 01:40:59 PM PDT 24
Peak memory 200348 kb
Host smart-5bb3e56b-ca6a-45da-8325-76ec6be682fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177252387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.4177252387
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.1835125601
Short name T144
Test name
Test status
Simulation time 144674224867 ps
CPU time 454.58 seconds
Started Apr 25 01:40:01 PM PDT 24
Finished Apr 25 01:47:37 PM PDT 24
Peak memory 216792 kb
Host smart-68b1ccbf-b6ec-420f-94c5-c354e1018376
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835125601 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.1835125601
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.467614712
Short name T819
Test name
Test status
Simulation time 221192394411 ps
CPU time 87.81 seconds
Started Apr 25 01:40:10 PM PDT 24
Finished Apr 25 01:41:39 PM PDT 24
Peak memory 200408 kb
Host smart-6fafbd8c-2ae2-4e99-8f70-688985fdbe5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467614712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.467614712
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.1174203878
Short name T105
Test name
Test status
Simulation time 90987811941 ps
CPU time 580.6 seconds
Started Apr 25 01:40:10 PM PDT 24
Finished Apr 25 01:49:52 PM PDT 24
Peak memory 225284 kb
Host smart-2f61756a-db2d-4c4a-9d6d-c750715c09b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174203878 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.1174203878
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.4246260889
Short name T43
Test name
Test status
Simulation time 25392683305 ps
CPU time 41.9 seconds
Started Apr 25 01:40:17 PM PDT 24
Finished Apr 25 01:40:59 PM PDT 24
Peak memory 200388 kb
Host smart-df271317-751d-4e74-81d2-856beefb8f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246260889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.4246260889
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.313240954
Short name T167
Test name
Test status
Simulation time 179271692328 ps
CPU time 696.32 seconds
Started Apr 25 01:40:10 PM PDT 24
Finished Apr 25 01:51:47 PM PDT 24
Peak memory 216888 kb
Host smart-aed57faa-e1e8-4560-9364-87346d126af9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313240954 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.313240954
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.3720132791
Short name T935
Test name
Test status
Simulation time 40126910829 ps
CPU time 62.16 seconds
Started Apr 25 01:40:09 PM PDT 24
Finished Apr 25 01:41:12 PM PDT 24
Peak memory 200360 kb
Host smart-b75f8d94-6cb9-4876-9ac8-85e1804b633c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720132791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.3720132791
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.840994747
Short name T565
Test name
Test status
Simulation time 97595685080 ps
CPU time 520.57 seconds
Started Apr 25 01:40:10 PM PDT 24
Finished Apr 25 01:48:52 PM PDT 24
Peak memory 225232 kb
Host smart-72303289-778d-4e43-af39-99c0cef1d434
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840994747 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.840994747
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.526165002
Short name T390
Test name
Test status
Simulation time 124766533280 ps
CPU time 101.38 seconds
Started Apr 25 01:40:16 PM PDT 24
Finished Apr 25 01:41:58 PM PDT 24
Peak memory 200408 kb
Host smart-81cae383-64cc-4ac3-ba8a-288fd4b3d67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526165002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.526165002
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.457049847
Short name T691
Test name
Test status
Simulation time 160543356376 ps
CPU time 770.08 seconds
Started Apr 25 01:40:10 PM PDT 24
Finished Apr 25 01:53:01 PM PDT 24
Peak memory 225264 kb
Host smart-9c20de5e-38aa-4d1e-a27d-65ba2d026b7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457049847 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.457049847
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.608343273
Short name T560
Test name
Test status
Simulation time 11673675559 ps
CPU time 7.13 seconds
Started Apr 25 01:40:10 PM PDT 24
Finished Apr 25 01:40:18 PM PDT 24
Peak memory 200436 kb
Host smart-77cad835-e18a-4f41-b92a-88793769252d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608343273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.608343273
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.722380405
Short name T145
Test name
Test status
Simulation time 733321071316 ps
CPU time 1095.23 seconds
Started Apr 25 01:40:10 PM PDT 24
Finished Apr 25 01:58:27 PM PDT 24
Peak memory 225092 kb
Host smart-fbd8998d-fc7d-461d-ba16-e7dc4d84f1df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722380405 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.722380405
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.3960381654
Short name T579
Test name
Test status
Simulation time 14860078778 ps
CPU time 32.02 seconds
Started Apr 25 01:40:09 PM PDT 24
Finished Apr 25 01:40:42 PM PDT 24
Peak memory 200304 kb
Host smart-40d65fa7-3629-4465-ab88-7be90bb1ebe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960381654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.3960381654
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.1485778882
Short name T1047
Test name
Test status
Simulation time 69108206907 ps
CPU time 777.63 seconds
Started Apr 25 01:40:16 PM PDT 24
Finished Apr 25 01:53:14 PM PDT 24
Peak memory 216844 kb
Host smart-591997b6-73c0-4213-bfc6-f3d5f45b1001
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485778882 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.1485778882
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.19293550
Short name T859
Test name
Test status
Simulation time 101992648 ps
CPU time 0.55 seconds
Started Apr 25 01:34:08 PM PDT 24
Finished Apr 25 01:34:10 PM PDT 24
Peak memory 195772 kb
Host smart-674f385a-f84b-4ac7-a4cd-f7e6f36431f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19293550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.19293550
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.2761872172
Short name T424
Test name
Test status
Simulation time 94444730319 ps
CPU time 75.86 seconds
Started Apr 25 01:34:01 PM PDT 24
Finished Apr 25 01:35:17 PM PDT 24
Peak memory 200412 kb
Host smart-82f8d640-1baa-4dd3-b94b-d3f5a878564e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761872172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.2761872172
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.1460864234
Short name T1102
Test name
Test status
Simulation time 69383624119 ps
CPU time 132.66 seconds
Started Apr 25 01:34:00 PM PDT 24
Finished Apr 25 01:36:13 PM PDT 24
Peak memory 200388 kb
Host smart-168e8945-a836-4d6b-854d-77253784b586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460864234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.1460864234
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.3231889724
Short name T180
Test name
Test status
Simulation time 25817098299 ps
CPU time 56.43 seconds
Started Apr 25 01:34:02 PM PDT 24
Finished Apr 25 01:34:59 PM PDT 24
Peak memory 200356 kb
Host smart-ecebd5ae-9c44-49b5-98e3-99527cf957e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231889724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.3231889724
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.1788137543
Short name T640
Test name
Test status
Simulation time 11651995621 ps
CPU time 7.42 seconds
Started Apr 25 01:34:03 PM PDT 24
Finished Apr 25 01:34:11 PM PDT 24
Peak memory 200108 kb
Host smart-999dabc5-ef90-49a7-870b-5f0f2c4ed495
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788137543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.1788137543
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.305713972
Short name T766
Test name
Test status
Simulation time 79842907956 ps
CPU time 723.47 seconds
Started Apr 25 01:34:02 PM PDT 24
Finished Apr 25 01:46:06 PM PDT 24
Peak memory 200384 kb
Host smart-d97d3226-702e-4a2a-8c01-8c87e286abcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=305713972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.305713972
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.1187696141
Short name T605
Test name
Test status
Simulation time 12326260353 ps
CPU time 22.27 seconds
Started Apr 25 01:34:02 PM PDT 24
Finished Apr 25 01:34:25 PM PDT 24
Peak memory 199136 kb
Host smart-b9809cf0-db5e-4b64-b0dc-95eb238f1ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187696141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.1187696141
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.1918329233
Short name T1181
Test name
Test status
Simulation time 122115008851 ps
CPU time 199.71 seconds
Started Apr 25 01:34:01 PM PDT 24
Finished Apr 25 01:37:21 PM PDT 24
Peak memory 198852 kb
Host smart-742bcea3-6bc6-4c03-a61e-50ebdb3f55f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918329233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.1918329233
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.185636375
Short name T511
Test name
Test status
Simulation time 21328973038 ps
CPU time 502.73 seconds
Started Apr 25 01:34:02 PM PDT 24
Finished Apr 25 01:42:25 PM PDT 24
Peak memory 200428 kb
Host smart-585701ce-7315-4950-9b14-f654c2f2c6f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=185636375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.185636375
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.2341787628
Short name T585
Test name
Test status
Simulation time 7288330938 ps
CPU time 16.8 seconds
Started Apr 25 01:34:03 PM PDT 24
Finished Apr 25 01:34:20 PM PDT 24
Peak memory 199244 kb
Host smart-cfa49549-850c-41eb-9e5d-5767c836f775
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2341787628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.2341787628
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.1666541847
Short name T781
Test name
Test status
Simulation time 140314999259 ps
CPU time 357.92 seconds
Started Apr 25 01:34:02 PM PDT 24
Finished Apr 25 01:40:00 PM PDT 24
Peak memory 200336 kb
Host smart-9d53e117-4514-470e-85f7-e7121100a53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666541847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1666541847
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.1937394853
Short name T361
Test name
Test status
Simulation time 5188722389 ps
CPU time 3 seconds
Started Apr 25 01:34:03 PM PDT 24
Finished Apr 25 01:34:07 PM PDT 24
Peak memory 196404 kb
Host smart-ba027389-dd4d-4cb2-b23b-445892efc027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937394853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1937394853
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.74827167
Short name T498
Test name
Test status
Simulation time 479852468 ps
CPU time 1.63 seconds
Started Apr 25 01:34:02 PM PDT 24
Finished Apr 25 01:34:04 PM PDT 24
Peak memory 198856 kb
Host smart-2a089594-1fe0-45ec-b41f-2785d4d3653e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74827167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.74827167
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.1053658882
Short name T1160
Test name
Test status
Simulation time 93054167850 ps
CPU time 167.94 seconds
Started Apr 25 01:34:07 PM PDT 24
Finished Apr 25 01:36:55 PM PDT 24
Peak memory 200308 kb
Host smart-6e4958c1-7f27-4d5b-99e1-d6081aa7cae9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053658882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.1053658882
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.3745813267
Short name T1031
Test name
Test status
Simulation time 3955931882 ps
CPU time 1.38 seconds
Started Apr 25 01:34:02 PM PDT 24
Finished Apr 25 01:34:04 PM PDT 24
Peak memory 198672 kb
Host smart-8d2884ae-2f2d-4356-bfbf-17981feea07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745813267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.3745813267
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.1663873798
Short name T616
Test name
Test status
Simulation time 8036513798 ps
CPU time 13.81 seconds
Started Apr 25 01:33:59 PM PDT 24
Finished Apr 25 01:34:14 PM PDT 24
Peak memory 199916 kb
Host smart-1f2d7fb6-7152-436a-bdb0-604da8c17c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663873798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.1663873798
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.2096333676
Short name T629
Test name
Test status
Simulation time 141311864488 ps
CPU time 66.46 seconds
Started Apr 25 01:40:16 PM PDT 24
Finished Apr 25 01:41:23 PM PDT 24
Peak memory 200460 kb
Host smart-bca45fe7-e747-4eaa-837c-c09f921dd22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096333676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2096333676
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.700528856
Short name T1053
Test name
Test status
Simulation time 82062719445 ps
CPU time 44.11 seconds
Started Apr 25 01:40:14 PM PDT 24
Finished Apr 25 01:40:59 PM PDT 24
Peak memory 200456 kb
Host smart-dab48f82-0cc8-4055-8060-0a26f6b9d659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700528856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.700528856
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.1980529948
Short name T128
Test name
Test status
Simulation time 55475510209 ps
CPU time 158.17 seconds
Started Apr 25 01:40:18 PM PDT 24
Finished Apr 25 01:42:56 PM PDT 24
Peak memory 217076 kb
Host smart-db1a89ee-c7ed-4e3f-a135-cc11262ab3e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980529948 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.1980529948
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.446620699
Short name T794
Test name
Test status
Simulation time 20316857171 ps
CPU time 37.59 seconds
Started Apr 25 01:40:16 PM PDT 24
Finished Apr 25 01:40:54 PM PDT 24
Peak memory 200348 kb
Host smart-fb145f00-f881-44a4-a8c6-173a7729773d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446620699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.446620699
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.3870814623
Short name T602
Test name
Test status
Simulation time 25824043685 ps
CPU time 249.08 seconds
Started Apr 25 01:40:15 PM PDT 24
Finished Apr 25 01:44:25 PM PDT 24
Peak memory 216144 kb
Host smart-4152aed9-70c9-43c5-bdcd-ca873d29b0b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870814623 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.3870814623
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.2780007059
Short name T1128
Test name
Test status
Simulation time 92432587968 ps
CPU time 299.1 seconds
Started Apr 25 01:40:15 PM PDT 24
Finished Apr 25 01:45:15 PM PDT 24
Peak memory 200348 kb
Host smart-521dffe0-ea77-4bb3-8328-b8495c2d6409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780007059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2780007059
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.3206084680
Short name T665
Test name
Test status
Simulation time 308267611482 ps
CPU time 847.2 seconds
Started Apr 25 01:40:16 PM PDT 24
Finished Apr 25 01:54:24 PM PDT 24
Peak memory 231004 kb
Host smart-eb435d9d-ef08-40f7-85e3-d46a52bebc9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206084680 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.3206084680
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.3048033833
Short name T784
Test name
Test status
Simulation time 12175213467 ps
CPU time 19.18 seconds
Started Apr 25 01:40:18 PM PDT 24
Finished Apr 25 01:40:37 PM PDT 24
Peak memory 200312 kb
Host smart-c630d25b-766d-424b-988f-0f940d9020fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048033833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.3048033833
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.1461300286
Short name T863
Test name
Test status
Simulation time 140938344983 ps
CPU time 369.75 seconds
Started Apr 25 01:40:18 PM PDT 24
Finished Apr 25 01:46:28 PM PDT 24
Peak memory 217064 kb
Host smart-19462217-1117-47ae-a077-809d25bd2df0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461300286 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.1461300286
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.1195805492
Short name T971
Test name
Test status
Simulation time 19525851010 ps
CPU time 33.8 seconds
Started Apr 25 01:40:29 PM PDT 24
Finished Apr 25 01:41:03 PM PDT 24
Peak memory 200416 kb
Host smart-530c3562-b610-4da3-9314-d66128820883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195805492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.1195805492
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.670783231
Short name T231
Test name
Test status
Simulation time 46427721547 ps
CPU time 396.39 seconds
Started Apr 25 01:40:17 PM PDT 24
Finished Apr 25 01:46:54 PM PDT 24
Peak memory 216856 kb
Host smart-a4029539-a81d-4276-b877-0bcbf9b4e274
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670783231 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.670783231
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.3637011701
Short name T828
Test name
Test status
Simulation time 23225129591 ps
CPU time 41.37 seconds
Started Apr 25 01:40:15 PM PDT 24
Finished Apr 25 01:40:57 PM PDT 24
Peak memory 200456 kb
Host smart-b66a0bfb-ab8b-4484-9232-769a0b6d6cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637011701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.3637011701
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.4187038101
Short name T117
Test name
Test status
Simulation time 21357023169 ps
CPU time 232.57 seconds
Started Apr 25 01:40:15 PM PDT 24
Finished Apr 25 01:44:08 PM PDT 24
Peak memory 217084 kb
Host smart-5bb8d6fa-b9de-4194-8ebe-e07594de9089
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187038101 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.4187038101
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.1579125316
Short name T175
Test name
Test status
Simulation time 34116950632 ps
CPU time 28.65 seconds
Started Apr 25 01:40:19 PM PDT 24
Finished Apr 25 01:40:48 PM PDT 24
Peak memory 200228 kb
Host smart-10263357-20fa-4109-a5db-133acfe9b378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579125316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.1579125316
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.4025211049
Short name T134
Test name
Test status
Simulation time 31514542888 ps
CPU time 368.25 seconds
Started Apr 25 01:40:18 PM PDT 24
Finished Apr 25 01:46:26 PM PDT 24
Peak memory 215100 kb
Host smart-8e7c4342-3913-4168-bcf5-889f975262e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025211049 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.4025211049
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.3436244177
Short name T204
Test name
Test status
Simulation time 59593354002 ps
CPU time 32.85 seconds
Started Apr 25 01:40:15 PM PDT 24
Finished Apr 25 01:40:48 PM PDT 24
Peak memory 200424 kb
Host smart-1fcd8f34-5b8c-4ea3-a86a-5a87f955b9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436244177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.3436244177
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.474733265
Short name T627
Test name
Test status
Simulation time 26340081775 ps
CPU time 615.76 seconds
Started Apr 25 01:40:17 PM PDT 24
Finished Apr 25 01:50:34 PM PDT 24
Peak memory 217048 kb
Host smart-a4664d8e-56f9-49b5-bd76-74ff8f141916
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474733265 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.474733265
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.487550367
Short name T217
Test name
Test status
Simulation time 16277494498 ps
CPU time 33.9 seconds
Started Apr 25 01:40:21 PM PDT 24
Finished Apr 25 01:40:55 PM PDT 24
Peak memory 200440 kb
Host smart-24d031d7-0984-4739-82db-9591dcec1d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487550367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.487550367
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.2849230222
Short name T1037
Test name
Test status
Simulation time 405035286304 ps
CPU time 1331.74 seconds
Started Apr 25 01:40:21 PM PDT 24
Finished Apr 25 02:02:33 PM PDT 24
Peak memory 229204 kb
Host smart-ebfaea32-e832-42ec-bd5f-f4fa519c7709
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849230222 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.2849230222
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.1691097826
Short name T852
Test name
Test status
Simulation time 15519868 ps
CPU time 0.54 seconds
Started Apr 25 01:34:13 PM PDT 24
Finished Apr 25 01:34:14 PM PDT 24
Peak memory 195812 kb
Host smart-4c494799-7049-4f3c-b02a-01caa158a5f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691097826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.1691097826
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.2869096366
Short name T251
Test name
Test status
Simulation time 23849846569 ps
CPU time 50.28 seconds
Started Apr 25 01:34:07 PM PDT 24
Finished Apr 25 01:34:58 PM PDT 24
Peak memory 200384 kb
Host smart-27894b2c-0234-4833-8d7e-e2ad6b6f9bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869096366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.2869096366
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.2382334515
Short name T1028
Test name
Test status
Simulation time 104346941643 ps
CPU time 27.49 seconds
Started Apr 25 01:34:08 PM PDT 24
Finished Apr 25 01:34:36 PM PDT 24
Peak memory 200380 kb
Host smart-73b7bc1b-d7a8-4c15-8222-1d4514165ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382334515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.2382334515
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.1915330655
Short name T672
Test name
Test status
Simulation time 56586879768 ps
CPU time 14.27 seconds
Started Apr 25 01:34:06 PM PDT 24
Finished Apr 25 01:34:21 PM PDT 24
Peak memory 200400 kb
Host smart-d69348af-ac14-4124-8cf6-ccd7478b5029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915330655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.1915330655
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.3045923861
Short name T457
Test name
Test status
Simulation time 31245164119 ps
CPU time 33.97 seconds
Started Apr 25 01:34:07 PM PDT 24
Finished Apr 25 01:34:41 PM PDT 24
Peak memory 200156 kb
Host smart-217afdbd-5de5-4692-8399-55c75c18373a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045923861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.3045923861
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.4011928745
Short name T796
Test name
Test status
Simulation time 252489102278 ps
CPU time 312.83 seconds
Started Apr 25 01:34:07 PM PDT 24
Finished Apr 25 01:39:21 PM PDT 24
Peak memory 200412 kb
Host smart-28d006ca-50e0-4582-8bcf-a39cec746b85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4011928745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.4011928745
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.3380398754
Short name T931
Test name
Test status
Simulation time 9633684948 ps
CPU time 11.11 seconds
Started Apr 25 01:34:05 PM PDT 24
Finished Apr 25 01:34:17 PM PDT 24
Peak memory 198924 kb
Host smart-308ee327-4aa2-4b20-8654-79ea0e1487a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380398754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.3380398754
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.2901967256
Short name T529
Test name
Test status
Simulation time 375505078485 ps
CPU time 81.68 seconds
Started Apr 25 01:34:07 PM PDT 24
Finished Apr 25 01:35:29 PM PDT 24
Peak memory 208776 kb
Host smart-90ecaf68-8ee3-4b43-bbc3-939965885a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901967256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.2901967256
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.3890321484
Short name T998
Test name
Test status
Simulation time 15295008200 ps
CPU time 801.15 seconds
Started Apr 25 01:34:09 PM PDT 24
Finished Apr 25 01:47:30 PM PDT 24
Peak memory 200432 kb
Host smart-4f86575e-1e85-406b-8783-9622c67db87d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3890321484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3890321484
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.1374155360
Short name T894
Test name
Test status
Simulation time 5713058745 ps
CPU time 9.25 seconds
Started Apr 25 01:34:08 PM PDT 24
Finished Apr 25 01:34:18 PM PDT 24
Peak memory 198512 kb
Host smart-441b779d-d3d4-49dd-9ed7-077b32816f19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1374155360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.1374155360
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.1405493505
Short name T548
Test name
Test status
Simulation time 131770647165 ps
CPU time 50.97 seconds
Started Apr 25 01:34:09 PM PDT 24
Finished Apr 25 01:35:00 PM PDT 24
Peak memory 200140 kb
Host smart-e56feaf7-0c90-4b31-acbe-5ca07c91c975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405493505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.1405493505
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.362774540
Short name T87
Test name
Test status
Simulation time 1713600381 ps
CPU time 1.39 seconds
Started Apr 25 01:34:07 PM PDT 24
Finished Apr 25 01:34:09 PM PDT 24
Peak memory 195820 kb
Host smart-2910a733-a6bc-4225-8908-cc7da4cecf9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362774540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.362774540
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.4089233986
Short name T1075
Test name
Test status
Simulation time 286027547 ps
CPU time 1.95 seconds
Started Apr 25 01:34:09 PM PDT 24
Finished Apr 25 01:34:12 PM PDT 24
Peak memory 199060 kb
Host smart-a26c619a-4d5c-4479-bbf1-d1b3bb739ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089233986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.4089233986
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.3861193250
Short name T732
Test name
Test status
Simulation time 193014496893 ps
CPU time 96.09 seconds
Started Apr 25 01:34:16 PM PDT 24
Finished Apr 25 01:35:52 PM PDT 24
Peak memory 200376 kb
Host smart-d7c52be7-1d05-47ce-969c-27892bfd6e1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861193250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.3861193250
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.2776996312
Short name T986
Test name
Test status
Simulation time 226589014921 ps
CPU time 700.57 seconds
Started Apr 25 01:34:15 PM PDT 24
Finished Apr 25 01:45:56 PM PDT 24
Peak memory 216872 kb
Host smart-e2ff70dc-3270-45db-9556-91263e9345bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776996312 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.2776996312
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.3526516414
Short name T790
Test name
Test status
Simulation time 933479511 ps
CPU time 3.03 seconds
Started Apr 25 01:34:07 PM PDT 24
Finished Apr 25 01:34:11 PM PDT 24
Peak memory 199156 kb
Host smart-9fa1c87a-686e-4460-b250-ed6eb1ba677b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526516414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3526516414
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.2632955689
Short name T284
Test name
Test status
Simulation time 69101600446 ps
CPU time 33.39 seconds
Started Apr 25 01:34:05 PM PDT 24
Finished Apr 25 01:34:39 PM PDT 24
Peak memory 200444 kb
Host smart-b0c05b12-7b97-409e-a01e-6c652a388a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632955689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.2632955689
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.1974083459
Short name T344
Test name
Test status
Simulation time 11560337926 ps
CPU time 24.18 seconds
Started Apr 25 01:40:22 PM PDT 24
Finished Apr 25 01:40:47 PM PDT 24
Peak memory 200416 kb
Host smart-d82223ce-f233-42b3-aa30-1965d9c14794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974083459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.1974083459
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.3633565156
Short name T911
Test name
Test status
Simulation time 80492808036 ps
CPU time 840.26 seconds
Started Apr 25 01:40:21 PM PDT 24
Finished Apr 25 01:54:22 PM PDT 24
Peak memory 212968 kb
Host smart-a5c823e4-2f47-41f4-a1fa-9901dc9d44f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633565156 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.3633565156
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.1053630076
Short name T1017
Test name
Test status
Simulation time 55182513288 ps
CPU time 45.61 seconds
Started Apr 25 01:40:22 PM PDT 24
Finished Apr 25 01:41:08 PM PDT 24
Peak memory 200420 kb
Host smart-59f915b8-e43e-4852-aa1d-b68b0b958d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053630076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.1053630076
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.1282654596
Short name T197
Test name
Test status
Simulation time 126981699983 ps
CPU time 211.12 seconds
Started Apr 25 01:40:21 PM PDT 24
Finished Apr 25 01:43:53 PM PDT 24
Peak memory 200388 kb
Host smart-e7c422fe-24ad-413e-a6a3-77b9d7aca8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282654596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.1282654596
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.3587050432
Short name T788
Test name
Test status
Simulation time 285652184753 ps
CPU time 1439.69 seconds
Started Apr 25 01:40:21 PM PDT 24
Finished Apr 25 02:04:21 PM PDT 24
Peak memory 225212 kb
Host smart-4cc84392-5196-4563-9384-11ce20b82b81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587050432 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.3587050432
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.2840968229
Short name T121
Test name
Test status
Simulation time 165311938900 ps
CPU time 111.54 seconds
Started Apr 25 01:40:21 PM PDT 24
Finished Apr 25 01:42:13 PM PDT 24
Peak memory 200392 kb
Host smart-0b1db8da-f6c2-418c-993a-84b288c124e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840968229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.2840968229
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.4244372822
Short name T572
Test name
Test status
Simulation time 53000673932 ps
CPU time 527.18 seconds
Started Apr 25 01:40:22 PM PDT 24
Finished Apr 25 01:49:10 PM PDT 24
Peak memory 215948 kb
Host smart-3f5cb4f8-2602-47fa-97e0-dca176b7301f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244372822 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.4244372822
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.3464566165
Short name T742
Test name
Test status
Simulation time 96243508894 ps
CPU time 42.37 seconds
Started Apr 25 01:40:30 PM PDT 24
Finished Apr 25 01:41:13 PM PDT 24
Peak memory 200316 kb
Host smart-4e67f013-0f2b-4e92-9710-908aa00e3343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464566165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.3464566165
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.3573783071
Short name T613
Test name
Test status
Simulation time 19416508317 ps
CPU time 171.13 seconds
Started Apr 25 01:40:26 PM PDT 24
Finished Apr 25 01:43:17 PM PDT 24
Peak memory 216664 kb
Host smart-82d0fdd1-a519-4aff-8aa0-912fa9aeeeb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573783071 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.3573783071
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.2496773767
Short name T642
Test name
Test status
Simulation time 110458338491 ps
CPU time 46.5 seconds
Started Apr 25 01:40:26 PM PDT 24
Finished Apr 25 01:41:13 PM PDT 24
Peak memory 200464 kb
Host smart-b4e3a7de-738a-437b-b477-21b0bdcd0951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496773767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.2496773767
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.2787178899
Short name T630
Test name
Test status
Simulation time 16499385247 ps
CPU time 195.06 seconds
Started Apr 25 01:40:26 PM PDT 24
Finished Apr 25 01:43:42 PM PDT 24
Peak memory 215844 kb
Host smart-04739d6d-c81d-41ce-bf57-139452d5c92b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787178899 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.2787178899
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.1601588656
Short name T1099
Test name
Test status
Simulation time 17862014270 ps
CPU time 29.33 seconds
Started Apr 25 01:40:27 PM PDT 24
Finished Apr 25 01:40:57 PM PDT 24
Peak memory 200108 kb
Host smart-bee61d06-e946-4406-9aa1-fff1cb96ddb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601588656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.1601588656
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.3788335887
Short name T48
Test name
Test status
Simulation time 19763940392 ps
CPU time 160.5 seconds
Started Apr 25 01:40:31 PM PDT 24
Finished Apr 25 01:43:12 PM PDT 24
Peak memory 216520 kb
Host smart-c5ca6ca2-95eb-49e7-89b9-7afd1a6a32a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788335887 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.3788335887
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.3124318774
Short name T122
Test name
Test status
Simulation time 16728426192 ps
CPU time 32.56 seconds
Started Apr 25 01:40:26 PM PDT 24
Finished Apr 25 01:40:59 PM PDT 24
Peak memory 200448 kb
Host smart-c17b12d7-a96e-49d2-aa88-c57850d2e2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124318774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.3124318774
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.861506445
Short name T189
Test name
Test status
Simulation time 209275293271 ps
CPU time 706.66 seconds
Started Apr 25 01:40:27 PM PDT 24
Finished Apr 25 01:52:15 PM PDT 24
Peak memory 225240 kb
Host smart-ea64c69a-ace4-446b-8a3e-a62706983c4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861506445 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.861506445
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.4008070369
Short name T381
Test name
Test status
Simulation time 103827904721 ps
CPU time 175.7 seconds
Started Apr 25 01:40:27 PM PDT 24
Finished Apr 25 01:43:23 PM PDT 24
Peak memory 200360 kb
Host smart-0432e391-55f6-4be1-a8b3-53997365faad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008070369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.4008070369
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.1612470967
Short name T1100
Test name
Test status
Simulation time 300990412024 ps
CPU time 1163.25 seconds
Started Apr 25 01:40:28 PM PDT 24
Finished Apr 25 01:59:52 PM PDT 24
Peak memory 216884 kb
Host smart-d083e532-cede-4da6-9d90-32c1d1f9f166
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612470967 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.1612470967
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.1784605134
Short name T733
Test name
Test status
Simulation time 18920855023 ps
CPU time 17.58 seconds
Started Apr 25 01:40:28 PM PDT 24
Finished Apr 25 01:40:46 PM PDT 24
Peak memory 200292 kb
Host smart-fb7a93f6-bed4-4634-b444-d7a511aab69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784605134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.1784605134
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.915273517
Short name T51
Test name
Test status
Simulation time 412192221634 ps
CPU time 1590.73 seconds
Started Apr 25 01:40:27 PM PDT 24
Finished Apr 25 02:06:58 PM PDT 24
Peak memory 225084 kb
Host smart-ea015aee-bdb2-46f1-9117-e7f0c0de3647
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915273517 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.915273517
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.670137022
Short name T341
Test name
Test status
Simulation time 19856865 ps
CPU time 0.6 seconds
Started Apr 25 01:34:23 PM PDT 24
Finished Apr 25 01:34:24 PM PDT 24
Peak memory 195780 kb
Host smart-807befb3-8364-464e-a7ee-5b7a0a8f95bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670137022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.670137022
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.2460171278
Short name T724
Test name
Test status
Simulation time 35363090590 ps
CPU time 29.95 seconds
Started Apr 25 01:34:16 PM PDT 24
Finished Apr 25 01:34:46 PM PDT 24
Peak memory 200356 kb
Host smart-baa3f003-f12f-42d2-b20f-46289954670b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460171278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.2460171278
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.1486589313
Short name T701
Test name
Test status
Simulation time 162506114524 ps
CPU time 295.1 seconds
Started Apr 25 01:34:14 PM PDT 24
Finished Apr 25 01:39:10 PM PDT 24
Peak memory 200424 kb
Host smart-2b2c550c-3676-4b25-b55a-6782d869f4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486589313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1486589313
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.401389134
Short name T800
Test name
Test status
Simulation time 200626508124 ps
CPU time 97.82 seconds
Started Apr 25 01:34:15 PM PDT 24
Finished Apr 25 01:35:53 PM PDT 24
Peak memory 200436 kb
Host smart-d79dc1b9-fdeb-482b-90f8-b1f5591e9984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401389134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.401389134
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.1206231144
Short name T1111
Test name
Test status
Simulation time 64367498254 ps
CPU time 94.14 seconds
Started Apr 25 01:34:16 PM PDT 24
Finished Apr 25 01:35:51 PM PDT 24
Peak memory 200448 kb
Host smart-d8ec8f38-a8dd-431b-9ef8-0cb7174464dd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206231144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.1206231144
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.2748661952
Short name T281
Test name
Test status
Simulation time 57291784538 ps
CPU time 235.38 seconds
Started Apr 25 01:34:23 PM PDT 24
Finished Apr 25 01:38:19 PM PDT 24
Peak memory 200280 kb
Host smart-16bbaacd-b6c6-458c-8f7e-50a288949ce1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2748661952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2748661952
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.360209855
Short name T770
Test name
Test status
Simulation time 7294514596 ps
CPU time 14.22 seconds
Started Apr 25 01:34:21 PM PDT 24
Finished Apr 25 01:34:36 PM PDT 24
Peak memory 199936 kb
Host smart-634eab11-3ba9-4e9c-8f17-6d9ca0abec63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360209855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.360209855
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.386351873
Short name T265
Test name
Test status
Simulation time 116395523259 ps
CPU time 64.16 seconds
Started Apr 25 01:34:15 PM PDT 24
Finished Apr 25 01:35:19 PM PDT 24
Peak memory 200504 kb
Host smart-aff9d0a1-8031-4af8-99a0-0b0dd64ab417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386351873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.386351873
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.1369956416
Short name T870
Test name
Test status
Simulation time 11312069098 ps
CPU time 318.42 seconds
Started Apr 25 01:34:19 PM PDT 24
Finished Apr 25 01:39:38 PM PDT 24
Peak memory 200436 kb
Host smart-fa8208bd-a209-49ac-9a43-8f6181d1ee29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1369956416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.1369956416
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.3649114012
Short name T366
Test name
Test status
Simulation time 7243773610 ps
CPU time 16.02 seconds
Started Apr 25 01:34:14 PM PDT 24
Finished Apr 25 01:34:31 PM PDT 24
Peak memory 198696 kb
Host smart-94b08727-70ed-4900-b4af-55cab5831846
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3649114012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.3649114012
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.2903905662
Short name T97
Test name
Test status
Simulation time 82419258043 ps
CPU time 32.75 seconds
Started Apr 25 01:34:16 PM PDT 24
Finished Apr 25 01:34:49 PM PDT 24
Peak memory 200380 kb
Host smart-89c63464-0238-4247-90df-9a38de67a58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903905662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.2903905662
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.653606350
Short name T374
Test name
Test status
Simulation time 3625028770 ps
CPU time 1.75 seconds
Started Apr 25 01:34:15 PM PDT 24
Finished Apr 25 01:34:17 PM PDT 24
Peak memory 196464 kb
Host smart-e6412ec4-8918-493c-bda3-484a73dde1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653606350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.653606350
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.3883875785
Short name T304
Test name
Test status
Simulation time 320146706 ps
CPU time 0.91 seconds
Started Apr 25 01:34:15 PM PDT 24
Finished Apr 25 01:34:16 PM PDT 24
Peak memory 198752 kb
Host smart-1b647113-e7be-4606-b530-103d24b5dd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883875785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.3883875785
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.1100309858
Short name T178
Test name
Test status
Simulation time 96431364939 ps
CPU time 129.92 seconds
Started Apr 25 01:34:23 PM PDT 24
Finished Apr 25 01:36:33 PM PDT 24
Peak memory 200336 kb
Host smart-56a11f67-f3c9-496e-abc7-f46e6b5b01e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100309858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.1100309858
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.3011139815
Short name T1088
Test name
Test status
Simulation time 6539393742 ps
CPU time 19.48 seconds
Started Apr 25 01:34:14 PM PDT 24
Finished Apr 25 01:34:34 PM PDT 24
Peak memory 199380 kb
Host smart-92427d3b-15c3-43b5-8f82-af8d3fad6737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011139815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.3011139815
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.2833648442
Short name T956
Test name
Test status
Simulation time 41999580297 ps
CPU time 38.31 seconds
Started Apr 25 01:34:14 PM PDT 24
Finished Apr 25 01:34:53 PM PDT 24
Peak memory 200440 kb
Host smart-c6f06785-ff8c-4f93-934f-66bd91fc7100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833648442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.2833648442
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.3340222662
Short name T168
Test name
Test status
Simulation time 89943738998 ps
CPU time 43.8 seconds
Started Apr 25 01:40:29 PM PDT 24
Finished Apr 25 01:41:13 PM PDT 24
Peak memory 200420 kb
Host smart-c9ccc325-d1ca-4148-9d79-67555172fee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340222662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.3340222662
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.877051703
Short name T566
Test name
Test status
Simulation time 46701580986 ps
CPU time 304.68 seconds
Started Apr 25 01:40:32 PM PDT 24
Finished Apr 25 01:45:37 PM PDT 24
Peak memory 208684 kb
Host smart-74b425ce-805a-456a-aef7-903ec7e291ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877051703 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.877051703
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.1201069152
Short name T885
Test name
Test status
Simulation time 48992545507 ps
CPU time 23 seconds
Started Apr 25 01:40:35 PM PDT 24
Finished Apr 25 01:40:58 PM PDT 24
Peak memory 199764 kb
Host smart-2a5ec8bb-1046-4941-8d11-bcee5bb7df5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201069152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.1201069152
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.1914316232
Short name T864
Test name
Test status
Simulation time 41684992609 ps
CPU time 34.04 seconds
Started Apr 25 01:40:35 PM PDT 24
Finished Apr 25 01:41:09 PM PDT 24
Peak memory 200284 kb
Host smart-9ef78d07-5412-4d81-aadc-7f1d1fa3d2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914316232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.1914316232
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.2237594654
Short name T569
Test name
Test status
Simulation time 546673889041 ps
CPU time 839.98 seconds
Started Apr 25 01:40:42 PM PDT 24
Finished Apr 25 01:54:43 PM PDT 24
Peak memory 225220 kb
Host smart-a116715e-e832-4864-898d-f2b684f0f120
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237594654 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.2237594654
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.3219988646
Short name T131
Test name
Test status
Simulation time 38231128868 ps
CPU time 15.44 seconds
Started Apr 25 01:40:34 PM PDT 24
Finished Apr 25 01:40:50 PM PDT 24
Peak memory 199496 kb
Host smart-0f8eb97a-e885-470e-addc-405e9ca5c2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219988646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.3219988646
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.3330073124
Short name T1045
Test name
Test status
Simulation time 10020434849 ps
CPU time 20.68 seconds
Started Apr 25 01:40:31 PM PDT 24
Finished Apr 25 01:40:52 PM PDT 24
Peak memory 200260 kb
Host smart-ba084a7b-54de-4b7b-bc99-21d67d45ba6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330073124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.3330073124
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.1967250296
Short name T1169
Test name
Test status
Simulation time 182328766042 ps
CPU time 838.66 seconds
Started Apr 25 01:40:34 PM PDT 24
Finished Apr 25 01:54:33 PM PDT 24
Peak memory 216824 kb
Host smart-02191903-dd60-4df7-a535-6d6fcab31609
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967250296 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.1967250296
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.1078179125
Short name T805
Test name
Test status
Simulation time 4491155089 ps
CPU time 11.14 seconds
Started Apr 25 01:40:35 PM PDT 24
Finished Apr 25 01:40:47 PM PDT 24
Peak memory 200060 kb
Host smart-b2ba81e4-35f1-440a-aa1e-bad4ae43da45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078179125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.1078179125
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.677749941
Short name T94
Test name
Test status
Simulation time 50208982644 ps
CPU time 267.48 seconds
Started Apr 25 01:40:34 PM PDT 24
Finished Apr 25 01:45:02 PM PDT 24
Peak memory 208640 kb
Host smart-2d906d21-e066-42e3-bda7-dcdecbbda3b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677749941 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.677749941
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.1998496495
Short name T221
Test name
Test status
Simulation time 13414246082 ps
CPU time 8.82 seconds
Started Apr 25 01:40:38 PM PDT 24
Finished Apr 25 01:40:47 PM PDT 24
Peak memory 200316 kb
Host smart-142f6467-64a2-4978-8b83-9bfea607cc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998496495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.1998496495
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.398797908
Short name T52
Test name
Test status
Simulation time 95555308144 ps
CPU time 316.53 seconds
Started Apr 25 01:40:33 PM PDT 24
Finished Apr 25 01:45:50 PM PDT 24
Peak memory 209228 kb
Host smart-2f94c994-ce89-462d-a322-fbe035c2371f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398797908 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.398797908
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.2945919242
Short name T445
Test name
Test status
Simulation time 34625190690 ps
CPU time 26.56 seconds
Started Apr 25 01:40:38 PM PDT 24
Finished Apr 25 01:41:06 PM PDT 24
Peak memory 200432 kb
Host smart-19359e5e-d13d-48fe-aacd-19367c602c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945919242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2945919242
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.4102483799
Short name T216
Test name
Test status
Simulation time 155645018932 ps
CPU time 656.49 seconds
Started Apr 25 01:40:40 PM PDT 24
Finished Apr 25 01:51:37 PM PDT 24
Peak memory 216608 kb
Host smart-0776614f-cef6-4ff7-aaa1-4bb2667baeda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102483799 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.4102483799
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.4157243133
Short name T182
Test name
Test status
Simulation time 24636479448 ps
CPU time 35.73 seconds
Started Apr 25 01:40:38 PM PDT 24
Finished Apr 25 01:41:15 PM PDT 24
Peak memory 200336 kb
Host smart-f33b5bd6-d860-4a2e-b03b-2d99ce700d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157243133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.4157243133
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.476538444
Short name T1109
Test name
Test status
Simulation time 32632417914 ps
CPU time 828.23 seconds
Started Apr 25 01:40:40 PM PDT 24
Finished Apr 25 01:54:28 PM PDT 24
Peak memory 208708 kb
Host smart-d82c6e52-0859-42ad-b121-19b7b2de880f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476538444 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.476538444
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.1708335432
Short name T215
Test name
Test status
Simulation time 101490509132 ps
CPU time 110.73 seconds
Started Apr 25 01:40:38 PM PDT 24
Finished Apr 25 01:42:29 PM PDT 24
Peak memory 200412 kb
Host smart-e505f7b6-5856-4e0c-a3c5-781394c8e637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708335432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.1708335432
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.2269463266
Short name T50
Test name
Test status
Simulation time 70743091620 ps
CPU time 1210.2 seconds
Started Apr 25 01:40:39 PM PDT 24
Finished Apr 25 02:00:50 PM PDT 24
Peak memory 225292 kb
Host smart-94d6a170-1cc0-4c45-922c-127bb6d9a549
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269463266 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.2269463266
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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