Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	113913	1			T1	8		T2	33		T3	71
all_values[1]	113913	1			T1	8		T2	33		T3	71
all_values[2]	113913	1			T1	8		T2	33		T3	71
all_values[3]	113913	1			T1	8		T2	33		T3	71
all_values[4]	113913	1			T1	8		T2	33		T3	71
all_values[5]	113913	1			T1	8		T2	33		T3	71
all_values[6]	113913	1			T1	8		T2	33		T3	71
all_values[7]	113913	1			T1	8		T2	33		T3	71

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

451573

1

T1

31

T2

92

T3

281

auto[1]

459731

1

T1

33

T2

172

T3

287

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

855715

1

T1

47

T2

225

T3

490

auto[1]

55589

1

T1

17

T2

39

T3

78

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	35790	1			T3	26		T6	4		T7	11
all_values[0]	auto[0]	auto[1]	23029	1			T2	5		T3	36		T5	2
all_values[0]	auto[1]	auto[0]	34246	1			T2	1		T3	2		T7	12
all_values[0]	auto[1]	auto[1]	20848	1			T1	8		T2	27		T3	7
all_values[1]	auto[0]	auto[0]	56512	1			T1	1		T2	25		T3	15
all_values[1]	auto[0]	auto[1]	1840	1			T3	1		T12	6		T38	31
all_values[1]	auto[1]	auto[0]	54130	1			T1	3		T2	8		T3	54
all_values[1]	auto[1]	auto[1]	1431	1			T1	4		T3	1		T9	1
all_values[2]	auto[0]	auto[0]	51391	1			T1	2		T3	33		T5	1
all_values[2]	auto[0]	auto[1]	2757	1			T1	4		T3	9		T5	1
all_values[2]	auto[1]	auto[0]	57258	1			T1	1		T2	26		T3	21
all_values[2]	auto[1]	auto[1]	2507	1			T1	1		T2	7		T3	8
all_values[3]	auto[0]	auto[0]	60149	1			T1	1		T2	25		T3	9
all_values[3]	auto[0]	auto[1]	329	1			T3	2		T12	6		T14	1
all_values[3]	auto[1]	auto[0]	53098	1			T1	7		T2	8		T3	59
all_values[3]	auto[1]	auto[1]	337	1			T3	1		T12	4		T13	3
all_values[4]	auto[0]	auto[0]	56876	1			T1	7		T3	48		T4	1
all_values[4]	auto[0]	auto[1]	435	1			T3	2		T12	10		T15	2
all_values[4]	auto[1]	auto[0]	56076	1			T1	1		T2	33		T3	20
all_values[4]	auto[1]	auto[1]	526	1			T3	1		T12	4		T15	1
all_values[5]	auto[0]	auto[0]	55098	1			T1	8		T2	19		T3	27
all_values[5]	auto[0]	auto[1]	201	1			T12	3		T15	1		T19	2
all_values[5]	auto[1]	auto[0]	58402	1			T2	14		T3	39		T6	2
all_values[5]	auto[1]	auto[1]	212	1			T3	5		T12	2		T19	1
all_values[6]	auto[0]	auto[0]	54648	1			T2	13		T3	34		T5	2
all_values[6]	auto[0]	auto[1]	194	1			T3	1		T12	4		T19	3
all_values[6]	auto[1]	auto[0]	58880	1			T1	8		T2	20		T3	32
all_values[6]	auto[1]	auto[1]	191	1			T3	4		T12	3		T15	4
all_values[7]	auto[0]	auto[0]	51918	1			T1	8		T2	5		T3	38
all_values[7]	auto[0]	auto[1]	406	1			T12	4		T15	5		T18	2
all_values[7]	auto[1]	auto[0]	61243	1			T2	28		T3	33		T8	7
all_values[7]	auto[1]	auto[1]	346	1			T12	4		T16	4		T15	9