Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2258	1			T1	1		T3	2		T4	6
auto[BaudRate115200]	2171	1			T1	3		T2	1		T6	1
auto[BaudRate230400]	1966	1			T5	2		T6	2		T7	3
auto[BaudRate128Kbps]	2085	1			T1	2		T2	5		T3	1
auto[BaudRate256Kbps]	2273	1			T2	1		T3	4		T7	2
auto[BaudRate1Mbps]	1874	1			T2	3		T3	2		T6	1
auto[BaudRate1p5Mbps]	1257	1			T2	2		T3	4		T7	2

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1175	1			T40	9		T41	6		T109	8
freqs[25]	1209	1			T9	76		T20	54		T37	2
freqs[48]	233	1			T18	17		T188	8		T274	2
freqs[50]	476	1			T3	13		T11	7		T36	6
freqs[100]	1228	1			T2	12		T8	6		T43	10

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	176	1			T142	1		T124	1		T147	2
auto[BaudRate9600]	freqs[25]	196	1			T9	11		T20	12		T251	1
auto[BaudRate9600]	freqs[48]	48	1			T18	2		T188	1		T316	7
auto[BaudRate9600]	freqs[50]	60	1			T3	2		T11	2		T36	1
auto[BaudRate9600]	freqs[100]	198	1			T43	1		T106	4		T29	5
auto[BaudRate115200]	freqs[24]	152	1			T40	1		T109	1		T142	1
auto[BaudRate115200]	freqs[25]	184	1			T9	8		T20	6		T37	1
auto[BaudRate115200]	freqs[48]	39	1			T18	5		T274	1		T317	1
auto[BaudRate115200]	freqs[50]	53	1			T11	1		T36	2		T129	2
auto[BaudRate115200]	freqs[100]	187	1			T2	1		T8	1		T43	1
auto[BaudRate230400]	freqs[24]	193	1			T40	2		T109	2		T142	2
auto[BaudRate230400]	freqs[25]	161	1			T9	7		T20	6		T14	2
auto[BaudRate230400]	freqs[48]	27	1			T18	1		T274	1		T317	2
auto[BaudRate230400]	freqs[50]	54	1			T11	1		T36	2		T129	2
auto[BaudRate230400]	freqs[100]	144	1			T43	1		T106	2		T19	2
auto[BaudRate128Kbps]	freqs[24]	171	1			T40	2		T109	1		T142	1
auto[BaudRate128Kbps]	freqs[25]	155	1			T9	5		T20	9		T269	1
auto[BaudRate128Kbps]	freqs[48]	31	1			T18	4		T317	1		T318	2
auto[BaudRate128Kbps]	freqs[50]	62	1			T3	1		T11	1		T36	1
auto[BaudRate128Kbps]	freqs[100]	175	1			T2	5		T8	1		T43	2
auto[BaudRate256Kbps]	freqs[24]	176	1			T40	2		T142	2		T295	1
auto[BaudRate256Kbps]	freqs[25]	209	1			T9	16		T20	9		T37	1
auto[BaudRate256Kbps]	freqs[48]	28	1			T18	1		T188	2		T319	1
auto[BaudRate256Kbps]	freqs[50]	72	1			T3	4		T11	1		T256	4
auto[BaudRate256Kbps]	freqs[100]	180	1			T2	1		T8	2		T43	1
auto[BaudRate1Mbps]	freqs[24]	228	1			T41	3		T109	3		T295	2
auto[BaudRate1Mbps]	freqs[25]	200	1			T9	25		T20	9		T251	1
auto[BaudRate1Mbps]	freqs[48]	27	1			T18	1		T188	3		T320	1
auto[BaudRate1Mbps]	freqs[50]	104	1			T3	2		T11	1		T104	3
auto[BaudRate1Mbps]	freqs[100]	170	1			T2	3		T8	2		T43	3
auto[BaudRate1p5Mbps]	freqs[25]	104	1			T9	4		T20	3		T260	2
auto[BaudRate1p5Mbps]	freqs[48]	33	1			T18	3		T188	2		T317	1
auto[BaudRate1p5Mbps]	freqs[50]	71	1			T3	4		T256	2		T104	1
auto[BaudRate1p5Mbps]	freqs[100]	174	1			T2	2		T43	1		T106	2

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded