Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.43	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	9	121	93.08

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	9	121	93.08	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	32222609	1			T1	8		T2	70		T3	80098
all_levels[1]	187639	1			T1	1		T2	2		T3	1527
all_levels[2]	2196	1			T6	1		T7	10		T9	1
all_levels[3]	938	1			T6	2		T7	4		T10	2
all_levels[4]	670	1			T1	2		T7	3		T10	3
all_levels[5]	536	1			T7	7		T10	1		T38	1
all_levels[6]	449	1			T6	1		T36	1		T39	3
all_levels[7]	332	1			T16	1		T15	2		T13	1
all_levels[8]	303	1			T10	2		T118	1		T15	2
all_levels[9]	272	1			T6	1		T38	2		T16	1
all_levels[10]	204	1			T36	1		T16	1		T13	1
all_levels[11]	149	1			T10	1		T38	1		T39	1
all_levels[12]	171	1			T10	1		T38	1		T39	2
all_levels[13]	129	1			T2	1		T7	1		T118	3
all_levels[14]	142	1			T1	1		T10	2		T16	3
all_levels[15]	111	1			T2	2		T38	1		T44	1
all_levels[16]	103	1			T43	1		T44	2		T129	1
all_levels[17]	95	1			T7	1		T36	1		T39	1
all_levels[18]	92	1			T38	1		T15	1		T43	1
all_levels[19]	75	1			T39	1		T130	1		T131	1
all_levels[20]	103	1			T9	1		T130	1		T21	1
all_levels[21]	70	1			T132	3		T21	1		T131	1
all_levels[22]	51	1			T38	1		T133	1		T134	3
all_levels[23]	63	1			T10	1		T39	2		T16	1
all_levels[24]	52	1			T43	1		T131	1		T135	1
all_levels[25]	56	1			T38	2		T39	1		T16	1
all_levels[26]	45	1			T39	1		T14	2		T131	1
all_levels[27]	51	1			T10	1		T136	1		T129	1
all_levels[28]	44	1			T1	1		T39	1		T137	1
all_levels[29]	40	1			T130	1		T51	1		T138	1
all_levels[30]	47	1			T38	1		T15	2		T139	1
all_levels[31]	27	1			T38	1		T16	1		T21	1
all_levels[32]	23	1			T16	1		T140	1		T141	1
all_levels[33]	28	1			T142	1		T131	1		T143	1
all_levels[34]	25	1			T144	1		T143	1		T139	1
all_levels[35]	16	1			T39	2		T142	1		T31	1
all_levels[36]	22	1			T145	2		T50	1		T146	1
all_levels[37]	21	1			T1	2		T15	1		T18	1
all_levels[38]	17	1			T9	1		T43	1		T131	1
all_levels[39]	15	1			T38	1		T147	1		T148	2
all_levels[40]	20	1			T38	1		T118	1		T143	1
all_levels[41]	11	1			T144	1		T149	1		T150	1
all_levels[42]	15	1			T151	1		T152	1		T153	1
all_levels[43]	24	1			T1	1		T136	1		T149	1
all_levels[44]	18	1			T43	1		T154	1		T55	1
all_levels[45]	21	1			T44	1		T14	2		T31	1
all_levels[46]	15	1			T43	1		T130	1		T155	1
all_levels[47]	22	1			T43	1		T50	1		T51	1
all_levels[48]	10	1			T149	2		T156	1		T157	2
all_levels[49]	14	1			T140	1		T158	1		T159	1
all_levels[50]	8	1			T16	1		T14	1		T160	1
all_levels[51]	9	1			T13	1		T161	1		T55	1
all_levels[52]	9	1			T15	2		T44	1		T14	1
all_levels[53]	10	1			T155	1		T162	1		T163	1
all_levels[54]	7	1			T164	1		T165	1		T166	1
all_levels[55]	7	1			T129	1		T167	1		T168	1
all_levels[56]	6	1			T149	1		T169	1		T170	2
all_levels[57]	9	1			T144	1		T171	1		T172	1
all_levels[58]	7	1			T69	2		T173	2		T146	1
all_levels[59]	4	1			T164	1		T174	1		T175	1
all_levels[60]	9	1			T114	1		T176	1		T177	3
all_levels[61]	5	1			T178	1		T179	1		T180	1
all_levels[62]	9	1			T13	1		T136	1		T181	2
all_levels[63]	12	1			T9	1		T15	1		T144	1
all_levels[64]	122	1			T12	3		T13	1		T14	2

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32413822

1

T1

11

T2

75

T3

81625

auto[1]

4612

1

T1

5

T4

1

T6

4

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	9	121	93.08	9

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[32]]	[auto[1]]	0	1	1
[all_levels[41]]	[auto[1]]	0	1	1
[all_levels[49]]	[auto[1]]	0	1	1
[all_levels[51] , all_levels[52]]	[auto[1]]	--	--	2
[all_levels[54]]	[auto[1]]	0	1	1
[all_levels[59]]	[auto[1]]	0	1	1
[all_levels[61]]	[auto[1]]	0	1	1
[all_levels[63]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	32218391	1			T1	5		T2	70		T3	80098
all_levels[0]	auto[1]	4218	1			T1	3		T4	1		T6	4
all_levels[1]	auto[0]	187578	1			T1	1		T2	2		T3	1527
all_levels[1]	auto[1]	61	1			T132	1		T182	1		T133	2
all_levels[2]	auto[0]	2167	1			T6	1		T7	10		T9	1
all_levels[2]	auto[1]	29	1			T118	1		T31	1		T183	2
all_levels[3]	auto[0]	918	1			T6	2		T7	4		T10	2
all_levels[3]	auto[1]	20	1			T184	1		T185	1		T186	1
all_levels[4]	auto[0]	640	1			T1	1		T7	3		T10	2
all_levels[4]	auto[1]	30	1			T1	1		T10	1		T109	3
all_levels[5]	auto[0]	511	1			T7	7		T10	1		T38	1
all_levels[5]	auto[1]	25	1			T187	1		T188	2		T161	4
all_levels[6]	auto[0]	435	1			T6	1		T36	1		T39	3
all_levels[6]	auto[1]	14	1			T50	1		T189	1		T190	4
all_levels[7]	auto[0]	318	1			T16	1		T15	2		T13	1
all_levels[7]	auto[1]	14	1			T191	1		T149	1		T192	2
all_levels[8]	auto[0]	292	1			T10	1		T118	1		T15	2
all_levels[8]	auto[1]	11	1			T10	1		T135	1		T193	3
all_levels[9]	auto[0]	262	1			T6	1		T38	1		T16	1
all_levels[9]	auto[1]	10	1			T38	1		T194	1		T195	1
all_levels[10]	auto[0]	199	1			T36	1		T16	1		T13	1
all_levels[10]	auto[1]	5	1			T196	2		T197	1		T198	1
all_levels[11]	auto[0]	141	1			T10	1		T38	1		T39	1
all_levels[11]	auto[1]	8	1			T199	1		T200	1		T201	2
all_levels[12]	auto[0]	160	1			T10	1		T38	1		T39	1
all_levels[12]	auto[1]	11	1			T39	1		T145	1		T202	1
all_levels[13]	auto[0]	122	1			T2	1		T7	1		T118	3
all_levels[13]	auto[1]	7	1			T188	3		T203	1		T204	1
all_levels[14]	auto[0]	135	1			T1	1		T10	2		T16	3
all_levels[14]	auto[1]	7	1			T204	2		T205	1		T186	1
all_levels[15]	auto[0]	107	1			T2	2		T38	1		T44	1
all_levels[15]	auto[1]	4	1			T206	1		T207	1		T208	1
all_levels[16]	auto[0]	97	1			T43	1		T44	2		T129	1
all_levels[16]	auto[1]	6	1			T209	1		T210	1		T211	2
all_levels[17]	auto[0]	89	1			T7	1		T36	1		T39	1
all_levels[17]	auto[1]	6	1			T212	2		T213	3		T214	1
all_levels[18]	auto[0]	86	1			T38	1		T15	1		T43	1
all_levels[18]	auto[1]	6	1			T183	1		T215	1		T216	2
all_levels[19]	auto[0]	73	1			T39	1		T130	1		T131	1
all_levels[19]	auto[1]	2	1			T217	1		T218	1		-	-
all_levels[20]	auto[0]	89	1			T9	1		T130	1		T21	1
all_levels[20]	auto[1]	14	1			T219	1		T179	1		T157	1
all_levels[21]	auto[0]	62	1			T132	1		T21	1		T131	1
all_levels[21]	auto[1]	8	1			T132	2		T144	1		T141	1
all_levels[22]	auto[0]	48	1			T38	1		T133	1		T134	2
all_levels[22]	auto[1]	3	1			T134	1		T135	1		T220	1
all_levels[23]	auto[0]	56	1			T10	1		T39	2		T16	1
all_levels[23]	auto[1]	7	1			T221	6		T222	1		-	-
all_levels[24]	auto[0]	50	1			T43	1		T131	1		T135	1
all_levels[24]	auto[1]	2	1			T208	1		T223	1		-	-
all_levels[25]	auto[0]	52	1			T38	2		T39	1		T16	1
all_levels[25]	auto[1]	4	1			T224	1		T225	1		T216	2
all_levels[26]	auto[0]	40	1			T39	1		T14	1		T131	1
all_levels[26]	auto[1]	5	1			T14	1		T51	2		T226	2
all_levels[27]	auto[0]	50	1			T10	1		T136	1		T129	1
all_levels[27]	auto[1]	1	1			T160	1		-	-		-	-
all_levels[28]	auto[0]	38	1			T1	1		T39	1		T137	1
all_levels[28]	auto[1]	6	1			T227	3		T228	1		T229	2
all_levels[29]	auto[0]	37	1			T130	1		T51	1		T138	1
all_levels[29]	auto[1]	3	1			T230	1		T231	1		T232	1
all_levels[30]	auto[0]	41	1			T38	1		T15	2		T139	1
all_levels[30]	auto[1]	6	1			T207	1		T233	2		T234	3
all_levels[31]	auto[0]	26	1			T38	1		T16	1		T21	1
all_levels[31]	auto[1]	1	1			T184	1		-	-		-	-
all_levels[32]	auto[0]	23	1			T16	1		T140	1		T141	1
all_levels[33]	auto[0]	26	1			T142	1		T131	1		T143	1
all_levels[33]	auto[1]	2	1			T235	1		T236	1		-	-
all_levels[34]	auto[0]	24	1			T144	1		T143	1		T139	1
all_levels[34]	auto[1]	1	1			T184	1		-	-		-	-
all_levels[35]	auto[0]	15	1			T39	1		T142	1		T31	1
all_levels[35]	auto[1]	1	1			T39	1		-	-		-	-
all_levels[36]	auto[0]	20	1			T145	1		T50	1		T146	1
all_levels[36]	auto[1]	2	1			T145	1		T237	1		-	-
all_levels[37]	auto[0]	18	1			T1	1		T15	1		T18	1
all_levels[37]	auto[1]	3	1			T1	1		T238	2		-	-
all_levels[38]	auto[0]	16	1			T9	1		T43	1		T131	1
all_levels[38]	auto[1]	1	1			T189	1		-	-		-	-
all_levels[39]	auto[0]	13	1			T38	1		T147	1		T148	2
all_levels[39]	auto[1]	2	1			T239	2		-	-		-	-
all_levels[40]	auto[0]	19	1			T38	1		T118	1		T143	1
all_levels[40]	auto[1]	1	1			T240	1		-	-		-	-
all_levels[41]	auto[0]	11	1			T144	1		T149	1		T150	1
all_levels[42]	auto[0]	12	1			T151	1		T152	1		T153	1
all_levels[42]	auto[1]	3	1			T241	3		-	-		-	-
all_levels[43]	auto[0]	19	1			T1	1		T136	1		T149	1
all_levels[43]	auto[1]	5	1			T177	3		T228	2		-	-
all_levels[44]	auto[0]	17	1			T43	1		T154	1		T55	1
all_levels[44]	auto[1]	1	1			T242	1		-	-		-	-
all_levels[45]	auto[0]	19	1			T44	1		T14	1		T31	1
all_levels[45]	auto[1]	2	1			T14	1		T137	1		-	-
all_levels[46]	auto[0]	14	1			T43	1		T130	1		T155	1
all_levels[46]	auto[1]	1	1			T243	1		-	-		-	-
all_levels[47]	auto[0]	20	1			T43	1		T50	1		T51	1
all_levels[47]	auto[1]	2	1			T244	2		-	-		-	-
all_levels[48]	auto[0]	9	1			T149	2		T156	1		T157	1
all_levels[48]	auto[1]	1	1			T157	1		-	-		-	-
all_levels[49]	auto[0]	14	1			T140	1		T158	1		T159	1
all_levels[50]	auto[0]	7	1			T16	1		T14	1		T160	1
all_levels[50]	auto[1]	1	1			T245	1		-	-		-	-
all_levels[51]	auto[0]	9	1			T13	1		T161	1		T55	1
all_levels[52]	auto[0]	9	1			T15	2		T44	1		T14	1
all_levels[53]	auto[0]	8	1			T155	1		T162	1		T163	1
all_levels[53]	auto[1]	2	1			T246	2		-	-		-	-
all_levels[54]	auto[0]	7	1			T164	1		T165	1		T166	1
all_levels[55]	auto[0]	6	1			T129	1		T167	1		T168	1
all_levels[55]	auto[1]	1	1			T247	1		-	-		-	-
all_levels[56]	auto[0]	5	1			T149	1		T169	1		T170	1
all_levels[56]	auto[1]	1	1			T170	1		-	-		-	-
all_levels[57]	auto[0]	7	1			T144	1		T171	1		T172	1
all_levels[57]	auto[1]	2	1			T209	1		T248	1		-	-
all_levels[58]	auto[0]	6	1			T69	2		T173	1		T146	1
all_levels[58]	auto[1]	1	1			T173	1		-	-		-	-
all_levels[59]	auto[0]	4	1			T164	1		T174	1		T175	1
all_levels[60]	auto[0]	7	1			T114	1		T176	1		T177	1
all_levels[60]	auto[1]	2	1			T177	2		-	-		-	-
all_levels[61]	auto[0]	5	1			T178	1		T179	1		T180	1
all_levels[62]	auto[0]	7	1			T13	1		T136	1		T181	1
all_levels[62]	auto[1]	2	1			T181	1		T249	1		-	-
all_levels[63]	auto[0]	12	1			T9	1		T15	1		T144	1
all_levels[64]	auto[0]	104	1			T12	1		T13	1		T14	2
all_levels[64]	auto[1]	18	1			T12	2		T250	1		T165	1