Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	113913	1			T1	8		T2	33		T3	71
all_pins[1]	113913	1			T1	8		T2	33		T3	71
all_pins[2]	113913	1			T1	8		T2	33		T3	71
all_pins[3]	113913	1			T1	8		T2	33		T3	71
all_pins[4]	113913	1			T1	8		T2	33		T3	71
all_pins[5]	113913	1			T1	8		T2	33		T3	71
all_pins[6]	113913	1			T1	8		T2	33		T3	71
all_pins[7]	113913	1			T1	8		T2	33		T3	71

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	884022	1			T1	50		T2	230		T3	541
values[0x1]	27282	1			T1	14		T2	34		T3	27
transitions[0x0=>0x1]	26223	1			T1	10		T2	34		T3	20
transitions[0x1=>0x0]	25799	1			T1	9		T2	33		T3	20

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	93007	1			T2	6		T3	64		T5	2
all_pins[0]	values[0x1]	20906	1			T1	8		T2	27		T3	7
all_pins[0]	transitions[0x0=>0x1]	20398	1			T1	4		T2	27		T3	6
all_pins[0]	transitions[0x1=>0x0]	923	1			T9	1		T12	7		T251	9
all_pins[1]	values[0x0]	112482	1			T1	4		T2	33		T3	70
all_pins[1]	values[0x1]	1431	1			T1	4		T3	1		T9	1
all_pins[1]	transitions[0x0=>0x1]	1312	1			T1	4		T9	1		T10	6
all_pins[1]	transitions[0x1=>0x0]	2464	1			T1	1		T2	7		T3	7
all_pins[2]	values[0x0]	111330	1			T1	7		T2	26		T3	63
all_pins[2]	values[0x1]	2583	1			T1	1		T2	7		T3	8
all_pins[2]	transitions[0x0=>0x1]	2524	1			T1	1		T2	7		T3	7
all_pins[2]	transitions[0x1=>0x0]	278	1			T12	2		T13	3		T18	2
all_pins[3]	values[0x0]	113576	1			T1	8		T2	33		T3	70
all_pins[3]	values[0x1]	337	1			T3	1		T12	4		T13	3
all_pins[3]	transitions[0x0=>0x1]	297	1			T3	1		T12	3		T13	3
all_pins[3]	transitions[0x1=>0x0]	486	1			T3	1		T12	3		T15	1
all_pins[4]	values[0x0]	113387	1			T1	8		T2	33		T3	70
all_pins[4]	values[0x1]	526	1			T3	1		T12	4		T15	1
all_pins[4]	transitions[0x0=>0x1]	446	1			T12	4		T15	1		T19	4
all_pins[4]	transitions[0x1=>0x0]	194	1			T3	4		T12	2		T18	2
all_pins[5]	values[0x0]	113639	1			T1	8		T2	33		T3	66
all_pins[5]	values[0x1]	274	1			T3	5		T12	2		T18	2
all_pins[5]	transitions[0x0=>0x1]	219	1			T3	2		T12	2		T18	2
all_pins[5]	transitions[0x1=>0x0]	824	1			T1	1		T3	1		T7	2
all_pins[6]	values[0x0]	113034	1			T1	7		T2	33		T3	67
all_pins[6]	values[0x1]	879	1			T1	1		T3	4		T7	2
all_pins[6]	transitions[0x0=>0x1]	831	1			T1	1		T3	4		T7	2
all_pins[6]	transitions[0x1=>0x0]	298	1			T12	3		T16	4		T15	7
all_pins[7]	values[0x0]	113567	1			T1	8		T2	33		T3	71
all_pins[7]	values[0x1]	346	1			T12	4		T16	4		T15	9
all_pins[7]	transitions[0x0=>0x1]	196	1			T12	2		T16	4		T15	8
all_pins[7]	transitions[0x1=>0x0]	20332	1			T1	7		T2	26		T3	7