Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7389005	1			T1	9		T2	33		T3	37134
all_levels[1]	1252753	1			T1	3		T2	1		T3	93
all_levels[2]	408164	1			T2	2		T3	95		T6	1
all_levels[3]	359559	1			T2	2		T3	90		T7	16
all_levels[4]	496324	1			T2	5		T3	106		T6	1
all_levels[5]	221937	1			T3	102		T7	8		T8	2
all_levels[6]	271722	1			T3	85		T6	1		T9	1764
all_levels[7]	486903	1			T2	3		T3	101		T7	1
all_levels[8]	374096	1			T3	103		T9	1751		T10	7
all_levels[9]	371788	1			T2	2		T3	92		T6	1
all_levels[10]	317272	1			T3	98		T8	1		T9	1947
all_levels[11]	236245	1			T1	1		T3	111		T9	1578
all_levels[12]	273465	1			T3	98		T7	81		T9	1733
all_levels[13]	292207	1			T3	95		T7	21		T9	2074
all_levels[14]	269269	1			T3	104		T7	1		T9	1777
all_levels[15]	258222	1			T2	1		T3	93		T7	7
all_levels[16]	778835	1			T2	2		T3	85		T9	2069
all_levels[17]	203349	1			T3	94		T7	3		T9	1909
all_levels[18]	217354	1			T2	1		T3	95		T7	58
all_levels[19]	261661	1			T2	2		T3	96		T9	1615
all_levels[20]	237469	1			T2	1		T3	84		T7	95
all_levels[21]	201458	1			T3	92		T7	5		T9	2219
all_levels[22]	286297	1			T3	86		T9	1614		T12	14
all_levels[23]	251894	1			T3	99		T6	8		T9	1464
all_levels[24]	228916	1			T3	104		T9	2138		T12	5
all_levels[25]	256952	1			T2	2		T3	91		T9	2179
all_levels[26]	279509	1			T3	91		T7	53		T9	1641
all_levels[27]	179537	1			T3	101		T8	1		T9	1841
all_levels[28]	196609	1			T3	105		T9	1875		T12	12
all_levels[29]	212311	1			T3	94		T9	1770		T11	1
all_levels[30]	178796	1			T3	103		T9	1675		T12	9
all_levels[31]	1046044	1			T2	2		T3	1241		T9	5279
all_levels[32]	14122132	1			T1	4		T2	17		T3	40365

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32413822

1

T1

11

T2

75

T3

81625

auto[1]

4232

1

T1

6

T2

1

T3

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	7386700	1			T1	5		T2	33		T3	37134
all_levels[0]	auto[1]	2305	1			T1	4		T4	1		T6	1
all_levels[1]	auto[0]	1252433	1			T1	2		T2	1		T3	93
all_levels[1]	auto[1]	320	1			T1	1		T9	1		T12	13
all_levels[2]	auto[0]	408120	1			T2	2		T3	95		T6	1
all_levels[2]	auto[1]	44	1			T11	2		T14	1		T188	2
all_levels[3]	auto[0]	359415	1			T2	2		T3	90		T7	16
all_levels[3]	auto[1]	144	1			T10	1		T11	1		T263	9
all_levels[4]	auto[0]	496294	1			T2	5		T3	106		T6	1
all_levels[4]	auto[1]	30	1			T14	1		T109	3		T321	2
all_levels[5]	auto[0]	221909	1			T3	102		T7	8		T8	1
all_levels[5]	auto[1]	28	1			T8	1		T161	1		T275	1
all_levels[6]	auto[0]	271695	1			T3	85		T6	1		T9	1764
all_levels[6]	auto[1]	27	1			T133	1		T292	2		T51	2
all_levels[7]	auto[0]	486773	1			T2	3		T3	101		T7	1
all_levels[7]	auto[1]	130	1			T38	2		T182	1		T29	1
all_levels[8]	auto[0]	374076	1			T3	103		T9	1751		T10	4
all_levels[8]	auto[1]	20	1			T10	3		T182	1		T250	1
all_levels[9]	auto[0]	371756	1			T2	2		T3	92		T6	1
all_levels[9]	auto[1]	32	1			T134	3		T204	2		T322	3
all_levels[10]	auto[0]	317253	1			T3	98		T8	1		T9	1947
all_levels[10]	auto[1]	19	1			T12	1		T235	1		T323	1
all_levels[11]	auto[0]	236222	1			T1	1		T3	111		T9	1578
all_levels[11]	auto[1]	23	1			T38	2		T135	1		T290	1
all_levels[12]	auto[0]	273432	1			T3	98		T7	81		T9	1733
all_levels[12]	auto[1]	33	1			T39	3		T187	1		T32	1
all_levels[13]	auto[0]	292184	1			T3	95		T7	21		T9	2074
all_levels[13]	auto[1]	23	1			T291	1		T196	2		T324	1
all_levels[14]	auto[0]	269243	1			T3	104		T7	1		T9	1777
all_levels[14]	auto[1]	26	1			T259	1		T48	1		T137	1
all_levels[15]	auto[0]	258037	1			T2	1		T3	93		T7	7
all_levels[15]	auto[1]	185	1			T8	1		T10	1		T13	1
all_levels[16]	auto[0]	778803	1			T2	2		T3	85		T9	2069
all_levels[16]	auto[1]	32	1			T187	1		T144	1		T183	1
all_levels[17]	auto[0]	203333	1			T3	94		T7	3		T9	1909
all_levels[17]	auto[1]	16	1			T206	1		T325	1		T307	1
all_levels[18]	auto[0]	217333	1			T2	1		T3	95		T7	58
all_levels[18]	auto[1]	21	1			T193	2		T326	1		T149	3
all_levels[19]	auto[0]	261634	1			T2	2		T3	96		T9	1615
all_levels[19]	auto[1]	27	1			T188	2		T124	1		T50	1
all_levels[20]	auto[0]	237433	1			T2	1		T3	84		T7	95
all_levels[20]	auto[1]	36	1			T38	1		T161	1		T259	1
all_levels[21]	auto[0]	201440	1			T3	92		T7	5		T9	2219
all_levels[21]	auto[1]	18	1			T327	1		T328	1		T113	1
all_levels[22]	auto[0]	286265	1			T3	86		T9	1614		T12	14
all_levels[22]	auto[1]	32	1			T305	2		T268	1		T295	1
all_levels[23]	auto[0]	251874	1			T3	99		T6	8		T9	1464
all_levels[23]	auto[1]	20	1			T292	2		T191	1		T147	2
all_levels[24]	auto[0]	228905	1			T3	104		T9	2138		T12	5
all_levels[24]	auto[1]	11	1			T190	1		T216	2		T329	1
all_levels[25]	auto[0]	256929	1			T2	2		T3	91		T9	2179
all_levels[25]	auto[1]	23	1			T12	1		T51	1		T250	1
all_levels[26]	auto[0]	279492	1			T3	91		T7	53		T9	1641
all_levels[26]	auto[1]	17	1			T15	1		T330	2		T321	1
all_levels[27]	auto[0]	179524	1			T3	101		T8	1		T9	1841
all_levels[27]	auto[1]	13	1			T187	2		T131	1		T144	1
all_levels[28]	auto[0]	196593	1			T3	105		T9	1875		T12	12
all_levels[28]	auto[1]	16	1			T118	2		T261	1		T50	1
all_levels[29]	auto[0]	212298	1			T3	94		T9	1770		T11	1
all_levels[29]	auto[1]	13	1			T33	1		T331	1		T332	1
all_levels[30]	auto[0]	178782	1			T3	103		T9	1675		T12	9
all_levels[30]	auto[1]	14	1			T182	3		T70	2		T333	1
all_levels[31]	auto[0]	1046023	1			T2	2		T3	1241		T9	5279
all_levels[31]	auto[1]	21	1			T212	2		T191	2		T325	1
all_levels[32]	auto[0]	14121619	1			T1	3		T2	16		T3	40364
all_levels[32]	auto[1]	513	1			T1	1		T2	1		T3	1