Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	848	1			T3	7		T12	14		T15	7
all_values[1]	848	1			T3	7		T12	14		T15	7
all_values[2]	848	1			T3	7		T12	14		T15	7
all_values[3]	848	1			T3	7		T12	14		T15	7
all_values[4]	848	1			T3	7		T12	14		T15	7
all_values[5]	848	1			T3	7		T12	14		T15	7
all_values[6]	848	1			T3	7		T12	14		T15	7
all_values[7]	848	1			T3	7		T12	14		T15	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3676

1

T3

34

T12

62

T15

26

auto[1]

3108

1

T3

22

T12

50

T15

30

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2531

1

T3

20

T12

45

T15

20

auto[1]

4253

1

T3

36

T12

67

T15

36

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4029

1

T3

36

T12

70

T15

32

auto[1]

2755

1

T3

20

T12

42

T15

24

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	4	44	91.67	4
Automatically Generated Cross Bins	48	4	44	91.67	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	264	1			T3	4		T12	4		T15	1
all_values[0]	auto[0]	auto[1]	auto[1]	253	1			T3	1		T12	6		T15	3
all_values[0]	auto[1]	auto[0]	auto[1]	188	1			T3	1		T12	4		T19	2
all_values[0]	auto[1]	auto[1]	auto[1]	143	1			T3	1		T15	3		T19	1
all_values[1]	auto[0]	auto[0]	auto[0]	257	1			T3	3		T12	5		T15	1
all_values[1]	auto[0]	auto[1]	auto[0]	236	1			T3	2		T12	4		T15	3
all_values[1]	auto[1]	auto[0]	auto[1]	192	1			T3	1		T12	5		T15	2
all_values[1]	auto[1]	auto[1]	auto[1]	163	1			T3	1		T15	1		T19	2
all_values[2]	auto[0]	auto[0]	auto[0]	192	1			T12	3		T19	1		T28	1
all_values[2]	auto[0]	auto[0]	auto[1]	90	1			T3	2		T12	2		T15	2
all_values[2]	auto[0]	auto[1]	auto[0]	155	1			T12	2		T19	3		T31	2
all_values[2]	auto[0]	auto[1]	auto[1]	76	1			T3	1		T12	3		T15	1
all_values[2]	auto[1]	auto[0]	auto[1]	192	1			T3	2		T12	2		T15	3
all_values[2]	auto[1]	auto[1]	auto[1]	143	1			T3	2		T12	2		T15	1
all_values[3]	auto[0]	auto[0]	auto[0]	195	1			T3	1		T12	1		T15	4
all_values[3]	auto[0]	auto[0]	auto[1]	91	1			T3	1		T12	3		T19	2
all_values[3]	auto[0]	auto[1]	auto[0]	153	1			T3	2		T12	3		T15	2
all_values[3]	auto[0]	auto[1]	auto[1]	76	1			T28	1		T29	3		T124	1
all_values[3]	auto[1]	auto[0]	auto[1]	192	1			T3	1		T12	6		T15	1
all_values[3]	auto[1]	auto[1]	auto[1]	141	1			T3	2		T12	1		T19	1
all_values[4]	auto[0]	auto[0]	auto[0]	186	1			T3	2		T12	3		T19	1
all_values[4]	auto[0]	auto[0]	auto[1]	69	1			T3	1		T12	2		T29	1
all_values[4]	auto[0]	auto[1]	auto[0]	167	1			T3	1		T15	2		T19	2
all_values[4]	auto[0]	auto[1]	auto[1]	75	1			T19	1		T28	1		T29	1
all_values[4]	auto[1]	auto[0]	auto[1]	199	1			T3	3		T12	5		T15	2
all_values[4]	auto[1]	auto[1]	auto[1]	152	1			T12	4		T15	3		T19	2
all_values[5]	auto[0]	auto[0]	auto[0]	171	1			T3	2		T12	4		T15	5
all_values[5]	auto[0]	auto[0]	auto[1]	81	1			T12	1		T19	1		T29	2
all_values[5]	auto[0]	auto[1]	auto[0]	142	1			T12	3		T15	1		T29	1
all_values[5]	auto[0]	auto[1]	auto[1]	94	1			T3	3		T28	1		T29	1
all_values[5]	auto[1]	auto[0]	auto[1]	192	1			T12	3		T15	1		T19	3
all_values[5]	auto[1]	auto[1]	auto[1]	168	1			T3	2		T12	3		T28	1
all_values[6]	auto[0]	auto[0]	auto[0]	169	1			T12	2		T28	1		T29	1
all_values[6]	auto[0]	auto[0]	auto[1]	78	1			T3	2		T12	3		T19	4
all_values[6]	auto[0]	auto[1]	auto[0]	157	1			T12	4		T15	2		T28	2
all_values[6]	auto[0]	auto[1]	auto[1]	79	1			T3	1		T12	1		T15	1
all_values[6]	auto[1]	auto[0]	auto[1]	212	1			T3	2		T12	1		T19	3
all_values[6]	auto[1]	auto[1]	auto[1]	153	1			T3	2		T12	3		T15	4
all_values[7]	auto[0]	auto[0]	auto[0]	190	1			T3	6		T12	1		T19	1
all_values[7]	auto[0]	auto[0]	auto[1]	100	1			T15	4		T19	2		T124	2
all_values[7]	auto[0]	auto[1]	auto[0]	161	1			T3	1		T12	10		T29	7
all_values[7]	auto[0]	auto[1]	auto[1]	72	1			T19	1		T28	1		T29	1
all_values[7]	auto[1]	auto[0]	auto[1]	176	1			T12	2		T28	1		T29	1
all_values[7]	auto[1]	auto[1]	auto[1]	149	1			T12	1		T15	3		T19	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal