Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.27	99.27	97.95	100.00		98.80	100.00	99.61

Total test records in report: 1315

T1260	/workspace/coverage/cover_reg_top/1.uart_intr_test.1938812488	Apr 28 12:55:21 PM PDT 24	Apr 28 12:55:22 PM PDT 24	12525604 ps
T1261	/workspace/coverage/cover_reg_top/25.uart_intr_test.1553683969	Apr 28 12:55:44 PM PDT 24	Apr 28 12:55:46 PM PDT 24	17271185 ps
T1262	/workspace/coverage/cover_reg_top/14.uart_tl_errors.3923844958	Apr 28 12:55:41 PM PDT 24	Apr 28 12:55:43 PM PDT 24	179810065 ps
T1263	/workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2145598103	Apr 28 12:55:43 PM PDT 24	Apr 28 12:55:44 PM PDT 24	64810531 ps
T1264	/workspace/coverage/cover_reg_top/27.uart_intr_test.2326742305	Apr 28 12:55:45 PM PDT 24	Apr 28 12:55:47 PM PDT 24	16287523 ps
T99	/workspace/coverage/cover_reg_top/17.uart_tl_intg_err.791548817	Apr 28 12:55:38 PM PDT 24	Apr 28 12:55:41 PM PDT 24	593110714 ps
T1265	/workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1408809696	Apr 28 12:55:26 PM PDT 24	Apr 28 12:55:27 PM PDT 24	70332115 ps
T1266	/workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.1528241822	Apr 28 12:55:24 PM PDT 24	Apr 28 12:55:25 PM PDT 24	43944870 ps
T1267	/workspace/coverage/cover_reg_top/12.uart_csr_rw.1003714409	Apr 28 12:55:33 PM PDT 24	Apr 28 12:55:34 PM PDT 24	68769455 ps
T1268	/workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.139712296	Apr 28 12:55:23 PM PDT 24	Apr 28 12:55:26 PM PDT 24	115726967 ps
T1269	/workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3605274426	Apr 28 12:55:24 PM PDT 24	Apr 28 12:55:27 PM PDT 24	93853490 ps
T1270	/workspace/coverage/cover_reg_top/16.uart_tl_intg_err.974452236	Apr 28 12:55:39 PM PDT 24	Apr 28 12:55:41 PM PDT 24	83620887 ps
T1271	/workspace/coverage/cover_reg_top/28.uart_intr_test.1534236579	Apr 28 12:55:42 PM PDT 24	Apr 28 12:55:43 PM PDT 24	92641223 ps
T1272	/workspace/coverage/cover_reg_top/0.uart_csr_rw.1216389920	Apr 28 12:55:22 PM PDT 24	Apr 28 12:55:23 PM PDT 24	94386027 ps
T1273	/workspace/coverage/cover_reg_top/4.uart_tl_errors.3779321110	Apr 28 12:55:24 PM PDT 24	Apr 28 12:55:27 PM PDT 24	371202991 ps
T1274	/workspace/coverage/cover_reg_top/30.uart_intr_test.315204664	Apr 28 12:55:43 PM PDT 24	Apr 28 12:55:45 PM PDT 24	34793070 ps
T1275	/workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.544817368	Apr 28 12:55:37 PM PDT 24	Apr 28 12:55:38 PM PDT 24	19168170 ps
T1276	/workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3482796185	Apr 28 12:55:29 PM PDT 24	Apr 28 12:55:30 PM PDT 24	28149421 ps
T1277	/workspace/coverage/cover_reg_top/15.uart_intr_test.1667292989	Apr 28 12:55:41 PM PDT 24	Apr 28 12:55:42 PM PDT 24	35978337 ps
T1278	/workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3774851754	Apr 28 12:55:33 PM PDT 24	Apr 28 12:55:35 PM PDT 24	61925055 ps
T1279	/workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.985522182	Apr 28 12:55:22 PM PDT 24	Apr 28 12:55:24 PM PDT 24	18651588 ps
T81	/workspace/coverage/cover_reg_top/16.uart_csr_rw.2945805883	Apr 28 12:55:38 PM PDT 24	Apr 28 12:55:39 PM PDT 24	31897120 ps
T127	/workspace/coverage/cover_reg_top/12.uart_tl_intg_err.1671718985	Apr 28 12:55:32 PM PDT 24	Apr 28 12:55:34 PM PDT 24	97929253 ps
T1280	/workspace/coverage/cover_reg_top/16.uart_tl_errors.3917391211	Apr 28 12:55:39 PM PDT 24	Apr 28 12:55:41 PM PDT 24	59640755 ps
T1281	/workspace/coverage/cover_reg_top/0.uart_intr_test.773514950	Apr 28 12:55:19 PM PDT 24	Apr 28 12:55:20 PM PDT 24	36610676 ps
T1282	/workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2249947585	Apr 28 12:55:19 PM PDT 24	Apr 28 12:55:21 PM PDT 24	43047464 ps
T1283	/workspace/coverage/cover_reg_top/38.uart_intr_test.2275186059	Apr 28 12:55:42 PM PDT 24	Apr 28 12:55:43 PM PDT 24	17402331 ps
T1284	/workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1004821258	Apr 28 12:55:39 PM PDT 24	Apr 28 12:55:41 PM PDT 24	36889706 ps
T74	/workspace/coverage/cover_reg_top/19.uart_csr_rw.361748685	Apr 28 12:55:44 PM PDT 24	Apr 28 12:55:45 PM PDT 24	19534924 ps
T1285	/workspace/coverage/cover_reg_top/2.uart_csr_rw.468012026	Apr 28 12:55:28 PM PDT 24	Apr 28 12:55:30 PM PDT 24	15120795 ps
T1286	/workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3136523703	Apr 28 12:55:33 PM PDT 24	Apr 28 12:55:34 PM PDT 24	183189007 ps
T1287	/workspace/coverage/cover_reg_top/9.uart_tl_intg_err.490008774	Apr 28 12:55:33 PM PDT 24	Apr 28 12:55:35 PM PDT 24	166977257 ps
T1288	/workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1300217525	Apr 28 12:55:25 PM PDT 24	Apr 28 12:55:27 PM PDT 24	50820522 ps
T1289	/workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3822684202	Apr 28 12:55:30 PM PDT 24	Apr 28 12:55:32 PM PDT 24	37547859 ps
T1290	/workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.531596903	Apr 28 12:55:32 PM PDT 24	Apr 28 12:55:34 PM PDT 24	21674471 ps
T1291	/workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1232827137	Apr 28 12:55:47 PM PDT 24	Apr 28 12:55:48 PM PDT 24	99193812 ps
T1292	/workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1200939377	Apr 28 12:55:33 PM PDT 24	Apr 28 12:55:35 PM PDT 24	34106324 ps
T1293	/workspace/coverage/cover_reg_top/41.uart_intr_test.1331465199	Apr 28 12:55:50 PM PDT 24	Apr 28 12:55:52 PM PDT 24	31699943 ps
T1294	/workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3972500962	Apr 28 12:55:43 PM PDT 24	Apr 28 12:55:45 PM PDT 24	113652681 ps
T1295	/workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1776743798	Apr 28 12:55:23 PM PDT 24	Apr 28 12:55:25 PM PDT 24	15286135 ps
T75	/workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2252624064	Apr 28 12:55:27 PM PDT 24	Apr 28 12:55:29 PM PDT 24	20253024 ps
T1296	/workspace/coverage/cover_reg_top/32.uart_intr_test.3822248928	Apr 28 12:55:45 PM PDT 24	Apr 28 12:55:46 PM PDT 24	11964793 ps
T76	/workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2771733664	Apr 28 12:55:29 PM PDT 24	Apr 28 12:55:31 PM PDT 24	118311892 ps
T1297	/workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.618666018	Apr 28 12:55:38 PM PDT 24	Apr 28 12:55:40 PM PDT 24	77470467 ps
T1298	/workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.57442048	Apr 28 12:55:25 PM PDT 24	Apr 28 12:55:26 PM PDT 24	73813306 ps
T1299	/workspace/coverage/cover_reg_top/8.uart_tl_errors.3441467154	Apr 28 12:55:32 PM PDT 24	Apr 28 12:55:34 PM PDT 24	84083268 ps
T1300	/workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3316019575	Apr 28 12:55:24 PM PDT 24	Apr 28 12:55:26 PM PDT 24	91391565 ps
T1301	/workspace/coverage/cover_reg_top/44.uart_intr_test.149956959	Apr 28 12:55:49 PM PDT 24	Apr 28 12:55:51 PM PDT 24	16364424 ps
T1302	/workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.415125507	Apr 28 12:55:38 PM PDT 24	Apr 28 12:55:39 PM PDT 24	29499035 ps
T1303	/workspace/coverage/cover_reg_top/47.uart_intr_test.526578053	Apr 28 12:55:49 PM PDT 24	Apr 28 12:55:51 PM PDT 24	11666355 ps
T1304	/workspace/coverage/cover_reg_top/29.uart_intr_test.538317179	Apr 28 12:55:46 PM PDT 24	Apr 28 12:55:47 PM PDT 24	26698947 ps
T1305	/workspace/coverage/cover_reg_top/46.uart_intr_test.2730095903	Apr 28 12:55:51 PM PDT 24	Apr 28 12:55:53 PM PDT 24	47785958 ps
T1306	/workspace/coverage/cover_reg_top/17.uart_tl_errors.4032972951	Apr 28 12:55:40 PM PDT 24	Apr 28 12:55:42 PM PDT 24	100560328 ps
T1307	/workspace/coverage/cover_reg_top/15.uart_csr_rw.3048575620	Apr 28 12:55:38 PM PDT 24	Apr 28 12:55:40 PM PDT 24	21679800 ps
T1308	/workspace/coverage/cover_reg_top/18.uart_csr_rw.2740736702	Apr 28 12:55:50 PM PDT 24	Apr 28 12:55:52 PM PDT 24	11438021 ps
T82	/workspace/coverage/cover_reg_top/1.uart_csr_rw.2194074704	Apr 28 12:55:22 PM PDT 24	Apr 28 12:55:23 PM PDT 24	65776016 ps
T100	/workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1717171450	Apr 28 12:55:27 PM PDT 24	Apr 28 12:55:29 PM PDT 24	76700565 ps
T1309	/workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.4290224781	Apr 28 12:55:42 PM PDT 24	Apr 28 12:55:43 PM PDT 24	91035545 ps
T1310	/workspace/coverage/cover_reg_top/4.uart_intr_test.809814890	Apr 28 12:55:23 PM PDT 24	Apr 28 12:55:25 PM PDT 24	138883100 ps
T77	/workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2439144242	Apr 28 12:55:26 PM PDT 24	Apr 28 12:55:28 PM PDT 24	172033448 ps
T1311	/workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3435335458	Apr 28 12:55:33 PM PDT 24	Apr 28 12:55:35 PM PDT 24	45109725 ps
T1312	/workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2972209491	Apr 28 12:55:28 PM PDT 24	Apr 28 12:55:30 PM PDT 24	150502421 ps
T1313	/workspace/coverage/cover_reg_top/45.uart_intr_test.2762495842	Apr 28 12:55:50 PM PDT 24	Apr 28 12:55:52 PM PDT 24	19954247 ps
T1314	/workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2800744973	Apr 28 12:55:19 PM PDT 24	Apr 28 12:55:21 PM PDT 24	57022803 ps
T1315	/workspace/coverage/cover_reg_top/14.uart_intr_test.3702941476	Apr 28 12:55:41 PM PDT 24	Apr 28 12:55:42 PM PDT 24	16513764 ps

Test location	/workspace/coverage/default/85.uart_stress_all_with_rand_reset.1753023394
Short name	T9
Test name
Test status
Simulation time	142984186260 ps
CPU time	880.97 seconds
Started	Apr 28 01:09:19 PM PDT 24
Finished	Apr 28 01:24:00 PM PDT 24
Peak memory	216868 kb
Host	smart-e2f9b269-f46c-463b-acff-99719f5de487
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753023394 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.1753023394
Directory	/workspace/85.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/89.uart_stress_all_with_rand_reset.525651798
Short name	T12
Test name
Test status
Simulation time	214156046548 ps
CPU time	605.76 seconds
Started	Apr 28 01:09:19 PM PDT 24
Finished	Apr 28 01:19:25 PM PDT 24
Peak memory	225208 kb
Host	smart-dcec5eb0-dcc8-4a89-afbe-836b4bd9dfb1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525651798 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.525651798
Directory	/workspace/89.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.uart_stress_all.3532022884
Short name	T155
Test name
Test status
Simulation time	281095007895 ps
CPU time	2343.92 seconds
Started	Apr 28 01:06:54 PM PDT 24
Finished	Apr 28 01:45:58 PM PDT 24
Peak memory	200340 kb
Host	smart-86713021-7883-4c9c-bd5c-4e64cead12f8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532022884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.3532022884
Directory	/workspace/28.uart_stress_all/latest

Test location	/workspace/coverage/default/28.uart_stress_all_with_rand_reset.2612826479
Short name	T21
Test name
Test status
Simulation time	305808055369 ps
CPU time	587.31 seconds
Started	Apr 28 01:06:53 PM PDT 24
Finished	Apr 28 01:16:41 PM PDT 24
Peak memory	228828 kb
Host	smart-1e415bc3-ed10-4bce-91ba-fd858fc22a38
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612826479 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.2612826479
Directory	/workspace/28.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.uart_stress_all.3070069699
Short name	T15
Test name
Test status
Simulation time	517242095090 ps
CPU time	349.66 seconds
Started	Apr 28 01:05:32 PM PDT 24
Finished	Apr 28 01:11:22 PM PDT 24
Peak memory	200460 kb
Host	smart-fa1e0ca4-862e-4649-89b9-81447f7f5f92
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070069699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.3070069699
Directory	/workspace/9.uart_stress_all/latest

Test location	/workspace/coverage/default/55.uart_stress_all_with_rand_reset.3441728432
Short name	T55
Test name
Test status
Simulation time	741387549786 ps
CPU time	2001.03 seconds
Started	Apr 28 01:08:55 PM PDT 24
Finished	Apr 28 01:42:17 PM PDT 24
Peak memory	233424 kb
Host	smart-81b20416-ac1f-44e5-9bc5-db8d203109e2
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441728432 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.3441728432
Directory	/workspace/55.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/30.uart_long_xfer_wo_dly.3268140534
Short name	T104
Test name
Test status
Simulation time	166697038110 ps
CPU time	933.58 seconds
Started	Apr 28 01:07:06 PM PDT 24
Finished	Apr 28 01:22:40 PM PDT 24
Peak memory	200248 kb
Host	smart-f6d00803-741c-47f9-92c7-a13ac98f9b66
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3268140534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.3268140534
Directory	/workspace/30.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/2.uart_sec_cm.227335635
Short name	T25
Test name
Test status
Simulation time	60182625 ps
CPU time	0.85 seconds
Started	Apr 28 01:05:13 PM PDT 24
Finished	Apr 28 01:05:15 PM PDT 24
Peak memory	218492 kb
Host	smart-986c598d-ed39-4cc1-823c-6e42cb650154
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227335635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.227335635
Directory	/workspace/2.uart_sec_cm/latest

Test location	/workspace/coverage/default/163.uart_fifo_reset.553314340
Short name	T203
Test name
Test status
Simulation time	282677275138 ps
CPU time	130.02 seconds
Started	Apr 28 01:10:03 PM PDT 24
Finished	Apr 28 01:12:14 PM PDT 24
Peak memory	200388 kb
Host	smart-d87a8988-36ba-40cf-a0e8-277c456d9454
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=553314340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.553314340
Directory	/workspace/163.uart_fifo_reset/latest

Test location	/workspace/coverage/default/48.uart_stress_all.872340328
Short name	T50
Test name
Test status
Simulation time	424765473296 ps
CPU time	616.35 seconds
Started	Apr 28 01:08:46 PM PDT 24
Finished	Apr 28 01:19:03 PM PDT 24
Peak memory	208772 kb
Host	smart-288eb2bd-7f92-4a0b-ae59-76f453eaed6a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872340328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.872340328
Directory	/workspace/48.uart_stress_all/latest

Test location	/workspace/coverage/default/3.uart_stress_all_with_rand_reset.1504942191
Short name	T154
Test name
Test status
Simulation time	147062571345 ps
CPU time	624.12 seconds
Started	Apr 28 01:05:22 PM PDT 24
Finished	Apr 28 01:15:47 PM PDT 24
Peak memory	225268 kb
Host	smart-1d7187ff-0c6d-4e04-989b-79dd8abf5e14
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504942191 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.1504942191
Directory	/workspace/3.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/57.uart_fifo_reset.3263956163
Short name	T131
Test name
Test status
Simulation time	78403313587 ps
CPU time	38.06 seconds
Started	Apr 28 01:08:56 PM PDT 24
Finished	Apr 28 01:09:35 PM PDT 24
Peak memory	200400 kb
Host	smart-9b33374c-d642-4000-90af-3682145316aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3263956163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.3263956163
Directory	/workspace/57.uart_fifo_reset/latest

Test location	/workspace/coverage/default/19.uart_stress_all_with_rand_reset.3411791771
Short name	T54
Test name
Test status
Simulation time	79169681916 ps
CPU time	1069.03 seconds
Started	Apr 28 01:06:13 PM PDT 24
Finished	Apr 28 01:24:03 PM PDT 24
Peak memory	216836 kb
Host	smart-fffefa68-1f99-4ed4-86f5-9d1d6f1bd01b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411791771 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.3411791771
Directory	/workspace/19.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/41.uart_stress_all_with_rand_reset.3673861848
Short name	T149
Test name
Test status
Simulation time	691034043723 ps
CPU time	785.93 seconds
Started	Apr 28 01:08:04 PM PDT 24
Finished	Apr 28 01:21:11 PM PDT 24
Peak memory	217012 kb
Host	smart-bdde2ef5-41be-48d3-9db1-6d88c2a7c4a1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673861848 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.3673861848
Directory	/workspace/41.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_tl_intg_err.454939454
Short name	T98
Test name
Test status
Simulation time	86867591 ps
CPU time	1.3 seconds
Started	Apr 28 12:55:28 PM PDT 24
Finished	Apr 28 12:55:30 PM PDT 24
Peak memory	199208 kb
Host	smart-d66e2244-c622-4a38-9302-3d1e589ce8f0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454939454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.454939454
Directory	/workspace/6.uart_tl_intg_err/latest

Test location	/workspace/coverage/default/39.uart_stress_all.3131103934
Short name	T18
Test name
Test status
Simulation time	195094194545 ps
CPU time	170.13 seconds
Started	Apr 28 01:08:08 PM PDT 24
Finished	Apr 28 01:11:00 PM PDT 24
Peak memory	200300 kb
Host	smart-b210997c-f701-4959-8876-125f5cb2dbb7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131103934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.3131103934
Directory	/workspace/39.uart_stress_all/latest

Test location	/workspace/coverage/default/18.uart_alert_test.3465029144
Short name	T24
Test name
Test status
Simulation time	10319344 ps
CPU time	0.54 seconds
Started	Apr 28 01:06:07 PM PDT 24
Finished	Apr 28 01:06:08 PM PDT 24
Peak memory	195816 kb
Host	smart-51bb084a-dc5a-45f5-b003-052fb2bbb137
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465029144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.3465029144
Directory	/workspace/18.uart_alert_test/latest

Test location	/workspace/coverage/default/153.uart_fifo_reset.131685231
Short name	T144
Test name
Test status
Simulation time	225774148339 ps
CPU time	76.51 seconds
Started	Apr 28 01:09:59 PM PDT 24
Finished	Apr 28 01:11:16 PM PDT 24
Peak memory	200312 kb
Host	smart-b7363212-8ed0-4bd3-8bfc-20528f30a61c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=131685231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.131685231
Directory	/workspace/153.uart_fifo_reset/latest

Test location	/workspace/coverage/default/17.uart_stress_all.2968627934
Short name	T165
Test name
Test status
Simulation time	304923848013 ps
CPU time	411.09 seconds
Started	Apr 28 01:06:03 PM PDT 24
Finished	Apr 28 01:12:55 PM PDT 24
Peak memory	200292 kb
Host	smart-383ecab4-b441-4e63-b43e-bc76a8d3b79d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968627934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.2968627934
Directory	/workspace/17.uart_stress_all/latest

Test location	/workspace/coverage/default/16.uart_rx_parity_err.2930761869
Short name	T142
Test name
Test status
Simulation time	90851048237 ps
CPU time	51.31 seconds
Started	Apr 28 01:05:54 PM PDT 24
Finished	Apr 28 01:06:46 PM PDT 24
Peak memory	200468 kb
Host	smart-0ded4a08-9ef4-4ca2-b65a-68d7b4cc5c88
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2930761869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.2930761869
Directory	/workspace/16.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/44.uart_fifo_full.3322818850
Short name	T265
Test name
Test status
Simulation time	126321210756 ps
CPU time	271.43 seconds
Started	Apr 28 01:08:19 PM PDT 24
Finished	Apr 28 01:12:51 PM PDT 24
Peak memory	200340 kb
Host	smart-fe313906-c8e5-4875-9d9e-4d0627d73244
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3322818850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.3322818850
Directory	/workspace/44.uart_fifo_full/latest

Test location	/workspace/coverage/default/2.uart_stress_all_with_rand_reset.1311121211
Short name	T125
Test name
Test status
Simulation time	141044213268 ps
CPU time	711.07 seconds
Started	Apr 28 01:05:12 PM PDT 24
Finished	Apr 28 01:17:05 PM PDT 24
Peak memory	225244 kb
Host	smart-894075eb-e6b0-4a3a-84a4-cac64e50d5b8
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311121211 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.1311121211
Directory	/workspace/2.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.4213141905
Short name	T73
Test name
Test status
Simulation time	84528338 ps
CPU time	0.59 seconds
Started	Apr 28 12:55:19 PM PDT 24
Finished	Apr 28 12:55:20 PM PDT 24
Peak memory	195644 kb
Host	smart-0d57ab7c-e904-426d-b7d2-71e2ec025970
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213141905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.4213141905
Directory	/workspace/0.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_csr_rw.1898859314
Short name	T85
Test name
Test status
Simulation time	25071612 ps
CPU time	0.62 seconds
Started	Apr 28 12:55:32 PM PDT 24
Finished	Apr 28 12:55:33 PM PDT 24
Peak memory	195668 kb
Host	smart-db749341-201d-4c52-8695-1c1ecbb326eb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898859314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.1898859314
Directory	/workspace/10.uart_csr_rw/latest

Test location	/workspace/coverage/default/38.uart_rx_parity_err.3595581209
Short name	T16
Test name
Test status
Simulation time	170295405848 ps
CPU time	202.24 seconds
Started	Apr 28 01:07:49 PM PDT 24
Finished	Apr 28 01:11:12 PM PDT 24
Peak memory	200432 kb
Host	smart-ce1e4db6-8988-4bb9-aafd-d39b9117baf4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3595581209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.3595581209
Directory	/workspace/38.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/237.uart_fifo_reset.1937251411
Short name	T147
Test name
Test status
Simulation time	179523417953 ps
CPU time	66.54 seconds
Started	Apr 28 01:10:44 PM PDT 24
Finished	Apr 28 01:11:51 PM PDT 24
Peak memory	200240 kb
Host	smart-50a5089c-e8d9-4c44-a721-7df6bff633b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1937251411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.1937251411
Directory	/workspace/237.uart_fifo_reset/latest

Test location	/workspace/coverage/default/258.uart_fifo_reset.3252285779
Short name	T178
Test name
Test status
Simulation time	130302759786 ps
CPU time	62.46 seconds
Started	Apr 28 01:10:53 PM PDT 24
Finished	Apr 28 01:11:57 PM PDT 24
Peak memory	200280 kb
Host	smart-1d034a9e-0876-47eb-a73c-bad9fde6fe02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3252285779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.3252285779
Directory	/workspace/258.uart_fifo_reset/latest

Test location	/workspace/coverage/default/29.uart_stress_all_with_rand_reset.1850315649
Short name	T32
Test name
Test status
Simulation time	60733587406 ps
CPU time	857.43 seconds
Started	Apr 28 01:07:03 PM PDT 24
Finished	Apr 28 01:21:21 PM PDT 24
Peak memory	216844 kb
Host	smart-778ace1d-c3b4-4aa4-afe1-590a4e7575d5
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850315649 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.1850315649
Directory	/workspace/29.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/178.uart_fifo_reset.89230402
Short name	T158
Test name
Test status
Simulation time	53378273573 ps
CPU time	31.78 seconds
Started	Apr 28 01:10:09 PM PDT 24
Finished	Apr 28 01:10:41 PM PDT 24
Peak memory	200292 kb
Host	smart-96717b88-6ea7-4f09-8414-22f87b1de565
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=89230402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.89230402
Directory	/workspace/178.uart_fifo_reset/latest

Test location	/workspace/coverage/default/27.uart_fifo_full.2553033825
Short name	T136
Test name
Test status
Simulation time	165839740208 ps
CPU time	88.69 seconds
Started	Apr 28 01:06:43 PM PDT 24
Finished	Apr 28 01:08:13 PM PDT 24
Peak memory	200232 kb
Host	smart-0c54babd-0429-42ce-8120-f38f335fb6c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2553033825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.2553033825
Directory	/workspace/27.uart_fifo_full/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_tl_intg_err.1671718985
Short name	T127
Test name
Test status
Simulation time	97929253 ps
CPU time	1.28 seconds
Started	Apr 28 12:55:32 PM PDT 24
Finished	Apr 28 12:55:34 PM PDT 24
Peak memory	199684 kb
Host	smart-d2155d17-2c15-478e-acae-447488255ba3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671718985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.1671718985
Directory	/workspace/12.uart_tl_intg_err/latest

Test location	/workspace/coverage/default/138.uart_fifo_reset.3093533281
Short name	T206
Test name
Test status
Simulation time	63905477840 ps
CPU time	103.49 seconds
Started	Apr 28 01:09:55 PM PDT 24
Finished	Apr 28 01:11:39 PM PDT 24
Peak memory	200220 kb
Host	smart-83be93ce-a6b0-4083-8c51-56bd5beaff9c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3093533281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.3093533281
Directory	/workspace/138.uart_fifo_reset/latest

Test location	/workspace/coverage/default/14.uart_perf.819214425
Short name	T47
Test name
Test status
Simulation time	9169590642 ps
CPU time	460.37 seconds
Started	Apr 28 01:05:40 PM PDT 24
Finished	Apr 28 01:13:21 PM PDT 24
Peak memory	200344 kb
Host	smart-582b0605-78ef-4c01-8b0c-04118e0ec66a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=819214425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.819214425
Directory	/workspace/14.uart_perf/latest

Test location	/workspace/coverage/default/34.uart_fifo_reset.3585519089
Short name	T173
Test name
Test status
Simulation time	63702221416 ps
CPU time	50.28 seconds
Started	Apr 28 01:07:20 PM PDT 24
Finished	Apr 28 01:08:11 PM PDT 24
Peak memory	200420 kb
Host	smart-8805e058-e70f-47ab-8c42-4a3fb1b933b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3585519089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.3585519089
Directory	/workspace/34.uart_fifo_reset/latest

Test location	/workspace/coverage/default/48.uart_fifo_reset.399280200
Short name	T11
Test name
Test status
Simulation time	53614184766 ps
CPU time	58.54 seconds
Started	Apr 28 01:08:42 PM PDT 24
Finished	Apr 28 01:09:41 PM PDT 24
Peak memory	200312 kb
Host	smart-2c2518b6-9597-4705-bef0-382683907fd3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=399280200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.399280200
Directory	/workspace/48.uart_fifo_reset/latest

Test location	/workspace/coverage/default/158.uart_fifo_reset.3014163170
Short name	T189
Test name
Test status
Simulation time	19632692826 ps
CPU time	42.98 seconds
Started	Apr 28 01:09:57 PM PDT 24
Finished	Apr 28 01:10:40 PM PDT 24
Peak memory	200420 kb
Host	smart-8e9cc594-ac2b-4318-b527-30782af7ac70
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3014163170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.3014163170
Directory	/workspace/158.uart_fifo_reset/latest

Test location	/workspace/coverage/default/172.uart_fifo_reset.776458483
Short name	T186
Test name
Test status
Simulation time	184350705170 ps
CPU time	423.08 seconds
Started	Apr 28 01:10:06 PM PDT 24
Finished	Apr 28 01:17:10 PM PDT 24
Peak memory	200396 kb
Host	smart-ed784157-65d3-466f-81d4-52c951142829
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=776458483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.776458483
Directory	/workspace/172.uart_fifo_reset/latest

Test location	/workspace/coverage/default/21.uart_noise_filter.2615495898
Short name	T293
Test name
Test status
Simulation time	74512537209 ps
CPU time	129.84 seconds
Started	Apr 28 01:06:18 PM PDT 24
Finished	Apr 28 01:08:28 PM PDT 24
Peak memory	199516 kb
Host	smart-49d0cbde-61cf-4c1e-b2a1-0b2a3f19838a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2615495898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.2615495898
Directory	/workspace/21.uart_noise_filter/latest

Test location	/workspace/coverage/default/21.uart_stress_all_with_rand_reset.1154455049
Short name	T676
Test name
Test status
Simulation time	379321645404 ps
CPU time	778.81 seconds
Started	Apr 28 01:06:17 PM PDT 24
Finished	Apr 28 01:19:17 PM PDT 24
Peak memory	216812 kb
Host	smart-6c0f7236-20b9-4862-a441-307dfba9b7fd
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154455049 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.1154455049
Directory	/workspace/21.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/54.uart_fifo_reset.4111769846
Short name	T177
Test name
Test status
Simulation time	184263386137 ps
CPU time	113.09 seconds
Started	Apr 28 01:08:56 PM PDT 24
Finished	Apr 28 01:10:49 PM PDT 24
Peak memory	200296 kb
Host	smart-eacdb975-701a-4f85-8f34-418357d102cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4111769846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.4111769846
Directory	/workspace/54.uart_fifo_reset/latest

Test location	/workspace/coverage/default/19.uart_stress_all.328767659
Short name	T124
Test name
Test status
Simulation time	142097919489 ps
CPU time	299.34 seconds
Started	Apr 28 01:06:14 PM PDT 24
Finished	Apr 28 01:11:14 PM PDT 24
Peak memory	200348 kb
Host	smart-d04e5b49-e141-4915-ab20-dffa36060f7e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328767659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.328767659
Directory	/workspace/19.uart_stress_all/latest

Test location	/workspace/coverage/default/198.uart_fifo_reset.1638688828
Short name	T38
Test name
Test status
Simulation time	134975705368 ps
CPU time	105.01 seconds
Started	Apr 28 01:10:18 PM PDT 24
Finished	Apr 28 01:12:03 PM PDT 24
Peak memory	200392 kb
Host	smart-2db4d775-ee51-4c73-9aac-67ce212074d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1638688828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.1638688828
Directory	/workspace/198.uart_fifo_reset/latest

Test location	/workspace/coverage/default/23.uart_stress_all_with_rand_reset.2436910160
Short name	T241
Test name
Test status
Simulation time	181718793321 ps
CPU time	309.15 seconds
Started	Apr 28 01:06:29 PM PDT 24
Finished	Apr 28 01:11:38 PM PDT 24
Peak memory	216864 kb
Host	smart-f89316c4-9d24-4823-b9ce-a0f68307d1ea
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436910160 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.2436910160
Directory	/workspace/23.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/26.uart_stress_all.716950739
Short name	T225
Test name
Test status
Simulation time	335798714187 ps
CPU time	256.37 seconds
Started	Apr 28 01:06:44 PM PDT 24
Finished	Apr 28 01:11:01 PM PDT 24
Peak memory	200320 kb
Host	smart-d6126f42-d731-4f7d-bb2c-59d16604dd4f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716950739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.716950739
Directory	/workspace/26.uart_stress_all/latest

Test location	/workspace/coverage/default/101.uart_fifo_reset.3208509800
Short name	T184
Test name
Test status
Simulation time	41135132788 ps
CPU time	62.84 seconds
Started	Apr 28 01:09:29 PM PDT 24
Finished	Apr 28 01:10:33 PM PDT 24
Peak memory	200436 kb
Host	smart-ef7c24e7-7e95-4a73-a4a1-fcc1abb686e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3208509800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3208509800
Directory	/workspace/101.uart_fifo_reset/latest

Test location	/workspace/coverage/default/111.uart_fifo_reset.688183021
Short name	T209
Test name
Test status
Simulation time	10883754187 ps
CPU time	20.3 seconds
Started	Apr 28 01:09:29 PM PDT 24
Finished	Apr 28 01:09:50 PM PDT 24
Peak memory	200440 kb
Host	smart-c7ae38c6-322e-4de0-9c2c-366930fba40e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=688183021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.688183021
Directory	/workspace/111.uart_fifo_reset/latest

Test location	/workspace/coverage/default/127.uart_fifo_reset.698439320
Short name	T39
Test name
Test status
Simulation time	78162378234 ps
CPU time	69.24 seconds
Started	Apr 28 01:09:40 PM PDT 24
Finished	Apr 28 01:10:50 PM PDT 24
Peak memory	200276 kb
Host	smart-386ef931-161f-47eb-b0f8-cabf4aebb5e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=698439320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.698439320
Directory	/workspace/127.uart_fifo_reset/latest

Test location	/workspace/coverage/default/137.uart_fifo_reset.4225808870
Short name	T14
Test name
Test status
Simulation time	67868689082 ps
CPU time	32.25 seconds
Started	Apr 28 01:09:54 PM PDT 24
Finished	Apr 28 01:10:27 PM PDT 24
Peak memory	200212 kb
Host	smart-8a31a088-d09b-4914-a0d0-c3404c3381b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4225808870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.4225808870
Directory	/workspace/137.uart_fifo_reset/latest

Test location	/workspace/coverage/default/146.uart_fifo_reset.3599661984
Short name	T232
Test name
Test status
Simulation time	122326257581 ps
CPU time	45.72 seconds
Started	Apr 28 01:09:57 PM PDT 24
Finished	Apr 28 01:10:43 PM PDT 24
Peak memory	200064 kb
Host	smart-67d1c83d-e7cd-476f-b2c9-5a30ce467c24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3599661984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.3599661984
Directory	/workspace/146.uart_fifo_reset/latest

Test location	/workspace/coverage/default/219.uart_fifo_reset.429154335
Short name	T134
Test name
Test status
Simulation time	35522673823 ps
CPU time	52.78 seconds
Started	Apr 28 01:10:32 PM PDT 24
Finished	Apr 28 01:11:25 PM PDT 24
Peak memory	200120 kb
Host	smart-f6dd371f-82cc-4f28-b3f0-efa937c43005
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=429154335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.429154335
Directory	/workspace/219.uart_fifo_reset/latest

Test location	/workspace/coverage/default/239.uart_fifo_reset.496458133
Short name	T291
Test name
Test status
Simulation time	50596977715 ps
CPU time	106.73 seconds
Started	Apr 28 01:10:45 PM PDT 24
Finished	Apr 28 01:12:33 PM PDT 24
Peak memory	200420 kb
Host	smart-5dd6dd7a-ced9-4574-a903-29b027e2488d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=496458133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.496458133
Directory	/workspace/239.uart_fifo_reset/latest

Test location	/workspace/coverage/default/24.uart_stress_all.1830267946
Short name	T198
Test name
Test status
Simulation time	108647417899 ps
CPU time	616.52 seconds
Started	Apr 28 01:06:33 PM PDT 24
Finished	Apr 28 01:16:50 PM PDT 24
Peak memory	200392 kb
Host	smart-cd9324f4-188b-4526-9492-d58e602398ba
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830267946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.1830267946
Directory	/workspace/24.uart_stress_all/latest

Test location	/workspace/coverage/default/25.uart_fifo_full.2078323106
Short name	T175
Test name
Test status
Simulation time	59555970082 ps
CPU time	56.62 seconds
Started	Apr 28 01:06:36 PM PDT 24
Finished	Apr 28 01:07:33 PM PDT 24
Peak memory	200348 kb
Host	smart-a1eff756-1a10-4eab-9ed5-6e662e69d18d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2078323106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.2078323106
Directory	/workspace/25.uart_fifo_full/latest

Test location	/workspace/coverage/default/277.uart_fifo_reset.193983321
Short name	T216
Test name
Test status
Simulation time	105211620664 ps
CPU time	51.71 seconds
Started	Apr 28 01:11:04 PM PDT 24
Finished	Apr 28 01:11:57 PM PDT 24
Peak memory	200308 kb
Host	smart-77bb34ae-56fb-4d97-95d9-e61d1afad601
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=193983321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.193983321
Directory	/workspace/277.uart_fifo_reset/latest

Test location	/workspace/coverage/default/30.uart_perf.1522452532
Short name	T417
Test name
Test status
Simulation time	33114914799 ps
CPU time	268.08 seconds
Started	Apr 28 01:07:07 PM PDT 24
Finished	Apr 28 01:11:36 PM PDT 24
Peak memory	200260 kb
Host	smart-760172c2-2f98-41fd-a310-bbc07dcaca20
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1522452532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.1522452532
Directory	/workspace/30.uart_perf/latest

Test location	/workspace/coverage/default/82.uart_stress_all_with_rand_reset.594554365
Short name	T218
Test name
Test status
Simulation time	250625612914 ps
CPU time	1207.68 seconds
Started	Apr 28 01:09:15 PM PDT 24
Finished	Apr 28 01:29:23 PM PDT 24
Peak memory	216820 kb
Host	smart-e7dfb220-147e-4a69-9cc7-99b2acdaf9da
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594554365 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.594554365
Directory	/workspace/82.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/0.uart_tx_rx.3402569003
Short name	T495
Test name
Test status
Simulation time	59062566400 ps
CPU time	468.31 seconds
Started	Apr 28 01:05:06 PM PDT 24
Finished	Apr 28 01:12:56 PM PDT 24
Peak memory	200388 kb
Host	smart-637d3a03-57f5-4025-a34b-c947e13a7cae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3402569003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.3402569003
Directory	/workspace/0.uart_tx_rx/latest

Test location	/workspace/coverage/default/114.uart_fifo_reset.3491202105
Short name	T221
Test name
Test status
Simulation time	27772872676 ps
CPU time	47.04 seconds
Started	Apr 28 01:09:31 PM PDT 24
Finished	Apr 28 01:10:18 PM PDT 24
Peak memory	200208 kb
Host	smart-a90a0ae9-00a1-4b20-832a-f23efe1f8082
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3491202105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.3491202105
Directory	/workspace/114.uart_fifo_reset/latest

Test location	/workspace/coverage/default/120.uart_fifo_reset.2663836256
Short name	T160
Test name
Test status
Simulation time	121135890984 ps
CPU time	168.8 seconds
Started	Apr 28 01:09:36 PM PDT 24
Finished	Apr 28 01:12:25 PM PDT 24
Peak memory	200392 kb
Host	smart-791c2b5d-0b68-4ebe-9720-adc3f90927b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2663836256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.2663836256
Directory	/workspace/120.uart_fifo_reset/latest

Test location	/workspace/coverage/default/135.uart_fifo_reset.1561645160
Short name	T233
Test name
Test status
Simulation time	123846988750 ps
CPU time	120.02 seconds
Started	Apr 28 01:09:54 PM PDT 24
Finished	Apr 28 01:11:54 PM PDT 24
Peak memory	200360 kb
Host	smart-9c326237-05f3-43aa-95d6-14820a1cf1b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1561645160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.1561645160
Directory	/workspace/135.uart_fifo_reset/latest

Test location	/workspace/coverage/default/154.uart_fifo_reset.1234222375
Short name	T697
Test name
Test status
Simulation time	69690302448 ps
CPU time	26.9 seconds
Started	Apr 28 01:09:56 PM PDT 24
Finished	Apr 28 01:10:23 PM PDT 24
Peak memory	200104 kb
Host	smart-8ceabad5-5a37-4547-9c47-2d041c11b606
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1234222375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.1234222375
Directory	/workspace/154.uart_fifo_reset/latest

Test location	/workspace/coverage/default/176.uart_fifo_reset.1112874836
Short name	T181
Test name
Test status
Simulation time	57797095600 ps
CPU time	23.04 seconds
Started	Apr 28 01:10:06 PM PDT 24
Finished	Apr 28 01:10:29 PM PDT 24
Peak memory	200432 kb
Host	smart-5c6495c2-27dc-4c56-a5c1-24ecc3301d91
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1112874836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.1112874836
Directory	/workspace/176.uart_fifo_reset/latest

Test location	/workspace/coverage/default/202.uart_fifo_reset.1041538215
Short name	T1
Test name
Test status
Simulation time	41093281692 ps
CPU time	36.35 seconds
Started	Apr 28 01:10:23 PM PDT 24
Finished	Apr 28 01:11:01 PM PDT 24
Peak memory	200428 kb
Host	smart-98362d12-093b-4a7f-88f0-c6b63c2d33f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1041538215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.1041538215
Directory	/workspace/202.uart_fifo_reset/latest

Test location	/workspace/coverage/default/207.uart_fifo_reset.2462442631
Short name	T245
Test name
Test status
Simulation time	385359056536 ps
CPU time	44.99 seconds
Started	Apr 28 01:10:25 PM PDT 24
Finished	Apr 28 01:11:10 PM PDT 24
Peak memory	200304 kb
Host	smart-c4293d78-3879-48f0-8291-16228956faa2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2462442631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2462442631
Directory	/workspace/207.uart_fifo_reset/latest

Test location	/workspace/coverage/default/21.uart_stress_all.554996535
Short name	T247
Test name
Test status
Simulation time	277156448265 ps
CPU time	264.03 seconds
Started	Apr 28 01:06:22 PM PDT 24
Finished	Apr 28 01:10:47 PM PDT 24
Peak memory	200620 kb
Host	smart-e0f40edc-8f0c-4c50-9c04-0c1fdb4064f6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554996535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.554996535
Directory	/workspace/21.uart_stress_all/latest

Test location	/workspace/coverage/default/210.uart_fifo_reset.1658888757
Short name	T239
Test name
Test status
Simulation time	11075293608 ps
CPU time	10.74 seconds
Started	Apr 28 01:10:23 PM PDT 24
Finished	Apr 28 01:10:35 PM PDT 24
Peak memory	200244 kb
Host	smart-3a5da6f8-adb1-4ad4-841e-602e29987de3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1658888757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.1658888757
Directory	/workspace/210.uart_fifo_reset/latest

Test location	/workspace/coverage/default/216.uart_fifo_reset.3884724066
Short name	T208
Test name
Test status
Simulation time	76755858309 ps
CPU time	51.96 seconds
Started	Apr 28 01:10:29 PM PDT 24
Finished	Apr 28 01:11:22 PM PDT 24
Peak memory	200372 kb
Host	smart-e71c62ee-4995-45fe-b76c-7733c82c7d09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3884724066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.3884724066
Directory	/workspace/216.uart_fifo_reset/latest

Test location	/workspace/coverage/default/222.uart_fifo_reset.958382459
Short name	T235
Test name
Test status
Simulation time	41338974551 ps
CPU time	92.8 seconds
Started	Apr 28 01:10:33 PM PDT 24
Finished	Apr 28 01:12:06 PM PDT 24
Peak memory	200368 kb
Host	smart-e91d0882-e5a6-43f1-88e6-a996f6b1d871
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=958382459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.958382459
Directory	/workspace/222.uart_fifo_reset/latest

Test location	/workspace/coverage/default/246.uart_fifo_reset.2681377173
Short name	T145
Test name
Test status
Simulation time	71953025104 ps
CPU time	47.56 seconds
Started	Apr 28 01:10:47 PM PDT 24
Finished	Apr 28 01:11:35 PM PDT 24
Peak memory	200408 kb
Host	smart-bca3e7a3-f892-4be8-8d4e-907a2b31cc35
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2681377173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.2681377173
Directory	/workspace/246.uart_fifo_reset/latest

Test location	/workspace/coverage/default/250.uart_fifo_reset.2061923596
Short name	T242
Test name
Test status
Simulation time	99441297151 ps
CPU time	271.21 seconds
Started	Apr 28 01:10:47 PM PDT 24
Finished	Apr 28 01:15:19 PM PDT 24
Peak memory	200348 kb
Host	smart-4a2ddee4-f3a8-447a-ba01-953b7d98f8f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2061923596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2061923596
Directory	/workspace/250.uart_fifo_reset/latest

Test location	/workspace/coverage/default/261.uart_fifo_reset.726563739
Short name	T229
Test name
Test status
Simulation time	239093073863 ps
CPU time	100.34 seconds
Started	Apr 28 01:10:53 PM PDT 24
Finished	Apr 28 01:12:35 PM PDT 24
Peak memory	200380 kb
Host	smart-d5caf2a4-7810-4e47-bd4c-8c57b6ef7945
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=726563739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.726563739
Directory	/workspace/261.uart_fifo_reset/latest

Test location	/workspace/coverage/default/284.uart_fifo_reset.2196143782
Short name	T157
Test name
Test status
Simulation time	21826048501 ps
CPU time	21.04 seconds
Started	Apr 28 01:11:04 PM PDT 24
Finished	Apr 28 01:11:26 PM PDT 24
Peak memory	200392 kb
Host	smart-8fe6dd16-50ec-4020-8a27-f3a9e95f107e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2196143782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.2196143782
Directory	/workspace/284.uart_fifo_reset/latest

Test location	/workspace/coverage/default/295.uart_fifo_reset.827633436
Short name	T240
Test name
Test status
Simulation time	27719420792 ps
CPU time	47 seconds
Started	Apr 28 01:11:11 PM PDT 24
Finished	Apr 28 01:11:58 PM PDT 24
Peak memory	200260 kb
Host	smart-3a08bc68-cdbc-49f1-aee6-888d4df29e08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=827633436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.827633436
Directory	/workspace/295.uart_fifo_reset/latest

Test location	/workspace/coverage/default/34.uart_stress_all.642093883
Short name	T213
Test name
Test status
Simulation time	42653431126 ps
CPU time	87.13 seconds
Started	Apr 28 01:07:26 PM PDT 24
Finished	Apr 28 01:08:53 PM PDT 24
Peak memory	200340 kb
Host	smart-aa361129-a987-43a5-ae53-ac3848ecbbef
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642093883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.642093883
Directory	/workspace/34.uart_stress_all/latest

Test location	/workspace/coverage/default/41.uart_fifo_reset.1473124252
Short name	T244
Test name
Test status
Simulation time	128638050882 ps
CPU time	13.25 seconds
Started	Apr 28 01:08:02 PM PDT 24
Finished	Apr 28 01:08:16 PM PDT 24
Peak memory	200224 kb
Host	smart-8ac96023-30f5-40f2-a25b-2c2553eb46e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1473124252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.1473124252
Directory	/workspace/41.uart_fifo_reset/latest

Test location	/workspace/coverage/default/58.uart_fifo_reset.2812075642
Short name	T243
Test name
Test status
Simulation time	105626593836 ps
CPU time	46.25 seconds
Started	Apr 28 01:09:05 PM PDT 24
Finished	Apr 28 01:09:51 PM PDT 24
Peak memory	200388 kb
Host	smart-31a67ce0-0d3a-4fff-afba-f142d6a92e2b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2812075642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.2812075642
Directory	/workspace/58.uart_fifo_reset/latest

Test location	/workspace/coverage/default/69.uart_stress_all_with_rand_reset.1508553309
Short name	T170
Test name
Test status
Simulation time	131554044731 ps
CPU time	421.65 seconds
Started	Apr 28 01:09:14 PM PDT 24
Finished	Apr 28 01:16:16 PM PDT 24
Peak memory	216732 kb
Host	smart-38e55140-8122-48e2-8043-7073de35f373
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508553309 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.1508553309
Directory	/workspace/69.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/8.uart_stress_all.3738942171
Short name	T246
Test name
Test status
Simulation time	233084227075 ps
CPU time	112.3 seconds
Started	Apr 28 01:05:28 PM PDT 24
Finished	Apr 28 01:07:21 PM PDT 24
Peak memory	216340 kb
Host	smart-e64bad87-3fe4-41b9-834b-799cbcef26d7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738942171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.3738942171
Directory	/workspace/8.uart_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3531415961
Short name	T1188
Test name
Test status
Simulation time	32154630 ps
CPU time	0.82 seconds
Started	Apr 28 12:55:22 PM PDT 24
Finished	Apr 28 12:55:23 PM PDT 24
Peak memory	196772 kb
Host	smart-79e43e08-2091-4039-9f93-5b9dd11ab6f9
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531415961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.3531415961
Directory	/workspace/0.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2485601945
Short name	T1207
Test name
Test status
Simulation time	2554040928 ps
CPU time	1.54 seconds
Started	Apr 28 12:55:22 PM PDT 24
Finished	Apr 28 12:55:24 PM PDT 24
Peak memory	198420 kb
Host	smart-c734fd69-0249-4306-95ee-3105611a0029
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485601945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.2485601945
Directory	/workspace/0.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2897699360
Short name	T1208
Test name
Test status
Simulation time	53142338 ps
CPU time	0.66 seconds
Started	Apr 28 12:55:24 PM PDT 24
Finished	Apr 28 12:55:25 PM PDT 24
Peak memory	198212 kb
Host	smart-4ba591df-3891-49fc-bafb-398f5a30f45a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897699360 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.2897699360
Directory	/workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_rw.1216389920
Short name	T1272
Test name
Test status
Simulation time	94386027 ps
CPU time	0.56 seconds
Started	Apr 28 12:55:22 PM PDT 24
Finished	Apr 28 12:55:23 PM PDT 24
Peak memory	195700 kb
Host	smart-a2b197de-e478-4b72-bf31-fb2393e607bf
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216389920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.1216389920
Directory	/workspace/0.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_intr_test.773514950
Short name	T1281
Test name
Test status
Simulation time	36610676 ps
CPU time	0.57 seconds
Started	Apr 28 12:55:19 PM PDT 24
Finished	Apr 28 12:55:20 PM PDT 24
Peak memory	194764 kb
Host	smart-3cb37087-272f-4c30-a9ef-d7df6ea32c43
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773514950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.773514950
Directory	/workspace/0.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2800744973
Short name	T1314
Test name
Test status
Simulation time	57022803 ps
CPU time	0.73 seconds
Started	Apr 28 12:55:19 PM PDT 24
Finished	Apr 28 12:55:21 PM PDT 24
Peak memory	197252 kb
Host	smart-76e3f8e1-c898-4893-9152-6e3af6f5712b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800744973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr _outstanding.2800744973
Directory	/workspace/0.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_tl_errors.3262071616
Short name	T1184
Test name
Test status
Simulation time	35817309 ps
CPU time	1.06 seconds
Started	Apr 28 12:55:18 PM PDT 24
Finished	Apr 28 12:55:20 PM PDT 24
Peak memory	200080 kb
Host	smart-0fa391a3-0e33-4117-b0de-1b2e87d45a12
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262071616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.3262071616
Directory	/workspace/0.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2249947585
Short name	T1282
Test name
Test status
Simulation time	43047464 ps
CPU time	0.96 seconds
Started	Apr 28 12:55:19 PM PDT 24
Finished	Apr 28 12:55:21 PM PDT 24
Peak memory	199256 kb
Host	smart-9aaebdc6-e6f0-44f5-a689-d285b1f02579
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249947585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2249947585
Directory	/workspace/0.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2771733664
Short name	T76
Test name
Test status
Simulation time	118311892 ps
CPU time	0.8 seconds
Started	Apr 28 12:55:29 PM PDT 24
Finished	Apr 28 12:55:31 PM PDT 24
Peak memory	196628 kb
Host	smart-29da0f30-2877-40e6-80f0-e1bcfc32dc9e
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771733664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.2771733664
Directory	/workspace/1.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.799893403
Short name	T1211
Test name
Test status
Simulation time	861840668 ps
CPU time	2.59 seconds
Started	Apr 28 12:55:24 PM PDT 24
Finished	Apr 28 12:55:28 PM PDT 24
Peak memory	198064 kb
Host	smart-befbbecd-6f1e-4e57-8419-2e8775792355
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799893403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.799893403
Directory	/workspace/1.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.722116353
Short name	T1247
Test name
Test status
Simulation time	40814816 ps
CPU time	0.63 seconds
Started	Apr 28 12:55:24 PM PDT 24
Finished	Apr 28 12:55:25 PM PDT 24
Peak memory	195712 kb
Host	smart-3eb22a10-0cb9-4690-8b9f-c3e052e01628
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722116353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.722116353
Directory	/workspace/1.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1366332573
Short name	T1183
Test name
Test status
Simulation time	99630377 ps
CPU time	1.11 seconds
Started	Apr 28 12:55:23 PM PDT 24
Finished	Apr 28 12:55:25 PM PDT 24
Peak memory	200276 kb
Host	smart-8396e01e-42e7-4894-af3e-e6140a8a1e2b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366332573 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.1366332573
Directory	/workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_rw.2194074704
Short name	T82
Test name
Test status
Simulation time	65776016 ps
CPU time	0.57 seconds
Started	Apr 28 12:55:22 PM PDT 24
Finished	Apr 28 12:55:23 PM PDT 24
Peak memory	195696 kb
Host	smart-ddd8ce16-a519-4c5c-bfe8-db937dfc8e02
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194074704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.2194074704
Directory	/workspace/1.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_intr_test.1938812488
Short name	T1260
Test name
Test status
Simulation time	12525604 ps
CPU time	0.56 seconds
Started	Apr 28 12:55:21 PM PDT 24
Finished	Apr 28 12:55:22 PM PDT 24
Peak memory	194544 kb
Host	smart-07bfbc02-2fb3-4020-b1f3-3d906b127d10
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938812488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.1938812488
Directory	/workspace/1.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.657785537
Short name	T1250
Test name
Test status
Simulation time	67489062 ps
CPU time	0.66 seconds
Started	Apr 28 12:55:25 PM PDT 24
Finished	Apr 28 12:55:26 PM PDT 24
Peak memory	196300 kb
Host	smart-441f63bd-35cc-401d-957b-cb33acb01f70
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657785537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr_ outstanding.657785537
Directory	/workspace/1.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_tl_errors.2019359291
Short name	T1244
Test name
Test status
Simulation time	22483340 ps
CPU time	1.04 seconds
Started	Apr 28 12:55:22 PM PDT 24
Finished	Apr 28 12:55:24 PM PDT 24
Peak memory	200356 kb
Host	smart-19fad9d7-7b3b-454f-993c-0e480be1f5d8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019359291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.2019359291
Directory	/workspace/1.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_tl_intg_err.604550130
Short name	T126
Test name
Test status
Simulation time	107617237 ps
CPU time	1.3 seconds
Started	Apr 28 12:55:21 PM PDT 24
Finished	Apr 28 12:55:24 PM PDT 24
Peak memory	199672 kb
Host	smart-d48f49a6-6762-4611-89a5-0a09492b51a3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604550130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.604550130
Directory	/workspace/1.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1200939377
Short name	T1292
Test name
Test status
Simulation time	34106324 ps
CPU time	0.72 seconds
Started	Apr 28 12:55:33 PM PDT 24
Finished	Apr 28 12:55:35 PM PDT 24
Peak memory	198164 kb
Host	smart-bfb8d11b-d5bd-41e7-bd5b-71a93d0dc8ef
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200939377 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.1200939377
Directory	/workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_intr_test.821431570
Short name	T1197
Test name
Test status
Simulation time	15423364 ps
CPU time	0.57 seconds
Started	Apr 28 12:55:32 PM PDT 24
Finished	Apr 28 12:55:34 PM PDT 24
Peak memory	194632 kb
Host	smart-59cae531-d1ab-484a-9de4-72aee753bfe2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821431570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.821431570
Directory	/workspace/10.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3435335458
Short name	T1311
Test name
Test status
Simulation time	45109725 ps
CPU time	0.67 seconds
Started	Apr 28 12:55:33 PM PDT 24
Finished	Apr 28 12:55:35 PM PDT 24
Peak memory	195776 kb
Host	smart-ae015312-a253-4efc-b16c-9f99fac40e4e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435335458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs r_outstanding.3435335458
Directory	/workspace/10.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_tl_errors.2641436763
Short name	T1221
Test name
Test status
Simulation time	73680266 ps
CPU time	1.01 seconds
Started	Apr 28 12:55:32 PM PDT 24
Finished	Apr 28 12:55:34 PM PDT 24
Peak memory	200208 kb
Host	smart-0c9bb8b1-8a94-43c2-a3f9-48499c61674c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641436763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.2641436763
Directory	/workspace/10.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2794036222
Short name	T1245
Test name
Test status
Simulation time	94204403 ps
CPU time	0.93 seconds
Started	Apr 28 12:55:34 PM PDT 24
Finished	Apr 28 12:55:36 PM PDT 24
Peak memory	199152 kb
Host	smart-b14becd4-e0db-489c-ac1d-31f3ff4f40d8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794036222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.2794036222
Directory	/workspace/10.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.531596903
Short name	T1290
Test name
Test status
Simulation time	21674471 ps
CPU time	0.98 seconds
Started	Apr 28 12:55:32 PM PDT 24
Finished	Apr 28 12:55:34 PM PDT 24
Peak memory	200180 kb
Host	smart-9d00e511-4886-43f9-b839-1244ef3e2ab2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531596903 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.531596903
Directory	/workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_csr_rw.1739231935
Short name	T72
Test name
Test status
Simulation time	13134563 ps
CPU time	0.59 seconds
Started	Apr 28 12:55:36 PM PDT 24
Finished	Apr 28 12:55:37 PM PDT 24
Peak memory	195704 kb
Host	smart-30212273-6978-454c-9341-808cd7f6737e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739231935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.1739231935
Directory	/workspace/11.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_intr_test.1465548995
Short name	T1185
Test name
Test status
Simulation time	25939238 ps
CPU time	0.64 seconds
Started	Apr 28 12:55:35 PM PDT 24
Finished	Apr 28 12:55:36 PM PDT 24
Peak memory	194680 kb
Host	smart-1b54e90d-b6b7-42bc-8190-1e4fe0ee33fb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465548995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.1465548995
Directory	/workspace/11.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3773000464
Short name	T1251
Test name
Test status
Simulation time	236526154 ps
CPU time	0.69 seconds
Started	Apr 28 12:55:32 PM PDT 24
Finished	Apr 28 12:55:34 PM PDT 24
Peak memory	195260 kb
Host	smart-8da34a53-30df-4ac7-9d66-9beab835bd3b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773000464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs r_outstanding.3773000464
Directory	/workspace/11.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_tl_errors.3592762624
Short name	T1187
Test name
Test status
Simulation time	52229088 ps
CPU time	1.18 seconds
Started	Apr 28 12:55:32 PM PDT 24
Finished	Apr 28 12:55:34 PM PDT 24
Peak memory	200288 kb
Host	smart-5192f0b0-9169-44e4-b503-cb74cd72b0ed
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592762624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3592762624
Directory	/workspace/11.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3136523703
Short name	T1286
Test name
Test status
Simulation time	183189007 ps
CPU time	0.93 seconds
Started	Apr 28 12:55:33 PM PDT 24
Finished	Apr 28 12:55:34 PM PDT 24
Peak memory	199152 kb
Host	smart-4ce2525a-71d4-465e-b63d-057a7e4732a5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136523703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.3136523703
Directory	/workspace/11.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2275529180
Short name	T1219
Test name
Test status
Simulation time	33016577 ps
CPU time	1.56 seconds
Started	Apr 28 12:55:42 PM PDT 24
Finished	Apr 28 12:55:44 PM PDT 24
Peak memory	200164 kb
Host	smart-6824379d-6ade-49e6-ad50-12e6eba29c97
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275529180 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.2275529180
Directory	/workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_csr_rw.1003714409
Short name	T1267
Test name
Test status
Simulation time	68769455 ps
CPU time	0.59 seconds
Started	Apr 28 12:55:33 PM PDT 24
Finished	Apr 28 12:55:34 PM PDT 24
Peak memory	195944 kb
Host	smart-d753f478-a9b1-4daf-ab60-6c89f205a386
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003714409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.1003714409
Directory	/workspace/12.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_intr_test.715762438
Short name	T1224
Test name
Test status
Simulation time	32137796 ps
CPU time	0.55 seconds
Started	Apr 28 12:55:36 PM PDT 24
Finished	Apr 28 12:55:37 PM PDT 24
Peak memory	194572 kb
Host	smart-e710ef13-576f-4f5f-b886-a2a1d6b13674
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715762438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.715762438
Directory	/workspace/12.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.4285638773
Short name	T1252
Test name
Test status
Simulation time	21045582 ps
CPU time	0.69 seconds
Started	Apr 28 12:55:33 PM PDT 24
Finished	Apr 28 12:55:34 PM PDT 24
Peak memory	195864 kb
Host	smart-ab40adc6-3a63-48db-ada7-83333c99a2ac
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285638773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs r_outstanding.4285638773
Directory	/workspace/12.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_tl_errors.4054455305
Short name	T1248
Test name
Test status
Simulation time	109831444 ps
CPU time	2.12 seconds
Started	Apr 28 12:55:34 PM PDT 24
Finished	Apr 28 12:55:37 PM PDT 24
Peak memory	200412 kb
Host	smart-a6f5d29e-957a-4f51-9196-2417ada70b51
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054455305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.4054455305
Directory	/workspace/12.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.594835262
Short name	T1226
Test name
Test status
Simulation time	28359816 ps
CPU time	0.8 seconds
Started	Apr 28 12:55:42 PM PDT 24
Finished	Apr 28 12:55:44 PM PDT 24
Peak memory	199364 kb
Host	smart-e4270f12-07fd-4027-b64e-27a75028fe62
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594835262 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.594835262
Directory	/workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_csr_rw.2400133534
Short name	T78
Test name
Test status
Simulation time	27751728 ps
CPU time	0.61 seconds
Started	Apr 28 12:55:41 PM PDT 24
Finished	Apr 28 12:55:42 PM PDT 24
Peak memory	195628 kb
Host	smart-ac3bf391-2034-4ef9-8f2d-bc29b8bd4aa2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400133534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.2400133534
Directory	/workspace/13.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_intr_test.3550871208
Short name	T1243
Test name
Test status
Simulation time	13189257 ps
CPU time	0.59 seconds
Started	Apr 28 12:55:43 PM PDT 24
Finished	Apr 28 12:55:45 PM PDT 24
Peak memory	194780 kb
Host	smart-27666a75-b648-4c4e-be4d-1aca5a62d375
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550871208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.3550871208
Directory	/workspace/13.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.415125507
Short name	T1302
Test name
Test status
Simulation time	29499035 ps
CPU time	0.68 seconds
Started	Apr 28 12:55:38 PM PDT 24
Finished	Apr 28 12:55:39 PM PDT 24
Peak memory	196880 kb
Host	smart-273f637d-e220-493d-9ce8-00a074e44102
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415125507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr _outstanding.415125507
Directory	/workspace/13.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_tl_errors.4205923545
Short name	T1217
Test name
Test status
Simulation time	163259166 ps
CPU time	1.18 seconds
Started	Apr 28 12:55:42 PM PDT 24
Finished	Apr 28 12:55:44 PM PDT 24
Peak memory	200272 kb
Host	smart-eade0a24-64b0-42b2-9cde-8c2cb442e0c2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205923545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.4205923545
Directory	/workspace/13.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_tl_intg_err.23515579
Short name	T96
Test name
Test status
Simulation time	42916636 ps
CPU time	0.9 seconds
Started	Apr 28 12:55:39 PM PDT 24
Finished	Apr 28 12:55:40 PM PDT 24
Peak memory	199064 kb
Host	smart-5a9eb33e-8280-4093-a331-e1b9b37111e2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23515579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.23515579
Directory	/workspace/13.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.618666018
Short name	T1297
Test name
Test status
Simulation time	77470467 ps
CPU time	0.63 seconds
Started	Apr 28 12:55:38 PM PDT 24
Finished	Apr 28 12:55:40 PM PDT 24
Peak memory	198124 kb
Host	smart-7bcef343-b638-4cf5-be91-8c7587722499
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618666018 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.618666018
Directory	/workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_csr_rw.2707846077
Short name	T87
Test name
Test status
Simulation time	30311537 ps
CPU time	0.66 seconds
Started	Apr 28 12:55:42 PM PDT 24
Finished	Apr 28 12:55:43 PM PDT 24
Peak memory	195688 kb
Host	smart-80265e9e-c961-4d43-a3b7-48ab11278fa2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707846077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.2707846077
Directory	/workspace/14.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_intr_test.3702941476
Short name	T1315
Test name
Test status
Simulation time	16513764 ps
CPU time	0.59 seconds
Started	Apr 28 12:55:41 PM PDT 24
Finished	Apr 28 12:55:42 PM PDT 24
Peak memory	194660 kb
Host	smart-54e326b5-a558-40f8-ad44-3a292951966c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702941476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.3702941476
Directory	/workspace/14.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2253610884
Short name	T89
Test name
Test status
Simulation time	106692284 ps
CPU time	0.76 seconds
Started	Apr 28 12:55:40 PM PDT 24
Finished	Apr 28 12:55:41 PM PDT 24
Peak memory	197376 kb
Host	smart-b3de06f0-f58b-4450-8faf-f2b43abb641f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253610884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs r_outstanding.2253610884
Directory	/workspace/14.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_tl_errors.3923844958
Short name	T1262
Test name
Test status
Simulation time	179810065 ps
CPU time	1.27 seconds
Started	Apr 28 12:55:41 PM PDT 24
Finished	Apr 28 12:55:43 PM PDT 24
Peak memory	200264 kb
Host	smart-24014c3c-55f2-4c9f-b75c-1c8c3f1640cb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923844958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.3923844958
Directory	/workspace/14.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_tl_intg_err.1252557579
Short name	T128
Test name
Test status
Simulation time	178905903 ps
CPU time	0.92 seconds
Started	Apr 28 12:55:37 PM PDT 24
Finished	Apr 28 12:55:39 PM PDT 24
Peak memory	199176 kb
Host	smart-b47ec67a-c3c7-4a77-a5ac-dbad2c0aa7f1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252557579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.1252557579
Directory	/workspace/14.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.4290224781
Short name	T1309
Test name
Test status
Simulation time	91035545 ps
CPU time	1.2 seconds
Started	Apr 28 12:55:42 PM PDT 24
Finished	Apr 28 12:55:43 PM PDT 24
Peak memory	200140 kb
Host	smart-1a5bb237-9486-4d47-a28f-0bb2e2c35577
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290224781 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.4290224781
Directory	/workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_csr_rw.3048575620
Short name	T1307
Test name
Test status
Simulation time	21679800 ps
CPU time	0.59 seconds
Started	Apr 28 12:55:38 PM PDT 24
Finished	Apr 28 12:55:40 PM PDT 24
Peak memory	195520 kb
Host	smart-75c7d9d1-9961-4305-b89a-5886f27417ce
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048575620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.3048575620
Directory	/workspace/15.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_intr_test.1667292989
Short name	T1277
Test name
Test status
Simulation time	35978337 ps
CPU time	0.66 seconds
Started	Apr 28 12:55:41 PM PDT 24
Finished	Apr 28 12:55:42 PM PDT 24
Peak memory	194656 kb
Host	smart-7a22fb2e-afe8-436f-ab1f-85fd27139934
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667292989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.1667292989
Directory	/workspace/15.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1345874134
Short name	T84
Test name
Test status
Simulation time	143285539 ps
CPU time	0.64 seconds
Started	Apr 28 12:55:38 PM PDT 24
Finished	Apr 28 12:55:39 PM PDT 24
Peak memory	195932 kb
Host	smart-29f7224c-6a06-4209-8a5d-61dc032d4243
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345874134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs r_outstanding.1345874134
Directory	/workspace/15.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_tl_errors.1762753563
Short name	T1205
Test name
Test status
Simulation time	99348252 ps
CPU time	1.27 seconds
Started	Apr 28 12:55:39 PM PDT 24
Finished	Apr 28 12:55:41 PM PDT 24
Peak memory	200184 kb
Host	smart-2eb178e9-1e23-48a2-9df4-5cabce834f0a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762753563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.1762753563
Directory	/workspace/15.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2804242683
Short name	T1242
Test name
Test status
Simulation time	76574675 ps
CPU time	1.39 seconds
Started	Apr 28 12:55:40 PM PDT 24
Finished	Apr 28 12:55:42 PM PDT 24
Peak memory	199532 kb
Host	smart-030bc603-33b4-412d-8da9-be7c74880968
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804242683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.2804242683
Directory	/workspace/15.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1004821258
Short name	T1284
Test name
Test status
Simulation time	36889706 ps
CPU time	0.69 seconds
Started	Apr 28 12:55:39 PM PDT 24
Finished	Apr 28 12:55:41 PM PDT 24
Peak memory	198456 kb
Host	smart-2165188b-91f1-444f-907b-5774bb7e1e51
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004821258 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.1004821258
Directory	/workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_csr_rw.2945805883
Short name	T81
Test name
Test status
Simulation time	31897120 ps
CPU time	0.57 seconds
Started	Apr 28 12:55:38 PM PDT 24
Finished	Apr 28 12:55:39 PM PDT 24
Peak memory	195592 kb
Host	smart-1c95b38a-9bd7-4097-bd6e-97d7a78c9bec
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945805883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.2945805883
Directory	/workspace/16.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_intr_test.1705007197
Short name	T1218
Test name
Test status
Simulation time	48564911 ps
CPU time	0.57 seconds
Started	Apr 28 12:55:41 PM PDT 24
Finished	Apr 28 12:55:42 PM PDT 24
Peak memory	194580 kb
Host	smart-39b7373f-9cc2-41ce-a805-bcbcc30f5f9c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705007197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.1705007197
Directory	/workspace/16.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3255077149
Short name	T90
Test name
Test status
Simulation time	54152538 ps
CPU time	0.86 seconds
Started	Apr 28 12:55:38 PM PDT 24
Finished	Apr 28 12:55:39 PM PDT 24
Peak memory	197544 kb
Host	smart-7a76f231-0093-46d2-8a87-f41f1c4be045
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255077149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs r_outstanding.3255077149
Directory	/workspace/16.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_tl_errors.3917391211
Short name	T1280
Test name
Test status
Simulation time	59640755 ps
CPU time	1.38 seconds
Started	Apr 28 12:55:39 PM PDT 24
Finished	Apr 28 12:55:41 PM PDT 24
Peak memory	200360 kb
Host	smart-51bc5b93-3ecd-4cd1-aa24-0bdb40c12133
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917391211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.3917391211
Directory	/workspace/16.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_tl_intg_err.974452236
Short name	T1270
Test name
Test status
Simulation time	83620887 ps
CPU time	0.93 seconds
Started	Apr 28 12:55:39 PM PDT 24
Finished	Apr 28 12:55:41 PM PDT 24
Peak memory	199132 kb
Host	smart-cd1483d0-22e8-4155-96a0-988204292fa1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974452236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.974452236
Directory	/workspace/16.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1232827137
Short name	T1291
Test name
Test status
Simulation time	99193812 ps
CPU time	0.8 seconds
Started	Apr 28 12:55:47 PM PDT 24
Finished	Apr 28 12:55:48 PM PDT 24
Peak memory	200084 kb
Host	smart-9e5e5c85-04e9-43fb-a0b6-83629d41c95a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232827137 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.1232827137
Directory	/workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_csr_rw.2964826255
Short name	T88
Test name
Test status
Simulation time	48979262 ps
CPU time	0.6 seconds
Started	Apr 28 12:55:48 PM PDT 24
Finished	Apr 28 12:55:49 PM PDT 24
Peak memory	195584 kb
Host	smart-552658e6-b7d2-4c2e-9b21-85e18602fe58
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964826255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.2964826255
Directory	/workspace/17.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_intr_test.448221698
Short name	T1232
Test name
Test status
Simulation time	15000806 ps
CPU time	0.59 seconds
Started	Apr 28 12:55:46 PM PDT 24
Finished	Apr 28 12:55:47 PM PDT 24
Peak memory	194564 kb
Host	smart-cafed453-c19d-4f9b-bef1-13fbc581aeb0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448221698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.448221698
Directory	/workspace/17.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2145598103
Short name	T1263
Test name
Test status
Simulation time	64810531 ps
CPU time	0.65 seconds
Started	Apr 28 12:55:43 PM PDT 24
Finished	Apr 28 12:55:44 PM PDT 24
Peak memory	195120 kb
Host	smart-923f8ffb-bc11-49ef-9621-d9a74410b54d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145598103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs r_outstanding.2145598103
Directory	/workspace/17.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_tl_errors.4032972951
Short name	T1306
Test name
Test status
Simulation time	100560328 ps
CPU time	1.35 seconds
Started	Apr 28 12:55:40 PM PDT 24
Finished	Apr 28 12:55:42 PM PDT 24
Peak memory	200264 kb
Host	smart-21d42a98-60d4-4daf-ad9e-b4450a48c2e7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032972951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.4032972951
Directory	/workspace/17.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_tl_intg_err.791548817
Short name	T99
Test name
Test status
Simulation time	593110714 ps
CPU time	1.4 seconds
Started	Apr 28 12:55:38 PM PDT 24
Finished	Apr 28 12:55:41 PM PDT 24
Peak memory	199600 kb
Host	smart-23173017-85fd-470d-83b0-41cf619156f0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791548817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.791548817
Directory	/workspace/17.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2537695209
Short name	T1235
Test name
Test status
Simulation time	26755444 ps
CPU time	0.68 seconds
Started	Apr 28 12:55:45 PM PDT 24
Finished	Apr 28 12:55:46 PM PDT 24
Peak memory	198288 kb
Host	smart-0d23c41e-e812-46be-833d-153a1fdece76
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537695209 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.2537695209
Directory	/workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_csr_rw.2740736702
Short name	T1308
Test name
Test status
Simulation time	11438021 ps
CPU time	0.57 seconds
Started	Apr 28 12:55:50 PM PDT 24
Finished	Apr 28 12:55:52 PM PDT 24
Peak memory	195556 kb
Host	smart-be7c38f5-6f55-4e98-a7fb-fa193303e803
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740736702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.2740736702
Directory	/workspace/18.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_intr_test.2204621685
Short name	T1256
Test name
Test status
Simulation time	49109387 ps
CPU time	0.54 seconds
Started	Apr 28 12:55:50 PM PDT 24
Finished	Apr 28 12:55:51 PM PDT 24
Peak memory	194532 kb
Host	smart-8db2601f-3743-41ba-9562-546af6eb60e1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204621685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.2204621685
Directory	/workspace/18.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.1565531423
Short name	T1215
Test name
Test status
Simulation time	133550153 ps
CPU time	0.72 seconds
Started	Apr 28 12:55:49 PM PDT 24
Finished	Apr 28 12:55:51 PM PDT 24
Peak memory	197424 kb
Host	smart-a982b681-bb83-4c8f-8cf8-3de061dbbf9c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565531423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs r_outstanding.1565531423
Directory	/workspace/18.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_tl_errors.3614139222
Short name	T1190
Test name
Test status
Simulation time	44020033 ps
CPU time	1.75 seconds
Started	Apr 28 12:55:45 PM PDT 24
Finished	Apr 28 12:55:48 PM PDT 24
Peak memory	200284 kb
Host	smart-ed2e042e-7ed7-4cda-ac83-a9da485d73fe
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614139222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.3614139222
Directory	/workspace/18.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3494352381
Short name	T93
Test name
Test status
Simulation time	315069423 ps
CPU time	1.28 seconds
Started	Apr 28 12:55:45 PM PDT 24
Finished	Apr 28 12:55:47 PM PDT 24
Peak memory	199580 kb
Host	smart-0e8f934b-fb72-44df-85bb-f9fbe1f8e924
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494352381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.3494352381
Directory	/workspace/18.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3972500962
Short name	T1294
Test name
Test status
Simulation time	113652681 ps
CPU time	0.85 seconds
Started	Apr 28 12:55:43 PM PDT 24
Finished	Apr 28 12:55:45 PM PDT 24
Peak memory	200132 kb
Host	smart-7d4e4a39-bfdd-44f0-9b4a-e557c9c9ad6f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972500962 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.3972500962
Directory	/workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_csr_rw.361748685
Short name	T74
Test name
Test status
Simulation time	19534924 ps
CPU time	0.62 seconds
Started	Apr 28 12:55:44 PM PDT 24
Finished	Apr 28 12:55:45 PM PDT 24
Peak memory	195788 kb
Host	smart-01ee7f4f-dca5-4524-a5a3-717022c53f4e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361748685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.361748685
Directory	/workspace/19.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_intr_test.2334234748
Short name	T1231
Test name
Test status
Simulation time	12696523 ps
CPU time	0.55 seconds
Started	Apr 28 12:55:47 PM PDT 24
Finished	Apr 28 12:55:48 PM PDT 24
Peak memory	194696 kb
Host	smart-dc43018a-cedc-44c2-8f09-79d711fb0b0e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334234748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.2334234748
Directory	/workspace/19.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.818401932
Short name	T91
Test name
Test status
Simulation time	38237713 ps
CPU time	0.72 seconds
Started	Apr 28 12:55:44 PM PDT 24
Finished	Apr 28 12:55:45 PM PDT 24
Peak memory	197304 kb
Host	smart-f8990c2a-c065-4d7c-afc8-67ead84f437c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818401932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr _outstanding.818401932
Directory	/workspace/19.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_tl_errors.2647236012
Short name	T1210
Test name
Test status
Simulation time	274600410 ps
CPU time	1.63 seconds
Started	Apr 28 12:55:43 PM PDT 24
Finished	Apr 28 12:55:45 PM PDT 24
Peak memory	200132 kb
Host	smart-c9503434-53e3-4132-b088-c765dc546436
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647236012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.2647236012
Directory	/workspace/19.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2892700677
Short name	T94
Test name
Test status
Simulation time	45057280 ps
CPU time	0.94 seconds
Started	Apr 28 12:55:48 PM PDT 24
Finished	Apr 28 12:55:49 PM PDT 24
Peak memory	199184 kb
Host	smart-27fd5959-c2f3-4436-aa81-1399533953ee
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892700677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.2892700677
Directory	/workspace/19.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2439144242
Short name	T77
Test name
Test status
Simulation time	172033448 ps
CPU time	0.77 seconds
Started	Apr 28 12:55:26 PM PDT 24
Finished	Apr 28 12:55:28 PM PDT 24
Peak memory	196500 kb
Host	smart-e78115f6-79c7-4b24-ac57-67aba9c40da9
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439144242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.2439144242
Directory	/workspace/2.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3605274426
Short name	T1269
Test name
Test status
Simulation time	93853490 ps
CPU time	1.49 seconds
Started	Apr 28 12:55:24 PM PDT 24
Finished	Apr 28 12:55:27 PM PDT 24
Peak memory	197780 kb
Host	smart-aa5ceccd-06c7-401a-920d-0b9cf1124b1a
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605274426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.3605274426
Directory	/workspace/2.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3407374494
Short name	T1194
Test name
Test status
Simulation time	13019422 ps
CPU time	0.59 seconds
Started	Apr 28 12:55:24 PM PDT 24
Finished	Apr 28 12:55:25 PM PDT 24
Peak memory	195584 kb
Host	smart-ecd90457-3b77-4ea4-bf82-face69636fbd
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407374494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.3407374494
Directory	/workspace/2.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.807010742
Short name	T1213
Test name
Test status
Simulation time	13213682 ps
CPU time	0.64 seconds
Started	Apr 28 12:55:29 PM PDT 24
Finished	Apr 28 12:55:31 PM PDT 24
Peak memory	197756 kb
Host	smart-2b15049f-9646-4795-b1d4-7b6596af7a38
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807010742 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.807010742
Directory	/workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_rw.468012026
Short name	T1285
Test name
Test status
Simulation time	15120795 ps
CPU time	0.57 seconds
Started	Apr 28 12:55:28 PM PDT 24
Finished	Apr 28 12:55:30 PM PDT 24
Peak memory	195572 kb
Host	smart-c428fe53-bad6-46ea-b40e-b773b089f6c2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468012026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.468012026
Directory	/workspace/2.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_intr_test.186551302
Short name	T1238
Test name
Test status
Simulation time	31306403 ps
CPU time	0.55 seconds
Started	Apr 28 12:55:22 PM PDT 24
Finished	Apr 28 12:55:23 PM PDT 24
Peak memory	194724 kb
Host	smart-6ed4e5f1-5c73-46bd-91de-1fe7cd65fbb2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186551302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.186551302
Directory	/workspace/2.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.1528241822
Short name	T1266
Test name
Test status
Simulation time	43944870 ps
CPU time	0.69 seconds
Started	Apr 28 12:55:24 PM PDT 24
Finished	Apr 28 12:55:25 PM PDT 24
Peak memory	197188 kb
Host	smart-41ca4f91-5f8f-47cc-97ac-1791ba41061b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528241822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr _outstanding.1528241822
Directory	/workspace/2.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_tl_errors.4088571891
Short name	T1229
Test name
Test status
Simulation time	427502082 ps
CPU time	2.14 seconds
Started	Apr 28 12:55:29 PM PDT 24
Finished	Apr 28 12:55:32 PM PDT 24
Peak memory	200404 kb
Host	smart-3ab0840f-2e2e-47bf-8a9b-2d385fd37d59
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088571891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.4088571891
Directory	/workspace/2.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3316019575
Short name	T1300
Test name
Test status
Simulation time	91391565 ps
CPU time	1.28 seconds
Started	Apr 28 12:55:24 PM PDT 24
Finished	Apr 28 12:55:26 PM PDT 24
Peak memory	199792 kb
Host	smart-67e12ec3-62cd-47fe-a87f-31d3de3c848d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316019575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.3316019575
Directory	/workspace/2.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.uart_intr_test.3542546399
Short name	T1257
Test name
Test status
Simulation time	63270821 ps
CPU time	0.62 seconds
Started	Apr 28 12:55:44 PM PDT 24
Finished	Apr 28 12:55:45 PM PDT 24
Peak memory	194612 kb
Host	smart-661fb19b-8f9a-49cb-88ad-d2578a808692
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542546399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.3542546399
Directory	/workspace/20.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.uart_intr_test.607007131
Short name	T1253
Test name
Test status
Simulation time	13966895 ps
CPU time	0.59 seconds
Started	Apr 28 12:55:46 PM PDT 24
Finished	Apr 28 12:55:47 PM PDT 24
Peak memory	194696 kb
Host	smart-cd5b018f-f8ea-4608-af10-e620905709a9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607007131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.607007131
Directory	/workspace/21.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.uart_intr_test.2375967784
Short name	T1204
Test name
Test status
Simulation time	27194614 ps
CPU time	0.56 seconds
Started	Apr 28 12:55:45 PM PDT 24
Finished	Apr 28 12:55:47 PM PDT 24
Peak memory	194596 kb
Host	smart-61c0aa23-a12c-4b7f-b985-efc60bc3eaa9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375967784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.2375967784
Directory	/workspace/22.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.uart_intr_test.1991969441
Short name	T1259
Test name
Test status
Simulation time	19850480 ps
CPU time	0.57 seconds
Started	Apr 28 12:55:45 PM PDT 24
Finished	Apr 28 12:55:47 PM PDT 24
Peak memory	194688 kb
Host	smart-068148b5-0463-4611-ad8e-1f666f990741
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991969441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.1991969441
Directory	/workspace/23.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.uart_intr_test.444506130
Short name	T1199
Test name
Test status
Simulation time	20777954 ps
CPU time	0.55 seconds
Started	Apr 28 12:55:44 PM PDT 24
Finished	Apr 28 12:55:45 PM PDT 24
Peak memory	194680 kb
Host	smart-64fd0e09-70eb-4dc4-8717-347dff4bdd52
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444506130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.444506130
Directory	/workspace/24.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.uart_intr_test.1553683969
Short name	T1261
Test name
Test status
Simulation time	17271185 ps
CPU time	0.58 seconds
Started	Apr 28 12:55:44 PM PDT 24
Finished	Apr 28 12:55:46 PM PDT 24
Peak memory	194616 kb
Host	smart-559addb9-27cc-49b7-825b-a25f0e799fef
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553683969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.1553683969
Directory	/workspace/25.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.uart_intr_test.4130093683
Short name	T1236
Test name
Test status
Simulation time	50117991 ps
CPU time	0.54 seconds
Started	Apr 28 12:55:44 PM PDT 24
Finished	Apr 28 12:55:46 PM PDT 24
Peak memory	194612 kb
Host	smart-a91ed772-e5eb-4022-a1c3-57651c65d25a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130093683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.4130093683
Directory	/workspace/26.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.uart_intr_test.2326742305
Short name	T1264
Test name
Test status
Simulation time	16287523 ps
CPU time	0.56 seconds
Started	Apr 28 12:55:45 PM PDT 24
Finished	Apr 28 12:55:47 PM PDT 24
Peak memory	194612 kb
Host	smart-722f7f51-ff39-4364-a757-7249781fdd2b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326742305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.2326742305
Directory	/workspace/27.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.uart_intr_test.1534236579
Short name	T1271
Test name
Test status
Simulation time	92641223 ps
CPU time	0.59 seconds
Started	Apr 28 12:55:42 PM PDT 24
Finished	Apr 28 12:55:43 PM PDT 24
Peak memory	194700 kb
Host	smart-68793a5b-a34a-4341-a05a-9fd44bd62f24
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534236579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.1534236579
Directory	/workspace/28.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.uart_intr_test.538317179
Short name	T1304
Test name
Test status
Simulation time	26698947 ps
CPU time	0.59 seconds
Started	Apr 28 12:55:46 PM PDT 24
Finished	Apr 28 12:55:47 PM PDT 24
Peak memory	194652 kb
Host	smart-3eb37d4a-b33b-4232-beea-ac97c37792e2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538317179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.538317179
Directory	/workspace/29.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1776743798
Short name	T1295
Test name
Test status
Simulation time	15286135 ps
CPU time	0.68 seconds
Started	Apr 28 12:55:23 PM PDT 24
Finished	Apr 28 12:55:25 PM PDT 24
Peak memory	195220 kb
Host	smart-0930cef1-0905-4cb5-a65a-60092c1bc4b8
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776743798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1776743798
Directory	/workspace/3.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.139712296
Short name	T1268
Test name
Test status
Simulation time	115726967 ps
CPU time	1.5 seconds
Started	Apr 28 12:55:23 PM PDT 24
Finished	Apr 28 12:55:26 PM PDT 24
Peak memory	198012 kb
Host	smart-05430490-30a2-4b8a-b209-c8420ce1b36c
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139712296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.139712296
Directory	/workspace/3.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.985522182
Short name	T1279
Test name
Test status
Simulation time	18651588 ps
CPU time	0.56 seconds
Started	Apr 28 12:55:22 PM PDT 24
Finished	Apr 28 12:55:24 PM PDT 24
Peak memory	195708 kb
Host	smart-1b4fa9ba-aa79-4617-bc88-2c7aa3e47d1a
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985522182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.985522182
Directory	/workspace/3.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2887751896
Short name	T1258
Test name
Test status
Simulation time	28002689 ps
CPU time	0.83 seconds
Started	Apr 28 12:55:28 PM PDT 24
Finished	Apr 28 12:55:30 PM PDT 24
Peak memory	200056 kb
Host	smart-9f632b9b-f47c-4555-9003-22aad50b9004
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887751896 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.2887751896
Directory	/workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_rw.3201574158
Short name	T1195
Test name
Test status
Simulation time	20708140 ps
CPU time	0.58 seconds
Started	Apr 28 12:55:29 PM PDT 24
Finished	Apr 28 12:55:30 PM PDT 24
Peak memory	195644 kb
Host	smart-59a0716e-c582-43cf-aa2d-ade2dd2137e0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201574158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.3201574158
Directory	/workspace/3.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_intr_test.1104001039
Short name	T1196
Test name
Test status
Simulation time	23081511 ps
CPU time	0.56 seconds
Started	Apr 28 12:55:23 PM PDT 24
Finished	Apr 28 12:55:24 PM PDT 24
Peak memory	194648 kb
Host	smart-a546500c-aff6-4040-bbf8-331eab40c45a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104001039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.1104001039
Directory	/workspace/3.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.57442048
Short name	T1298
Test name
Test status
Simulation time	73813306 ps
CPU time	0.65 seconds
Started	Apr 28 12:55:25 PM PDT 24
Finished	Apr 28 12:55:26 PM PDT 24
Peak memory	195796 kb
Host	smart-3ad7d426-87c6-4a4b-9f0d-87f4117f3bea
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57442048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_o utstanding.57442048
Directory	/workspace/3.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_tl_errors.777936468
Short name	T1222
Test name
Test status
Simulation time	449918837 ps
CPU time	2.29 seconds
Started	Apr 28 12:55:24 PM PDT 24
Finished	Apr 28 12:55:27 PM PDT 24
Peak memory	200368 kb
Host	smart-11d8ab4f-1a4e-46e6-a8f1-30d341b0a7e0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777936468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.777936468
Directory	/workspace/3.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1300217525
Short name	T1288
Test name
Test status
Simulation time	50820522 ps
CPU time	0.92 seconds
Started	Apr 28 12:55:25 PM PDT 24
Finished	Apr 28 12:55:27 PM PDT 24
Peak memory	199028 kb
Host	smart-068c4f81-6ea1-492e-8ef0-3f760d6ae4da
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300217525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.1300217525
Directory	/workspace/3.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.uart_intr_test.315204664
Short name	T1274
Test name
Test status
Simulation time	34793070 ps
CPU time	0.56 seconds
Started	Apr 28 12:55:43 PM PDT 24
Finished	Apr 28 12:55:45 PM PDT 24
Peak memory	194636 kb
Host	smart-267bc9e8-1dcd-4c5c-9c85-72b5a429c913
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315204664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.315204664
Directory	/workspace/30.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.uart_intr_test.3183136180
Short name	T1191
Test name
Test status
Simulation time	51913081 ps
CPU time	0.56 seconds
Started	Apr 28 12:55:45 PM PDT 24
Finished	Apr 28 12:55:46 PM PDT 24
Peak memory	194612 kb
Host	smart-3d0e3324-065c-431f-bac6-9c0aceaef364
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183136180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.3183136180
Directory	/workspace/31.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.uart_intr_test.3822248928
Short name	T1296
Test name
Test status
Simulation time	11964793 ps
CPU time	0.6 seconds
Started	Apr 28 12:55:45 PM PDT 24
Finished	Apr 28 12:55:46 PM PDT 24
Peak memory	194596 kb
Host	smart-c1ce1a8d-2ac0-445b-ace4-be5c342a562e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822248928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.3822248928
Directory	/workspace/32.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.uart_intr_test.65772260
Short name	T1246
Test name
Test status
Simulation time	13092475 ps
CPU time	0.55 seconds
Started	Apr 28 12:55:50 PM PDT 24
Finished	Apr 28 12:55:52 PM PDT 24
Peak memory	194552 kb
Host	smart-7d77a4d1-2e11-466b-a069-1a6dee033689
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65772260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.65772260
Directory	/workspace/33.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.uart_intr_test.1947049856
Short name	T1200
Test name
Test status
Simulation time	14206613 ps
CPU time	0.59 seconds
Started	Apr 28 12:55:45 PM PDT 24
Finished	Apr 28 12:55:46 PM PDT 24
Peak memory	194584 kb
Host	smart-20a8fa9c-a186-4135-8004-593fe8ecc396
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947049856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.1947049856
Directory	/workspace/34.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.uart_intr_test.2566892065
Short name	T1230
Test name
Test status
Simulation time	16182596 ps
CPU time	0.58 seconds
Started	Apr 28 12:55:50 PM PDT 24
Finished	Apr 28 12:55:52 PM PDT 24
Peak memory	194568 kb
Host	smart-3e73b606-f80d-4dd2-9347-1aafb315199e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566892065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.2566892065
Directory	/workspace/35.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.uart_intr_test.2675608778
Short name	T1214
Test name
Test status
Simulation time	27958468 ps
CPU time	0.57 seconds
Started	Apr 28 12:55:49 PM PDT 24
Finished	Apr 28 12:55:51 PM PDT 24
Peak memory	194732 kb
Host	smart-e43a49d2-b196-4b0f-b2f1-8449ec32290e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675608778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2675608778
Directory	/workspace/36.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.uart_intr_test.544911956
Short name	T1228
Test name
Test status
Simulation time	41504698 ps
CPU time	0.55 seconds
Started	Apr 28 12:55:46 PM PDT 24
Finished	Apr 28 12:55:47 PM PDT 24
Peak memory	194696 kb
Host	smart-d3bb4429-b415-4679-8822-43f00f696325
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544911956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.544911956
Directory	/workspace/37.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.uart_intr_test.2275186059
Short name	T1283
Test name
Test status
Simulation time	17402331 ps
CPU time	0.58 seconds
Started	Apr 28 12:55:42 PM PDT 24
Finished	Apr 28 12:55:43 PM PDT 24
Peak memory	194512 kb
Host	smart-544c9b4e-2486-4c55-ad3f-b81634a48f58
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275186059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.2275186059
Directory	/workspace/38.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.uart_intr_test.1991279411
Short name	T1193
Test name
Test status
Simulation time	13058786 ps
CPU time	0.58 seconds
Started	Apr 28 12:55:48 PM PDT 24
Finished	Apr 28 12:55:49 PM PDT 24
Peak memory	194564 kb
Host	smart-ebd11167-f838-4338-9e29-3797e80036f8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991279411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.1991279411
Directory	/workspace/39.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2252624064
Short name	T75
Test name
Test status
Simulation time	20253024 ps
CPU time	0.76 seconds
Started	Apr 28 12:55:27 PM PDT 24
Finished	Apr 28 12:55:29 PM PDT 24
Peak memory	196804 kb
Host	smart-a4d59fd3-f5ea-4b3e-83bb-fd9992364eae
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252624064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.2252624064
Directory	/workspace/4.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3156844702
Short name	T1255
Test name
Test status
Simulation time	68789507 ps
CPU time	1.41 seconds
Started	Apr 28 12:55:30 PM PDT 24
Finished	Apr 28 12:55:32 PM PDT 24
Peak memory	198152 kb
Host	smart-a93c3124-d7f0-4e15-8b1f-507b7c134a10
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156844702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.3156844702
Directory	/workspace/4.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1408809696
Short name	T1265
Test name
Test status
Simulation time	70332115 ps
CPU time	0.62 seconds
Started	Apr 28 12:55:26 PM PDT 24
Finished	Apr 28 12:55:27 PM PDT 24
Peak memory	195592 kb
Host	smart-87a84ae8-0f53-41aa-8450-8bd1223fb2ad
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408809696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.1408809696
Directory	/workspace/4.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2972209491
Short name	T1312
Test name
Test status
Simulation time	150502421 ps
CPU time	0.88 seconds
Started	Apr 28 12:55:28 PM PDT 24
Finished	Apr 28 12:55:30 PM PDT 24
Peak memory	200040 kb
Host	smart-2e11b530-2354-44b1-ac6c-0fd78a7c37a3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972209491 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.2972209491
Directory	/workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_rw.2469436228
Short name	T80
Test name
Test status
Simulation time	12461980 ps
CPU time	0.59 seconds
Started	Apr 28 12:55:29 PM PDT 24
Finished	Apr 28 12:55:31 PM PDT 24
Peak memory	195788 kb
Host	smart-32163480-10e0-4e3b-88b6-fa1970bb056a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469436228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.2469436228
Directory	/workspace/4.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_intr_test.809814890
Short name	T1310
Test name
Test status
Simulation time	138883100 ps
CPU time	0.57 seconds
Started	Apr 28 12:55:23 PM PDT 24
Finished	Apr 28 12:55:25 PM PDT 24
Peak memory	194568 kb
Host	smart-e56669e5-96bb-4518-88cf-f3e6416e7328
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809814890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.809814890
Directory	/workspace/4.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2492918929
Short name	T1223
Test name
Test status
Simulation time	18837591 ps
CPU time	0.63 seconds
Started	Apr 28 12:55:33 PM PDT 24
Finished	Apr 28 12:55:35 PM PDT 24
Peak memory	195900 kb
Host	smart-b6f32b07-61c9-4b31-b06b-bca214b6a580
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492918929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr _outstanding.2492918929
Directory	/workspace/4.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_tl_errors.3779321110
Short name	T1273
Test name
Test status
Simulation time	371202991 ps
CPU time	2.01 seconds
Started	Apr 28 12:55:24 PM PDT 24
Finished	Apr 28 12:55:27 PM PDT 24
Peak memory	200192 kb
Host	smart-639aa625-c783-4926-9dae-990ad21830d3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779321110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.3779321110
Directory	/workspace/4.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2062806173
Short name	T97
Test name
Test status
Simulation time	87903185 ps
CPU time	0.94 seconds
Started	Apr 28 12:55:26 PM PDT 24
Finished	Apr 28 12:55:28 PM PDT 24
Peak memory	198888 kb
Host	smart-56b3b2fc-7eaf-4364-b8f1-f2f856c06e92
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062806173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.2062806173
Directory	/workspace/4.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.uart_intr_test.887916036
Short name	T1249
Test name
Test status
Simulation time	13486853 ps
CPU time	0.6 seconds
Started	Apr 28 12:55:49 PM PDT 24
Finished	Apr 28 12:55:51 PM PDT 24
Peak memory	194788 kb
Host	smart-40098cd4-6a3f-49db-9571-b7c622775416
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887916036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.887916036
Directory	/workspace/40.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.uart_intr_test.1331465199
Short name	T1293
Test name
Test status
Simulation time	31699943 ps
CPU time	0.55 seconds
Started	Apr 28 12:55:50 PM PDT 24
Finished	Apr 28 12:55:52 PM PDT 24
Peak memory	194660 kb
Host	smart-5e86cc5a-3ce6-4d34-a216-46b567f7472f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331465199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.1331465199
Directory	/workspace/41.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.uart_intr_test.2235007103
Short name	T1192
Test name
Test status
Simulation time	30536115 ps
CPU time	0.64 seconds
Started	Apr 28 12:55:50 PM PDT 24
Finished	Apr 28 12:55:52 PM PDT 24
Peak memory	194692 kb
Host	smart-7aeab5ee-e330-4f2e-8650-786b2ef9cf90
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235007103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.2235007103
Directory	/workspace/42.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.uart_intr_test.389826566
Short name	T1241
Test name
Test status
Simulation time	71796980 ps
CPU time	0.58 seconds
Started	Apr 28 12:55:50 PM PDT 24
Finished	Apr 28 12:55:52 PM PDT 24
Peak memory	194680 kb
Host	smart-91a36146-fc92-4d63-94fb-3a39ec994ab4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389826566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.389826566
Directory	/workspace/43.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.uart_intr_test.149956959
Short name	T1301
Test name
Test status
Simulation time	16364424 ps
CPU time	0.58 seconds
Started	Apr 28 12:55:49 PM PDT 24
Finished	Apr 28 12:55:51 PM PDT 24
Peak memory	194792 kb
Host	smart-424339ea-0557-42f7-90d7-3342eb5ac79b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149956959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.149956959
Directory	/workspace/44.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.uart_intr_test.2762495842
Short name	T1313
Test name
Test status
Simulation time	19954247 ps
CPU time	0.58 seconds
Started	Apr 28 12:55:50 PM PDT 24
Finished	Apr 28 12:55:52 PM PDT 24
Peak memory	194572 kb
Host	smart-78a5a365-a005-404b-a678-d0be690087d2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762495842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.2762495842
Directory	/workspace/45.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.uart_intr_test.2730095903
Short name	T1305
Test name
Test status
Simulation time	47785958 ps
CPU time	0.56 seconds
Started	Apr 28 12:55:51 PM PDT 24
Finished	Apr 28 12:55:53 PM PDT 24
Peak memory	194592 kb
Host	smart-804d5976-3761-4339-bfe8-c47a75ff9c15
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730095903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2730095903
Directory	/workspace/46.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.uart_intr_test.526578053
Short name	T1303
Test name
Test status
Simulation time	11666355 ps
CPU time	0.58 seconds
Started	Apr 28 12:55:49 PM PDT 24
Finished	Apr 28 12:55:51 PM PDT 24
Peak memory	194692 kb
Host	smart-2e4e019f-0e42-45c4-ac9b-b4046609482a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526578053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.526578053
Directory	/workspace/47.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.uart_intr_test.2052072531
Short name	T1225
Test name
Test status
Simulation time	18291990 ps
CPU time	0.59 seconds
Started	Apr 28 12:55:49 PM PDT 24
Finished	Apr 28 12:55:51 PM PDT 24
Peak memory	194592 kb
Host	smart-75743cb7-a335-4329-a106-fbc29da31aa0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052072531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2052072531
Directory	/workspace/48.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.uart_intr_test.313900930
Short name	T1201
Test name
Test status
Simulation time	29460077 ps
CPU time	0.57 seconds
Started	Apr 28 12:55:50 PM PDT 24
Finished	Apr 28 12:55:52 PM PDT 24
Peak memory	194760 kb
Host	smart-f9d7268b-6cc5-40a5-8b57-fb74705f1e92
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313900930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.313900930
Directory	/workspace/49.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3822684202
Short name	T1289
Test name
Test status
Simulation time	37547859 ps
CPU time	0.76 seconds
Started	Apr 28 12:55:30 PM PDT 24
Finished	Apr 28 12:55:32 PM PDT 24
Peak memory	198644 kb
Host	smart-11c7e546-a14a-4a90-bfa8-aab00ef5871b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822684202 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.3822684202
Directory	/workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_csr_rw.3146618211
Short name	T1216
Test name
Test status
Simulation time	22005070 ps
CPU time	0.57 seconds
Started	Apr 28 12:55:30 PM PDT 24
Finished	Apr 28 12:55:32 PM PDT 24
Peak memory	195596 kb
Host	smart-31cbfe72-d9b8-43a0-a8dd-9654a2d0f244
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146618211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3146618211
Directory	/workspace/5.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_intr_test.4272291409
Short name	T1182
Test name
Test status
Simulation time	22334622 ps
CPU time	0.56 seconds
Started	Apr 28 12:55:29 PM PDT 24
Finished	Apr 28 12:55:31 PM PDT 24
Peak memory	194568 kb
Host	smart-1ac70a50-3f25-4e31-aeb8-7548ea14e5ca
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272291409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.4272291409
Directory	/workspace/5.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3774851754
Short name	T1278
Test name
Test status
Simulation time	61925055 ps
CPU time	0.72 seconds
Started	Apr 28 12:55:33 PM PDT 24
Finished	Apr 28 12:55:35 PM PDT 24
Peak memory	196152 kb
Host	smart-f9a51a8a-ef9f-4a86-90b9-1d4252c470ad
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774851754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr _outstanding.3774851754
Directory	/workspace/5.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_tl_errors.73731684
Short name	T1202
Test name
Test status
Simulation time	48755737 ps
CPU time	2.58 seconds
Started	Apr 28 12:55:27 PM PDT 24
Finished	Apr 28 12:55:30 PM PDT 24
Peak memory	200412 kb
Host	smart-8e7b3315-5aeb-401f-b7eb-d23145bdfdcc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73731684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.73731684
Directory	/workspace/5.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1717171450
Short name	T100
Test name
Test status
Simulation time	76700565 ps
CPU time	1.26 seconds
Started	Apr 28 12:55:27 PM PDT 24
Finished	Apr 28 12:55:29 PM PDT 24
Peak memory	199460 kb
Host	smart-c2fb5e89-b7bf-4ce6-9bb2-356b8d92b971
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717171450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.1717171450
Directory	/workspace/5.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.779324969
Short name	T1206
Test name
Test status
Simulation time	68616852 ps
CPU time	0.71 seconds
Started	Apr 28 12:55:28 PM PDT 24
Finished	Apr 28 12:55:29 PM PDT 24
Peak memory	198536 kb
Host	smart-236c5e64-8e74-4ff9-88fd-25b123df17b8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779324969 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.779324969
Directory	/workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_csr_rw.523888174
Short name	T83
Test name
Test status
Simulation time	17968490 ps
CPU time	0.58 seconds
Started	Apr 28 12:55:28 PM PDT 24
Finished	Apr 28 12:55:30 PM PDT 24
Peak memory	195704 kb
Host	smart-0c8ad7c5-44da-48b9-acfc-77cb197f1b3f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523888174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.523888174
Directory	/workspace/6.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_intr_test.940125536
Short name	T1198
Test name
Test status
Simulation time	16077544 ps
CPU time	0.6 seconds
Started	Apr 28 12:55:30 PM PDT 24
Finished	Apr 28 12:55:31 PM PDT 24
Peak memory	194588 kb
Host	smart-77464080-1bea-4772-ae73-2850e68485c3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940125536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.940125536
Directory	/workspace/6.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1165716069
Short name	T1233
Test name
Test status
Simulation time	15925411 ps
CPU time	0.71 seconds
Started	Apr 28 12:55:29 PM PDT 24
Finished	Apr 28 12:55:30 PM PDT 24
Peak memory	197332 kb
Host	smart-7fda9276-ab26-4aa8-8d49-aaf258413111
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165716069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr _outstanding.1165716069
Directory	/workspace/6.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_tl_errors.3565867577
Short name	T1189
Test name
Test status
Simulation time	85115626 ps
CPU time	1.91 seconds
Started	Apr 28 12:55:30 PM PDT 24
Finished	Apr 28 12:55:33 PM PDT 24
Peak memory	200240 kb
Host	smart-a6dce894-e5f9-4539-9222-c68f6325e6c9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565867577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.3565867577
Directory	/workspace/6.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.803725615
Short name	T1220
Test name
Test status
Simulation time	133133033 ps
CPU time	0.96 seconds
Started	Apr 28 12:55:31 PM PDT 24
Finished	Apr 28 12:55:32 PM PDT 24
Peak memory	200084 kb
Host	smart-6ceba40d-4c34-479f-8561-1933d2fe6a6b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803725615 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.803725615
Directory	/workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_csr_rw.4105969096
Short name	T79
Test name
Test status
Simulation time	82557079 ps
CPU time	0.63 seconds
Started	Apr 28 12:55:27 PM PDT 24
Finished	Apr 28 12:55:28 PM PDT 24
Peak memory	195900 kb
Host	smart-988402a9-7c8e-4e15-8454-98289db22d29
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105969096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.4105969096
Directory	/workspace/7.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_intr_test.1022172374
Short name	T1212
Test name
Test status
Simulation time	46863140 ps
CPU time	0.6 seconds
Started	Apr 28 12:55:30 PM PDT 24
Finished	Apr 28 12:55:31 PM PDT 24
Peak memory	194576 kb
Host	smart-07001fba-b515-4ad6-814c-499523c8d1bf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022172374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.1022172374
Directory	/workspace/7.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.185063413
Short name	T1254
Test name
Test status
Simulation time	145387100 ps
CPU time	0.71 seconds
Started	Apr 28 12:55:33 PM PDT 24
Finished	Apr 28 12:55:35 PM PDT 24
Peak memory	194820 kb
Host	smart-dfed90bd-4684-40c7-a92f-d43bd0d264d6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185063413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_ outstanding.185063413
Directory	/workspace/7.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_tl_errors.4200893379
Short name	T1203
Test name
Test status
Simulation time	88129209 ps
CPU time	1.6 seconds
Started	Apr 28 12:55:32 PM PDT 24
Finished	Apr 28 12:55:35 PM PDT 24
Peak memory	200312 kb
Host	smart-ca4ddffb-ba67-4cd6-9433-a3d499ab7c34
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200893379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.4200893379
Directory	/workspace/7.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_tl_intg_err.976045432
Short name	T92
Test name
Test status
Simulation time	154507934 ps
CPU time	1 seconds
Started	Apr 28 12:55:30 PM PDT 24
Finished	Apr 28 12:55:32 PM PDT 24
Peak memory	199180 kb
Host	smart-346ccd9b-56c1-4688-9095-be458d32836a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976045432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.976045432
Directory	/workspace/7.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3482796185
Short name	T1276
Test name
Test status
Simulation time	28149421 ps
CPU time	0.76 seconds
Started	Apr 28 12:55:29 PM PDT 24
Finished	Apr 28 12:55:30 PM PDT 24
Peak memory	199352 kb
Host	smart-55ae0984-bf32-4a5e-87eb-7528cedc097e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482796185 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.3482796185
Directory	/workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_csr_rw.2672834969
Short name	T1234
Test name
Test status
Simulation time	11069791 ps
CPU time	0.55 seconds
Started	Apr 28 12:55:32 PM PDT 24
Finished	Apr 28 12:55:33 PM PDT 24
Peak memory	195572 kb
Host	smart-a6e183a4-31a1-43ce-8079-dfd196b8f899
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672834969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.2672834969
Directory	/workspace/8.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_intr_test.66158315
Short name	T1186
Test name
Test status
Simulation time	13110042 ps
CPU time	0.61 seconds
Started	Apr 28 12:55:28 PM PDT 24
Finished	Apr 28 12:55:30 PM PDT 24
Peak memory	194704 kb
Host	smart-3a0bb5f6-c04e-4f98-8ba5-8360ab90f396
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66158315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.66158315
Directory	/workspace/8.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3918901069
Short name	T1240
Test name
Test status
Simulation time	52456077 ps
CPU time	0.69 seconds
Started	Apr 28 12:55:29 PM PDT 24
Finished	Apr 28 12:55:31 PM PDT 24
Peak memory	196916 kb
Host	smart-41c022fc-5fe4-4582-b684-cb4e96000467
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918901069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr _outstanding.3918901069
Directory	/workspace/8.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_tl_errors.3441467154
Short name	T1299
Test name
Test status
Simulation time	84083268 ps
CPU time	1.85 seconds
Started	Apr 28 12:55:32 PM PDT 24
Finished	Apr 28 12:55:34 PM PDT 24
Peak memory	200260 kb
Host	smart-a1ee7926-2633-4e5d-bb76-f5322a97703c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441467154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.3441467154
Directory	/workspace/8.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_tl_intg_err.557508188
Short name	T1237
Test name
Test status
Simulation time	201340899 ps
CPU time	0.89 seconds
Started	Apr 28 12:55:27 PM PDT 24
Finished	Apr 28 12:55:29 PM PDT 24
Peak memory	198860 kb
Host	smart-687fc037-a829-46d4-a7d5-366be0b93cf7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557508188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.557508188
Directory	/workspace/8.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.544817368
Short name	T1275
Test name
Test status
Simulation time	19168170 ps
CPU time	0.94 seconds
Started	Apr 28 12:55:37 PM PDT 24
Finished	Apr 28 12:55:38 PM PDT 24
Peak memory	200028 kb
Host	smart-7498ef18-cfb0-4b64-9d04-9ec2d05bcd5d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544817368 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.544817368
Directory	/workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_csr_rw.1436928279
Short name	T1239
Test name
Test status
Simulation time	23645155 ps
CPU time	0.56 seconds
Started	Apr 28 12:55:38 PM PDT 24
Finished	Apr 28 12:55:39 PM PDT 24
Peak memory	195652 kb
Host	smart-6c1a30f8-65a3-47bb-9c94-7a6c5b37f0a2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436928279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.1436928279
Directory	/workspace/9.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_intr_test.2708809532
Short name	T1227
Test name
Test status
Simulation time	60478460 ps
CPU time	0.57 seconds
Started	Apr 28 12:55:34 PM PDT 24
Finished	Apr 28 12:55:35 PM PDT 24
Peak memory	194696 kb
Host	smart-efc852da-2117-47d0-b6ff-5c075c5d8265
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708809532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.2708809532
Directory	/workspace/9.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.3010155787
Short name	T86
Test name
Test status
Simulation time	44221600 ps
CPU time	0.65 seconds
Started	Apr 28 12:55:32 PM PDT 24
Finished	Apr 28 12:55:34 PM PDT 24
Peak memory	194852 kb
Host	smart-e8bc42aa-e108-4752-82ed-b6cb6334c14b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010155787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr _outstanding.3010155787
Directory	/workspace/9.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_tl_errors.3857328711
Short name	T1209
Test name
Test status
Simulation time	85939833 ps
CPU time	1.31 seconds
Started	Apr 28 12:55:33 PM PDT 24
Finished	Apr 28 12:55:35 PM PDT 24
Peak memory	200248 kb
Host	smart-a4594a30-08ce-4e53-a7b3-9b1578dbe835
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857328711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.3857328711
Directory	/workspace/9.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_tl_intg_err.490008774
Short name	T1287
Test name
Test status
Simulation time	166977257 ps
CPU time	0.92 seconds
Started	Apr 28 12:55:33 PM PDT 24
Finished	Apr 28 12:55:35 PM PDT 24
Peak memory	199400 kb
Host	smart-a97bb23a-026a-42ff-a8aa-8a653dac4557
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490008774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.490008774
Directory	/workspace/9.uart_tl_intg_err/latest

Test location	/workspace/coverage/default/0.uart_alert_test.2686853304
Short name	T943
Test name
Test status
Simulation time	16183088 ps
CPU time	0.58 seconds
Started	Apr 28 01:05:07 PM PDT 24
Finished	Apr 28 01:05:09 PM PDT 24
Peak memory	195824 kb
Host	smart-945b36be-f65c-41f3-984a-d10886b3be1f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686853304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2686853304
Directory	/workspace/0.uart_alert_test/latest

Test location	/workspace/coverage/default/0.uart_fifo_full.3940184257
Short name	T627
Test name
Test status
Simulation time	39016948484 ps
CPU time	33.93 seconds
Started	Apr 28 01:05:12 PM PDT 24
Finished	Apr 28 01:05:48 PM PDT 24
Peak memory	200420 kb
Host	smart-890197e4-66f6-4e70-a07e-989dda026f11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3940184257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.3940184257
Directory	/workspace/0.uart_fifo_full/latest

Test location	/workspace/coverage/default/0.uart_fifo_overflow.2995681946
Short name	T574
Test name
Test status
Simulation time	17677585901 ps
CPU time	29.78 seconds
Started	Apr 28 01:05:09 PM PDT 24
Finished	Apr 28 01:05:40 PM PDT 24
Peak memory	200452 kb
Host	smart-007063db-b049-4a95-b020-c10dac786521
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2995681946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.2995681946
Directory	/workspace/0.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/0.uart_fifo_reset.4124477584
Short name	T837
Test name
Test status
Simulation time	213772678140 ps
CPU time	97.73 seconds
Started	Apr 28 01:05:09 PM PDT 24
Finished	Apr 28 01:06:48 PM PDT 24
Peak memory	200304 kb
Host	smart-d8c05234-adfa-4fd8-9fa0-60eacc482409
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4124477584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.4124477584
Directory	/workspace/0.uart_fifo_reset/latest

Test location	/workspace/coverage/default/0.uart_intr.3414533053
Short name	T873
Test name
Test status
Simulation time	228603886784 ps
CPU time	426.76 seconds
Started	Apr 28 01:05:12 PM PDT 24
Finished	Apr 28 01:12:20 PM PDT 24
Peak memory	200132 kb
Host	smart-9ad70786-2e45-4dea-94b9-53921661fac4
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414533053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.3414533053
Directory	/workspace/0.uart_intr/latest

Test location	/workspace/coverage/default/0.uart_long_xfer_wo_dly.2879524479
Short name	T877
Test name
Test status
Simulation time	99259374555 ps
CPU time	576.3 seconds
Started	Apr 28 01:05:11 PM PDT 24
Finished	Apr 28 01:14:49 PM PDT 24
Peak memory	200408 kb
Host	smart-b2c02eb8-d35d-4ecb-93f4-41af3c21546f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2879524479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.2879524479
Directory	/workspace/0.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/0.uart_loopback.2497675118
Short name	T710
Test name
Test status
Simulation time	5830637859 ps
CPU time	5.09 seconds
Started	Apr 28 01:05:10 PM PDT 24
Finished	Apr 28 01:05:16 PM PDT 24
Peak memory	198788 kb
Host	smart-aafa3149-9350-4425-b6a1-26a72f71c211
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2497675118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.2497675118
Directory	/workspace/0.uart_loopback/latest

Test location	/workspace/coverage/default/0.uart_noise_filter.1737154769
Short name	T952
Test name
Test status
Simulation time	223386277587 ps
CPU time	128.5 seconds
Started	Apr 28 01:05:08 PM PDT 24
Finished	Apr 28 01:07:18 PM PDT 24
Peak memory	200692 kb
Host	smart-0cb9b219-44a6-4b5e-a384-67cf4eb8f5db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1737154769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.1737154769
Directory	/workspace/0.uart_noise_filter/latest

Test location	/workspace/coverage/default/0.uart_perf.1011066156
Short name	T961
Test name
Test status
Simulation time	4582235412 ps
CPU time	139.38 seconds
Started	Apr 28 01:05:10 PM PDT 24
Finished	Apr 28 01:07:31 PM PDT 24
Peak memory	200416 kb
Host	smart-2bb5bf3d-ea00-4009-b237-dbb310ce9768
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1011066156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.1011066156
Directory	/workspace/0.uart_perf/latest

Test location	/workspace/coverage/default/0.uart_rx_oversample.2510046634
Short name	T787
Test name
Test status
Simulation time	4092139062 ps
CPU time	15.39 seconds
Started	Apr 28 01:05:08 PM PDT 24
Finished	Apr 28 01:05:24 PM PDT 24
Peak memory	198536 kb
Host	smart-840cb7ef-a46c-43c3-8ba5-b3f8e0bf99ff
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2510046634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.2510046634
Directory	/workspace/0.uart_rx_oversample/latest

Test location	/workspace/coverage/default/0.uart_rx_parity_err.185777851
Short name	T299
Test name
Test status
Simulation time	68661159963 ps
CPU time	31.63 seconds
Started	Apr 28 01:05:10 PM PDT 24
Finished	Apr 28 01:05:42 PM PDT 24
Peak memory	200256 kb
Host	smart-70e7c8a5-01bd-43f8-8708-e43f2d87a2c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=185777851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.185777851
Directory	/workspace/0.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/0.uart_rx_start_bit_filter.3996285710
Short name	T772
Test name
Test status
Simulation time	4262413846 ps
CPU time	1.85 seconds
Started	Apr 28 01:05:10 PM PDT 24
Finished	Apr 28 01:05:13 PM PDT 24
Peak memory	196256 kb
Host	smart-64243597-0ede-4632-ba3e-b936bc42c792
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3996285710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.3996285710
Directory	/workspace/0.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/0.uart_sec_cm.2854878638
Short name	T101
Test name
Test status
Simulation time	667192529 ps
CPU time	0.89 seconds
Started	Apr 28 01:05:10 PM PDT 24
Finished	Apr 28 01:05:12 PM PDT 24
Peak memory	218796 kb
Host	smart-62696b54-aa5c-4624-9e1d-f39b27f76a7b
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854878638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.2854878638
Directory	/workspace/0.uart_sec_cm/latest

Test location	/workspace/coverage/default/0.uart_smoke.315096321
Short name	T49
Test name
Test status
Simulation time	692432407 ps
CPU time	3.4 seconds
Started	Apr 28 01:05:10 PM PDT 24
Finished	Apr 28 01:05:14 PM PDT 24
Peak memory	199872 kb
Host	smart-fbf08782-6d11-4789-9c2d-ba5922a24533
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=315096321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.315096321
Directory	/workspace/0.uart_smoke/latest

Test location	/workspace/coverage/default/0.uart_stress_all.502664430
Short name	T2
Test name
Test status
Simulation time	31691674484 ps
CPU time	43.91 seconds
Started	Apr 28 01:05:09 PM PDT 24
Finished	Apr 28 01:05:54 PM PDT 24
Peak memory	200388 kb
Host	smart-da73df96-22d9-4bb1-8f7b-c4a876bc5108
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502664430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.502664430
Directory	/workspace/0.uart_stress_all/latest

Test location	/workspace/coverage/default/0.uart_stress_all_with_rand_reset.3424675693
Short name	T61
Test name
Test status
Simulation time	384667673145 ps
CPU time	558.4 seconds
Started	Apr 28 01:05:12 PM PDT 24
Finished	Apr 28 01:14:32 PM PDT 24
Peak memory	208572 kb
Host	smart-e56b1f45-f218-434f-bc4f-e028645c6b07
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424675693 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.3424675693
Directory	/workspace/0.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/0.uart_tx_ovrd.3609998023
Short name	T1130
Test name
Test status
Simulation time	7075753345 ps
CPU time	13.75 seconds
Started	Apr 28 01:05:10 PM PDT 24
Finished	Apr 28 01:05:25 PM PDT 24
Peak memory	199496 kb
Host	smart-0500b04e-c621-43e7-a04f-54292c0be572
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3609998023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.3609998023
Directory	/workspace/0.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/1.uart_alert_test.2560278467
Short name	T782
Test name
Test status
Simulation time	33240656 ps
CPU time	0.55 seconds
Started	Apr 28 01:05:08 PM PDT 24
Finished	Apr 28 01:05:10 PM PDT 24
Peak memory	194668 kb
Host	smart-a047a4b1-9c7a-4b95-9a94-2060ad682a6f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560278467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.2560278467
Directory	/workspace/1.uart_alert_test/latest

Test location	/workspace/coverage/default/1.uart_fifo_full.841155820
Short name	T538
Test name
Test status
Simulation time	235283936400 ps
CPU time	827.5 seconds
Started	Apr 28 01:05:16 PM PDT 24
Finished	Apr 28 01:19:04 PM PDT 24
Peak memory	200380 kb
Host	smart-158b40b1-0c78-453e-98e8-aabd2a0ffb44
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=841155820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.841155820
Directory	/workspace/1.uart_fifo_full/latest

Test location	/workspace/coverage/default/1.uart_fifo_overflow.2862124160
Short name	T881
Test name
Test status
Simulation time	23702320197 ps
CPU time	23.44 seconds
Started	Apr 28 01:05:11 PM PDT 24
Finished	Apr 28 01:05:35 PM PDT 24
Peak memory	200448 kb
Host	smart-4ed26f41-cca5-4e9b-a300-b70cf42d49f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2862124160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.2862124160
Directory	/workspace/1.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/1.uart_fifo_reset.133818932
Short name	T350
Test name
Test status
Simulation time	40984643346 ps
CPU time	66.57 seconds
Started	Apr 28 01:05:10 PM PDT 24
Finished	Apr 28 01:06:18 PM PDT 24
Peak memory	200384 kb
Host	smart-c8a590b2-b6f5-46c0-8ed4-faa84fc55ad9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=133818932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.133818932
Directory	/workspace/1.uart_fifo_reset/latest

Test location	/workspace/coverage/default/1.uart_intr.3102284476
Short name	T853
Test name
Test status
Simulation time	20163148841 ps
CPU time	38.33 seconds
Started	Apr 28 01:05:11 PM PDT 24
Finished	Apr 28 01:05:50 PM PDT 24
Peak memory	200260 kb
Host	smart-f4d46a84-517e-491d-9980-427bf1843afe
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102284476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.3102284476
Directory	/workspace/1.uart_intr/latest

Test location	/workspace/coverage/default/1.uart_long_xfer_wo_dly.1208455212
Short name	T426
Test name
Test status
Simulation time	189301397155 ps
CPU time	180.22 seconds
Started	Apr 28 01:05:10 PM PDT 24
Finished	Apr 28 01:08:12 PM PDT 24
Peak memory	200036 kb
Host	smart-0106e93f-a66a-4891-926f-515b7d2211dc
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1208455212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.1208455212
Directory	/workspace/1.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/1.uart_loopback.421706255
Short name	T857
Test name
Test status
Simulation time	4169330681 ps
CPU time	3.94 seconds
Started	Apr 28 01:05:10 PM PDT 24
Finished	Apr 28 01:05:15 PM PDT 24
Peak memory	198840 kb
Host	smart-b730e41c-561c-47f1-ac07-347c70a1e5cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=421706255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.421706255
Directory	/workspace/1.uart_loopback/latest

Test location	/workspace/coverage/default/1.uart_noise_filter.3026271520
Short name	T1173
Test name
Test status
Simulation time	29449020407 ps
CPU time	26.76 seconds
Started	Apr 28 01:05:13 PM PDT 24
Finished	Apr 28 01:05:41 PM PDT 24
Peak memory	200272 kb
Host	smart-bf84a9bc-f2ec-49d3-b31d-85c6fd725278
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3026271520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.3026271520
Directory	/workspace/1.uart_noise_filter/latest

Test location	/workspace/coverage/default/1.uart_perf.2229596599
Short name	T311
Test name
Test status
Simulation time	11300216233 ps
CPU time	716.2 seconds
Started	Apr 28 01:05:15 PM PDT 24
Finished	Apr 28 01:17:12 PM PDT 24
Peak memory	200416 kb
Host	smart-ee110da0-e436-4228-b3fe-ec3adb10dbd1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2229596599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.2229596599
Directory	/workspace/1.uart_perf/latest

Test location	/workspace/coverage/default/1.uart_rx_oversample.3418184396
Short name	T655
Test name
Test status
Simulation time	3575191596 ps
CPU time	7.49 seconds
Started	Apr 28 01:05:11 PM PDT 24
Finished	Apr 28 01:05:19 PM PDT 24
Peak memory	199308 kb
Host	smart-4d0aa467-97a5-4d35-af2f-390cf3941eaf
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3418184396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.3418184396
Directory	/workspace/1.uart_rx_oversample/latest

Test location	/workspace/coverage/default/1.uart_rx_parity_err.373495927
Short name	T1009
Test name
Test status
Simulation time	25760727302 ps
CPU time	37.99 seconds
Started	Apr 28 01:05:11 PM PDT 24
Finished	Apr 28 01:05:50 PM PDT 24
Peak memory	199452 kb
Host	smart-5d0ee26c-b22d-4fff-ba46-b7a2d5760f4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=373495927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.373495927
Directory	/workspace/1.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/1.uart_rx_start_bit_filter.523637398
Short name	T1071
Test name
Test status
Simulation time	5715420934 ps
CPU time	2.46 seconds
Started	Apr 28 01:05:08 PM PDT 24
Finished	Apr 28 01:05:12 PM PDT 24
Peak memory	196444 kb
Host	smart-63f7c15a-c69c-443a-ada1-e320e6645ea8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=523637398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.523637398
Directory	/workspace/1.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/1.uart_sec_cm.3203654005
Short name	T27
Test name
Test status
Simulation time	135407441 ps
CPU time	0.77 seconds
Started	Apr 28 01:05:05 PM PDT 24
Finished	Apr 28 01:05:08 PM PDT 24
Peak memory	218608 kb
Host	smart-153c705e-f4b9-46f2-80f4-fa3dd7663f19
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203654005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.3203654005
Directory	/workspace/1.uart_sec_cm/latest

Test location	/workspace/coverage/default/1.uart_smoke.4011601413
Short name	T704
Test name
Test status
Simulation time	682908803 ps
CPU time	2.03 seconds
Started	Apr 28 01:05:16 PM PDT 24
Finished	Apr 28 01:05:18 PM PDT 24
Peak memory	199144 kb
Host	smart-377e4171-07c7-4b87-a3e0-43c26b340c9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4011601413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.4011601413
Directory	/workspace/1.uart_smoke/latest

Test location	/workspace/coverage/default/1.uart_stress_all.1500586847
Short name	T224
Test name
Test status
Simulation time	243809983826 ps
CPU time	521.63 seconds
Started	Apr 28 01:05:09 PM PDT 24
Finished	Apr 28 01:13:51 PM PDT 24
Peak memory	200348 kb
Host	smart-d323ae8c-b7d2-45ac-9254-594ebcb35f9c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500586847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.1500586847
Directory	/workspace/1.uart_stress_all/latest

Test location	/workspace/coverage/default/1.uart_stress_all_with_rand_reset.686290521
Short name	T666
Test name
Test status
Simulation time	33920171939 ps
CPU time	505.06 seconds
Started	Apr 28 01:05:11 PM PDT 24
Finished	Apr 28 01:13:38 PM PDT 24
Peak memory	216940 kb
Host	smart-73854cc0-9d53-45fe-8eb9-7cc8a6b5c2d1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686290521 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.686290521
Directory	/workspace/1.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.uart_tx_ovrd.3994022052
Short name	T1006
Test name
Test status
Simulation time	714205519 ps
CPU time	2.6 seconds
Started	Apr 28 01:05:11 PM PDT 24
Finished	Apr 28 01:05:15 PM PDT 24
Peak memory	199396 kb
Host	smart-b1a70530-3a3b-4f71-8668-60f3f0fecb9f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3994022052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.3994022052
Directory	/workspace/1.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/1.uart_tx_rx.1560272028
Short name	T548
Test name
Test status
Simulation time	88003034506 ps
CPU time	151.71 seconds
Started	Apr 28 01:05:11 PM PDT 24
Finished	Apr 28 01:07:44 PM PDT 24
Peak memory	200364 kb
Host	smart-1904c6b2-8a8b-4a31-adbd-a2b02d7341c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1560272028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.1560272028
Directory	/workspace/1.uart_tx_rx/latest

Test location	/workspace/coverage/default/10.uart_alert_test.34942207
Short name	T1139
Test name
Test status
Simulation time	16825614 ps
CPU time	0.57 seconds
Started	Apr 28 01:05:36 PM PDT 24
Finished	Apr 28 01:05:37 PM PDT 24
Peak memory	195796 kb
Host	smart-159659c0-aee9-4435-9d7d-a51bafe5ed76
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34942207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.34942207
Directory	/workspace/10.uart_alert_test/latest

Test location	/workspace/coverage/default/10.uart_fifo_full.4205635527
Short name	T36
Test name
Test status
Simulation time	41829679285 ps
CPU time	35.03 seconds
Started	Apr 28 01:05:34 PM PDT 24
Finished	Apr 28 01:06:10 PM PDT 24
Peak memory	200436 kb
Host	smart-f19850c6-7ea3-4064-ab9b-4d24ca793e96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4205635527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.4205635527
Directory	/workspace/10.uart_fifo_full/latest

Test location	/workspace/coverage/default/10.uart_fifo_overflow.1403369645
Short name	T531
Test name
Test status
Simulation time	16097718444 ps
CPU time	36.18 seconds
Started	Apr 28 01:05:32 PM PDT 24
Finished	Apr 28 01:06:09 PM PDT 24
Peak memory	200324 kb
Host	smart-1150f980-eb0c-460f-a26e-68c848810422
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1403369645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.1403369645
Directory	/workspace/10.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/10.uart_fifo_reset.1184822521
Short name	T506
Test name
Test status
Simulation time	71452623919 ps
CPU time	138.89 seconds
Started	Apr 28 01:05:33 PM PDT 24
Finished	Apr 28 01:07:52 PM PDT 24
Peak memory	200300 kb
Host	smart-b4e012f3-a3e3-4752-995c-6dce0c9ff910
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1184822521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.1184822521
Directory	/workspace/10.uart_fifo_reset/latest

Test location	/workspace/coverage/default/10.uart_intr.1350754021
Short name	T279
Test name
Test status
Simulation time	22853775559 ps
CPU time	10.8 seconds
Started	Apr 28 01:05:31 PM PDT 24
Finished	Apr 28 01:05:42 PM PDT 24
Peak memory	199372 kb
Host	smart-146bd788-89aa-42a1-883e-745d1215d2b3
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350754021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.1350754021
Directory	/workspace/10.uart_intr/latest

Test location	/workspace/coverage/default/10.uart_long_xfer_wo_dly.3247176980
Short name	T727
Test name
Test status
Simulation time	45348229892 ps
CPU time	199.52 seconds
Started	Apr 28 01:05:38 PM PDT 24
Finished	Apr 28 01:08:58 PM PDT 24
Peak memory	200292 kb
Host	smart-160f113a-58e6-43fa-944f-b726edc16e3d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3247176980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.3247176980
Directory	/workspace/10.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/10.uart_loopback.2129707620
Short name	T726
Test name
Test status
Simulation time	10021366268 ps
CPU time	9.5 seconds
Started	Apr 28 01:05:32 PM PDT 24
Finished	Apr 28 01:05:42 PM PDT 24
Peak memory	199212 kb
Host	smart-9c725c36-6c66-4a6e-8a88-5f84980ceb68
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2129707620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.2129707620
Directory	/workspace/10.uart_loopback/latest

Test location	/workspace/coverage/default/10.uart_noise_filter.4068545319
Short name	T1153
Test name
Test status
Simulation time	111464954070 ps
CPU time	233.87 seconds
Started	Apr 28 01:05:30 PM PDT 24
Finished	Apr 28 01:09:25 PM PDT 24
Peak memory	200384 kb
Host	smart-f58090d2-9880-4036-b8ee-9085e4ac3254
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4068545319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.4068545319
Directory	/workspace/10.uart_noise_filter/latest

Test location	/workspace/coverage/default/10.uart_perf.168493517
Short name	T1108
Test name
Test status
Simulation time	11270904481 ps
CPU time	629.99 seconds
Started	Apr 28 01:05:34 PM PDT 24
Finished	Apr 28 01:16:05 PM PDT 24
Peak memory	200428 kb
Host	smart-85e2dca6-a1b2-4c14-9c02-598e0a986e62
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=168493517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.168493517
Directory	/workspace/10.uart_perf/latest

Test location	/workspace/coverage/default/10.uart_rx_oversample.1287618809
Short name	T886
Test name
Test status
Simulation time	4210498839 ps
CPU time	8.25 seconds
Started	Apr 28 01:05:35 PM PDT 24
Finished	Apr 28 01:05:43 PM PDT 24
Peak memory	199636 kb
Host	smart-7248b744-0dd0-44d1-a56b-db0e380fa3df
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1287618809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.1287618809
Directory	/workspace/10.uart_rx_oversample/latest

Test location	/workspace/coverage/default/10.uart_rx_parity_err.1425718511
Short name	T818
Test name
Test status
Simulation time	36788902011 ps
CPU time	15.13 seconds
Started	Apr 28 01:05:30 PM PDT 24
Finished	Apr 28 01:05:45 PM PDT 24
Peak memory	200404 kb
Host	smart-0735bcc4-e067-44b1-9908-acc08b66693e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1425718511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.1425718511
Directory	/workspace/10.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/10.uart_rx_start_bit_filter.2121621490
Short name	T1086
Test name
Test status
Simulation time	1665668356 ps
CPU time	1.32 seconds
Started	Apr 28 01:05:32 PM PDT 24
Finished	Apr 28 01:05:34 PM PDT 24
Peak memory	195732 kb
Host	smart-5da668df-3a6b-46f4-906e-b74de34e3690
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2121621490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.2121621490
Directory	/workspace/10.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/10.uart_smoke.4215387855
Short name	T748
Test name
Test status
Simulation time	290486020 ps
CPU time	1.57 seconds
Started	Apr 28 01:05:32 PM PDT 24
Finished	Apr 28 01:05:34 PM PDT 24
Peak memory	198608 kb
Host	smart-1c2f2356-cc3e-46ae-88cb-dae93b059b3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4215387855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.4215387855
Directory	/workspace/10.uart_smoke/latest

Test location	/workspace/coverage/default/10.uart_stress_all.2630886581
Short name	T622
Test name
Test status
Simulation time	273762521103 ps
CPU time	73.09 seconds
Started	Apr 28 01:05:39 PM PDT 24
Finished	Apr 28 01:06:52 PM PDT 24
Peak memory	200432 kb
Host	smart-914626a0-5817-402d-a35d-fc921fa552a7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630886581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.2630886581
Directory	/workspace/10.uart_stress_all/latest

Test location	/workspace/coverage/default/10.uart_stress_all_with_rand_reset.347202392
Short name	T614
Test name
Test status
Simulation time	72253603907 ps
CPU time	640.87 seconds
Started	Apr 28 01:05:36 PM PDT 24
Finished	Apr 28 01:16:17 PM PDT 24
Peak memory	216872 kb
Host	smart-218843fc-9652-41b8-ba2d-778e6135b9ee
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347202392 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.347202392
Directory	/workspace/10.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/10.uart_tx_ovrd.3567744446
Short name	T688
Test name
Test status
Simulation time	407187783 ps
CPU time	1.33 seconds
Started	Apr 28 01:05:32 PM PDT 24
Finished	Apr 28 01:05:34 PM PDT 24
Peak memory	198204 kb
Host	smart-21d100fc-716a-41f4-b13b-addb82a0518c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3567744446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.3567744446
Directory	/workspace/10.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/10.uart_tx_rx.1377930947
Short name	T673
Test name
Test status
Simulation time	72747210928 ps
CPU time	18.21 seconds
Started	Apr 28 01:05:33 PM PDT 24
Finished	Apr 28 01:05:52 PM PDT 24
Peak memory	200376 kb
Host	smart-d13e2d0d-de37-4772-a115-79564fe64fa4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1377930947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.1377930947
Directory	/workspace/10.uart_tx_rx/latest

Test location	/workspace/coverage/default/100.uart_fifo_reset.694553389
Short name	T593
Test name
Test status
Simulation time	160635828998 ps
CPU time	283.41 seconds
Started	Apr 28 01:09:29 PM PDT 24
Finished	Apr 28 01:14:13 PM PDT 24
Peak memory	200468 kb
Host	smart-1d76bffd-9e7c-425a-8fdc-afcb83fa5e7d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=694553389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.694553389
Directory	/workspace/100.uart_fifo_reset/latest

Test location	/workspace/coverage/default/102.uart_fifo_reset.3264560010
Short name	T978
Test name
Test status
Simulation time	25514547934 ps
CPU time	45.58 seconds
Started	Apr 28 01:09:32 PM PDT 24
Finished	Apr 28 01:10:18 PM PDT 24
Peak memory	200440 kb
Host	smart-2a95b1a6-2787-430e-bb63-04a5cdd40181
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3264560010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.3264560010
Directory	/workspace/102.uart_fifo_reset/latest

Test location	/workspace/coverage/default/103.uart_fifo_reset.998050796
Short name	T912
Test name
Test status
Simulation time	43445309139 ps
CPU time	75.92 seconds
Started	Apr 28 01:09:29 PM PDT 24
Finished	Apr 28 01:10:45 PM PDT 24
Peak memory	200404 kb
Host	smart-e2fe6ab1-aec0-493c-85dd-0b5cfd7bc59a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=998050796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.998050796
Directory	/workspace/103.uart_fifo_reset/latest

Test location	/workspace/coverage/default/104.uart_fifo_reset.1296457119
Short name	T1033
Test name
Test status
Simulation time	126171848201 ps
CPU time	120.6 seconds
Started	Apr 28 01:09:30 PM PDT 24
Finished	Apr 28 01:11:31 PM PDT 24
Peak memory	200428 kb
Host	smart-96011816-c49e-4b20-8feb-a36ceb863108
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1296457119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.1296457119
Directory	/workspace/104.uart_fifo_reset/latest

Test location	/workspace/coverage/default/105.uart_fifo_reset.655192199
Short name	T1011
Test name
Test status
Simulation time	17135731572 ps
CPU time	26.31 seconds
Started	Apr 28 01:09:29 PM PDT 24
Finished	Apr 28 01:09:55 PM PDT 24
Peak memory	200260 kb
Host	smart-0137cbbc-860f-4134-bdd9-fc0c86a4ba99
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=655192199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.655192199
Directory	/workspace/105.uart_fifo_reset/latest

Test location	/workspace/coverage/default/106.uart_fifo_reset.3053928244
Short name	T851
Test name
Test status
Simulation time	98223007686 ps
CPU time	88.4 seconds
Started	Apr 28 01:09:32 PM PDT 24
Finished	Apr 28 01:11:01 PM PDT 24
Peak memory	200308 kb
Host	smart-aab15f9f-13c1-4867-9884-a5bbd600e531
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3053928244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.3053928244
Directory	/workspace/106.uart_fifo_reset/latest

Test location	/workspace/coverage/default/107.uart_fifo_reset.355231856
Short name	T1105
Test name
Test status
Simulation time	39612660721 ps
CPU time	9.99 seconds
Started	Apr 28 01:09:29 PM PDT 24
Finished	Apr 28 01:09:40 PM PDT 24
Peak memory	200244 kb
Host	smart-7a9f064c-f22b-4457-b95d-53cdd3cbbe02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=355231856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.355231856
Directory	/workspace/107.uart_fifo_reset/latest

Test location	/workspace/coverage/default/108.uart_fifo_reset.3614601093
Short name	T217
Test name
Test status
Simulation time	30345863434 ps
CPU time	53.17 seconds
Started	Apr 28 01:09:29 PM PDT 24
Finished	Apr 28 01:10:22 PM PDT 24
Peak memory	200432 kb
Host	smart-106fa9da-b17c-4169-b71f-562a968e2994
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3614601093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.3614601093
Directory	/workspace/108.uart_fifo_reset/latest

Test location	/workspace/coverage/default/109.uart_fifo_reset.3159465778
Short name	T1044
Test name
Test status
Simulation time	6098069364 ps
CPU time	3.28 seconds
Started	Apr 28 01:09:29 PM PDT 24
Finished	Apr 28 01:09:33 PM PDT 24
Peak memory	199136 kb
Host	smart-ede2af50-a26a-4579-ac37-a123f9f87ce4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3159465778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.3159465778
Directory	/workspace/109.uart_fifo_reset/latest

Test location	/workspace/coverage/default/11.uart_alert_test.809793472
Short name	T829
Test name
Test status
Simulation time	11837371 ps
CPU time	0.56 seconds
Started	Apr 28 01:05:36 PM PDT 24
Finished	Apr 28 01:05:38 PM PDT 24
Peak memory	195108 kb
Host	smart-4396d0fc-31e1-43ea-a8e8-46045223c3ac
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809793472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.809793472
Directory	/workspace/11.uart_alert_test/latest

Test location	/workspace/coverage/default/11.uart_fifo_full.2885510708
Short name	T478
Test name
Test status
Simulation time	108881466191 ps
CPU time	47.26 seconds
Started	Apr 28 01:05:38 PM PDT 24
Finished	Apr 28 01:06:26 PM PDT 24
Peak memory	200416 kb
Host	smart-f55720c1-1617-46fd-9d70-9d15a4cc4206
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2885510708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.2885510708
Directory	/workspace/11.uart_fifo_full/latest

Test location	/workspace/coverage/default/11.uart_fifo_overflow.3832919978
Short name	T419
Test name
Test status
Simulation time	152635789878 ps
CPU time	62.8 seconds
Started	Apr 28 01:05:43 PM PDT 24
Finished	Apr 28 01:06:47 PM PDT 24
Peak memory	200376 kb
Host	smart-ff303334-6135-4eb9-bea0-c7476be4564f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3832919978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.3832919978
Directory	/workspace/11.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/11.uart_fifo_reset.1373483910
Short name	T634
Test name
Test status
Simulation time	54664824781 ps
CPU time	85.44 seconds
Started	Apr 28 01:05:37 PM PDT 24
Finished	Apr 28 01:07:04 PM PDT 24
Peak memory	200392 kb
Host	smart-ab7e3345-df1a-4f1f-863f-f8b632cc1043
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1373483910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.1373483910
Directory	/workspace/11.uart_fifo_reset/latest

Test location	/workspace/coverage/default/11.uart_intr.1918962896
Short name	T821
Test name
Test status
Simulation time	37352461675 ps
CPU time	78.85 seconds
Started	Apr 28 01:05:38 PM PDT 24
Finished	Apr 28 01:06:58 PM PDT 24
Peak memory	200396 kb
Host	smart-59f12ba6-e207-489c-bb23-38994ba8030e
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918962896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.1918962896
Directory	/workspace/11.uart_intr/latest

Test location	/workspace/coverage/default/11.uart_long_xfer_wo_dly.1978747191
Short name	T940
Test name
Test status
Simulation time	85272725573 ps
CPU time	169.42 seconds
Started	Apr 28 01:05:40 PM PDT 24
Finished	Apr 28 01:08:30 PM PDT 24
Peak memory	200372 kb
Host	smart-18a25b82-e70f-4eee-abba-1d2fe0e16062
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1978747191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.1978747191
Directory	/workspace/11.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/11.uart_loopback.1434351275
Short name	T947
Test name
Test status
Simulation time	1287770752 ps
CPU time	3.14 seconds
Started	Apr 28 01:05:38 PM PDT 24
Finished	Apr 28 01:05:42 PM PDT 24
Peak memory	199620 kb
Host	smart-7605663d-69aa-4e45-8415-d39335df934f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1434351275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.1434351275
Directory	/workspace/11.uart_loopback/latest

Test location	/workspace/coverage/default/11.uart_noise_filter.273487831
Short name	T865
Test name
Test status
Simulation time	70579963116 ps
CPU time	108.51 seconds
Started	Apr 28 01:05:36 PM PDT 24
Finished	Apr 28 01:07:25 PM PDT 24
Peak memory	200576 kb
Host	smart-b48f30a0-7e5c-457d-a901-6b8b2a41bb6d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=273487831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.273487831
Directory	/workspace/11.uart_noise_filter/latest

Test location	/workspace/coverage/default/11.uart_perf.2314288587
Short name	T487
Test name
Test status
Simulation time	8279674982 ps
CPU time	81.2 seconds
Started	Apr 28 01:05:36 PM PDT 24
Finished	Apr 28 01:06:58 PM PDT 24
Peak memory	200256 kb
Host	smart-77eb326a-8dab-449c-916b-dbeb63298883
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2314288587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.2314288587
Directory	/workspace/11.uart_perf/latest

Test location	/workspace/coverage/default/11.uart_rx_oversample.1775982192
Short name	T849
Test name
Test status
Simulation time	7437492955 ps
CPU time	74.14 seconds
Started	Apr 28 01:05:36 PM PDT 24
Finished	Apr 28 01:06:52 PM PDT 24
Peak memory	199760 kb
Host	smart-f72a3e0e-acff-420a-995d-465d445fbca1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1775982192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.1775982192
Directory	/workspace/11.uart_rx_oversample/latest

Test location	/workspace/coverage/default/11.uart_rx_parity_err.2530903513
Short name	T286
Test name
Test status
Simulation time	167034368925 ps
CPU time	116.14 seconds
Started	Apr 28 01:05:38 PM PDT 24
Finished	Apr 28 01:07:35 PM PDT 24
Peak memory	200392 kb
Host	smart-72dbf4bf-8721-410c-bfae-bfd4a7ab9e74
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2530903513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.2530903513
Directory	/workspace/11.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/11.uart_rx_start_bit_filter.1140021391
Short name	T904
Test name
Test status
Simulation time	3400369649 ps
CPU time	5.65 seconds
Started	Apr 28 01:05:36 PM PDT 24
Finished	Apr 28 01:05:43 PM PDT 24
Peak memory	196244 kb
Host	smart-afbf336c-efdd-405d-a4cc-eeb4d4a3e0b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1140021391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.1140021391
Directory	/workspace/11.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/11.uart_smoke.2622619517
Short name	T338
Test name
Test status
Simulation time	128566751 ps
CPU time	1 seconds
Started	Apr 28 01:05:44 PM PDT 24
Finished	Apr 28 01:05:46 PM PDT 24
Peak memory	198952 kb
Host	smart-3624794a-7e3c-4a41-8856-47917c991ee0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2622619517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.2622619517
Directory	/workspace/11.uart_smoke/latest

Test location	/workspace/coverage/default/11.uart_stress_all.850436728
Short name	T524
Test name
Test status
Simulation time	189997843758 ps
CPU time	183.73 seconds
Started	Apr 28 01:05:36 PM PDT 24
Finished	Apr 28 01:08:41 PM PDT 24
Peak memory	200688 kb
Host	smart-5aa67f70-038e-44ab-927f-37893f0b81f6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850436728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.850436728
Directory	/workspace/11.uart_stress_all/latest

Test location	/workspace/coverage/default/11.uart_stress_all_with_rand_reset.1650636514
Short name	T805
Test name
Test status
Simulation time	392442786728 ps
CPU time	1526.73 seconds
Started	Apr 28 01:05:42 PM PDT 24
Finished	Apr 28 01:31:11 PM PDT 24
Peak memory	225364 kb
Host	smart-4989e6bb-4e7a-479a-87cb-0afde57ef561
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650636514 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.1650636514
Directory	/workspace/11.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/11.uart_tx_ovrd.2431347711
Short name	T642
Test name
Test status
Simulation time	768717593 ps
CPU time	2.37 seconds
Started	Apr 28 01:05:37 PM PDT 24
Finished	Apr 28 01:05:40 PM PDT 24
Peak memory	199776 kb
Host	smart-92466441-6b02-46f3-9351-3c3837a3e75f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2431347711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.2431347711
Directory	/workspace/11.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/11.uart_tx_rx.551956614
Short name	T295
Test name
Test status
Simulation time	40795589196 ps
CPU time	16.36 seconds
Started	Apr 28 01:05:36 PM PDT 24
Finished	Apr 28 01:05:53 PM PDT 24
Peak memory	200368 kb
Host	smart-9843b08b-fe79-41d3-afaa-cfcbea4ef6d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=551956614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.551956614
Directory	/workspace/11.uart_tx_rx/latest

Test location	/workspace/coverage/default/110.uart_fifo_reset.217586512
Short name	T162
Test name
Test status
Simulation time	77486681704 ps
CPU time	30.94 seconds
Started	Apr 28 01:09:30 PM PDT 24
Finished	Apr 28 01:10:01 PM PDT 24
Peak memory	200436 kb
Host	smart-b2b19ec6-b907-46d5-b9e0-fce4d69f284c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=217586512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.217586512
Directory	/workspace/110.uart_fifo_reset/latest

Test location	/workspace/coverage/default/112.uart_fifo_reset.2540159808
Short name	T810
Test name
Test status
Simulation time	66075345339 ps
CPU time	27.56 seconds
Started	Apr 28 01:09:30 PM PDT 24
Finished	Apr 28 01:09:58 PM PDT 24
Peak memory	200308 kb
Host	smart-fe16a224-5800-40f8-ae7f-843c6ebd8c5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2540159808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.2540159808
Directory	/workspace/112.uart_fifo_reset/latest

Test location	/workspace/coverage/default/113.uart_fifo_reset.433042624
Short name	T1138
Test name
Test status
Simulation time	16805661907 ps
CPU time	47.56 seconds
Started	Apr 28 01:09:30 PM PDT 24
Finished	Apr 28 01:10:18 PM PDT 24
Peak memory	200308 kb
Host	smart-9bc79b49-be1e-4b15-b314-96a638c8b035
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=433042624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.433042624
Directory	/workspace/113.uart_fifo_reset/latest

Test location	/workspace/coverage/default/115.uart_fifo_reset.3463508793
Short name	T763
Test name
Test status
Simulation time	156651771453 ps
CPU time	44.7 seconds
Started	Apr 28 01:09:31 PM PDT 24
Finished	Apr 28 01:10:17 PM PDT 24
Peak memory	200328 kb
Host	smart-5cd30748-3b35-4e08-8e84-4e9cc8cb0eda
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3463508793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.3463508793
Directory	/workspace/115.uart_fifo_reset/latest

Test location	/workspace/coverage/default/116.uart_fifo_reset.1535548345
Short name	T161
Test name
Test status
Simulation time	108828862388 ps
CPU time	36.81 seconds
Started	Apr 28 01:09:31 PM PDT 24
Finished	Apr 28 01:10:08 PM PDT 24
Peak memory	200436 kb
Host	smart-d5e34199-795e-4c3a-b6c5-92040b644328
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1535548345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.1535548345
Directory	/workspace/116.uart_fifo_reset/latest

Test location	/workspace/coverage/default/117.uart_fifo_reset.316538968
Short name	T324
Test name
Test status
Simulation time	69991863240 ps
CPU time	43.65 seconds
Started	Apr 28 01:09:36 PM PDT 24
Finished	Apr 28 01:10:21 PM PDT 24
Peak memory	200444 kb
Host	smart-9a66f33c-f5bb-47e0-ba78-85d46bbd53dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=316538968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.316538968
Directory	/workspace/117.uart_fifo_reset/latest

Test location	/workspace/coverage/default/118.uart_fifo_reset.865354870
Short name	T599
Test name
Test status
Simulation time	32823306051 ps
CPU time	14.67 seconds
Started	Apr 28 01:09:34 PM PDT 24
Finished	Apr 28 01:09:49 PM PDT 24
Peak memory	200168 kb
Host	smart-19d90a88-9036-4ff5-8264-2d48ca6f2f07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=865354870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.865354870
Directory	/workspace/118.uart_fifo_reset/latest

Test location	/workspace/coverage/default/119.uart_fifo_reset.1832662627
Short name	T460
Test name
Test status
Simulation time	9426246688 ps
CPU time	14.64 seconds
Started	Apr 28 01:09:35 PM PDT 24
Finished	Apr 28 01:09:50 PM PDT 24
Peak memory	200344 kb
Host	smart-782357e5-9fe1-42bb-b7bb-89a52376510b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1832662627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.1832662627
Directory	/workspace/119.uart_fifo_reset/latest

Test location	/workspace/coverage/default/12.uart_alert_test.3966951111
Short name	T529
Test name
Test status
Simulation time	13872542 ps
CPU time	0.55 seconds
Started	Apr 28 01:05:40 PM PDT 24
Finished	Apr 28 01:05:41 PM PDT 24
Peak memory	195792 kb
Host	smart-3242930b-ce57-4354-a61e-0c828721098d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966951111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.3966951111
Directory	/workspace/12.uart_alert_test/latest

Test location	/workspace/coverage/default/12.uart_fifo_full.1395544304
Short name	T734
Test name
Test status
Simulation time	67443356782 ps
CPU time	18.29 seconds
Started	Apr 28 01:05:37 PM PDT 24
Finished	Apr 28 01:05:56 PM PDT 24
Peak memory	200052 kb
Host	smart-954230c8-f147-4043-97d2-9d00732098a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1395544304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.1395544304
Directory	/workspace/12.uart_fifo_full/latest

Test location	/workspace/coverage/default/12.uart_fifo_overflow.1406535877
Short name	T312
Test name
Test status
Simulation time	198036916293 ps
CPU time	223.43 seconds
Started	Apr 28 01:05:39 PM PDT 24
Finished	Apr 28 01:09:23 PM PDT 24
Peak memory	200248 kb
Host	smart-9418833f-6e50-4f6b-89ce-a15bcefe2e2a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1406535877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.1406535877
Directory	/workspace/12.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/12.uart_fifo_reset.1215494248
Short name	T1024
Test name
Test status
Simulation time	43160232871 ps
CPU time	19.58 seconds
Started	Apr 28 01:05:40 PM PDT 24
Finished	Apr 28 01:06:00 PM PDT 24
Peak memory	200348 kb
Host	smart-dcc95296-b95a-40a9-b432-ef85571addbd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1215494248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.1215494248
Directory	/workspace/12.uart_fifo_reset/latest

Test location	/workspace/coverage/default/12.uart_intr.3992311604
Short name	T418
Test name
Test status
Simulation time	364265892569 ps
CPU time	140.74 seconds
Started	Apr 28 01:05:37 PM PDT 24
Finished	Apr 28 01:07:59 PM PDT 24
Peak memory	199644 kb
Host	smart-d1e10dc5-15c2-49cc-a43d-fd874f9c750c
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992311604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.3992311604
Directory	/workspace/12.uart_intr/latest

Test location	/workspace/coverage/default/12.uart_long_xfer_wo_dly.1295664531
Short name	T511
Test name
Test status
Simulation time	165493925160 ps
CPU time	401.55 seconds
Started	Apr 28 01:05:38 PM PDT 24
Finished	Apr 28 01:12:20 PM PDT 24
Peak memory	200440 kb
Host	smart-479e126f-6f3e-4257-a798-ee0033813fc8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1295664531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1295664531
Directory	/workspace/12.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/12.uart_loopback.3451875751
Short name	T1034
Test name
Test status
Simulation time	9139105184 ps
CPU time	2.9 seconds
Started	Apr 28 01:05:36 PM PDT 24
Finished	Apr 28 01:05:39 PM PDT 24
Peak memory	200456 kb
Host	smart-69a73c46-409b-4e15-a6e6-f80a7bc6e518
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3451875751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.3451875751
Directory	/workspace/12.uart_loopback/latest

Test location	/workspace/coverage/default/12.uart_noise_filter.3556514911
Short name	T1170
Test name
Test status
Simulation time	59851863444 ps
CPU time	105.41 seconds
Started	Apr 28 01:05:37 PM PDT 24
Finished	Apr 28 01:07:24 PM PDT 24
Peak memory	200556 kb
Host	smart-4cd345e8-75f3-43d0-b0c0-59eabbd3118a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3556514911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.3556514911
Directory	/workspace/12.uart_noise_filter/latest

Test location	/workspace/coverage/default/12.uart_perf.1700132407
Short name	T987
Test name
Test status
Simulation time	22021156956 ps
CPU time	233.18 seconds
Started	Apr 28 01:05:37 PM PDT 24
Finished	Apr 28 01:09:31 PM PDT 24
Peak memory	200432 kb
Host	smart-66a14446-7dd5-4c22-b88e-36785ef5b2b5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1700132407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.1700132407
Directory	/workspace/12.uart_perf/latest

Test location	/workspace/coverage/default/12.uart_rx_oversample.2881925672
Short name	T510
Test name
Test status
Simulation time	2541674919 ps
CPU time	6.44 seconds
Started	Apr 28 01:05:41 PM PDT 24
Finished	Apr 28 01:05:49 PM PDT 24
Peak memory	198736 kb
Host	smart-11206f3f-53b1-480e-a68c-8ad9fb610d6f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2881925672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.2881925672
Directory	/workspace/12.uart_rx_oversample/latest

Test location	/workspace/coverage/default/12.uart_rx_parity_err.1300276985
Short name	T985
Test name
Test status
Simulation time	27377589037 ps
CPU time	26.81 seconds
Started	Apr 28 01:05:42 PM PDT 24
Finished	Apr 28 01:06:10 PM PDT 24
Peak memory	200328 kb
Host	smart-3716d0c6-5322-4ddf-8f6b-708cee96d082
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1300276985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.1300276985
Directory	/workspace/12.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/12.uart_rx_start_bit_filter.1752078564
Short name	T907
Test name
Test status
Simulation time	3958927343 ps
CPU time	5.8 seconds
Started	Apr 28 01:05:40 PM PDT 24
Finished	Apr 28 01:05:46 PM PDT 24
Peak memory	196412 kb
Host	smart-da96c1d6-709d-43a7-87cb-14058d3e174b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1752078564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.1752078564
Directory	/workspace/12.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/12.uart_smoke.1851602404
Short name	T651
Test name
Test status
Simulation time	6102559001 ps
CPU time	6.95 seconds
Started	Apr 28 01:05:44 PM PDT 24
Finished	Apr 28 01:05:52 PM PDT 24
Peak memory	200072 kb
Host	smart-11a0cd80-2cac-4273-a3cb-4ec25bcbe7ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1851602404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.1851602404
Directory	/workspace/12.uart_smoke/latest

Test location	/workspace/coverage/default/12.uart_stress_all.1726312520
Short name	T1064
Test name
Test status
Simulation time	114959944993 ps
CPU time	39.61 seconds
Started	Apr 28 01:05:37 PM PDT 24
Finished	Apr 28 01:06:17 PM PDT 24
Peak memory	200304 kb
Host	smart-e99994b1-14c2-4fe7-b688-32d3f8c5edcf
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726312520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.1726312520
Directory	/workspace/12.uart_stress_all/latest

Test location	/workspace/coverage/default/12.uart_stress_all_with_rand_reset.1051367013
Short name	T752
Test name
Test status
Simulation time	394845759262 ps
CPU time	816.8 seconds
Started	Apr 28 01:05:37 PM PDT 24
Finished	Apr 28 01:19:15 PM PDT 24
Peak memory	216848 kb
Host	smart-986f5fb8-e380-4c90-9c3c-e7df73db5247
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051367013 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.1051367013
Directory	/workspace/12.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/12.uart_tx_ovrd.54784111
Short name	T457
Test name
Test status
Simulation time	598087807 ps
CPU time	2.09 seconds
Started	Apr 28 01:05:41 PM PDT 24
Finished	Apr 28 01:05:44 PM PDT 24
Peak memory	198820 kb
Host	smart-5ffd641b-74d1-477b-a7d6-80ea851ed8e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=54784111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.54784111
Directory	/workspace/12.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/12.uart_tx_rx.359597048
Short name	T561
Test name
Test status
Simulation time	17262027691 ps
CPU time	12.1 seconds
Started	Apr 28 01:05:37 PM PDT 24
Finished	Apr 28 01:05:50 PM PDT 24
Peak memory	200432 kb
Host	smart-219a5a50-5993-49e8-8d90-c52a5185b6ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=359597048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.359597048
Directory	/workspace/12.uart_tx_rx/latest

Test location	/workspace/coverage/default/121.uart_fifo_reset.2932979955
Short name	T470
Test name
Test status
Simulation time	135134525840 ps
CPU time	267.51 seconds
Started	Apr 28 01:09:37 PM PDT 24
Finished	Apr 28 01:14:05 PM PDT 24
Peak memory	200304 kb
Host	smart-8d682aee-238b-4fc0-9c35-a54acd35bf92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2932979955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.2932979955
Directory	/workspace/121.uart_fifo_reset/latest

Test location	/workspace/coverage/default/122.uart_fifo_reset.3093726733
Short name	T1156
Test name
Test status
Simulation time	196115792386 ps
CPU time	46.11 seconds
Started	Apr 28 01:09:34 PM PDT 24
Finished	Apr 28 01:10:21 PM PDT 24
Peak memory	200440 kb
Host	smart-9007b209-e12e-41fc-bbf6-813c63269dc0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3093726733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.3093726733
Directory	/workspace/122.uart_fifo_reset/latest

Test location	/workspace/coverage/default/123.uart_fifo_reset.3403393161
Short name	T699
Test name
Test status
Simulation time	38935515172 ps
CPU time	77.26 seconds
Started	Apr 28 01:09:34 PM PDT 24
Finished	Apr 28 01:10:52 PM PDT 24
Peak memory	200400 kb
Host	smart-90546723-7bed-4ae5-aac4-9773f1058ccb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3403393161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.3403393161
Directory	/workspace/123.uart_fifo_reset/latest

Test location	/workspace/coverage/default/124.uart_fifo_reset.1785908608
Short name	T1175
Test name
Test status
Simulation time	49861595859 ps
CPU time	43.95 seconds
Started	Apr 28 01:09:41 PM PDT 24
Finished	Apr 28 01:10:25 PM PDT 24
Peak memory	200068 kb
Host	smart-f5661b04-802f-46f1-b48f-9ac4be2da60b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1785908608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.1785908608
Directory	/workspace/124.uart_fifo_reset/latest

Test location	/workspace/coverage/default/125.uart_fifo_reset.110881691
Short name	T156
Test name
Test status
Simulation time	28610382209 ps
CPU time	33.55 seconds
Started	Apr 28 01:09:40 PM PDT 24
Finished	Apr 28 01:10:13 PM PDT 24
Peak memory	200384 kb
Host	smart-54cdb9e7-8551-4d4f-97b6-2027e5b671a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=110881691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.110881691
Directory	/workspace/125.uart_fifo_reset/latest

Test location	/workspace/coverage/default/126.uart_fifo_reset.1586826277
Short name	T1061
Test name
Test status
Simulation time	30648834407 ps
CPU time	51.42 seconds
Started	Apr 28 01:09:40 PM PDT 24
Finished	Apr 28 01:10:32 PM PDT 24
Peak memory	200364 kb
Host	smart-f1419423-71a1-4358-b803-228a58822530
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1586826277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.1586826277
Directory	/workspace/126.uart_fifo_reset/latest

Test location	/workspace/coverage/default/128.uart_fifo_reset.1905213797
Short name	T728
Test name
Test status
Simulation time	411961601979 ps
CPU time	71.74 seconds
Started	Apr 28 01:09:41 PM PDT 24
Finished	Apr 28 01:10:53 PM PDT 24
Peak memory	200456 kb
Host	smart-2f2d2e49-846c-4c59-8c5b-f9579c1aa31f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1905213797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.1905213797
Directory	/workspace/128.uart_fifo_reset/latest

Test location	/workspace/coverage/default/129.uart_fifo_reset.736988811
Short name	T472
Test name
Test status
Simulation time	6702208524 ps
CPU time	12.93 seconds
Started	Apr 28 01:09:40 PM PDT 24
Finished	Apr 28 01:09:53 PM PDT 24
Peak memory	200476 kb
Host	smart-685222cb-25a8-40dc-9de2-0c5fac6018e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=736988811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.736988811
Directory	/workspace/129.uart_fifo_reset/latest

Test location	/workspace/coverage/default/13.uart_alert_test.982817061
Short name	T407
Test name
Test status
Simulation time	14744270 ps
CPU time	0.54 seconds
Started	Apr 28 01:05:45 PM PDT 24
Finished	Apr 28 01:05:46 PM PDT 24
Peak memory	194784 kb
Host	smart-994f646e-29e9-4bfb-ae45-f13b6303b12f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982817061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.982817061
Directory	/workspace/13.uart_alert_test/latest

Test location	/workspace/coverage/default/13.uart_fifo_full.3378073048
Short name	T448
Test name
Test status
Simulation time	39549652296 ps
CPU time	69.5 seconds
Started	Apr 28 01:05:43 PM PDT 24
Finished	Apr 28 01:06:54 PM PDT 24
Peak memory	200380 kb
Host	smart-afb85256-8c58-483c-840d-9ec43d024ba4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3378073048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.3378073048
Directory	/workspace/13.uart_fifo_full/latest

Test location	/workspace/coverage/default/13.uart_fifo_overflow.3557500732
Short name	T461
Test name
Test status
Simulation time	66810319639 ps
CPU time	96.2 seconds
Started	Apr 28 01:05:41 PM PDT 24
Finished	Apr 28 01:07:18 PM PDT 24
Peak memory	200376 kb
Host	smart-f4ba0069-ef8e-446a-b867-baf9befa550a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3557500732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.3557500732
Directory	/workspace/13.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/13.uart_fifo_reset.2901676285
Short name	T775
Test name
Test status
Simulation time	35304827777 ps
CPU time	21.7 seconds
Started	Apr 28 01:05:42 PM PDT 24
Finished	Apr 28 01:06:05 PM PDT 24
Peak memory	200392 kb
Host	smart-17023333-98f0-4ec5-88f3-4396ad4b0b8c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2901676285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.2901676285
Directory	/workspace/13.uart_fifo_reset/latest

Test location	/workspace/coverage/default/13.uart_intr.911507640
Short name	T450
Test name
Test status
Simulation time	222539663788 ps
CPU time	362.29 seconds
Started	Apr 28 01:05:43 PM PDT 24
Finished	Apr 28 01:11:46 PM PDT 24
Peak memory	200264 kb
Host	smart-0ccfb967-4f7f-435c-82e7-14dad898831d
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911507640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.911507640
Directory	/workspace/13.uart_intr/latest

Test location	/workspace/coverage/default/13.uart_long_xfer_wo_dly.655188764
Short name	T689
Test name
Test status
Simulation time	130526918117 ps
CPU time	650.71 seconds
Started	Apr 28 01:05:41 PM PDT 24
Finished	Apr 28 01:16:33 PM PDT 24
Peak memory	200324 kb
Host	smart-6a9b0841-887a-4515-9879-05f5b612eefa
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=655188764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.655188764
Directory	/workspace/13.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/13.uart_loopback.1188894513
Short name	T1031
Test name
Test status
Simulation time	6888672470 ps
CPU time	11.78 seconds
Started	Apr 28 01:05:41 PM PDT 24
Finished	Apr 28 01:05:53 PM PDT 24
Peak memory	199060 kb
Host	smart-0d308a7c-789c-4067-84fc-a8ba1913c79a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1188894513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1188894513
Directory	/workspace/13.uart_loopback/latest

Test location	/workspace/coverage/default/13.uart_noise_filter.365835464
Short name	T106
Test name
Test status
Simulation time	86658319755 ps
CPU time	133.11 seconds
Started	Apr 28 01:05:41 PM PDT 24
Finished	Apr 28 01:07:55 PM PDT 24
Peak memory	200496 kb
Host	smart-f6cfb349-5d2d-4f29-b972-1284081266f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=365835464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.365835464
Directory	/workspace/13.uart_noise_filter/latest

Test location	/workspace/coverage/default/13.uart_perf.116501876
Short name	T1090
Test name
Test status
Simulation time	13327463767 ps
CPU time	740.42 seconds
Started	Apr 28 01:05:42 PM PDT 24
Finished	Apr 28 01:18:04 PM PDT 24
Peak memory	200252 kb
Host	smart-7d8ca327-9cc1-4639-9503-5bca366ca7fb
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=116501876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.116501876
Directory	/workspace/13.uart_perf/latest

Test location	/workspace/coverage/default/13.uart_rx_oversample.173326432
Short name	T1063
Test name
Test status
Simulation time	2613764068 ps
CPU time	1.73 seconds
Started	Apr 28 01:05:42 PM PDT 24
Finished	Apr 28 01:05:44 PM PDT 24
Peak memory	198520 kb
Host	smart-ce5c5c30-f700-43fb-ad4f-1a8a6a9732d4
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=173326432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.173326432
Directory	/workspace/13.uart_rx_oversample/latest

Test location	/workspace/coverage/default/13.uart_rx_parity_err.2246689902
Short name	T262
Test name
Test status
Simulation time	15646279693 ps
CPU time	35.51 seconds
Started	Apr 28 01:05:42 PM PDT 24
Finished	Apr 28 01:06:19 PM PDT 24
Peak memory	200384 kb
Host	smart-d3f31346-a413-4742-8045-13bbfe3d28c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2246689902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.2246689902
Directory	/workspace/13.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/13.uart_rx_start_bit_filter.2300771381
Short name	T35
Test name
Test status
Simulation time	30337841770 ps
CPU time	4.8 seconds
Started	Apr 28 01:05:45 PM PDT 24
Finished	Apr 28 01:05:51 PM PDT 24
Peak memory	196292 kb
Host	smart-a34f4097-15f2-4e58-addf-2bbd5b958488
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2300771381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.2300771381
Directory	/workspace/13.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/13.uart_smoke.2960761372
Short name	T1129
Test name
Test status
Simulation time	441286707 ps
CPU time	2.13 seconds
Started	Apr 28 01:05:41 PM PDT 24
Finished	Apr 28 01:05:43 PM PDT 24
Peak memory	198784 kb
Host	smart-c314301c-e980-473e-9c4e-3920f1a73cf7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2960761372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.2960761372
Directory	/workspace/13.uart_smoke/latest

Test location	/workspace/coverage/default/13.uart_stress_all.4259995731
Short name	T327
Test name
Test status
Simulation time	67702386198 ps
CPU time	44.17 seconds
Started	Apr 28 01:05:41 PM PDT 24
Finished	Apr 28 01:06:25 PM PDT 24
Peak memory	200368 kb
Host	smart-3f5048b6-6768-46f0-9f25-fddd2af7e839
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259995731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.4259995731
Directory	/workspace/13.uart_stress_all/latest

Test location	/workspace/coverage/default/13.uart_stress_all_with_rand_reset.2123670991
Short name	T1116
Test name
Test status
Simulation time	12875699439 ps
CPU time	420.65 seconds
Started	Apr 28 01:05:43 PM PDT 24
Finished	Apr 28 01:12:45 PM PDT 24
Peak memory	216828 kb
Host	smart-c4cf459d-5c18-409e-9e40-365d148614d8
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123670991 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.2123670991
Directory	/workspace/13.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.uart_tx_ovrd.1968609887
Short name	T991
Test name
Test status
Simulation time	1174831142 ps
CPU time	3.92 seconds
Started	Apr 28 01:05:42 PM PDT 24
Finished	Apr 28 01:05:47 PM PDT 24
Peak memory	199824 kb
Host	smart-dbd96aa2-2882-44a6-a56a-c8c2e9b6aa75
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1968609887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.1968609887
Directory	/workspace/13.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/13.uart_tx_rx.509332249
Short name	T555
Test name
Test status
Simulation time	125748527403 ps
CPU time	21.83 seconds
Started	Apr 28 01:05:44 PM PDT 24
Finished	Apr 28 01:06:06 PM PDT 24
Peak memory	200452 kb
Host	smart-a9d67195-d212-4ecb-a3c2-bfa9490c4a7e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=509332249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.509332249
Directory	/workspace/13.uart_tx_rx/latest

Test location	/workspace/coverage/default/130.uart_fifo_reset.3050213103
Short name	T675
Test name
Test status
Simulation time	34444736253 ps
CPU time	27.2 seconds
Started	Apr 28 01:09:40 PM PDT 24
Finished	Apr 28 01:10:08 PM PDT 24
Peak memory	200384 kb
Host	smart-4c8cfb34-7732-4a8a-9f9a-9b5d1e37ab37
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3050213103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.3050213103
Directory	/workspace/130.uart_fifo_reset/latest

Test location	/workspace/coverage/default/131.uart_fifo_reset.3057429781
Short name	T308
Test name
Test status
Simulation time	87771049659 ps
CPU time	61.18 seconds
Started	Apr 28 01:09:40 PM PDT 24
Finished	Apr 28 01:10:41 PM PDT 24
Peak memory	200208 kb
Host	smart-931b7b04-92e8-4a20-a5a2-b7f238825a3b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3057429781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.3057429781
Directory	/workspace/131.uart_fifo_reset/latest

Test location	/workspace/coverage/default/132.uart_fifo_reset.2494939807
Short name	T288
Test name
Test status
Simulation time	16597755582 ps
CPU time	15.14 seconds
Started	Apr 28 01:09:56 PM PDT 24
Finished	Apr 28 01:10:12 PM PDT 24
Peak memory	200344 kb
Host	smart-8d80e1bb-272c-4264-ac4d-9367249a9f3d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2494939807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.2494939807
Directory	/workspace/132.uart_fifo_reset/latest

Test location	/workspace/coverage/default/133.uart_fifo_reset.3440295435
Short name	T918
Test name
Test status
Simulation time	24003033973 ps
CPU time	36.59 seconds
Started	Apr 28 01:09:59 PM PDT 24
Finished	Apr 28 01:10:37 PM PDT 24
Peak memory	200452 kb
Host	smart-c5750b0f-65c7-41bf-b666-e77e8cac7ab8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3440295435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.3440295435
Directory	/workspace/133.uart_fifo_reset/latest

Test location	/workspace/coverage/default/134.uart_fifo_reset.2532721019
Short name	T323
Test name
Test status
Simulation time	11174580544 ps
CPU time	18.59 seconds
Started	Apr 28 01:09:53 PM PDT 24
Finished	Apr 28 01:10:12 PM PDT 24
Peak memory	200352 kb
Host	smart-b98e174f-ddf6-4b12-9e29-ad4c961a6ca6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2532721019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.2532721019
Directory	/workspace/134.uart_fifo_reset/latest

Test location	/workspace/coverage/default/136.uart_fifo_reset.3804178380
Short name	T989
Test name
Test status
Simulation time	96615555564 ps
CPU time	36.03 seconds
Started	Apr 28 01:09:53 PM PDT 24
Finished	Apr 28 01:10:30 PM PDT 24
Peak memory	200408 kb
Host	smart-7aa52901-feb8-40fb-81a4-3209ef3b8ce9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3804178380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.3804178380
Directory	/workspace/136.uart_fifo_reset/latest

Test location	/workspace/coverage/default/139.uart_fifo_reset.2972961373
Short name	T409
Test name
Test status
Simulation time	48134050561 ps
CPU time	19.25 seconds
Started	Apr 28 01:09:54 PM PDT 24
Finished	Apr 28 01:10:14 PM PDT 24
Peak memory	200420 kb
Host	smart-7b50051e-84d5-4ee6-83b5-367188639f81
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2972961373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.2972961373
Directory	/workspace/139.uart_fifo_reset/latest

Test location	/workspace/coverage/default/14.uart_alert_test.1145365100
Short name	T908
Test name
Test status
Simulation time	13085267 ps
CPU time	0.57 seconds
Started	Apr 28 01:05:41 PM PDT 24
Finished	Apr 28 01:05:42 PM PDT 24
Peak memory	195732 kb
Host	smart-9c16adf2-9182-44de-a66c-a1a111a961ad
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145365100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.1145365100
Directory	/workspace/14.uart_alert_test/latest

Test location	/workspace/coverage/default/14.uart_fifo_full.1237980940
Short name	T148
Test name
Test status
Simulation time	89507239853 ps
CPU time	34.74 seconds
Started	Apr 28 01:05:42 PM PDT 24
Finished	Apr 28 01:06:18 PM PDT 24
Peak memory	200264 kb
Host	smart-d51ab578-e47a-4a18-bc9a-b62588f3cfcb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1237980940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.1237980940
Directory	/workspace/14.uart_fifo_full/latest

Test location	/workspace/coverage/default/14.uart_fifo_overflow.4135580189
Short name	T798
Test name
Test status
Simulation time	48951886340 ps
CPU time	76.23 seconds
Started	Apr 28 01:05:43 PM PDT 24
Finished	Apr 28 01:07:00 PM PDT 24
Peak memory	200268 kb
Host	smart-08ab6a89-8368-4a3c-97a6-ba987a7c484a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4135580189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.4135580189
Directory	/workspace/14.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/14.uart_fifo_reset.2415344652
Short name	T781
Test name
Test status
Simulation time	16416567818 ps
CPU time	28.57 seconds
Started	Apr 28 01:05:42 PM PDT 24
Finished	Apr 28 01:06:12 PM PDT 24
Peak memory	200332 kb
Host	smart-3b7842ed-af56-4b83-8a31-d1eb16e5e29d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2415344652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.2415344652
Directory	/workspace/14.uart_fifo_reset/latest

Test location	/workspace/coverage/default/14.uart_intr.559602397
Short name	T1012
Test name
Test status
Simulation time	26976297843 ps
CPU time	5.75 seconds
Started	Apr 28 01:05:43 PM PDT 24
Finished	Apr 28 01:05:50 PM PDT 24
Peak memory	200332 kb
Host	smart-e0bbd7b4-c15d-4a49-9c41-15baf45f20ec
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559602397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.559602397
Directory	/workspace/14.uart_intr/latest

Test location	/workspace/coverage/default/14.uart_long_xfer_wo_dly.719690312
Short name	T485
Test name
Test status
Simulation time	61497758706 ps
CPU time	275.64 seconds
Started	Apr 28 01:05:41 PM PDT 24
Finished	Apr 28 01:10:18 PM PDT 24
Peak memory	200376 kb
Host	smart-b151caff-9bd7-4629-9c86-92ce758d70ba
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=719690312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.719690312
Directory	/workspace/14.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/14.uart_loopback.3781647668
Short name	T443
Test name
Test status
Simulation time	10545954641 ps
CPU time	24.1 seconds
Started	Apr 28 01:05:43 PM PDT 24
Finished	Apr 28 01:06:09 PM PDT 24
Peak memory	199832 kb
Host	smart-1d64b17c-f0c9-4285-83ef-6e99d5d4aaae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3781647668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.3781647668
Directory	/workspace/14.uart_loopback/latest

Test location	/workspace/coverage/default/14.uart_noise_filter.2846091487
Short name	T423
Test name
Test status
Simulation time	178817935055 ps
CPU time	75.66 seconds
Started	Apr 28 01:05:43 PM PDT 24
Finished	Apr 28 01:07:00 PM PDT 24
Peak memory	208552 kb
Host	smart-baf6c314-763e-4da5-a14a-2382e2157f03
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2846091487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.2846091487
Directory	/workspace/14.uart_noise_filter/latest

Test location	/workspace/coverage/default/14.uart_rx_oversample.2024741741
Short name	T1001
Test name
Test status
Simulation time	3447962106 ps
CPU time	21.36 seconds
Started	Apr 28 01:05:46 PM PDT 24
Finished	Apr 28 01:06:08 PM PDT 24
Peak memory	199316 kb
Host	smart-927373db-6ffb-4ac5-ae33-22ad380d9c69
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2024741741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.2024741741
Directory	/workspace/14.uart_rx_oversample/latest

Test location	/workspace/coverage/default/14.uart_rx_parity_err.1230133567
Short name	T690
Test name
Test status
Simulation time	22328241431 ps
CPU time	14.63 seconds
Started	Apr 28 01:05:42 PM PDT 24
Finished	Apr 28 01:05:58 PM PDT 24
Peak memory	200404 kb
Host	smart-0bcf70bf-fcca-4e2f-9522-9ea3460f98d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1230133567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.1230133567
Directory	/workspace/14.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/14.uart_rx_start_bit_filter.1702324575
Short name	T378
Test name
Test status
Simulation time	2316322954 ps
CPU time	2.35 seconds
Started	Apr 28 01:05:42 PM PDT 24
Finished	Apr 28 01:05:46 PM PDT 24
Peak memory	195944 kb
Host	smart-d8c51cd1-0cff-4a8b-a56d-c79baaf0c442
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1702324575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.1702324575
Directory	/workspace/14.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/14.uart_smoke.4263666862
Short name	T427
Test name
Test status
Simulation time	780773802 ps
CPU time	1.98 seconds
Started	Apr 28 01:05:42 PM PDT 24
Finished	Apr 28 01:05:46 PM PDT 24
Peak memory	199188 kb
Host	smart-d933eac0-9ade-4826-84a7-a9484bb03771
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4263666862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.4263666862
Directory	/workspace/14.uart_smoke/latest

Test location	/workspace/coverage/default/14.uart_stress_all.1824706312
Short name	T590
Test name
Test status
Simulation time	102076250874 ps
CPU time	97.57 seconds
Started	Apr 28 01:05:46 PM PDT 24
Finished	Apr 28 01:07:24 PM PDT 24
Peak memory	200424 kb
Host	smart-186c05a7-872f-4f94-b419-8e89a3125e0b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824706312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.1824706312
Directory	/workspace/14.uart_stress_all/latest

Test location	/workspace/coverage/default/14.uart_stress_all_with_rand_reset.1172065626
Short name	T968
Test name
Test status
Simulation time	71415667086 ps
CPU time	250.48 seconds
Started	Apr 28 01:05:43 PM PDT 24
Finished	Apr 28 01:09:55 PM PDT 24
Peak memory	208320 kb
Host	smart-b542e430-5c47-4b4e-a875-194aefb2c85f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172065626 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.1172065626
Directory	/workspace/14.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/14.uart_tx_ovrd.1966717791
Short name	T754
Test name
Test status
Simulation time	2396686093 ps
CPU time	1.64 seconds
Started	Apr 28 01:05:42 PM PDT 24
Finished	Apr 28 01:05:45 PM PDT 24
Peak memory	198960 kb
Host	smart-fbd2d3b7-cfa7-4ce7-ade1-c1ec0d19310c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1966717791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.1966717791
Directory	/workspace/14.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/14.uart_tx_rx.2083819590
Short name	T604
Test name
Test status
Simulation time	44042900637 ps
CPU time	72.97 seconds
Started	Apr 28 01:05:45 PM PDT 24
Finished	Apr 28 01:06:59 PM PDT 24
Peak memory	200404 kb
Host	smart-9b915a93-a50a-419f-9b5b-0c893bee9912
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2083819590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.2083819590
Directory	/workspace/14.uart_tx_rx/latest

Test location	/workspace/coverage/default/140.uart_fifo_reset.1979186480
Short name	T190
Test name
Test status
Simulation time	78673321265 ps
CPU time	153.93 seconds
Started	Apr 28 01:09:54 PM PDT 24
Finished	Apr 28 01:12:29 PM PDT 24
Peak memory	200368 kb
Host	smart-125edd71-3ba9-4f29-8d5d-85dc3e2cb9fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1979186480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1979186480
Directory	/workspace/140.uart_fifo_reset/latest

Test location	/workspace/coverage/default/141.uart_fifo_reset.961300052
Short name	T854
Test name
Test status
Simulation time	20022966373 ps
CPU time	38.92 seconds
Started	Apr 28 01:09:54 PM PDT 24
Finished	Apr 28 01:10:34 PM PDT 24
Peak memory	200416 kb
Host	smart-f88aa062-cf7d-423e-9e23-db3d76d58a3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=961300052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.961300052
Directory	/workspace/141.uart_fifo_reset/latest

Test location	/workspace/coverage/default/142.uart_fifo_reset.2059994893
Short name	T768
Test name
Test status
Simulation time	28277906198 ps
CPU time	28.04 seconds
Started	Apr 28 01:09:53 PM PDT 24
Finished	Apr 28 01:10:22 PM PDT 24
Peak memory	200368 kb
Host	smart-b139c233-6f32-49e3-9272-263a6e2670f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2059994893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.2059994893
Directory	/workspace/142.uart_fifo_reset/latest

Test location	/workspace/coverage/default/143.uart_fifo_reset.863732537
Short name	T10
Test name
Test status
Simulation time	33487318311 ps
CPU time	47.76 seconds
Started	Apr 28 01:09:55 PM PDT 24
Finished	Apr 28 01:10:43 PM PDT 24
Peak memory	200288 kb
Host	smart-e452751e-028c-4a6d-9fb3-5fbf1d7e9a4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=863732537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.863732537
Directory	/workspace/143.uart_fifo_reset/latest

Test location	/workspace/coverage/default/144.uart_fifo_reset.152480853
Short name	T381
Test name
Test status
Simulation time	42309298425 ps
CPU time	21.33 seconds
Started	Apr 28 01:09:58 PM PDT 24
Finished	Apr 28 01:10:20 PM PDT 24
Peak memory	200440 kb
Host	smart-2196ee2c-6fd2-4d47-b647-a70ebcb1e1cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=152480853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.152480853
Directory	/workspace/144.uart_fifo_reset/latest

Test location	/workspace/coverage/default/145.uart_fifo_reset.2745510686
Short name	T191
Test name
Test status
Simulation time	87856410890 ps
CPU time	126.63 seconds
Started	Apr 28 01:09:57 PM PDT 24
Finished	Apr 28 01:12:04 PM PDT 24
Peak memory	200364 kb
Host	smart-feee5f20-f541-42bd-ab93-b778dad3792b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2745510686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2745510686
Directory	/workspace/145.uart_fifo_reset/latest

Test location	/workspace/coverage/default/147.uart_fifo_reset.3915373734
Short name	T630
Test name
Test status
Simulation time	112105232510 ps
CPU time	47.39 seconds
Started	Apr 28 01:09:56 PM PDT 24
Finished	Apr 28 01:10:45 PM PDT 24
Peak memory	200436 kb
Host	smart-6b7235eb-0a47-433f-8e02-806e89bc8862
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3915373734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3915373734
Directory	/workspace/147.uart_fifo_reset/latest

Test location	/workspace/coverage/default/148.uart_fifo_reset.3052416845
Short name	T1059
Test name
Test status
Simulation time	18792416818 ps
CPU time	34.65 seconds
Started	Apr 28 01:09:56 PM PDT 24
Finished	Apr 28 01:10:32 PM PDT 24
Peak memory	200424 kb
Host	smart-0cdec8db-5c71-470c-a6de-2e2d8c531245
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3052416845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.3052416845
Directory	/workspace/148.uart_fifo_reset/latest

Test location	/workspace/coverage/default/149.uart_fifo_reset.3733094936
Short name	T658
Test name
Test status
Simulation time	20719370377 ps
CPU time	29.37 seconds
Started	Apr 28 01:09:58 PM PDT 24
Finished	Apr 28 01:10:28 PM PDT 24
Peak memory	200352 kb
Host	smart-c8065c9d-57e0-4281-93de-b4bd42f29275
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3733094936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.3733094936
Directory	/workspace/149.uart_fifo_reset/latest

Test location	/workspace/coverage/default/15.uart_alert_test.3535144633
Short name	T738
Test name
Test status
Simulation time	35916133 ps
CPU time	0.53 seconds
Started	Apr 28 01:05:51 PM PDT 24
Finished	Apr 28 01:05:52 PM PDT 24
Peak memory	194684 kb
Host	smart-d054791d-abe1-4c75-9b2a-8900d5568871
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535144633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.3535144633
Directory	/workspace/15.uart_alert_test/latest

Test location	/workspace/coverage/default/15.uart_fifo_full.2825040393
Short name	T660
Test name
Test status
Simulation time	127191779648 ps
CPU time	273.71 seconds
Started	Apr 28 01:05:41 PM PDT 24
Finished	Apr 28 01:10:15 PM PDT 24
Peak memory	200364 kb
Host	smart-14561e31-4041-491a-a2c2-94a90beb2793
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2825040393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2825040393
Directory	/workspace/15.uart_fifo_full/latest

Test location	/workspace/coverage/default/15.uart_fifo_overflow.2939964020
Short name	T973
Test name
Test status
Simulation time	34586079696 ps
CPU time	15.72 seconds
Started	Apr 28 01:05:42 PM PDT 24
Finished	Apr 28 01:05:59 PM PDT 24
Peak memory	200424 kb
Host	smart-8150b092-286e-445e-82aa-b6342bc300f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2939964020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.2939964020
Directory	/workspace/15.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/15.uart_fifo_reset.3938266717
Short name	T168
Test name
Test status
Simulation time	23028760305 ps
CPU time	38.68 seconds
Started	Apr 28 01:05:43 PM PDT 24
Finished	Apr 28 01:06:23 PM PDT 24
Peak memory	200220 kb
Host	smart-44f51e20-30c6-409e-ba01-2b8a9aec6eb8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3938266717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.3938266717
Directory	/workspace/15.uart_fifo_reset/latest

Test location	/workspace/coverage/default/15.uart_intr.3373740922
Short name	T64
Test name
Test status
Simulation time	25674160976 ps
CPU time	61.32 seconds
Started	Apr 28 01:05:46 PM PDT 24
Finished	Apr 28 01:06:48 PM PDT 24
Peak memory	200308 kb
Host	smart-6c2fc0e8-d2c2-4698-9cf8-76649a4eaa5b
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373740922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.3373740922
Directory	/workspace/15.uart_intr/latest

Test location	/workspace/coverage/default/15.uart_long_xfer_wo_dly.4066865721
Short name	T1080
Test name
Test status
Simulation time	135244498642 ps
CPU time	309.74 seconds
Started	Apr 28 01:05:46 PM PDT 24
Finished	Apr 28 01:10:56 PM PDT 24
Peak memory	200432 kb
Host	smart-838b131d-aead-4993-ba02-fff94c7f6a85
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4066865721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.4066865721
Directory	/workspace/15.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/15.uart_loopback.421136593
Short name	T995
Test name
Test status
Simulation time	2200149526 ps
CPU time	9.06 seconds
Started	Apr 28 01:05:49 PM PDT 24
Finished	Apr 28 01:05:59 PM PDT 24
Peak memory	199172 kb
Host	smart-8e594b50-ee94-40f6-adb1-440ed473b551
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=421136593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.421136593
Directory	/workspace/15.uart_loopback/latest

Test location	/workspace/coverage/default/15.uart_noise_filter.172265347
Short name	T269
Test name
Test status
Simulation time	81938047590 ps
CPU time	39.34 seconds
Started	Apr 28 01:05:46 PM PDT 24
Finished	Apr 28 01:06:25 PM PDT 24
Peak memory	200608 kb
Host	smart-6070b377-8583-4c6d-926b-8b408ea879fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=172265347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.172265347
Directory	/workspace/15.uart_noise_filter/latest

Test location	/workspace/coverage/default/15.uart_perf.3060284348
Short name	T686
Test name
Test status
Simulation time	15989042686 ps
CPU time	754.6 seconds
Started	Apr 28 01:05:48 PM PDT 24
Finished	Apr 28 01:18:23 PM PDT 24
Peak memory	200300 kb
Host	smart-c3de9e80-9e1a-44ed-a0e2-beb6959dfcbc
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3060284348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.3060284348
Directory	/workspace/15.uart_perf/latest

Test location	/workspace/coverage/default/15.uart_rx_oversample.2484622843
Short name	T344
Test name
Test status
Simulation time	4607584496 ps
CPU time	39.47 seconds
Started	Apr 28 01:05:46 PM PDT 24
Finished	Apr 28 01:06:26 PM PDT 24
Peak memory	198692 kb
Host	smart-ad363af3-8e6f-4bcc-b312-90df7398e548
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2484622843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.2484622843
Directory	/workspace/15.uart_rx_oversample/latest

Test location	/workspace/coverage/default/15.uart_rx_parity_err.1738276050
Short name	T275
Test name
Test status
Simulation time	31909253750 ps
CPU time	52.67 seconds
Started	Apr 28 01:05:47 PM PDT 24
Finished	Apr 28 01:06:40 PM PDT 24
Peak memory	200316 kb
Host	smart-ab125127-620a-44be-bc2d-baf86f023eca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1738276050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.1738276050
Directory	/workspace/15.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/15.uart_rx_start_bit_filter.352447935
Short name	T994
Test name
Test status
Simulation time	2582008366 ps
CPU time	1.69 seconds
Started	Apr 28 01:05:47 PM PDT 24
Finished	Apr 28 01:05:49 PM PDT 24
Peak memory	196020 kb
Host	smart-c8d15742-e35d-4c80-b181-c14192022adb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=352447935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.352447935
Directory	/workspace/15.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/15.uart_smoke.3316503680
Short name	T5
Test name
Test status
Simulation time	464668545 ps
CPU time	1.33 seconds
Started	Apr 28 01:05:43 PM PDT 24
Finished	Apr 28 01:05:46 PM PDT 24
Peak memory	198972 kb
Host	smart-427523f7-219e-421a-8fd4-3e1ccce59073
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3316503680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.3316503680
Directory	/workspace/15.uart_smoke/latest

Test location	/workspace/coverage/default/15.uart_stress_all.2197316435
Short name	T945
Test name
Test status
Simulation time	60708766181 ps
CPU time	24.76 seconds
Started	Apr 28 01:05:51 PM PDT 24
Finished	Apr 28 01:06:16 PM PDT 24
Peak memory	200248 kb
Host	smart-785e76c6-bf6e-4e6e-b8c2-ea9ddbd5bff9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197316435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.2197316435
Directory	/workspace/15.uart_stress_all/latest

Test location	/workspace/coverage/default/15.uart_stress_all_with_rand_reset.828721113
Short name	T114
Test name
Test status
Simulation time	98787941461 ps
CPU time	159.65 seconds
Started	Apr 28 01:05:52 PM PDT 24
Finished	Apr 28 01:08:32 PM PDT 24
Peak memory	209064 kb
Host	smart-36e22e34-7641-4a3b-ba19-f9478de588a8
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828721113 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.828721113
Directory	/workspace/15.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.uart_tx_ovrd.1731005885
Short name	T267
Test name
Test status
Simulation time	1062075022 ps
CPU time	1.68 seconds
Started	Apr 28 01:05:47 PM PDT 24
Finished	Apr 28 01:05:49 PM PDT 24
Peak memory	200280 kb
Host	smart-1b341d3b-5290-40f4-8abe-faba1c485c41
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1731005885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.1731005885
Directory	/workspace/15.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/15.uart_tx_rx.1286710155
Short name	T290
Test name
Test status
Simulation time	106804546041 ps
CPU time	17.62 seconds
Started	Apr 28 01:05:42 PM PDT 24
Finished	Apr 28 01:06:01 PM PDT 24
Peak memory	200276 kb
Host	smart-5380c98b-d2b9-4081-b1eb-24d0db90f04e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1286710155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.1286710155
Directory	/workspace/15.uart_tx_rx/latest

Test location	/workspace/coverage/default/150.uart_fifo_reset.3632226552
Short name	T569
Test name
Test status
Simulation time	93482218759 ps
CPU time	227.87 seconds
Started	Apr 28 01:09:55 PM PDT 24
Finished	Apr 28 01:13:44 PM PDT 24
Peak memory	200328 kb
Host	smart-f7fdf447-a38d-4678-b231-ffd47f0f34ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3632226552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.3632226552
Directory	/workspace/150.uart_fifo_reset/latest

Test location	/workspace/coverage/default/151.uart_fifo_reset.2695297047
Short name	T817
Test name
Test status
Simulation time	40212017710 ps
CPU time	32.4 seconds
Started	Apr 28 01:09:56 PM PDT 24
Finished	Apr 28 01:10:29 PM PDT 24
Peak memory	200348 kb
Host	smart-0b933280-ea19-41d7-918c-af7e327e71da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2695297047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.2695297047
Directory	/workspace/151.uart_fifo_reset/latest

Test location	/workspace/coverage/default/152.uart_fifo_reset.2589434746
Short name	T708
Test name
Test status
Simulation time	10178985274 ps
CPU time	16.41 seconds
Started	Apr 28 01:09:58 PM PDT 24
Finished	Apr 28 01:10:15 PM PDT 24
Peak memory	200404 kb
Host	smart-a6b81afd-57f5-4a20-8f08-0ff7b9324ab4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2589434746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2589434746
Directory	/workspace/152.uart_fifo_reset/latest

Test location	/workspace/coverage/default/155.uart_fifo_reset.2743896187
Short name	T784
Test name
Test status
Simulation time	145387677523 ps
CPU time	206.79 seconds
Started	Apr 28 01:09:58 PM PDT 24
Finished	Apr 28 01:13:25 PM PDT 24
Peak memory	200360 kb
Host	smart-4b0ab8dd-3607-445f-b51f-342e088b4666
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2743896187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.2743896187
Directory	/workspace/155.uart_fifo_reset/latest

Test location	/workspace/coverage/default/156.uart_fifo_reset.1525843359
Short name	T305
Test name
Test status
Simulation time	19049522189 ps
CPU time	29.98 seconds
Started	Apr 28 01:09:56 PM PDT 24
Finished	Apr 28 01:10:26 PM PDT 24
Peak memory	200320 kb
Host	smart-b15a8acd-c8ae-4765-a63d-ddedd1ec3cdf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1525843359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.1525843359
Directory	/workspace/156.uart_fifo_reset/latest

Test location	/workspace/coverage/default/157.uart_fifo_reset.1372419826
Short name	T185
Test name
Test status
Simulation time	229242072885 ps
CPU time	88.44 seconds
Started	Apr 28 01:09:55 PM PDT 24
Finished	Apr 28 01:11:25 PM PDT 24
Peak memory	200164 kb
Host	smart-09455427-6e4b-422c-a64b-82e56314b034
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1372419826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.1372419826
Directory	/workspace/157.uart_fifo_reset/latest

Test location	/workspace/coverage/default/159.uart_fifo_reset.3531609773
Short name	T827
Test name
Test status
Simulation time	114871860828 ps
CPU time	60.43 seconds
Started	Apr 28 01:09:56 PM PDT 24
Finished	Apr 28 01:10:57 PM PDT 24
Peak memory	200380 kb
Host	smart-b44579e2-a2d6-4dfd-a46f-fdb5577b61a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3531609773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.3531609773
Directory	/workspace/159.uart_fifo_reset/latest

Test location	/workspace/coverage/default/16.uart_alert_test.1817515575
Short name	T874
Test name
Test status
Simulation time	14313082 ps
CPU time	0.58 seconds
Started	Apr 28 01:05:57 PM PDT 24
Finished	Apr 28 01:05:58 PM PDT 24
Peak memory	195808 kb
Host	smart-914d36e2-f2be-4ec8-b9a0-742a9671dbb2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817515575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.1817515575
Directory	/workspace/16.uart_alert_test/latest

Test location	/workspace/coverage/default/16.uart_fifo_full.3357407370
Short name	T967
Test name
Test status
Simulation time	39703172250 ps
CPU time	64.43 seconds
Started	Apr 28 01:05:51 PM PDT 24
Finished	Apr 28 01:06:56 PM PDT 24
Peak memory	200264 kb
Host	smart-0e4a254d-40d7-4f00-ae9d-e84d5136094a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3357407370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.3357407370
Directory	/workspace/16.uart_fifo_full/latest

Test location	/workspace/coverage/default/16.uart_fifo_overflow.2677703742
Short name	T722
Test name
Test status
Simulation time	14342809189 ps
CPU time	26.54 seconds
Started	Apr 28 01:05:54 PM PDT 24
Finished	Apr 28 01:06:21 PM PDT 24
Peak memory	200300 kb
Host	smart-350acd70-471e-4eaa-a77a-52a5bad783b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2677703742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2677703742
Directory	/workspace/16.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/16.uart_fifo_reset.1829427172
Short name	T970
Test name
Test status
Simulation time	42589273367 ps
CPU time	19.26 seconds
Started	Apr 28 01:05:54 PM PDT 24
Finished	Apr 28 01:06:14 PM PDT 24
Peak memory	200432 kb
Host	smart-75ddca84-3d09-4c3e-8a42-4f5ee4bd3db9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1829427172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.1829427172
Directory	/workspace/16.uart_fifo_reset/latest

Test location	/workspace/coverage/default/16.uart_intr.206629950
Short name	T603
Test name
Test status
Simulation time	6436991264 ps
CPU time	5.7 seconds
Started	Apr 28 01:05:50 PM PDT 24
Finished	Apr 28 01:05:56 PM PDT 24
Peak memory	196508 kb
Host	smart-ac4479ce-c5ee-4b52-8344-d5c2a9b1324b
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206629950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.206629950
Directory	/workspace/16.uart_intr/latest

Test location	/workspace/coverage/default/16.uart_long_xfer_wo_dly.1483792186
Short name	T737
Test name
Test status
Simulation time	269685355540 ps
CPU time	119.8 seconds
Started	Apr 28 01:05:50 PM PDT 24
Finished	Apr 28 01:07:50 PM PDT 24
Peak memory	200368 kb
Host	smart-0e57fcee-ad77-4295-85f2-11936bdf8ee8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1483792186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.1483792186
Directory	/workspace/16.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/16.uart_loopback.3875760753
Short name	T484
Test name
Test status
Simulation time	614096122 ps
CPU time	0.74 seconds
Started	Apr 28 01:05:53 PM PDT 24
Finished	Apr 28 01:05:54 PM PDT 24
Peak memory	197372 kb
Host	smart-27ebb73a-0ad9-45bb-9a17-93730eb377a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3875760753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.3875760753
Directory	/workspace/16.uart_loopback/latest

Test location	/workspace/coverage/default/16.uart_noise_filter.2896788915
Short name	T864
Test name
Test status
Simulation time	92357563185 ps
CPU time	165.9 seconds
Started	Apr 28 01:05:54 PM PDT 24
Finished	Apr 28 01:08:41 PM PDT 24
Peak memory	200572 kb
Host	smart-fd721d5f-79da-49e7-ae94-4a26081960ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2896788915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.2896788915
Directory	/workspace/16.uart_noise_filter/latest

Test location	/workspace/coverage/default/16.uart_perf.539351426
Short name	T388
Test name
Test status
Simulation time	28483669051 ps
CPU time	593.38 seconds
Started	Apr 28 01:05:52 PM PDT 24
Finished	Apr 28 01:15:46 PM PDT 24
Peak memory	200428 kb
Host	smart-f3212163-27f7-4e65-a78f-49e0eb857e72
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=539351426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.539351426
Directory	/workspace/16.uart_perf/latest

Test location	/workspace/coverage/default/16.uart_rx_oversample.419862378
Short name	T776
Test name
Test status
Simulation time	3390009282 ps
CPU time	13.09 seconds
Started	Apr 28 01:05:53 PM PDT 24
Finished	Apr 28 01:06:06 PM PDT 24
Peak memory	199356 kb
Host	smart-34da49b0-1e4d-4600-96c8-5cf57c87c8fb
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=419862378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.419862378
Directory	/workspace/16.uart_rx_oversample/latest

Test location	/workspace/coverage/default/16.uart_rx_start_bit_filter.3665257207
Short name	T923
Test name
Test status
Simulation time	6005351603 ps
CPU time	3.05 seconds
Started	Apr 28 01:05:51 PM PDT 24
Finished	Apr 28 01:05:55 PM PDT 24
Peak memory	196340 kb
Host	smart-f5b20ef9-4ddc-4384-a0e5-a043fc08c16b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3665257207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.3665257207
Directory	/workspace/16.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/16.uart_smoke.3624301571
Short name	T319
Test name
Test status
Simulation time	5983218878 ps
CPU time	14.53 seconds
Started	Apr 28 01:05:51 PM PDT 24
Finished	Apr 28 01:06:06 PM PDT 24
Peak memory	199572 kb
Host	smart-5a3477ec-84e6-4740-b91f-2a87486973cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3624301571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.3624301571
Directory	/workspace/16.uart_smoke/latest

Test location	/workspace/coverage/default/16.uart_stress_all.3772568643
Short name	T307
Test name
Test status
Simulation time	324584259354 ps
CPU time	182.56 seconds
Started	Apr 28 01:05:57 PM PDT 24
Finished	Apr 28 01:09:00 PM PDT 24
Peak memory	200356 kb
Host	smart-6759d982-5863-4d91-af8d-7b15a51df33f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772568643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.3772568643
Directory	/workspace/16.uart_stress_all/latest

Test location	/workspace/coverage/default/16.uart_stress_all_with_rand_reset.3020869869
Short name	T654
Test name
Test status
Simulation time	93297602097 ps
CPU time	2335.84 seconds
Started	Apr 28 01:05:56 PM PDT 24
Finished	Apr 28 01:44:53 PM PDT 24
Peak memory	233432 kb
Host	smart-5360bcfd-c8ad-46bf-a27c-f92a14150aee
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020869869 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.3020869869
Directory	/workspace/16.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/16.uart_tx_ovrd.3601416863
Short name	T916
Test name
Test status
Simulation time	3051809843 ps
CPU time	1.69 seconds
Started	Apr 28 01:05:54 PM PDT 24
Finished	Apr 28 01:05:56 PM PDT 24
Peak memory	199256 kb
Host	smart-e3a422b9-b1e0-48ec-ae89-3917c901e02e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3601416863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.3601416863
Directory	/workspace/16.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/16.uart_tx_rx.3637524483
Short name	T687
Test name
Test status
Simulation time	9151313156 ps
CPU time	14.89 seconds
Started	Apr 28 01:05:54 PM PDT 24
Finished	Apr 28 01:06:09 PM PDT 24
Peak memory	200436 kb
Host	smart-4f0ad24e-eebf-4579-aa3a-a0af90fcf458
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3637524483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.3637524483
Directory	/workspace/16.uart_tx_rx/latest

Test location	/workspace/coverage/default/160.uart_fifo_reset.4147591719
Short name	T333
Test name
Test status
Simulation time	32162041138 ps
CPU time	28.58 seconds
Started	Apr 28 01:09:57 PM PDT 24
Finished	Apr 28 01:10:27 PM PDT 24
Peak memory	200352 kb
Host	smart-04ff182e-c685-438a-b1b6-027c2e55dce8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4147591719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.4147591719
Directory	/workspace/160.uart_fifo_reset/latest

Test location	/workspace/coverage/default/161.uart_fifo_reset.3208280248
Short name	T330
Test name
Test status
Simulation time	8024565852 ps
CPU time	14.32 seconds
Started	Apr 28 01:09:57 PM PDT 24
Finished	Apr 28 01:10:12 PM PDT 24
Peak memory	200344 kb
Host	smart-d795a1b0-84ed-4c27-9ac4-e1f25e33ca01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3208280248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.3208280248
Directory	/workspace/161.uart_fifo_reset/latest

Test location	/workspace/coverage/default/162.uart_fifo_reset.3369927401
Short name	T292
Test name
Test status
Simulation time	64296130857 ps
CPU time	21.7 seconds
Started	Apr 28 01:10:00 PM PDT 24
Finished	Apr 28 01:10:22 PM PDT 24
Peak memory	200428 kb
Host	smart-d8fed249-8d94-4a32-855b-2d643cb65b7f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3369927401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.3369927401
Directory	/workspace/162.uart_fifo_reset/latest

Test location	/workspace/coverage/default/164.uart_fifo_reset.2534296905
Short name	T1053
Test name
Test status
Simulation time	211557261331 ps
CPU time	54.6 seconds
Started	Apr 28 01:10:01 PM PDT 24
Finished	Apr 28 01:10:56 PM PDT 24
Peak memory	200472 kb
Host	smart-66229519-ce68-47c8-9d0f-635801528eaf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2534296905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.2534296905
Directory	/workspace/164.uart_fifo_reset/latest

Test location	/workspace/coverage/default/165.uart_fifo_reset.4030830030
Short name	T486
Test name
Test status
Simulation time	66708431554 ps
CPU time	28.19 seconds
Started	Apr 28 01:10:00 PM PDT 24
Finished	Apr 28 01:10:29 PM PDT 24
Peak memory	200308 kb
Host	smart-040cb086-594f-4a76-b6c2-94c2ee83070c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4030830030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.4030830030
Directory	/workspace/165.uart_fifo_reset/latest

Test location	/workspace/coverage/default/166.uart_fifo_reset.2751650554
Short name	T679
Test name
Test status
Simulation time	43837837206 ps
CPU time	77.28 seconds
Started	Apr 28 01:10:01 PM PDT 24
Finished	Apr 28 01:11:19 PM PDT 24
Peak memory	200348 kb
Host	smart-882a8a07-712f-48f7-a5d3-6ee4c7208624
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2751650554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.2751650554
Directory	/workspace/166.uart_fifo_reset/latest

Test location	/workspace/coverage/default/167.uart_fifo_reset.3422547178
Short name	T151
Test name
Test status
Simulation time	19827821868 ps
CPU time	8.79 seconds
Started	Apr 28 01:10:03 PM PDT 24
Finished	Apr 28 01:10:12 PM PDT 24
Peak memory	200284 kb
Host	smart-4dcc1ce1-6af2-4aac-ab98-d965f4b2d229
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3422547178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.3422547178
Directory	/workspace/167.uart_fifo_reset/latest

Test location	/workspace/coverage/default/168.uart_fifo_reset.3019235491
Short name	T395
Test name
Test status
Simulation time	106287539159 ps
CPU time	17.98 seconds
Started	Apr 28 01:10:01 PM PDT 24
Finished	Apr 28 01:10:20 PM PDT 24
Peak memory	200392 kb
Host	smart-e7342556-1db3-427b-a2c9-7e73569e643e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3019235491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.3019235491
Directory	/workspace/168.uart_fifo_reset/latest

Test location	/workspace/coverage/default/169.uart_fifo_reset.508619087
Short name	T215
Test name
Test status
Simulation time	75602174692 ps
CPU time	41.42 seconds
Started	Apr 28 01:10:10 PM PDT 24
Finished	Apr 28 01:10:52 PM PDT 24
Peak memory	200344 kb
Host	smart-fb3e7171-ec6c-4d2c-8446-6b044f29a766
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=508619087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.508619087
Directory	/workspace/169.uart_fifo_reset/latest

Test location	/workspace/coverage/default/17.uart_alert_test.339293125
Short name	T1005
Test name
Test status
Simulation time	18289606 ps
CPU time	0.55 seconds
Started	Apr 28 01:06:01 PM PDT 24
Finished	Apr 28 01:06:02 PM PDT 24
Peak memory	195192 kb
Host	smart-7bf5031c-690c-46fe-b1a0-c19621184d5c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339293125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.339293125
Directory	/workspace/17.uart_alert_test/latest

Test location	/workspace/coverage/default/17.uart_fifo_full.3865532026
Short name	T408
Test name
Test status
Simulation time	100528557852 ps
CPU time	153.84 seconds
Started	Apr 28 01:05:57 PM PDT 24
Finished	Apr 28 01:08:31 PM PDT 24
Peak memory	200264 kb
Host	smart-e8d01c2a-bbfc-4c64-9fbf-172d57d5dbfb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3865532026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.3865532026
Directory	/workspace/17.uart_fifo_full/latest

Test location	/workspace/coverage/default/17.uart_fifo_overflow.3757866217
Short name	T656
Test name
Test status
Simulation time	132460376911 ps
CPU time	169.28 seconds
Started	Apr 28 01:05:58 PM PDT 24
Finished	Apr 28 01:08:48 PM PDT 24
Peak memory	200412 kb
Host	smart-c6113088-8a2e-4a4e-aff1-34b12c41948e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3757866217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.3757866217
Directory	/workspace/17.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/17.uart_intr.172691733
Short name	T361
Test name
Test status
Simulation time	233184303488 ps
CPU time	86.92 seconds
Started	Apr 28 01:06:00 PM PDT 24
Finished	Apr 28 01:07:28 PM PDT 24
Peak memory	197780 kb
Host	smart-a5988978-825e-4dfb-bfd9-67f6630e1306
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172691733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.172691733
Directory	/workspace/17.uart_intr/latest

Test location	/workspace/coverage/default/17.uart_long_xfer_wo_dly.971721907
Short name	T955
Test name
Test status
Simulation time	40239463760 ps
CPU time	233.35 seconds
Started	Apr 28 01:06:01 PM PDT 24
Finished	Apr 28 01:09:55 PM PDT 24
Peak memory	200408 kb
Host	smart-1718212f-7af2-4fb0-a1e9-d8e2adf3a32a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=971721907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.971721907
Directory	/workspace/17.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/17.uart_loopback.272737258
Short name	T624
Test name
Test status
Simulation time	12587134130 ps
CPU time	7.75 seconds
Started	Apr 28 01:06:00 PM PDT 24
Finished	Apr 28 01:06:08 PM PDT 24
Peak memory	200132 kb
Host	smart-1da644e2-7721-45ce-96b2-6016c85d455f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=272737258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.272737258
Directory	/workspace/17.uart_loopback/latest

Test location	/workspace/coverage/default/17.uart_noise_filter.2878715593
Short name	T7
Test name
Test status
Simulation time	131194812024 ps
CPU time	84.05 seconds
Started	Apr 28 01:06:00 PM PDT 24
Finished	Apr 28 01:07:24 PM PDT 24
Peak memory	200572 kb
Host	smart-fd6d2574-8b5e-4639-8bcb-d69a93cea650
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2878715593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.2878715593
Directory	/workspace/17.uart_noise_filter/latest

Test location	/workspace/coverage/default/17.uart_perf.177456632
Short name	T719
Test name
Test status
Simulation time	8629787852 ps
CPU time	118.57 seconds
Started	Apr 28 01:06:01 PM PDT 24
Finished	Apr 28 01:08:01 PM PDT 24
Peak memory	200440 kb
Host	smart-3664f33c-5906-4590-8a89-460a72196448
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=177456632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.177456632
Directory	/workspace/17.uart_perf/latest

Test location	/workspace/coverage/default/17.uart_rx_oversample.1976141298
Short name	T976
Test name
Test status
Simulation time	3794538905 ps
CPU time	30.17 seconds
Started	Apr 28 01:06:01 PM PDT 24
Finished	Apr 28 01:06:32 PM PDT 24
Peak memory	199384 kb
Host	smart-6b9a47b0-3c11-4fa6-90fe-e2fb6ee216c2
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1976141298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.1976141298
Directory	/workspace/17.uart_rx_oversample/latest

Test location	/workspace/coverage/default/17.uart_rx_parity_err.2662504207
Short name	T1137
Test name
Test status
Simulation time	16283230426 ps
CPU time	27.22 seconds
Started	Apr 28 01:06:00 PM PDT 24
Finished	Apr 28 01:06:28 PM PDT 24
Peak memory	200172 kb
Host	smart-fca7371b-332f-4e97-a5a8-2bfedfcbdc12
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2662504207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.2662504207
Directory	/workspace/17.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/17.uart_rx_start_bit_filter.3132495078
Short name	T897
Test name
Test status
Simulation time	3720397597 ps
CPU time	2.09 seconds
Started	Apr 28 01:06:01 PM PDT 24
Finished	Apr 28 01:06:04 PM PDT 24
Peak memory	196708 kb
Host	smart-3f090dd8-3dd1-414c-a9ef-26b80ced61b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3132495078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.3132495078
Directory	/workspace/17.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/17.uart_smoke.399454967
Short name	T1103
Test name
Test status
Simulation time	948965040 ps
CPU time	2.09 seconds
Started	Apr 28 01:05:58 PM PDT 24
Finished	Apr 28 01:06:00 PM PDT 24
Peak memory	199240 kb
Host	smart-179eb510-4e8c-47b1-b379-84bb03db905c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=399454967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.399454967
Directory	/workspace/17.uart_smoke/latest

Test location	/workspace/coverage/default/17.uart_stress_all_with_rand_reset.1320530102
Short name	T678
Test name
Test status
Simulation time	127786975024 ps
CPU time	306.97 seconds
Started	Apr 28 01:06:02 PM PDT 24
Finished	Apr 28 01:11:09 PM PDT 24
Peak memory	226080 kb
Host	smart-2badfa07-87aa-4806-8048-2bf364aee197
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320530102 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.1320530102
Directory	/workspace/17.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/17.uart_tx_ovrd.3257125965
Short name	T721
Test name
Test status
Simulation time	6261156074 ps
CPU time	23.03 seconds
Started	Apr 28 01:06:03 PM PDT 24
Finished	Apr 28 01:06:26 PM PDT 24
Peak memory	200260 kb
Host	smart-a1ce1af8-ca64-401e-abcd-7bd6beab4cd4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3257125965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.3257125965
Directory	/workspace/17.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/17.uart_tx_rx.3591975139
Short name	T359
Test name
Test status
Simulation time	85134485643 ps
CPU time	17.71 seconds
Started	Apr 28 01:05:59 PM PDT 24
Finished	Apr 28 01:06:17 PM PDT 24
Peak memory	200376 kb
Host	smart-f8980144-072d-42da-bc57-a49662a66684
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3591975139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.3591975139
Directory	/workspace/17.uart_tx_rx/latest

Test location	/workspace/coverage/default/170.uart_fifo_reset.4054234446
Short name	T210
Test name
Test status
Simulation time	84209918465 ps
CPU time	63.39 seconds
Started	Apr 28 01:10:08 PM PDT 24
Finished	Apr 28 01:11:12 PM PDT 24
Peak memory	200376 kb
Host	smart-5b15f86a-a1fb-4954-bc87-e1dff1866bbd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4054234446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.4054234446
Directory	/workspace/170.uart_fifo_reset/latest

Test location	/workspace/coverage/default/171.uart_fifo_reset.3622201396
Short name	T252
Test name
Test status
Simulation time	65448976415 ps
CPU time	76.6 seconds
Started	Apr 28 01:10:08 PM PDT 24
Finished	Apr 28 01:11:25 PM PDT 24
Peak memory	200244 kb
Host	smart-9e9aba1c-6a12-4e00-8ff9-7cb357e633fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3622201396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3622201396
Directory	/workspace/171.uart_fifo_reset/latest

Test location	/workspace/coverage/default/173.uart_fifo_reset.1655083850
Short name	T194
Test name
Test status
Simulation time	64105880286 ps
CPU time	108.55 seconds
Started	Apr 28 01:10:06 PM PDT 24
Finished	Apr 28 01:11:55 PM PDT 24
Peak memory	200444 kb
Host	smart-c58699c7-2dc7-4c0c-9225-c872d1e25867
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1655083850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.1655083850
Directory	/workspace/173.uart_fifo_reset/latest

Test location	/workspace/coverage/default/174.uart_fifo_reset.1003891103
Short name	T379
Test name
Test status
Simulation time	12377168624 ps
CPU time	24.82 seconds
Started	Apr 28 01:10:10 PM PDT 24
Finished	Apr 28 01:10:35 PM PDT 24
Peak memory	200212 kb
Host	smart-5b7c37f0-9cb3-4cbc-8d0f-4960ca80d5a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1003891103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.1003891103
Directory	/workspace/174.uart_fifo_reset/latest

Test location	/workspace/coverage/default/175.uart_fifo_reset.1059425343
Short name	T597
Test name
Test status
Simulation time	212684052182 ps
CPU time	102.14 seconds
Started	Apr 28 01:10:06 PM PDT 24
Finished	Apr 28 01:11:48 PM PDT 24
Peak memory	200436 kb
Host	smart-db581e73-3158-47bb-9ef3-8c1c2359a0cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1059425343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.1059425343
Directory	/workspace/175.uart_fifo_reset/latest

Test location	/workspace/coverage/default/177.uart_fifo_reset.2403877068
Short name	T1003
Test name
Test status
Simulation time	28288425652 ps
CPU time	42.51 seconds
Started	Apr 28 01:10:07 PM PDT 24
Finished	Apr 28 01:10:50 PM PDT 24
Peak memory	200064 kb
Host	smart-7ff0af58-1e88-469e-8e6e-8346d6c3b1cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2403877068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.2403877068
Directory	/workspace/177.uart_fifo_reset/latest

Test location	/workspace/coverage/default/179.uart_fifo_reset.2815226574
Short name	T731
Test name
Test status
Simulation time	47233700085 ps
CPU time	29.88 seconds
Started	Apr 28 01:10:10 PM PDT 24
Finished	Apr 28 01:10:41 PM PDT 24
Peak memory	200328 kb
Host	smart-8c5879de-9924-403b-a014-e475b8d10516
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2815226574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.2815226574
Directory	/workspace/179.uart_fifo_reset/latest

Test location	/workspace/coverage/default/18.uart_fifo_full.1090023951
Short name	T536
Test name
Test status
Simulation time	33521264591 ps
CPU time	28.8 seconds
Started	Apr 28 01:06:00 PM PDT 24
Finished	Apr 28 01:06:30 PM PDT 24
Peak memory	200456 kb
Host	smart-128b62aa-adc8-4f05-b7f6-d2b0dcab6a30
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1090023951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.1090023951
Directory	/workspace/18.uart_fifo_full/latest

Test location	/workspace/coverage/default/18.uart_fifo_overflow.4200872439
Short name	T657
Test name
Test status
Simulation time	7213925708 ps
CPU time	12.51 seconds
Started	Apr 28 01:06:02 PM PDT 24
Finished	Apr 28 01:06:15 PM PDT 24
Peak memory	198900 kb
Host	smart-45779b47-958b-436a-9315-cb60e19ea286
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4200872439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.4200872439
Directory	/workspace/18.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/18.uart_fifo_reset.2014425614
Short name	T1140
Test name
Test status
Simulation time	176709369145 ps
CPU time	66.58 seconds
Started	Apr 28 01:06:02 PM PDT 24
Finished	Apr 28 01:07:09 PM PDT 24
Peak memory	200304 kb
Host	smart-a583e86c-9d97-46af-aa87-405fae40766e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2014425614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.2014425614
Directory	/workspace/18.uart_fifo_reset/latest

Test location	/workspace/coverage/default/18.uart_intr.221858965
Short name	T980
Test name
Test status
Simulation time	105518798980 ps
CPU time	116.45 seconds
Started	Apr 28 01:06:00 PM PDT 24
Finished	Apr 28 01:07:58 PM PDT 24
Peak memory	200188 kb
Host	smart-2ad038da-c28c-4eb0-b818-9380f7ac0550
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221858965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.221858965
Directory	/workspace/18.uart_intr/latest

Test location	/workspace/coverage/default/18.uart_long_xfer_wo_dly.807753240
Short name	T729
Test name
Test status
Simulation time	78705173427 ps
CPU time	266.31 seconds
Started	Apr 28 01:06:08 PM PDT 24
Finished	Apr 28 01:10:35 PM PDT 24
Peak memory	200228 kb
Host	smart-7f07a791-5500-4872-a660-3c3f642972d3
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=807753240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.807753240
Directory	/workspace/18.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/18.uart_loopback.771040651
Short name	T1073
Test name
Test status
Simulation time	121856233 ps
CPU time	1.3 seconds
Started	Apr 28 01:06:08 PM PDT 24
Finished	Apr 28 01:06:10 PM PDT 24
Peak memory	198168 kb
Host	smart-6fdd2747-6fac-4839-810a-d568b0a71c73
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=771040651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.771040651
Directory	/workspace/18.uart_loopback/latest

Test location	/workspace/coverage/default/18.uart_noise_filter.3018093524
Short name	T48
Test name
Test status
Simulation time	66365003778 ps
CPU time	62.67 seconds
Started	Apr 28 01:06:02 PM PDT 24
Finished	Apr 28 01:07:05 PM PDT 24
Peak memory	208876 kb
Host	smart-07bfa792-ac40-4b58-b1ba-12b6aba5fd50
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3018093524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.3018093524
Directory	/workspace/18.uart_noise_filter/latest

Test location	/workspace/coverage/default/18.uart_perf.1624734467
Short name	T411
Test name
Test status
Simulation time	8341640046 ps
CPU time	400.82 seconds
Started	Apr 28 01:06:07 PM PDT 24
Finished	Apr 28 01:12:49 PM PDT 24
Peak memory	200408 kb
Host	smart-e570d71f-52a4-408d-a302-010cf76c44bf
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1624734467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.1624734467
Directory	/workspace/18.uart_perf/latest

Test location	/workspace/coverage/default/18.uart_rx_oversample.3617412051
Short name	T990
Test name
Test status
Simulation time	6096774923 ps
CPU time	50.23 seconds
Started	Apr 28 01:06:01 PM PDT 24
Finished	Apr 28 01:06:52 PM PDT 24
Peak memory	199184 kb
Host	smart-4f597dc6-e34a-4729-b87a-95d08bd8e2b8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3617412051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.3617412051
Directory	/workspace/18.uart_rx_oversample/latest

Test location	/workspace/coverage/default/18.uart_rx_parity_err.3269707906
Short name	T1161
Test name
Test status
Simulation time	5653253423 ps
CPU time	8.51 seconds
Started	Apr 28 01:06:08 PM PDT 24
Finished	Apr 28 01:06:17 PM PDT 24
Peak memory	198968 kb
Host	smart-58321e7c-2558-411f-9dae-56d09ee142e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3269707906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.3269707906
Directory	/workspace/18.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/18.uart_rx_start_bit_filter.3482381913
Short name	T351
Test name
Test status
Simulation time	45143917086 ps
CPU time	8.86 seconds
Started	Apr 28 01:06:06 PM PDT 24
Finished	Apr 28 01:06:15 PM PDT 24
Peak memory	196144 kb
Host	smart-5cc04faa-392b-4b48-82a1-9acd53aa30c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3482381913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.3482381913
Directory	/workspace/18.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/18.uart_smoke.243648737
Short name	T1025
Test name
Test status
Simulation time	513598632 ps
CPU time	2.34 seconds
Started	Apr 28 01:06:01 PM PDT 24
Finished	Apr 28 01:06:05 PM PDT 24
Peak memory	199028 kb
Host	smart-b7043b94-1c43-442a-8937-a5bb85ac54c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=243648737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.243648737
Directory	/workspace/18.uart_smoke/latest

Test location	/workspace/coverage/default/18.uart_stress_all.830892507
Short name	T278
Test name
Test status
Simulation time	283070846946 ps
CPU time	392.48 seconds
Started	Apr 28 01:06:08 PM PDT 24
Finished	Apr 28 01:12:41 PM PDT 24
Peak memory	200308 kb
Host	smart-10cb2b02-92fb-4b8c-ad3b-3fcd3c4fcf32
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830892507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.830892507
Directory	/workspace/18.uart_stress_all/latest

Test location	/workspace/coverage/default/18.uart_stress_all_with_rand_reset.309437719
Short name	T544
Test name
Test status
Simulation time	6778010145 ps
CPU time	28.6 seconds
Started	Apr 28 01:06:07 PM PDT 24
Finished	Apr 28 01:06:36 PM PDT 24
Peak memory	200612 kb
Host	smart-c937270f-230f-4148-901d-47ada201c8b4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309437719 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.309437719
Directory	/workspace/18.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/18.uart_tx_ovrd.531971903
Short name	T1098
Test name
Test status
Simulation time	8716484302 ps
CPU time	6.82 seconds
Started	Apr 28 01:06:10 PM PDT 24
Finished	Apr 28 01:06:17 PM PDT 24
Peak memory	199652 kb
Host	smart-68e5af4f-0556-4e52-acd8-a3dcee87b7c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=531971903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.531971903
Directory	/workspace/18.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/18.uart_tx_rx.2642776054
Short name	T646
Test name
Test status
Simulation time	193421196687 ps
CPU time	21.62 seconds
Started	Apr 28 01:06:01 PM PDT 24
Finished	Apr 28 01:06:23 PM PDT 24
Peak memory	200256 kb
Host	smart-78e71f29-9607-49a4-b022-f730cf3ae0b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2642776054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.2642776054
Directory	/workspace/18.uart_tx_rx/latest

Test location	/workspace/coverage/default/180.uart_fifo_reset.3899691326
Short name	T204
Test name
Test status
Simulation time	16225256479 ps
CPU time	16.49 seconds
Started	Apr 28 01:10:05 PM PDT 24
Finished	Apr 28 01:10:22 PM PDT 24
Peak memory	200276 kb
Host	smart-b2ba11be-a0a9-4ad7-aa5f-96651b1398f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3899691326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.3899691326
Directory	/workspace/180.uart_fifo_reset/latest

Test location	/workspace/coverage/default/181.uart_fifo_reset.1650503885
Short name	T617
Test name
Test status
Simulation time	83777786076 ps
CPU time	30.53 seconds
Started	Apr 28 01:10:09 PM PDT 24
Finished	Apr 28 01:10:40 PM PDT 24
Peak memory	200360 kb
Host	smart-4f2cc3b7-9687-449c-9cc2-377eb2e9a7ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1650503885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1650503885
Directory	/workspace/181.uart_fifo_reset/latest

Test location	/workspace/coverage/default/182.uart_fifo_reset.1812788362
Short name	T331
Test name
Test status
Simulation time	48830137894 ps
CPU time	34.62 seconds
Started	Apr 28 01:10:06 PM PDT 24
Finished	Apr 28 01:10:42 PM PDT 24
Peak memory	200292 kb
Host	smart-9b90b469-1cc6-441e-95fb-3811f0aa8a2b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1812788362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1812788362
Directory	/workspace/182.uart_fifo_reset/latest

Test location	/workspace/coverage/default/183.uart_fifo_reset.4276115673
Short name	T946
Test name
Test status
Simulation time	41670681052 ps
CPU time	17.61 seconds
Started	Apr 28 01:10:07 PM PDT 24
Finished	Apr 28 01:10:25 PM PDT 24
Peak memory	200404 kb
Host	smart-7316224f-3ee4-4a0e-9abc-f707903c6c00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4276115673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.4276115673
Directory	/workspace/183.uart_fifo_reset/latest

Test location	/workspace/coverage/default/184.uart_fifo_reset.405610641
Short name	T680
Test name
Test status
Simulation time	34139549505 ps
CPU time	25.57 seconds
Started	Apr 28 01:10:10 PM PDT 24
Finished	Apr 28 01:10:36 PM PDT 24
Peak memory	200264 kb
Host	smart-a42b6e6b-67c4-41f6-a100-a3e7074db761
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=405610641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.405610641
Directory	/workspace/184.uart_fifo_reset/latest

Test location	/workspace/coverage/default/185.uart_fifo_reset.3533542979
Short name	T814
Test name
Test status
Simulation time	82677754112 ps
CPU time	98.4 seconds
Started	Apr 28 01:10:10 PM PDT 24
Finished	Apr 28 01:11:49 PM PDT 24
Peak memory	200196 kb
Host	smart-3f6c0028-29ed-4b9e-834e-ccb572e84adc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3533542979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.3533542979
Directory	/workspace/185.uart_fifo_reset/latest

Test location	/workspace/coverage/default/186.uart_fifo_reset.402012120
Short name	T1119
Test name
Test status
Simulation time	47642215659 ps
CPU time	40.81 seconds
Started	Apr 28 01:10:11 PM PDT 24
Finished	Apr 28 01:10:52 PM PDT 24
Peak memory	200436 kb
Host	smart-c52894b7-ae07-47ad-9a71-164889452581
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=402012120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.402012120
Directory	/workspace/186.uart_fifo_reset/latest

Test location	/workspace/coverage/default/187.uart_fifo_reset.4092748185
Short name	T398
Test name
Test status
Simulation time	20942499520 ps
CPU time	34.41 seconds
Started	Apr 28 01:10:12 PM PDT 24
Finished	Apr 28 01:10:47 PM PDT 24
Peak memory	200452 kb
Host	smart-c5541412-8094-4b2c-b51f-de864a39a355
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4092748185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.4092748185
Directory	/workspace/187.uart_fifo_reset/latest

Test location	/workspace/coverage/default/188.uart_fifo_reset.3735243657
Short name	T118
Test name
Test status
Simulation time	28197056762 ps
CPU time	42.39 seconds
Started	Apr 28 01:10:12 PM PDT 24
Finished	Apr 28 01:10:55 PM PDT 24
Peak memory	200352 kb
Host	smart-7fd9bbc6-e392-4163-9f7a-3f9f70d488d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3735243657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3735243657
Directory	/workspace/188.uart_fifo_reset/latest

Test location	/workspace/coverage/default/189.uart_fifo_reset.2053235697
Short name	T193
Test name
Test status
Simulation time	123700839748 ps
CPU time	47.07 seconds
Started	Apr 28 01:10:12 PM PDT 24
Finished	Apr 28 01:10:59 PM PDT 24
Peak memory	200452 kb
Host	smart-c88cbd0d-de29-4527-bc65-192e322cb9fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2053235697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.2053235697
Directory	/workspace/189.uart_fifo_reset/latest

Test location	/workspace/coverage/default/19.uart_alert_test.1485291290
Short name	T459
Test name
Test status
Simulation time	17826909 ps
CPU time	0.55 seconds
Started	Apr 28 01:06:15 PM PDT 24
Finished	Apr 28 01:06:16 PM PDT 24
Peak memory	195652 kb
Host	smart-da3c78fe-95a9-4901-ab75-9ecbec449f0a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485291290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.1485291290
Directory	/workspace/19.uart_alert_test/latest

Test location	/workspace/coverage/default/19.uart_fifo_full.814174147
Short name	T380
Test name
Test status
Simulation time	69079733572 ps
CPU time	122.65 seconds
Started	Apr 28 01:06:07 PM PDT 24
Finished	Apr 28 01:08:10 PM PDT 24
Peak memory	200396 kb
Host	smart-fc84efc0-e8b7-40b4-9846-f1bd3efbdbb2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=814174147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.814174147
Directory	/workspace/19.uart_fifo_full/latest

Test location	/workspace/coverage/default/19.uart_fifo_overflow.97036715
Short name	T608
Test name
Test status
Simulation time	40596226989 ps
CPU time	74.29 seconds
Started	Apr 28 01:06:09 PM PDT 24
Finished	Apr 28 01:07:23 PM PDT 24
Peak memory	200464 kb
Host	smart-b30b2878-7d00-4ce3-941e-f81f8be19919
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=97036715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.97036715
Directory	/workspace/19.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/19.uart_fifo_reset.796970364
Short name	T832
Test name
Test status
Simulation time	20150660432 ps
CPU time	22.5 seconds
Started	Apr 28 01:06:08 PM PDT 24
Finished	Apr 28 01:06:31 PM PDT 24
Peak memory	200204 kb
Host	smart-bf32b5fb-bca2-4871-bd0a-928a4aceebdf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=796970364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.796970364
Directory	/workspace/19.uart_fifo_reset/latest

Test location	/workspace/coverage/default/19.uart_intr.4031600231
Short name	T504
Test name
Test status
Simulation time	98369573737 ps
CPU time	266.06 seconds
Started	Apr 28 01:06:11 PM PDT 24
Finished	Apr 28 01:10:38 PM PDT 24
Peak memory	200256 kb
Host	smart-54db354b-764e-47ff-97ea-fdc95e986ed5
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031600231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.4031600231
Directory	/workspace/19.uart_intr/latest

Test location	/workspace/coverage/default/19.uart_long_xfer_wo_dly.3852605095
Short name	T1057
Test name
Test status
Simulation time	90046175659 ps
CPU time	696.89 seconds
Started	Apr 28 01:06:12 PM PDT 24
Finished	Apr 28 01:17:50 PM PDT 24
Peak memory	200436 kb
Host	smart-86068fa6-2bee-4692-b50f-5945b6d0ea1d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3852605095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.3852605095
Directory	/workspace/19.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/19.uart_loopback.1067479035
Short name	T1002
Test name
Test status
Simulation time	5198024000 ps
CPU time	3.94 seconds
Started	Apr 28 01:06:12 PM PDT 24
Finished	Apr 28 01:06:17 PM PDT 24
Peak memory	200356 kb
Host	smart-320c81eb-93d3-49c3-9e74-44c40991d7f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1067479035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.1067479035
Directory	/workspace/19.uart_loopback/latest

Test location	/workspace/coverage/default/19.uart_noise_filter.2991055710
Short name	T277
Test name
Test status
Simulation time	302235803975 ps
CPU time	74.64 seconds
Started	Apr 28 01:06:12 PM PDT 24
Finished	Apr 28 01:07:27 PM PDT 24
Peak memory	208624 kb
Host	smart-4f10c426-4aeb-4491-b87e-de0ad76f441e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2991055710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.2991055710
Directory	/workspace/19.uart_noise_filter/latest

Test location	/workspace/coverage/default/19.uart_perf.3091558075
Short name	T941
Test name
Test status
Simulation time	10794718032 ps
CPU time	363.54 seconds
Started	Apr 28 01:06:14 PM PDT 24
Finished	Apr 28 01:12:18 PM PDT 24
Peak memory	200344 kb
Host	smart-a9040e30-0903-4c78-bea4-8e2b2c5f8333
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3091558075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3091558075
Directory	/workspace/19.uart_perf/latest

Test location	/workspace/coverage/default/19.uart_rx_oversample.207877237
Short name	T4
Test name
Test status
Simulation time	3164493436 ps
CPU time	25.15 seconds
Started	Apr 28 01:06:12 PM PDT 24
Finished	Apr 28 01:06:38 PM PDT 24
Peak memory	200400 kb
Host	smart-29469a05-c051-4b85-ba92-2c9c152bb6d6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=207877237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.207877237
Directory	/workspace/19.uart_rx_oversample/latest

Test location	/workspace/coverage/default/19.uart_rx_parity_err.4186271581
Short name	T909
Test name
Test status
Simulation time	16879021454 ps
CPU time	34.25 seconds
Started	Apr 28 01:06:15 PM PDT 24
Finished	Apr 28 01:06:50 PM PDT 24
Peak memory	200348 kb
Host	smart-7a731dbf-a713-4ec1-9e62-623b922c59fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4186271581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.4186271581
Directory	/workspace/19.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/19.uart_rx_start_bit_filter.431688936
Short name	T696
Test name
Test status
Simulation time	3773997468 ps
CPU time	6.94 seconds
Started	Apr 28 01:06:11 PM PDT 24
Finished	Apr 28 01:06:19 PM PDT 24
Peak memory	196464 kb
Host	smart-a24632e2-a158-46fd-867a-1b10175d8e31
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=431688936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.431688936
Directory	/workspace/19.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/19.uart_smoke.2756206964
Short name	T475
Test name
Test status
Simulation time	654688377 ps
CPU time	2.93 seconds
Started	Apr 28 01:06:07 PM PDT 24
Finished	Apr 28 01:06:11 PM PDT 24
Peak memory	198740 kb
Host	smart-43b21fa5-7f23-4f6d-acec-7c18d4a835c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2756206964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.2756206964
Directory	/workspace/19.uart_smoke/latest

Test location	/workspace/coverage/default/19.uart_tx_ovrd.2583201247
Short name	T403
Test name
Test status
Simulation time	989129887 ps
CPU time	5.46 seconds
Started	Apr 28 01:06:12 PM PDT 24
Finished	Apr 28 01:06:19 PM PDT 24
Peak memory	198952 kb
Host	smart-236e7fb8-1aa4-4a46-a1e4-3b8a742c0c09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2583201247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.2583201247
Directory	/workspace/19.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/19.uart_tx_rx.2462736305
Short name	T429
Test name
Test status
Simulation time	32386259363 ps
CPU time	27.37 seconds
Started	Apr 28 01:06:07 PM PDT 24
Finished	Apr 28 01:06:35 PM PDT 24
Peak memory	200356 kb
Host	smart-abe11e60-8c8c-42d2-95ed-d9cc3a981095
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2462736305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.2462736305
Directory	/workspace/19.uart_tx_rx/latest

Test location	/workspace/coverage/default/190.uart_fifo_reset.2672850343
Short name	T1081
Test name
Test status
Simulation time	117006584349 ps
CPU time	45.43 seconds
Started	Apr 28 01:10:10 PM PDT 24
Finished	Apr 28 01:10:56 PM PDT 24
Peak memory	200424 kb
Host	smart-c79ada87-ba82-4146-ae11-4acd9cab465e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2672850343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.2672850343
Directory	/workspace/190.uart_fifo_reset/latest

Test location	/workspace/coverage/default/191.uart_fifo_reset.657389232
Short name	T841
Test name
Test status
Simulation time	19044855474 ps
CPU time	32.68 seconds
Started	Apr 28 01:10:11 PM PDT 24
Finished	Apr 28 01:10:44 PM PDT 24
Peak memory	200292 kb
Host	smart-f828b69d-61f6-4940-981f-66341e0b9de0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=657389232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.657389232
Directory	/workspace/191.uart_fifo_reset/latest

Test location	/workspace/coverage/default/192.uart_fifo_reset.1586096520
Short name	T329
Test name
Test status
Simulation time	84456394399 ps
CPU time	74.21 seconds
Started	Apr 28 01:10:12 PM PDT 24
Finished	Apr 28 01:11:27 PM PDT 24
Peak memory	200288 kb
Host	smart-ab6d45fb-c30f-4a27-84b3-d3177290e9e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1586096520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.1586096520
Directory	/workspace/192.uart_fifo_reset/latest

Test location	/workspace/coverage/default/193.uart_fifo_reset.3340251440
Short name	T861
Test name
Test status
Simulation time	45093858206 ps
CPU time	24.4 seconds
Started	Apr 28 01:10:13 PM PDT 24
Finished	Apr 28 01:10:38 PM PDT 24
Peak memory	200332 kb
Host	smart-3d37f4fb-f343-4be4-a1bf-a2127196ffbd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3340251440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3340251440
Directory	/workspace/193.uart_fifo_reset/latest

Test location	/workspace/coverage/default/194.uart_fifo_reset.3749739394
Short name	T452
Test name
Test status
Simulation time	49401476707 ps
CPU time	11.84 seconds
Started	Apr 28 01:10:16 PM PDT 24
Finished	Apr 28 01:10:28 PM PDT 24
Peak memory	200200 kb
Host	smart-415ca449-e5a8-45ff-8bbc-b3b74e037698
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3749739394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.3749739394
Directory	/workspace/194.uart_fifo_reset/latest

Test location	/workspace/coverage/default/195.uart_fifo_reset.2995719207
Short name	T746
Test name
Test status
Simulation time	59786001956 ps
CPU time	108.63 seconds
Started	Apr 28 01:10:16 PM PDT 24
Finished	Apr 28 01:12:05 PM PDT 24
Peak memory	200356 kb
Host	smart-99fe957d-5192-4acd-9b04-e55e228ebe29
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2995719207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.2995719207
Directory	/workspace/195.uart_fifo_reset/latest

Test location	/workspace/coverage/default/196.uart_fifo_reset.1108634252
Short name	T1168
Test name
Test status
Simulation time	25552191956 ps
CPU time	30.3 seconds
Started	Apr 28 01:10:18 PM PDT 24
Finished	Apr 28 01:10:48 PM PDT 24
Peak memory	200372 kb
Host	smart-76e9b447-cafa-4665-bebc-5991c0d6fe60
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1108634252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.1108634252
Directory	/workspace/196.uart_fifo_reset/latest

Test location	/workspace/coverage/default/197.uart_fifo_reset.3946182307
Short name	T1164
Test name
Test status
Simulation time	157825651789 ps
CPU time	220.15 seconds
Started	Apr 28 01:10:17 PM PDT 24
Finished	Apr 28 01:13:57 PM PDT 24
Peak memory	200272 kb
Host	smart-17839a6d-b612-413b-b328-4c3cd609a7e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3946182307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.3946182307
Directory	/workspace/197.uart_fifo_reset/latest

Test location	/workspace/coverage/default/199.uart_fifo_reset.1938382993
Short name	T298
Test name
Test status
Simulation time	33777263521 ps
CPU time	18.02 seconds
Started	Apr 28 01:10:17 PM PDT 24
Finished	Apr 28 01:10:35 PM PDT 24
Peak memory	200380 kb
Host	smart-788fc772-6a64-4290-aef7-ab68c0d71b1b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1938382993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.1938382993
Directory	/workspace/199.uart_fifo_reset/latest

Test location	/workspace/coverage/default/2.uart_alert_test.2525428893
Short name	T23
Test name
Test status
Simulation time	27357011 ps
CPU time	0.54 seconds
Started	Apr 28 01:05:13 PM PDT 24
Finished	Apr 28 01:05:14 PM PDT 24
Peak memory	195648 kb
Host	smart-e6630cab-13dd-4d91-9f49-ca9657bdf969
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525428893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.2525428893
Directory	/workspace/2.uart_alert_test/latest

Test location	/workspace/coverage/default/2.uart_fifo_full.2111281446
Short name	T796
Test name
Test status
Simulation time	104049507414 ps
CPU time	47.05 seconds
Started	Apr 28 01:05:13 PM PDT 24
Finished	Apr 28 01:06:01 PM PDT 24
Peak memory	200372 kb
Host	smart-1e682759-efe7-475b-a8db-c74819f941c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2111281446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.2111281446
Directory	/workspace/2.uart_fifo_full/latest

Test location	/workspace/coverage/default/2.uart_fifo_overflow.4011227668
Short name	T516
Test name
Test status
Simulation time	58890092660 ps
CPU time	84.82 seconds
Started	Apr 28 01:05:11 PM PDT 24
Finished	Apr 28 01:06:37 PM PDT 24
Peak memory	200448 kb
Host	smart-7399a9b4-fa59-440f-8188-6da495931d56
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4011227668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.4011227668
Directory	/workspace/2.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/2.uart_fifo_reset.1353098212
Short name	T202
Test name
Test status
Simulation time	61072305466 ps
CPU time	133.4 seconds
Started	Apr 28 01:05:13 PM PDT 24
Finished	Apr 28 01:07:27 PM PDT 24
Peak memory	200288 kb
Host	smart-ce3aceba-616c-4678-a9cb-8bb3070a6afc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1353098212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.1353098212
Directory	/workspace/2.uart_fifo_reset/latest

Test location	/workspace/coverage/default/2.uart_intr.4069797099
Short name	T512
Test name
Test status
Simulation time	25457005912 ps
CPU time	12.52 seconds
Started	Apr 28 01:05:22 PM PDT 24
Finished	Apr 28 01:05:36 PM PDT 24
Peak memory	199016 kb
Host	smart-516f291a-f23a-4929-884b-9cb70faadbcf
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069797099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.4069797099
Directory	/workspace/2.uart_intr/latest

Test location	/workspace/coverage/default/2.uart_long_xfer_wo_dly.795777598
Short name	T360
Test name
Test status
Simulation time	190750485870 ps
CPU time	1634.44 seconds
Started	Apr 28 01:05:16 PM PDT 24
Finished	Apr 28 01:32:31 PM PDT 24
Peak memory	200424 kb
Host	smart-a39de319-e713-4882-b6b9-f5c68b1d90c9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=795777598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.795777598
Directory	/workspace/2.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/2.uart_loopback.1164302589
Short name	T839
Test name
Test status
Simulation time	9402116765 ps
CPU time	21.32 seconds
Started	Apr 28 01:05:15 PM PDT 24
Finished	Apr 28 01:05:38 PM PDT 24
Peak memory	200428 kb
Host	smart-17606dce-97ec-49dc-b136-2604af599484
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1164302589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.1164302589
Directory	/workspace/2.uart_loopback/latest

Test location	/workspace/coverage/default/2.uart_noise_filter.3603996869
Short name	T440
Test name
Test status
Simulation time	9448666732 ps
CPU time	9.92 seconds
Started	Apr 28 01:05:15 PM PDT 24
Finished	Apr 28 01:05:25 PM PDT 24
Peak memory	200284 kb
Host	smart-d7ee17f8-964a-4d7d-ab32-03578834a9f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3603996869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.3603996869
Directory	/workspace/2.uart_noise_filter/latest

Test location	/workspace/coverage/default/2.uart_perf.2395443195
Short name	T258
Test name
Test status
Simulation time	9284456355 ps
CPU time	495.21 seconds
Started	Apr 28 01:05:13 PM PDT 24
Finished	Apr 28 01:13:29 PM PDT 24
Peak memory	200456 kb
Host	smart-621159f9-df4b-45bc-a95e-a063065d9c88
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2395443195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.2395443195
Directory	/workspace/2.uart_perf/latest

Test location	/workspace/coverage/default/2.uart_rx_oversample.3138433964
Short name	T518
Test name
Test status
Simulation time	5907277348 ps
CPU time	50.45 seconds
Started	Apr 28 01:05:12 PM PDT 24
Finished	Apr 28 01:06:04 PM PDT 24
Peak memory	200348 kb
Host	smart-32ca614c-2355-4115-b1b6-bb569b4748e5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3138433964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.3138433964
Directory	/workspace/2.uart_rx_oversample/latest

Test location	/workspace/coverage/default/2.uart_rx_parity_err.3049540327
Short name	T983
Test name
Test status
Simulation time	148790693827 ps
CPU time	130.43 seconds
Started	Apr 28 01:05:15 PM PDT 24
Finished	Apr 28 01:07:26 PM PDT 24
Peak memory	200200 kb
Host	smart-5cf65e13-74b9-4aba-89a9-43a9136155b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3049540327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.3049540327
Directory	/workspace/2.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/2.uart_rx_start_bit_filter.1340027402
Short name	T875
Test name
Test status
Simulation time	3240920824 ps
CPU time	3.47 seconds
Started	Apr 28 01:05:12 PM PDT 24
Finished	Apr 28 01:05:17 PM PDT 24
Peak memory	196288 kb
Host	smart-80a99f31-7eae-488d-80c4-6e964ab307cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1340027402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.1340027402
Directory	/workspace/2.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/2.uart_smoke.25249436
Short name	T903
Test name
Test status
Simulation time	5905866964 ps
CPU time	14.1 seconds
Started	Apr 28 01:05:12 PM PDT 24
Finished	Apr 28 01:05:28 PM PDT 24
Peak memory	200100 kb
Host	smart-52887981-1e46-454b-b115-2f16731ff636
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=25249436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.25249436
Directory	/workspace/2.uart_smoke/latest

Test location	/workspace/coverage/default/2.uart_stress_all.1763000206
Short name	T517
Test name
Test status
Simulation time	104598783477 ps
CPU time	315.53 seconds
Started	Apr 28 01:05:15 PM PDT 24
Finished	Apr 28 01:10:31 PM PDT 24
Peak memory	200556 kb
Host	smart-0090e989-d22e-4f9f-beac-5d79ccb00d60
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763000206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.1763000206
Directory	/workspace/2.uart_stress_all/latest

Test location	/workspace/coverage/default/2.uart_tx_ovrd.1467382543
Short name	T346
Test name
Test status
Simulation time	1418064868 ps
CPU time	2.03 seconds
Started	Apr 28 01:05:11 PM PDT 24
Finished	Apr 28 01:05:14 PM PDT 24
Peak memory	199416 kb
Host	smart-222224c9-38cd-489c-a196-19bc20bcd572
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1467382543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.1467382543
Directory	/workspace/2.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/2.uart_tx_rx.1814344901
Short name	T1149
Test name
Test status
Simulation time	50942608997 ps
CPU time	20.97 seconds
Started	Apr 28 01:05:15 PM PDT 24
Finished	Apr 28 01:05:37 PM PDT 24
Peak memory	198780 kb
Host	smart-babcec11-8695-4435-a4f7-a1780d4404dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1814344901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.1814344901
Directory	/workspace/2.uart_tx_rx/latest

Test location	/workspace/coverage/default/20.uart_alert_test.2464049908
Short name	T715
Test name
Test status
Simulation time	12328636 ps
CPU time	0.54 seconds
Started	Apr 28 01:06:20 PM PDT 24
Finished	Apr 28 01:06:21 PM PDT 24
Peak memory	195784 kb
Host	smart-b0f2f68b-1e12-4f06-ba44-6044c397c1d1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464049908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.2464049908
Directory	/workspace/20.uart_alert_test/latest

Test location	/workspace/coverage/default/20.uart_fifo_full.2888185668
Short name	T1016
Test name
Test status
Simulation time	65468140006 ps
CPU time	27.18 seconds
Started	Apr 28 01:06:12 PM PDT 24
Finished	Apr 28 01:06:40 PM PDT 24
Peak memory	200240 kb
Host	smart-b86a6f51-7b15-4bc1-867f-f8bdfaa3b311
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2888185668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.2888185668
Directory	/workspace/20.uart_fifo_full/latest

Test location	/workspace/coverage/default/20.uart_fifo_overflow.1850761747
Short name	T800
Test name
Test status
Simulation time	16753919711 ps
CPU time	26.1 seconds
Started	Apr 28 01:06:12 PM PDT 24
Finished	Apr 28 01:06:39 PM PDT 24
Peak memory	200348 kb
Host	smart-f5bbe910-0269-408f-a593-b5d9a4c87e0e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1850761747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.1850761747
Directory	/workspace/20.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/20.uart_fifo_reset.1522260187
Short name	T1144
Test name
Test status
Simulation time	202681292005 ps
CPU time	25.03 seconds
Started	Apr 28 01:06:11 PM PDT 24
Finished	Apr 28 01:06:38 PM PDT 24
Peak memory	200384 kb
Host	smart-fd4ae2d1-0ca6-45c8-9030-234247c10870
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1522260187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.1522260187
Directory	/workspace/20.uart_fifo_reset/latest

Test location	/workspace/coverage/default/20.uart_intr.3144718292
Short name	T870
Test name
Test status
Simulation time	64730479223 ps
CPU time	135.49 seconds
Started	Apr 28 01:06:13 PM PDT 24
Finished	Apr 28 01:08:29 PM PDT 24
Peak memory	200284 kb
Host	smart-c48e0e42-57f4-43a0-bb4e-f7d0e0e70d03
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144718292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.3144718292
Directory	/workspace/20.uart_intr/latest

Test location	/workspace/coverage/default/20.uart_long_xfer_wo_dly.1189640043
Short name	T674
Test name
Test status
Simulation time	132605909335 ps
CPU time	956.48 seconds
Started	Apr 28 01:06:16 PM PDT 24
Finished	Apr 28 01:22:14 PM PDT 24
Peak memory	200444 kb
Host	smart-57444f9a-947b-4faf-9f89-7eca4a6cf3e1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1189640043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.1189640043
Directory	/workspace/20.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/20.uart_loopback.2204794101
Short name	T393
Test name
Test status
Simulation time	8948832593 ps
CPU time	5.85 seconds
Started	Apr 28 01:06:21 PM PDT 24
Finished	Apr 28 01:06:28 PM PDT 24
Peak memory	200380 kb
Host	smart-91c66dcd-3507-4430-ae2d-733626ad581d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2204794101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2204794101
Directory	/workspace/20.uart_loopback/latest

Test location	/workspace/coverage/default/20.uart_noise_filter.2235351129
Short name	T353
Test name
Test status
Simulation time	193527678249 ps
CPU time	85.85 seconds
Started	Apr 28 01:06:12 PM PDT 24
Finished	Apr 28 01:07:39 PM PDT 24
Peak memory	200480 kb
Host	smart-7df0005a-fc3a-4021-9c76-db889ab8e426
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2235351129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.2235351129
Directory	/workspace/20.uart_noise_filter/latest

Test location	/workspace/coverage/default/20.uart_perf.901737556
Short name	T813
Test name
Test status
Simulation time	10745774627 ps
CPU time	163.41 seconds
Started	Apr 28 01:06:12 PM PDT 24
Finished	Apr 28 01:08:57 PM PDT 24
Peak memory	200332 kb
Host	smart-e7d70b28-9d71-4b32-8c60-1ba5175c4e50
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=901737556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.901737556
Directory	/workspace/20.uart_perf/latest

Test location	/workspace/coverage/default/20.uart_rx_oversample.717792219
Short name	T789
Test name
Test status
Simulation time	4709313814 ps
CPU time	8.26 seconds
Started	Apr 28 01:06:13 PM PDT 24
Finished	Apr 28 01:06:22 PM PDT 24
Peak memory	198804 kb
Host	smart-8489a478-374f-4f2a-91cf-f32f94c01207
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=717792219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.717792219
Directory	/workspace/20.uart_rx_oversample/latest

Test location	/workspace/coverage/default/20.uart_rx_parity_err.2760723946
Short name	T892
Test name
Test status
Simulation time	17085607259 ps
CPU time	25.59 seconds
Started	Apr 28 01:06:14 PM PDT 24
Finished	Apr 28 01:06:40 PM PDT 24
Peak memory	199368 kb
Host	smart-2e064774-33c1-4714-bcb6-677bf0cb812e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2760723946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.2760723946
Directory	/workspace/20.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/20.uart_rx_start_bit_filter.1570043913
Short name	T349
Test name
Test status
Simulation time	3586475334 ps
CPU time	1.5 seconds
Started	Apr 28 01:06:14 PM PDT 24
Finished	Apr 28 01:06:16 PM PDT 24
Peak memory	196440 kb
Host	smart-b2b6589a-9b98-43b3-804d-a53e9034594e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1570043913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.1570043913
Directory	/workspace/20.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/20.uart_smoke.1519899449
Short name	T432
Test name
Test status
Simulation time	840956507 ps
CPU time	3.73 seconds
Started	Apr 28 01:06:12 PM PDT 24
Finished	Apr 28 01:06:17 PM PDT 24
Peak memory	199100 kb
Host	smart-e5a8bcb9-4811-42ec-8ad3-abe2de2b7a21
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1519899449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.1519899449
Directory	/workspace/20.uart_smoke/latest

Test location	/workspace/coverage/default/20.uart_stress_all.4080843197
Short name	T924
Test name
Test status
Simulation time	348670883329 ps
CPU time	1043.76 seconds
Started	Apr 28 01:06:17 PM PDT 24
Finished	Apr 28 01:23:42 PM PDT 24
Peak memory	208792 kb
Host	smart-35ad918b-127a-4bec-b859-d84a6b4a77fd
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080843197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.4080843197
Directory	/workspace/20.uart_stress_all/latest

Test location	/workspace/coverage/default/20.uart_stress_all_with_rand_reset.4188622225
Short name	T927
Test name
Test status
Simulation time	114285170678 ps
CPU time	294.54 seconds
Started	Apr 28 01:06:16 PM PDT 24
Finished	Apr 28 01:11:11 PM PDT 24
Peak memory	210576 kb
Host	smart-d3bfe355-b6fa-422b-986e-1f836e38f7bb
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188622225 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.4188622225
Directory	/workspace/20.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.uart_tx_ovrd.3067238075
Short name	T489
Test name
Test status
Simulation time	2109182762 ps
CPU time	1.89 seconds
Started	Apr 28 01:06:14 PM PDT 24
Finished	Apr 28 01:06:17 PM PDT 24
Peak memory	199124 kb
Host	smart-a8eddaef-350b-4477-9bf8-936db165844d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3067238075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.3067238075
Directory	/workspace/20.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/20.uart_tx_rx.914764231
Short name	T103
Test name
Test status
Simulation time	71070933151 ps
CPU time	12.15 seconds
Started	Apr 28 01:06:12 PM PDT 24
Finished	Apr 28 01:06:26 PM PDT 24
Peak memory	200364 kb
Host	smart-581895fd-4f79-47e4-801d-19fc17aa1114
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=914764231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.914764231
Directory	/workspace/20.uart_tx_rx/latest

Test location	/workspace/coverage/default/200.uart_fifo_reset.3078400821
Short name	T424
Test name
Test status
Simulation time	120763435085 ps
CPU time	99.29 seconds
Started	Apr 28 01:10:23 PM PDT 24
Finished	Apr 28 01:12:03 PM PDT 24
Peak memory	200352 kb
Host	smart-edb71c39-6f2c-4eb0-af97-f34dd98f4f53
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3078400821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.3078400821
Directory	/workspace/200.uart_fifo_reset/latest

Test location	/workspace/coverage/default/201.uart_fifo_reset.114007963
Short name	T718
Test name
Test status
Simulation time	237553837774 ps
CPU time	82.34 seconds
Started	Apr 28 01:10:23 PM PDT 24
Finished	Apr 28 01:11:47 PM PDT 24
Peak memory	200268 kb
Host	smart-2d191f0f-ce72-49f2-a58b-03564fc027a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=114007963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.114007963
Directory	/workspace/201.uart_fifo_reset/latest

Test location	/workspace/coverage/default/203.uart_fifo_reset.975961541
Short name	T744
Test name
Test status
Simulation time	120804325572 ps
CPU time	114.59 seconds
Started	Apr 28 01:10:23 PM PDT 24
Finished	Apr 28 01:12:19 PM PDT 24
Peak memory	200288 kb
Host	smart-00c0b152-a8d5-4b13-aaa5-be2f8b192628
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=975961541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.975961541
Directory	/workspace/203.uart_fifo_reset/latest

Test location	/workspace/coverage/default/204.uart_fifo_reset.746769365
Short name	T200
Test name
Test status
Simulation time	62112498895 ps
CPU time	140.18 seconds
Started	Apr 28 01:10:24 PM PDT 24
Finished	Apr 28 01:12:45 PM PDT 24
Peak memory	200284 kb
Host	smart-149240f0-cf7e-4903-b3cd-9b6a46cfbc43
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=746769365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.746769365
Directory	/workspace/204.uart_fifo_reset/latest

Test location	/workspace/coverage/default/205.uart_fifo_reset.1558210760
Short name	T321
Test name
Test status
Simulation time	124956050542 ps
CPU time	209.86 seconds
Started	Apr 28 01:10:23 PM PDT 24
Finished	Apr 28 01:13:54 PM PDT 24
Peak memory	200428 kb
Host	smart-00feafbd-2321-4a22-ad88-4bface3ea16f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1558210760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.1558210760
Directory	/workspace/205.uart_fifo_reset/latest

Test location	/workspace/coverage/default/206.uart_fifo_reset.974624136
Short name	T1151
Test name
Test status
Simulation time	89378173754 ps
CPU time	41.01 seconds
Started	Apr 28 01:10:23 PM PDT 24
Finished	Apr 28 01:11:05 PM PDT 24
Peak memory	200128 kb
Host	smart-08ed05ac-ea8a-48fb-9cb0-29fa6b447a66
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=974624136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.974624136
Directory	/workspace/206.uart_fifo_reset/latest

Test location	/workspace/coverage/default/208.uart_fifo_reset.1156015201
Short name	T1134
Test name
Test status
Simulation time	152849854585 ps
CPU time	18.88 seconds
Started	Apr 28 01:10:24 PM PDT 24
Finished	Apr 28 01:10:44 PM PDT 24
Peak memory	200344 kb
Host	smart-aa29d30d-edfc-48c9-aa6b-0a77e32b2224
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1156015201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1156015201
Directory	/workspace/208.uart_fifo_reset/latest

Test location	/workspace/coverage/default/209.uart_fifo_reset.797378365
Short name	T1083
Test name
Test status
Simulation time	51690342407 ps
CPU time	26.31 seconds
Started	Apr 28 01:10:24 PM PDT 24
Finished	Apr 28 01:10:52 PM PDT 24
Peak memory	200448 kb
Host	smart-cf04182e-a905-4448-b6b7-80b2e761ab1e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=797378365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.797378365
Directory	/workspace/209.uart_fifo_reset/latest

Test location	/workspace/coverage/default/21.uart_alert_test.2500937892
Short name	T490
Test name
Test status
Simulation time	16214846 ps
CPU time	0.56 seconds
Started	Apr 28 01:06:22 PM PDT 24
Finished	Apr 28 01:06:24 PM PDT 24
Peak memory	195700 kb
Host	smart-36009bfb-a8a8-4100-9709-1356e57d2ff0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500937892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.2500937892
Directory	/workspace/21.uart_alert_test/latest

Test location	/workspace/coverage/default/21.uart_fifo_full.4134058331
Short name	T1152
Test name
Test status
Simulation time	135598702286 ps
CPU time	98.06 seconds
Started	Apr 28 01:06:17 PM PDT 24
Finished	Apr 28 01:07:56 PM PDT 24
Peak memory	200376 kb
Host	smart-3138ccb3-cc26-45f7-b3ee-d3899eaade66
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4134058331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.4134058331
Directory	/workspace/21.uart_fifo_full/latest

Test location	/workspace/coverage/default/21.uart_fifo_overflow.1947000920
Short name	T139
Test name
Test status
Simulation time	118283054651 ps
CPU time	341.26 seconds
Started	Apr 28 01:06:22 PM PDT 24
Finished	Apr 28 01:12:05 PM PDT 24
Peak memory	200360 kb
Host	smart-6b79b845-f8b0-4c50-9acb-6f0d7b1b5128
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1947000920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.1947000920
Directory	/workspace/21.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/21.uart_fifo_reset.2644030795
Short name	T182
Test name
Test status
Simulation time	26196937821 ps
CPU time	43.63 seconds
Started	Apr 28 01:06:18 PM PDT 24
Finished	Apr 28 01:07:02 PM PDT 24
Peak memory	200396 kb
Host	smart-18800228-ac76-445a-b199-f04a50f6e484
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2644030795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.2644030795
Directory	/workspace/21.uart_fifo_reset/latest

Test location	/workspace/coverage/default/21.uart_intr.1864689335
Short name	T1125
Test name
Test status
Simulation time	244599203557 ps
CPU time	342.35 seconds
Started	Apr 28 01:06:17 PM PDT 24
Finished	Apr 28 01:12:00 PM PDT 24
Peak memory	197544 kb
Host	smart-e30d152d-d98d-4a6c-bc40-58dc73325fe3
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864689335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.1864689335
Directory	/workspace/21.uart_intr/latest

Test location	/workspace/coverage/default/21.uart_long_xfer_wo_dly.1708908381
Short name	T42
Test name
Test status
Simulation time	76418872868 ps
CPU time	616.08 seconds
Started	Apr 28 01:06:17 PM PDT 24
Finished	Apr 28 01:16:35 PM PDT 24
Peak memory	200388 kb
Host	smart-2e6cd670-8455-4222-a350-acfceb22bef8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1708908381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.1708908381
Directory	/workspace/21.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/21.uart_loopback.494368614
Short name	T20
Test name
Test status
Simulation time	11986687927 ps
CPU time	13.03 seconds
Started	Apr 28 01:06:16 PM PDT 24
Finished	Apr 28 01:06:30 PM PDT 24
Peak memory	200412 kb
Host	smart-886c82e0-1faa-4550-a571-fccf8627acc8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=494368614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.494368614
Directory	/workspace/21.uart_loopback/latest

Test location	/workspace/coverage/default/21.uart_perf.3320271575
Short name	T605
Test name
Test status
Simulation time	5390104905 ps
CPU time	62.21 seconds
Started	Apr 28 01:06:21 PM PDT 24
Finished	Apr 28 01:07:25 PM PDT 24
Peak memory	200424 kb
Host	smart-f6dea42b-2afc-4228-acb6-9c81ea2be30b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3320271575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.3320271575
Directory	/workspace/21.uart_perf/latest

Test location	/workspace/coverage/default/21.uart_rx_oversample.3462581086
Short name	T871
Test name
Test status
Simulation time	1599636136 ps
CPU time	3.74 seconds
Started	Apr 28 01:06:16 PM PDT 24
Finished	Apr 28 01:06:20 PM PDT 24
Peak memory	198364 kb
Host	smart-31f28f1d-bf6c-40fe-bdcd-a98e15872d06
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3462581086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.3462581086
Directory	/workspace/21.uart_rx_oversample/latest

Test location	/workspace/coverage/default/21.uart_rx_parity_err.3252039550
Short name	T964
Test name
Test status
Simulation time	16089243823 ps
CPU time	28.26 seconds
Started	Apr 28 01:06:16 PM PDT 24
Finished	Apr 28 01:06:45 PM PDT 24
Peak memory	200228 kb
Host	smart-9ada762a-c86a-4dfe-9a5a-0068932aa978
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3252039550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.3252039550
Directory	/workspace/21.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/21.uart_rx_start_bit_filter.774935749
Short name	T1146
Test name
Test status
Simulation time	7288167301 ps
CPU time	12.18 seconds
Started	Apr 28 01:06:21 PM PDT 24
Finished	Apr 28 01:06:34 PM PDT 24
Peak memory	196724 kb
Host	smart-6fbd2e02-dba5-4480-8b46-d6e1a1227ed9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=774935749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.774935749
Directory	/workspace/21.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/21.uart_smoke.3235189020
Short name	T386
Test name
Test status
Simulation time	649965223 ps
CPU time	3.18 seconds
Started	Apr 28 01:06:19 PM PDT 24
Finished	Apr 28 01:06:22 PM PDT 24
Peak memory	198784 kb
Host	smart-24f9e6b8-3317-4b16-ac54-0c5fdd4b9f88
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3235189020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.3235189020
Directory	/workspace/21.uart_smoke/latest

Test location	/workspace/coverage/default/21.uart_tx_ovrd.4259276938
Short name	T369
Test name
Test status
Simulation time	1250799387 ps
CPU time	2.25 seconds
Started	Apr 28 01:06:18 PM PDT 24
Finished	Apr 28 01:06:21 PM PDT 24
Peak memory	198596 kb
Host	smart-2e998ce2-1b73-450d-bd10-2ac43780f5eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4259276938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.4259276938
Directory	/workspace/21.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/21.uart_tx_rx.1195995720
Short name	T898
Test name
Test status
Simulation time	166547141502 ps
CPU time	66.47 seconds
Started	Apr 28 01:06:17 PM PDT 24
Finished	Apr 28 01:07:24 PM PDT 24
Peak memory	200376 kb
Host	smart-ba7f32e7-ffe4-415c-bb8f-f2a85da88324
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1195995720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.1195995720
Directory	/workspace/21.uart_tx_rx/latest

Test location	/workspace/coverage/default/211.uart_fifo_reset.870478617
Short name	T596
Test name
Test status
Simulation time	83362831424 ps
CPU time	132.88 seconds
Started	Apr 28 01:10:29 PM PDT 24
Finished	Apr 28 01:12:42 PM PDT 24
Peak memory	200308 kb
Host	smart-a2b63f59-4643-45ec-9270-cc775453ba3a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=870478617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.870478617
Directory	/workspace/211.uart_fifo_reset/latest

Test location	/workspace/coverage/default/212.uart_fifo_reset.2869705966
Short name	T474
Test name
Test status
Simulation time	323495696987 ps
CPU time	39.98 seconds
Started	Apr 28 01:10:29 PM PDT 24
Finished	Apr 28 01:11:10 PM PDT 24
Peak memory	200452 kb
Host	smart-376b0c48-76e9-4801-8f55-d71a9c8d7b61
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2869705966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.2869705966
Directory	/workspace/212.uart_fifo_reset/latest

Test location	/workspace/coverage/default/213.uart_fifo_reset.2754084140
Short name	T1124
Test name
Test status
Simulation time	61410715031 ps
CPU time	15.35 seconds
Started	Apr 28 01:10:31 PM PDT 24
Finished	Apr 28 01:10:47 PM PDT 24
Peak memory	200460 kb
Host	smart-f0521563-1d1e-4b24-9392-6ade4471dc92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2754084140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2754084140
Directory	/workspace/213.uart_fifo_reset/latest

Test location	/workspace/coverage/default/214.uart_fifo_reset.3579149196
Short name	T825
Test name
Test status
Simulation time	14920925037 ps
CPU time	23.64 seconds
Started	Apr 28 01:10:28 PM PDT 24
Finished	Apr 28 01:10:53 PM PDT 24
Peak memory	200320 kb
Host	smart-7b0b6f15-5fa7-4a5c-bf77-1249bc6ba485
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3579149196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.3579149196
Directory	/workspace/214.uart_fifo_reset/latest

Test location	/workspace/coverage/default/215.uart_fifo_reset.931645673
Short name	T1115
Test name
Test status
Simulation time	16866019986 ps
CPU time	27.32 seconds
Started	Apr 28 01:10:29 PM PDT 24
Finished	Apr 28 01:10:57 PM PDT 24
Peak memory	200312 kb
Host	smart-595d5dca-9253-46d1-a2db-ab47598bcfce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=931645673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.931645673
Directory	/workspace/215.uart_fifo_reset/latest

Test location	/workspace/coverage/default/217.uart_fifo_reset.1257206423
Short name	T584
Test name
Test status
Simulation time	302428010548 ps
CPU time	38.37 seconds
Started	Apr 28 01:10:29 PM PDT 24
Finished	Apr 28 01:11:08 PM PDT 24
Peak memory	200332 kb
Host	smart-5f7c1cea-9009-4936-baf9-347a5e4a2373
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1257206423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1257206423
Directory	/workspace/217.uart_fifo_reset/latest

Test location	/workspace/coverage/default/218.uart_fifo_reset.250437088
Short name	T962
Test name
Test status
Simulation time	51826857697 ps
CPU time	15.26 seconds
Started	Apr 28 01:10:33 PM PDT 24
Finished	Apr 28 01:10:48 PM PDT 24
Peak memory	200448 kb
Host	smart-216bf822-0a65-4d85-acef-e31c281af30b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=250437088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.250437088
Directory	/workspace/218.uart_fifo_reset/latest

Test location	/workspace/coverage/default/22.uart_alert_test.2075095768
Short name	T22
Test name
Test status
Simulation time	13556095 ps
CPU time	0.58 seconds
Started	Apr 28 01:06:22 PM PDT 24
Finished	Apr 28 01:06:24 PM PDT 24
Peak memory	195804 kb
Host	smart-38b3454d-2bdd-42df-9552-8f50ff1b3462
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075095768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.2075095768
Directory	/workspace/22.uart_alert_test/latest

Test location	/workspace/coverage/default/22.uart_fifo_full.3123886607
Short name	T280
Test name
Test status
Simulation time	205610186296 ps
CPU time	579.41 seconds
Started	Apr 28 01:06:16 PM PDT 24
Finished	Apr 28 01:15:56 PM PDT 24
Peak memory	200360 kb
Host	smart-f1206dfd-67df-4bcd-bedb-dc759782657f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3123886607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.3123886607
Directory	/workspace/22.uart_fifo_full/latest

Test location	/workspace/coverage/default/22.uart_fifo_overflow.2382079442
Short name	T1131
Test name
Test status
Simulation time	28722351930 ps
CPU time	28.91 seconds
Started	Apr 28 01:06:22 PM PDT 24
Finished	Apr 28 01:06:52 PM PDT 24
Peak memory	200396 kb
Host	smart-84568347-6067-40c6-9c39-d1ee77675f1f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2382079442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2382079442
Directory	/workspace/22.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/22.uart_fifo_reset.1342294318
Short name	T1084
Test name
Test status
Simulation time	26133527826 ps
CPU time	11.44 seconds
Started	Apr 28 01:06:16 PM PDT 24
Finished	Apr 28 01:06:28 PM PDT 24
Peak memory	200484 kb
Host	smart-f2ffa8f4-9979-4050-a33f-307080e54c58
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1342294318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.1342294318
Directory	/workspace/22.uart_fifo_reset/latest

Test location	/workspace/coverage/default/22.uart_intr.2156201842
Short name	T822
Test name
Test status
Simulation time	47262996929 ps
CPU time	19.3 seconds
Started	Apr 28 01:06:18 PM PDT 24
Finished	Apr 28 01:06:38 PM PDT 24
Peak memory	199248 kb
Host	smart-53069925-e056-4d12-b1f5-ee8b19f993f5
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156201842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.2156201842
Directory	/workspace/22.uart_intr/latest

Test location	/workspace/coverage/default/22.uart_long_xfer_wo_dly.1723216611
Short name	T41
Test name
Test status
Simulation time	31757881777 ps
CPU time	64.72 seconds
Started	Apr 28 01:06:26 PM PDT 24
Finished	Apr 28 01:07:31 PM PDT 24
Peak memory	200380 kb
Host	smart-a835045d-2718-4407-b9ba-79eedf10ccd8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1723216611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.1723216611
Directory	/workspace/22.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/22.uart_loopback.1010538683
Short name	T1020
Test name
Test status
Simulation time	9439255532 ps
CPU time	13.11 seconds
Started	Apr 28 01:06:21 PM PDT 24
Finished	Apr 28 01:06:35 PM PDT 24
Peak memory	200436 kb
Host	smart-6ba71b2b-7bc0-4955-a898-4db92d2bfcb2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1010538683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1010538683
Directory	/workspace/22.uart_loopback/latest

Test location	/workspace/coverage/default/22.uart_noise_filter.1950602436
Short name	T1104
Test name
Test status
Simulation time	4361694517 ps
CPU time	8.99 seconds
Started	Apr 28 01:06:16 PM PDT 24
Finished	Apr 28 01:06:26 PM PDT 24
Peak memory	200380 kb
Host	smart-e2fd246f-36db-4208-81d8-0b60c1e45f69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1950602436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.1950602436
Directory	/workspace/22.uart_noise_filter/latest

Test location	/workspace/coverage/default/22.uart_perf.1237356802
Short name	T963
Test name
Test status
Simulation time	14310843324 ps
CPU time	112.09 seconds
Started	Apr 28 01:06:24 PM PDT 24
Finished	Apr 28 01:08:16 PM PDT 24
Peak memory	200404 kb
Host	smart-8531dc82-94d2-456b-b4a5-22dcda420d69
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1237356802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.1237356802
Directory	/workspace/22.uart_perf/latest

Test location	/workspace/coverage/default/22.uart_rx_oversample.324894612
Short name	T920
Test name
Test status
Simulation time	5647899978 ps
CPU time	12.95 seconds
Started	Apr 28 01:06:21 PM PDT 24
Finished	Apr 28 01:06:35 PM PDT 24
Peak memory	199620 kb
Host	smart-107bb2f5-92ca-4131-9d45-fbf0a8d3a701
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=324894612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.324894612
Directory	/workspace/22.uart_rx_oversample/latest

Test location	/workspace/coverage/default/22.uart_rx_parity_err.3639377322
Short name	T882
Test name
Test status
Simulation time	215804795551 ps
CPU time	531.96 seconds
Started	Apr 28 01:06:18 PM PDT 24
Finished	Apr 28 01:15:11 PM PDT 24
Peak memory	200344 kb
Host	smart-31cf606c-60bc-4547-be8d-36383a37b411
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3639377322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.3639377322
Directory	/workspace/22.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/22.uart_rx_start_bit_filter.1323818454
Short name	T591
Test name
Test status
Simulation time	5992558742 ps
CPU time	5 seconds
Started	Apr 28 01:06:17 PM PDT 24
Finished	Apr 28 01:06:22 PM PDT 24
Peak memory	196296 kb
Host	smart-c6d84e24-779e-4895-bbaf-acd29e3ffcc3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1323818454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.1323818454
Directory	/workspace/22.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/22.uart_smoke.1003256604
Short name	T270
Test name
Test status
Simulation time	5723603257 ps
CPU time	8.35 seconds
Started	Apr 28 01:06:21 PM PDT 24
Finished	Apr 28 01:06:29 PM PDT 24
Peak memory	200160 kb
Host	smart-e986d71a-b545-4cd9-a126-02c215e96402
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1003256604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.1003256604
Directory	/workspace/22.uart_smoke/latest

Test location	/workspace/coverage/default/22.uart_stress_all.922788322
Short name	T793
Test name
Test status
Simulation time	59369403381 ps
CPU time	74.28 seconds
Started	Apr 28 01:06:22 PM PDT 24
Finished	Apr 28 01:07:38 PM PDT 24
Peak memory	200412 kb
Host	smart-9c8eb963-9141-4e4f-9243-a4fcd0fbe167
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922788322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.922788322
Directory	/workspace/22.uart_stress_all/latest

Test location	/workspace/coverage/default/22.uart_stress_all_with_rand_reset.3305970194
Short name	T910
Test name
Test status
Simulation time	340427377301 ps
CPU time	841.27 seconds
Started	Apr 28 01:06:23 PM PDT 24
Finished	Apr 28 01:20:25 PM PDT 24
Peak memory	216760 kb
Host	smart-2403789e-4e16-4e26-b56b-076960caac1c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305970194 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.3305970194
Directory	/workspace/22.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/22.uart_tx_ovrd.657298570
Short name	T108
Test name
Test status
Simulation time	5967228025 ps
CPU time	22.66 seconds
Started	Apr 28 01:06:21 PM PDT 24
Finished	Apr 28 01:06:45 PM PDT 24
Peak memory	200216 kb
Host	smart-b7f877fe-1630-4a94-903d-7e5b6b0346d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=657298570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.657298570
Directory	/workspace/22.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/22.uart_tx_rx.6005673
Short name	T451
Test name
Test status
Simulation time	32048249716 ps
CPU time	15.36 seconds
Started	Apr 28 01:06:18 PM PDT 24
Finished	Apr 28 01:06:34 PM PDT 24
Peak memory	200376 kb
Host	smart-1aaaf955-a1de-4f45-b582-b35fbde5583d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=6005673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.6005673
Directory	/workspace/22.uart_tx_rx/latest

Test location	/workspace/coverage/default/220.uart_fifo_reset.373150735
Short name	T70
Test name
Test status
Simulation time	79290491704 ps
CPU time	39.07 seconds
Started	Apr 28 01:10:35 PM PDT 24
Finished	Apr 28 01:11:14 PM PDT 24
Peak memory	200300 kb
Host	smart-f0f45315-15dc-46bb-8914-ffc17a94712c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=373150735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.373150735
Directory	/workspace/220.uart_fifo_reset/latest

Test location	/workspace/coverage/default/221.uart_fifo_reset.4180087704
Short name	T325
Test name
Test status
Simulation time	159676288505 ps
CPU time	21.14 seconds
Started	Apr 28 01:10:33 PM PDT 24
Finished	Apr 28 01:10:55 PM PDT 24
Peak memory	198460 kb
Host	smart-cff9b1e7-a27c-444a-b921-7e0cd93553c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4180087704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.4180087704
Directory	/workspace/221.uart_fifo_reset/latest

Test location	/workspace/coverage/default/223.uart_fifo_reset.3902220446
Short name	T1091
Test name
Test status
Simulation time	13787618325 ps
CPU time	19.39 seconds
Started	Apr 28 01:10:34 PM PDT 24
Finished	Apr 28 01:10:54 PM PDT 24
Peak memory	200004 kb
Host	smart-3670c1f1-807e-4397-ba01-3f1a6c1d819a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3902220446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.3902220446
Directory	/workspace/223.uart_fifo_reset/latest

Test location	/workspace/coverage/default/224.uart_fifo_reset.3802473691
Short name	T883
Test name
Test status
Simulation time	84449808098 ps
CPU time	37.09 seconds
Started	Apr 28 01:10:33 PM PDT 24
Finished	Apr 28 01:11:11 PM PDT 24
Peak memory	199744 kb
Host	smart-44b6ea7f-ae30-4446-9d10-ee19ea0e6a64
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3802473691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.3802473691
Directory	/workspace/224.uart_fifo_reset/latest

Test location	/workspace/coverage/default/225.uart_fifo_reset.1266295541
Short name	T289
Test name
Test status
Simulation time	34129392157 ps
CPU time	13.53 seconds
Started	Apr 28 01:10:38 PM PDT 24
Finished	Apr 28 01:10:52 PM PDT 24
Peak memory	200040 kb
Host	smart-b9f3f354-fb8f-4948-a8fc-53b39b8a7a59
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1266295541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.1266295541
Directory	/workspace/225.uart_fifo_reset/latest

Test location	/workspace/coverage/default/226.uart_fifo_reset.904179815
Short name	T834
Test name
Test status
Simulation time	138763602947 ps
CPU time	257.04 seconds
Started	Apr 28 01:10:40 PM PDT 24
Finished	Apr 28 01:14:58 PM PDT 24
Peak memory	200388 kb
Host	smart-a1f486b4-7750-4c92-b22e-989728aac363
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=904179815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.904179815
Directory	/workspace/226.uart_fifo_reset/latest

Test location	/workspace/coverage/default/227.uart_fifo_reset.1199675295
Short name	T922
Test name
Test status
Simulation time	32265559801 ps
CPU time	15.47 seconds
Started	Apr 28 01:10:38 PM PDT 24
Finished	Apr 28 01:10:54 PM PDT 24
Peak memory	200324 kb
Host	smart-1da45c1d-8d5b-4f0b-b801-605325578136
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1199675295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.1199675295
Directory	/workspace/227.uart_fifo_reset/latest

Test location	/workspace/coverage/default/228.uart_fifo_reset.4226716151
Short name	T493
Test name
Test status
Simulation time	84022024865 ps
CPU time	73.93 seconds
Started	Apr 28 01:10:44 PM PDT 24
Finished	Apr 28 01:11:59 PM PDT 24
Peak memory	200356 kb
Host	smart-e689fc83-7245-4c7a-8d08-f49516d66fb9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4226716151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.4226716151
Directory	/workspace/228.uart_fifo_reset/latest

Test location	/workspace/coverage/default/229.uart_fifo_reset.369462419
Short name	T589
Test name
Test status
Simulation time	51440023623 ps
CPU time	43.49 seconds
Started	Apr 28 01:10:46 PM PDT 24
Finished	Apr 28 01:11:30 PM PDT 24
Peak memory	200392 kb
Host	smart-439a2de3-ed5e-4440-9692-e99d80a263b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=369462419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.369462419
Directory	/workspace/229.uart_fifo_reset/latest

Test location	/workspace/coverage/default/23.uart_alert_test.997624084
Short name	T421
Test name
Test status
Simulation time	14079768 ps
CPU time	0.57 seconds
Started	Apr 28 01:06:27 PM PDT 24
Finished	Apr 28 01:06:29 PM PDT 24
Peak memory	195808 kb
Host	smart-99bd8c70-cdf1-4233-bd10-0c1d493e32f3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997624084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.997624084
Directory	/workspace/23.uart_alert_test/latest

Test location	/workspace/coverage/default/23.uart_fifo_full.4271843347
Short name	T1167
Test name
Test status
Simulation time	133516848319 ps
CPU time	130.18 seconds
Started	Apr 28 01:06:27 PM PDT 24
Finished	Apr 28 01:08:38 PM PDT 24
Peak memory	200444 kb
Host	smart-c9e480c6-2fd5-4087-8c27-189b025dbe1e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4271843347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.4271843347
Directory	/workspace/23.uart_fifo_full/latest

Test location	/workspace/coverage/default/23.uart_fifo_overflow.711132272
Short name	T172
Test name
Test status
Simulation time	150303253127 ps
CPU time	122.93 seconds
Started	Apr 28 01:06:24 PM PDT 24
Finished	Apr 28 01:08:28 PM PDT 24
Peak memory	200352 kb
Host	smart-694cf362-3a79-4701-bd20-9d0735ff3bef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=711132272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.711132272
Directory	/workspace/23.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/23.uart_fifo_reset.1514824059
Short name	T287
Test name
Test status
Simulation time	54027605119 ps
CPU time	19.96 seconds
Started	Apr 28 01:06:22 PM PDT 24
Finished	Apr 28 01:06:43 PM PDT 24
Peak memory	200380 kb
Host	smart-12dd4aff-0220-4435-a058-dcad2ecaec6a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1514824059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.1514824059
Directory	/workspace/23.uart_fifo_reset/latest

Test location	/workspace/coverage/default/23.uart_intr.3411412155
Short name	T1082
Test name
Test status
Simulation time	15140102770 ps
CPU time	23.59 seconds
Started	Apr 28 01:06:22 PM PDT 24
Finished	Apr 28 01:06:46 PM PDT 24
Peak memory	200220 kb
Host	smart-15e8efa7-6261-474a-8186-42d55555e20e
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411412155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.3411412155
Directory	/workspace/23.uart_intr/latest

Test location	/workspace/coverage/default/23.uart_long_xfer_wo_dly.2996674516
Short name	T1143
Test name
Test status
Simulation time	105811790021 ps
CPU time	619 seconds
Started	Apr 28 01:06:27 PM PDT 24
Finished	Apr 28 01:16:47 PM PDT 24
Peak memory	200472 kb
Host	smart-87c0d13e-f8a5-4600-9bda-bb933d4a8972
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2996674516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.2996674516
Directory	/workspace/23.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/23.uart_loopback.1039222290
Short name	T564
Test name
Test status
Simulation time	9233847902 ps
CPU time	15.16 seconds
Started	Apr 28 01:06:27 PM PDT 24
Finished	Apr 28 01:06:43 PM PDT 24
Peak memory	199772 kb
Host	smart-4678b88e-8de0-4579-8f65-3f5f2eed3d60
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1039222290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.1039222290
Directory	/workspace/23.uart_loopback/latest

Test location	/workspace/coverage/default/23.uart_noise_filter.1753371512
Short name	T284
Test name
Test status
Simulation time	42844564497 ps
CPU time	87.55 seconds
Started	Apr 28 01:06:24 PM PDT 24
Finished	Apr 28 01:07:52 PM PDT 24
Peak memory	208524 kb
Host	smart-ab5effca-a0b0-4e4c-9b42-b24d8dc6a5a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1753371512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.1753371512
Directory	/workspace/23.uart_noise_filter/latest

Test location	/workspace/coverage/default/23.uart_perf.1896548407
Short name	T1157
Test name
Test status
Simulation time	12541481792 ps
CPU time	105.64 seconds
Started	Apr 28 01:06:28 PM PDT 24
Finished	Apr 28 01:08:14 PM PDT 24
Peak memory	200300 kb
Host	smart-a3e84076-08be-4b3b-80c7-492c68c507f7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1896548407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.1896548407
Directory	/workspace/23.uart_perf/latest

Test location	/workspace/coverage/default/23.uart_rx_oversample.715512676
Short name	T730
Test name
Test status
Simulation time	1480742125 ps
CPU time	5.56 seconds
Started	Apr 28 01:06:22 PM PDT 24
Finished	Apr 28 01:06:29 PM PDT 24
Peak memory	197156 kb
Host	smart-8802585c-df36-41c1-954f-5c35a5fe3833
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=715512676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.715512676
Directory	/workspace/23.uart_rx_oversample/latest

Test location	/workspace/coverage/default/23.uart_rx_parity_err.3729350604
Short name	T143
Test name
Test status
Simulation time	27025954047 ps
CPU time	47.11 seconds
Started	Apr 28 01:06:27 PM PDT 24
Finished	Apr 28 01:07:15 PM PDT 24
Peak memory	200248 kb
Host	smart-b6082582-94fa-4280-b4c3-2e2711f4c13c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3729350604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.3729350604
Directory	/workspace/23.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/23.uart_rx_start_bit_filter.2816820384
Short name	T848
Test name
Test status
Simulation time	2986280278 ps
CPU time	1.85 seconds
Started	Apr 28 01:06:29 PM PDT 24
Finished	Apr 28 01:06:31 PM PDT 24
Peak memory	196248 kb
Host	smart-617b068c-f600-46b7-ab7f-ab1f11b14020
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2816820384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.2816820384
Directory	/workspace/23.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/23.uart_smoke.4288427955
Short name	T573
Test name
Test status
Simulation time	737274564 ps
CPU time	2.99 seconds
Started	Apr 28 01:06:22 PM PDT 24
Finished	Apr 28 01:06:26 PM PDT 24
Peak memory	199112 kb
Host	smart-6c646796-520d-42d2-8191-547636c1c868
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4288427955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.4288427955
Directory	/workspace/23.uart_smoke/latest

Test location	/workspace/coverage/default/23.uart_stress_all.1555987009
Short name	T140
Test name
Test status
Simulation time	99188344670 ps
CPU time	155.28 seconds
Started	Apr 28 01:06:28 PM PDT 24
Finished	Apr 28 01:09:04 PM PDT 24
Peak memory	200296 kb
Host	smart-8f021831-7c26-45ec-9332-4d150bd67d65
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555987009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.1555987009
Directory	/workspace/23.uart_stress_all/latest

Test location	/workspace/coverage/default/23.uart_tx_ovrd.1803584758
Short name	T274
Test name
Test status
Simulation time	1399045336 ps
CPU time	2.94 seconds
Started	Apr 28 01:06:27 PM PDT 24
Finished	Apr 28 01:06:31 PM PDT 24
Peak memory	200080 kb
Host	smart-9dc0f559-39d3-4bb9-9fcb-fbe26d3397e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1803584758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.1803584758
Directory	/workspace/23.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/23.uart_tx_rx.1188736007
Short name	T618
Test name
Test status
Simulation time	42414238179 ps
CPU time	68.16 seconds
Started	Apr 28 01:06:22 PM PDT 24
Finished	Apr 28 01:07:31 PM PDT 24
Peak memory	200272 kb
Host	smart-81176d47-e962-4b9b-a2d2-18ce228d1e74
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1188736007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.1188736007
Directory	/workspace/23.uart_tx_rx/latest

Test location	/workspace/coverage/default/230.uart_fifo_reset.766802884
Short name	T551
Test name
Test status
Simulation time	13313751315 ps
CPU time	34.22 seconds
Started	Apr 28 01:10:43 PM PDT 24
Finished	Apr 28 01:11:18 PM PDT 24
Peak memory	200436 kb
Host	smart-7eb51abe-bc26-442c-86b7-c9a70aa45456
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=766802884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.766802884
Directory	/workspace/230.uart_fifo_reset/latest

Test location	/workspace/coverage/default/231.uart_fifo_reset.760767930
Short name	T414
Test name
Test status
Simulation time	69688969458 ps
CPU time	34.01 seconds
Started	Apr 28 01:10:45 PM PDT 24
Finished	Apr 28 01:11:20 PM PDT 24
Peak memory	200144 kb
Host	smart-262eb287-1b14-444b-b15c-02d3151ecdda
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=760767930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.760767930
Directory	/workspace/231.uart_fifo_reset/latest

Test location	/workspace/coverage/default/232.uart_fifo_reset.1708885794
Short name	T199
Test name
Test status
Simulation time	13265091725 ps
CPU time	20.75 seconds
Started	Apr 28 01:10:45 PM PDT 24
Finished	Apr 28 01:11:07 PM PDT 24
Peak memory	200260 kb
Host	smart-0608eacd-80fc-4702-9fb8-3c7d9b938a89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1708885794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.1708885794
Directory	/workspace/232.uart_fifo_reset/latest

Test location	/workspace/coverage/default/233.uart_fifo_reset.4165604107
Short name	T698
Test name
Test status
Simulation time	84027046926 ps
CPU time	33.58 seconds
Started	Apr 28 01:10:45 PM PDT 24
Finished	Apr 28 01:11:19 PM PDT 24
Peak memory	200424 kb
Host	smart-f959af3c-b2e2-4608-942f-90d519cc3adf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4165604107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.4165604107
Directory	/workspace/233.uart_fifo_reset/latest

Test location	/workspace/coverage/default/234.uart_fifo_reset.1470741497
Short name	T384
Test name
Test status
Simulation time	33154007999 ps
CPU time	15.54 seconds
Started	Apr 28 01:10:44 PM PDT 24
Finished	Apr 28 01:11:01 PM PDT 24
Peak memory	200368 kb
Host	smart-11808932-e75f-400d-b28f-63603405c924
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1470741497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.1470741497
Directory	/workspace/234.uart_fifo_reset/latest

Test location	/workspace/coverage/default/235.uart_fifo_reset.1176031287
Short name	T230
Test name
Test status
Simulation time	47301360191 ps
CPU time	19.21 seconds
Started	Apr 28 01:10:48 PM PDT 24
Finished	Apr 28 01:11:08 PM PDT 24
Peak memory	200392 kb
Host	smart-b77c1eee-4bfa-4ca8-907e-7c9e247381af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1176031287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.1176031287
Directory	/workspace/235.uart_fifo_reset/latest

Test location	/workspace/coverage/default/236.uart_fifo_reset.1278782348
Short name	T326
Test name
Test status
Simulation time	18580520203 ps
CPU time	14.43 seconds
Started	Apr 28 01:10:45 PM PDT 24
Finished	Apr 28 01:11:01 PM PDT 24
Peak memory	200052 kb
Host	smart-bd5a6af5-97d7-4cca-8e78-d14fbb97d9c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1278782348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.1278782348
Directory	/workspace/236.uart_fifo_reset/latest

Test location	/workspace/coverage/default/238.uart_fifo_reset.1655812613
Short name	T367
Test name
Test status
Simulation time	141006347652 ps
CPU time	69.02 seconds
Started	Apr 28 01:10:42 PM PDT 24
Finished	Apr 28 01:11:52 PM PDT 24
Peak memory	200432 kb
Host	smart-64493931-ceae-452c-955e-83051ebe3209
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1655812613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.1655812613
Directory	/workspace/238.uart_fifo_reset/latest

Test location	/workspace/coverage/default/24.uart_alert_test.2118448415
Short name	T515
Test name
Test status
Simulation time	14556715 ps
CPU time	0.55 seconds
Started	Apr 28 01:06:32 PM PDT 24
Finished	Apr 28 01:06:33 PM PDT 24
Peak memory	195828 kb
Host	smart-47797349-b7cd-4e87-b2f4-b87aaf8dd318
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118448415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.2118448415
Directory	/workspace/24.uart_alert_test/latest

Test location	/workspace/coverage/default/24.uart_fifo_full.1408212287
Short name	T758
Test name
Test status
Simulation time	51987230286 ps
CPU time	14.72 seconds
Started	Apr 28 01:06:28 PM PDT 24
Finished	Apr 28 01:06:43 PM PDT 24
Peak memory	200228 kb
Host	smart-6844d52e-a13c-4405-add0-d841dfeda02f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1408212287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.1408212287
Directory	/workspace/24.uart_fifo_full/latest

Test location	/workspace/coverage/default/24.uart_fifo_overflow.2815504540
Short name	T167
Test name
Test status
Simulation time	19950749654 ps
CPU time	28.33 seconds
Started	Apr 28 01:06:28 PM PDT 24
Finished	Apr 28 01:06:57 PM PDT 24
Peak memory	200236 kb
Host	smart-5d184ac1-3d3b-4857-9c35-71078c2d00c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2815504540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.2815504540
Directory	/workspace/24.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/24.uart_fifo_reset.2652782088
Short name	T238
Test name
Test status
Simulation time	47770435180 ps
CPU time	19.62 seconds
Started	Apr 28 01:06:27 PM PDT 24
Finished	Apr 28 01:06:47 PM PDT 24
Peak memory	200292 kb
Host	smart-e01b540d-1b15-4d1d-8072-91060fc9e187
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2652782088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.2652782088
Directory	/workspace/24.uart_fifo_reset/latest

Test location	/workspace/coverage/default/24.uart_intr.373178077
Short name	T1030
Test name
Test status
Simulation time	42647271604 ps
CPU time	58.27 seconds
Started	Apr 28 01:06:32 PM PDT 24
Finished	Apr 28 01:07:31 PM PDT 24
Peak memory	200344 kb
Host	smart-fd124937-3a44-4484-a489-9faba0fdde00
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373178077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.373178077
Directory	/workspace/24.uart_intr/latest

Test location	/workspace/coverage/default/24.uart_long_xfer_wo_dly.1164912127
Short name	T552
Test name
Test status
Simulation time	86759846263 ps
CPU time	778.44 seconds
Started	Apr 28 01:06:32 PM PDT 24
Finished	Apr 28 01:19:31 PM PDT 24
Peak memory	200364 kb
Host	smart-1d2b9573-b8a4-4dd5-af90-c0db2934960b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1164912127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1164912127
Directory	/workspace/24.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/24.uart_loopback.682160888
Short name	T619
Test name
Test status
Simulation time	2282468420 ps
CPU time	4.33 seconds
Started	Apr 28 01:06:33 PM PDT 24
Finished	Apr 28 01:06:37 PM PDT 24
Peak memory	198600 kb
Host	smart-0b066125-568d-4bfd-a97d-d18db5ccba02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=682160888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.682160888
Directory	/workspace/24.uart_loopback/latest

Test location	/workspace/coverage/default/24.uart_noise_filter.2396593838
Short name	T1113
Test name
Test status
Simulation time	58242475797 ps
CPU time	11.77 seconds
Started	Apr 28 01:06:32 PM PDT 24
Finished	Apr 28 01:06:45 PM PDT 24
Peak memory	195928 kb
Host	smart-58d46fd6-8e16-4a51-8270-6bb69ddfb0bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2396593838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.2396593838
Directory	/workspace/24.uart_noise_filter/latest

Test location	/workspace/coverage/default/24.uart_perf.1113707702
Short name	T926
Test name
Test status
Simulation time	10021121552 ps
CPU time	530.19 seconds
Started	Apr 28 01:06:33 PM PDT 24
Finished	Apr 28 01:15:24 PM PDT 24
Peak memory	200232 kb
Host	smart-8932bc35-ec51-46f9-82e3-a281e5bc13a0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1113707702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.1113707702
Directory	/workspace/24.uart_perf/latest

Test location	/workspace/coverage/default/24.uart_rx_oversample.3315445045
Short name	T725
Test name
Test status
Simulation time	2122905526 ps
CPU time	13.28 seconds
Started	Apr 28 01:06:33 PM PDT 24
Finished	Apr 28 01:06:47 PM PDT 24
Peak memory	198588 kb
Host	smart-91912e6f-4552-4ea2-8cda-114149fe09c3
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3315445045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.3315445045
Directory	/workspace/24.uart_rx_oversample/latest

Test location	/workspace/coverage/default/24.uart_rx_parity_err.1802560040
Short name	T931
Test name
Test status
Simulation time	150108455831 ps
CPU time	58.79 seconds
Started	Apr 28 01:06:36 PM PDT 24
Finished	Apr 28 01:07:36 PM PDT 24
Peak memory	200460 kb
Host	smart-29f98992-e488-4291-baa9-1fdba2c15105
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1802560040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1802560040
Directory	/workspace/24.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/24.uart_rx_start_bit_filter.2138365869
Short name	T491
Test name
Test status
Simulation time	1792622481 ps
CPU time	3.35 seconds
Started	Apr 28 01:06:36 PM PDT 24
Finished	Apr 28 01:06:40 PM PDT 24
Peak memory	195796 kb
Host	smart-f8cabe52-ae15-4f30-b4c3-44de4060fd5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2138365869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.2138365869
Directory	/workspace/24.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/24.uart_smoke.1364788733
Short name	T68
Test name
Test status
Simulation time	6209467068 ps
CPU time	8.24 seconds
Started	Apr 28 01:06:29 PM PDT 24
Finished	Apr 28 01:06:37 PM PDT 24
Peak memory	200128 kb
Host	smart-57af45c8-27d7-4e43-b553-e31f35b90e38
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1364788733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.1364788733
Directory	/workspace/24.uart_smoke/latest

Test location	/workspace/coverage/default/24.uart_stress_all_with_rand_reset.591811379
Short name	T572
Test name
Test status
Simulation time	62981969042 ps
CPU time	707.39 seconds
Started	Apr 28 01:06:33 PM PDT 24
Finished	Apr 28 01:18:21 PM PDT 24
Peak memory	216872 kb
Host	smart-f867d446-2049-4017-b7b8-320be96e9a3d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591811379 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.591811379
Directory	/workspace/24.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/24.uart_tx_ovrd.4067888301
Short name	T547
Test name
Test status
Simulation time	954390225 ps
CPU time	2.1 seconds
Started	Apr 28 01:06:32 PM PDT 24
Finished	Apr 28 01:06:35 PM PDT 24
Peak memory	198800 kb
Host	smart-b691c465-21b1-47ba-80f4-50270a66c68d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4067888301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.4067888301
Directory	/workspace/24.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/24.uart_tx_rx.4239777711
Short name	T643
Test name
Test status
Simulation time	59821757376 ps
CPU time	29.94 seconds
Started	Apr 28 01:06:29 PM PDT 24
Finished	Apr 28 01:06:59 PM PDT 24
Peak memory	200412 kb
Host	smart-b8e3af65-c393-428e-b927-c6151fa0cb08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4239777711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.4239777711
Directory	/workspace/24.uart_tx_rx/latest

Test location	/workspace/coverage/default/240.uart_fifo_reset.3263800223
Short name	T638
Test name
Test status
Simulation time	81756840129 ps
CPU time	165.83 seconds
Started	Apr 28 01:10:48 PM PDT 24
Finished	Apr 28 01:13:34 PM PDT 24
Peak memory	200356 kb
Host	smart-15bfaf45-4d73-4630-97a0-7404154099d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3263800223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.3263800223
Directory	/workspace/240.uart_fifo_reset/latest

Test location	/workspace/coverage/default/241.uart_fifo_reset.960062188
Short name	T196
Test name
Test status
Simulation time	38442312562 ps
CPU time	95.66 seconds
Started	Apr 28 01:10:48 PM PDT 24
Finished	Apr 28 01:12:24 PM PDT 24
Peak memory	200400 kb
Host	smart-a1e5bb6e-4e15-46da-941f-64622ddcfa68
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=960062188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.960062188
Directory	/workspace/241.uart_fifo_reset/latest

Test location	/workspace/coverage/default/242.uart_fifo_reset.1628852713
Short name	T838
Test name
Test status
Simulation time	122063995295 ps
CPU time	34 seconds
Started	Apr 28 01:10:50 PM PDT 24
Finished	Apr 28 01:11:25 PM PDT 24
Peak memory	200404 kb
Host	smart-7b5448f8-3a55-431f-9c54-54b2cbfac8d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1628852713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.1628852713
Directory	/workspace/242.uart_fifo_reset/latest

Test location	/workspace/coverage/default/243.uart_fifo_reset.3416298891
Short name	T1054
Test name
Test status
Simulation time	26075215876 ps
CPU time	28.06 seconds
Started	Apr 28 01:10:48 PM PDT 24
Finished	Apr 28 01:11:17 PM PDT 24
Peak memory	200288 kb
Host	smart-d77a5a75-772f-4e18-893c-f071102261ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3416298891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.3416298891
Directory	/workspace/243.uart_fifo_reset/latest

Test location	/workspace/coverage/default/244.uart_fifo_reset.1584463019
Short name	T568
Test name
Test status
Simulation time	41989872729 ps
CPU time	82.37 seconds
Started	Apr 28 01:10:52 PM PDT 24
Finished	Apr 28 01:12:16 PM PDT 24
Peak memory	200364 kb
Host	smart-972dd85a-4eed-4a21-9520-92732957232a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1584463019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1584463019
Directory	/workspace/244.uart_fifo_reset/latest

Test location	/workspace/coverage/default/245.uart_fifo_reset.1772560252
Short name	T706
Test name
Test status
Simulation time	143973666481 ps
CPU time	63.75 seconds
Started	Apr 28 01:10:47 PM PDT 24
Finished	Apr 28 01:11:51 PM PDT 24
Peak memory	200384 kb
Host	smart-7ccd696c-7d0f-4344-a4bb-7beaa071ee23
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1772560252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.1772560252
Directory	/workspace/245.uart_fifo_reset/latest

Test location	/workspace/coverage/default/247.uart_fifo_reset.2450218382
Short name	T259
Test name
Test status
Simulation time	47754664467 ps
CPU time	87.74 seconds
Started	Apr 28 01:10:52 PM PDT 24
Finished	Apr 28 01:12:21 PM PDT 24
Peak memory	200424 kb
Host	smart-12c1b0c3-63f5-45ed-a1e5-6cf38b2d30ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2450218382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.2450218382
Directory	/workspace/247.uart_fifo_reset/latest

Test location	/workspace/coverage/default/248.uart_fifo_reset.2303536735
Short name	T709
Test name
Test status
Simulation time	135871376537 ps
CPU time	49.6 seconds
Started	Apr 28 01:10:48 PM PDT 24
Finished	Apr 28 01:11:38 PM PDT 24
Peak memory	200436 kb
Host	smart-12edfc20-a406-47dd-bc5d-0a0db22a8f61
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2303536735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.2303536735
Directory	/workspace/248.uart_fifo_reset/latest

Test location	/workspace/coverage/default/249.uart_fifo_reset.214624148
Short name	T794
Test name
Test status
Simulation time	20536701666 ps
CPU time	40.39 seconds
Started	Apr 28 01:10:47 PM PDT 24
Finished	Apr 28 01:11:28 PM PDT 24
Peak memory	200380 kb
Host	smart-7c28dcf2-0dd6-4ff1-9d31-c21d5eb58f1b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=214624148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.214624148
Directory	/workspace/249.uart_fifo_reset/latest

Test location	/workspace/coverage/default/25.uart_alert_test.284817980
Short name	T347
Test name
Test status
Simulation time	13283227 ps
CPU time	0.55 seconds
Started	Apr 28 01:06:42 PM PDT 24
Finished	Apr 28 01:06:43 PM PDT 24
Peak memory	195796 kb
Host	smart-02fb0bd3-7f70-40e2-93c1-4e64d614371c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284817980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.284817980
Directory	/workspace/25.uart_alert_test/latest

Test location	/workspace/coverage/default/25.uart_fifo_overflow.3598641353
Short name	T163
Test name
Test status
Simulation time	56422087983 ps
CPU time	99.46 seconds
Started	Apr 28 01:06:35 PM PDT 24
Finished	Apr 28 01:08:15 PM PDT 24
Peak memory	200244 kb
Host	smart-ff7861c9-e7e1-42b2-b98e-4cabea1fff31
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3598641353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.3598641353
Directory	/workspace/25.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/25.uart_fifo_reset.2732360649
Short name	T707
Test name
Test status
Simulation time	25820510101 ps
CPU time	49.83 seconds
Started	Apr 28 01:06:41 PM PDT 24
Finished	Apr 28 01:07:31 PM PDT 24
Peak memory	200348 kb
Host	smart-7b2fd55b-97d6-44fa-b849-8a2e0b61b3d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2732360649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.2732360649
Directory	/workspace/25.uart_fifo_reset/latest

Test location	/workspace/coverage/default/25.uart_intr.951012255
Short name	T365
Test name
Test status
Simulation time	48536653195 ps
CPU time	46.13 seconds
Started	Apr 28 01:06:39 PM PDT 24
Finished	Apr 28 01:07:26 PM PDT 24
Peak memory	200224 kb
Host	smart-0342b4b5-ec24-4092-b12a-37ad8b6d11f1
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951012255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.951012255
Directory	/workspace/25.uart_intr/latest

Test location	/workspace/coverage/default/25.uart_long_xfer_wo_dly.2508766803
Short name	T425
Test name
Test status
Simulation time	165728642808 ps
CPU time	475.46 seconds
Started	Apr 28 01:06:39 PM PDT 24
Finished	Apr 28 01:14:36 PM PDT 24
Peak memory	200380 kb
Host	smart-6811226f-8d12-46f9-bacc-51271d787fb9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2508766803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.2508766803
Directory	/workspace/25.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/25.uart_loopback.2843210625
Short name	T356
Test name
Test status
Simulation time	12374348419 ps
CPU time	8.51 seconds
Started	Apr 28 01:06:38 PM PDT 24
Finished	Apr 28 01:06:47 PM PDT 24
Peak memory	200400 kb
Host	smart-cf41d54e-9712-4c86-8b7b-5ffb2313470f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2843210625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.2843210625
Directory	/workspace/25.uart_loopback/latest

Test location	/workspace/coverage/default/25.uart_noise_filter.3917627886
Short name	T285
Test name
Test status
Simulation time	221964386423 ps
CPU time	50.43 seconds
Started	Apr 28 01:06:39 PM PDT 24
Finished	Apr 28 01:07:31 PM PDT 24
Peak memory	208040 kb
Host	smart-859988f4-dc95-4c6c-a9a0-330eaefe3335
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3917627886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.3917627886
Directory	/workspace/25.uart_noise_filter/latest

Test location	/workspace/coverage/default/25.uart_perf.2833564268
Short name	T631
Test name
Test status
Simulation time	14252675025 ps
CPU time	171.83 seconds
Started	Apr 28 01:06:39 PM PDT 24
Finished	Apr 28 01:09:33 PM PDT 24
Peak memory	200420 kb
Host	smart-377224a0-6749-421c-8eb0-26c181bab897
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2833564268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.2833564268
Directory	/workspace/25.uart_perf/latest

Test location	/workspace/coverage/default/25.uart_rx_oversample.1932823536
Short name	T1040
Test name
Test status
Simulation time	5657519762 ps
CPU time	40.84 seconds
Started	Apr 28 01:06:39 PM PDT 24
Finished	Apr 28 01:07:21 PM PDT 24
Peak memory	200392 kb
Host	smart-56585ba5-526c-44cc-96c8-87c88f833b1a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1932823536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.1932823536
Directory	/workspace/25.uart_rx_oversample/latest

Test location	/workspace/coverage/default/25.uart_rx_parity_err.211096199
Short name	T129
Test name
Test status
Simulation time	14803567741 ps
CPU time	14.26 seconds
Started	Apr 28 01:06:39 PM PDT 24
Finished	Apr 28 01:06:55 PM PDT 24
Peak memory	200276 kb
Host	smart-f6887612-235f-4195-a7dc-44aa4cde2bf4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=211096199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.211096199
Directory	/workspace/25.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/25.uart_rx_start_bit_filter.1840744121
Short name	T464
Test name
Test status
Simulation time	1564655638 ps
CPU time	1.92 seconds
Started	Apr 28 01:06:45 PM PDT 24
Finished	Apr 28 01:06:48 PM PDT 24
Peak memory	195812 kb
Host	smart-7e3bedca-67df-43aa-9bf0-07b0d85d11b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1840744121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.1840744121
Directory	/workspace/25.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/25.uart_smoke.365461436
Short name	T932
Test name
Test status
Simulation time	626895541 ps
CPU time	3.92 seconds
Started	Apr 28 01:06:32 PM PDT 24
Finished	Apr 28 01:06:36 PM PDT 24
Peak memory	198696 kb
Host	smart-ee623bf6-2a9f-44ac-bfdf-462070400fea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=365461436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.365461436
Directory	/workspace/25.uart_smoke/latest

Test location	/workspace/coverage/default/25.uart_stress_all.3971973233
Short name	T1177
Test name
Test status
Simulation time	78342700602 ps
CPU time	629.55 seconds
Started	Apr 28 01:06:44 PM PDT 24
Finished	Apr 28 01:17:15 PM PDT 24
Peak memory	200404 kb
Host	smart-c6b37165-a455-4c25-acae-522c89872f2a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971973233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.3971973233
Directory	/workspace/25.uart_stress_all/latest

Test location	/workspace/coverage/default/25.uart_stress_all_with_rand_reset.4201622620
Short name	T117
Test name
Test status
Simulation time	431060090867 ps
CPU time	272.06 seconds
Started	Apr 28 01:06:45 PM PDT 24
Finished	Apr 28 01:11:18 PM PDT 24
Peak memory	212272 kb
Host	smart-956156e8-2bd2-4ce7-8d17-fe5186262511
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201622620 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.4201622620
Directory	/workspace/25.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/25.uart_tx_ovrd.1354017457
Short name	T887
Test name
Test status
Simulation time	789028616 ps
CPU time	2.72 seconds
Started	Apr 28 01:06:39 PM PDT 24
Finished	Apr 28 01:06:43 PM PDT 24
Peak memory	200016 kb
Host	smart-165eaf09-b57c-4ebc-9446-1fb6e507a6a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1354017457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.1354017457
Directory	/workspace/25.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/25.uart_tx_rx.4112392965
Short name	T644
Test name
Test status
Simulation time	23758478404 ps
CPU time	11.31 seconds
Started	Apr 28 01:06:33 PM PDT 24
Finished	Apr 28 01:06:45 PM PDT 24
Peak memory	200460 kb
Host	smart-8f599339-d8f3-44f2-893e-66ed001b6e3a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4112392965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.4112392965
Directory	/workspace/25.uart_tx_rx/latest

Test location	/workspace/coverage/default/251.uart_fifo_reset.1612601746
Short name	T1049
Test name
Test status
Simulation time	10265768669 ps
CPU time	18.14 seconds
Started	Apr 28 01:10:53 PM PDT 24
Finished	Apr 28 01:11:13 PM PDT 24
Peak memory	199972 kb
Host	smart-8621e3ca-b848-4e61-9fd6-7c1e3e77f7c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1612601746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.1612601746
Directory	/workspace/251.uart_fifo_reset/latest

Test location	/workspace/coverage/default/252.uart_fifo_reset.3879025246
Short name	T921
Test name
Test status
Simulation time	23307460183 ps
CPU time	47.99 seconds
Started	Apr 28 01:10:54 PM PDT 24
Finished	Apr 28 01:11:43 PM PDT 24
Peak memory	200372 kb
Host	smart-676802fb-d48f-4352-82e9-79c8c21ff5cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3879025246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.3879025246
Directory	/workspace/252.uart_fifo_reset/latest

Test location	/workspace/coverage/default/253.uart_fifo_reset.1907507700
Short name	T133
Test name
Test status
Simulation time	130104024338 ps
CPU time	128.7 seconds
Started	Apr 28 01:10:53 PM PDT 24
Finished	Apr 28 01:13:03 PM PDT 24
Peak memory	200408 kb
Host	smart-c3bf2352-414c-45ea-a4a5-c23589575dac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1907507700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.1907507700
Directory	/workspace/253.uart_fifo_reset/latest

Test location	/workspace/coverage/default/254.uart_fifo_reset.867812324
Short name	T647
Test name
Test status
Simulation time	112488467218 ps
CPU time	30.73 seconds
Started	Apr 28 01:10:54 PM PDT 24
Finished	Apr 28 01:11:26 PM PDT 24
Peak memory	200284 kb
Host	smart-400e517f-4934-4e32-b9a0-b61cbec35f11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=867812324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.867812324
Directory	/workspace/254.uart_fifo_reset/latest

Test location	/workspace/coverage/default/255.uart_fifo_reset.1150713390
Short name	T602
Test name
Test status
Simulation time	131213050287 ps
CPU time	44.02 seconds
Started	Apr 28 01:10:54 PM PDT 24
Finished	Apr 28 01:11:40 PM PDT 24
Peak memory	200400 kb
Host	smart-980414b3-8fea-4eea-b4b2-e012fb0c6125
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1150713390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.1150713390
Directory	/workspace/255.uart_fifo_reset/latest

Test location	/workspace/coverage/default/256.uart_fifo_reset.2753112924
Short name	T195
Test name
Test status
Simulation time	104600103174 ps
CPU time	82.4 seconds
Started	Apr 28 01:10:54 PM PDT 24
Finished	Apr 28 01:12:18 PM PDT 24
Peak memory	200376 kb
Host	smart-d79fe80f-80c0-461c-bc99-be3237a43715
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2753112924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.2753112924
Directory	/workspace/256.uart_fifo_reset/latest

Test location	/workspace/coverage/default/257.uart_fifo_reset.245112364
Short name	T456
Test name
Test status
Simulation time	70929928485 ps
CPU time	132.12 seconds
Started	Apr 28 01:10:54 PM PDT 24
Finished	Apr 28 01:13:08 PM PDT 24
Peak memory	200284 kb
Host	smart-3835c129-0360-440d-bcfd-9896565f8eb7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=245112364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.245112364
Directory	/workspace/257.uart_fifo_reset/latest

Test location	/workspace/coverage/default/259.uart_fifo_reset.2794642623
Short name	T219
Test name
Test status
Simulation time	47052237136 ps
CPU time	33.17 seconds
Started	Apr 28 01:10:54 PM PDT 24
Finished	Apr 28 01:11:28 PM PDT 24
Peak memory	200364 kb
Host	smart-aebb31ea-b87e-4f98-8c28-ff67a26d5454
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2794642623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.2794642623
Directory	/workspace/259.uart_fifo_reset/latest

Test location	/workspace/coverage/default/26.uart_alert_test.740685030
Short name	T953
Test name
Test status
Simulation time	45671785 ps
CPU time	0.57 seconds
Started	Apr 28 01:06:45 PM PDT 24
Finished	Apr 28 01:06:46 PM PDT 24
Peak memory	195656 kb
Host	smart-0a3737f5-33b6-4934-b01e-17359f4df79c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740685030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.740685030
Directory	/workspace/26.uart_alert_test/latest

Test location	/workspace/coverage/default/26.uart_fifo_full.4001186133
Short name	T494
Test name
Test status
Simulation time	203147876438 ps
CPU time	255.31 seconds
Started	Apr 28 01:06:40 PM PDT 24
Finished	Apr 28 01:10:56 PM PDT 24
Peak memory	200288 kb
Host	smart-9858471a-06a8-46cf-a483-97867dcb6a19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4001186133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.4001186133
Directory	/workspace/26.uart_fifo_full/latest

Test location	/workspace/coverage/default/26.uart_fifo_overflow.4163264966
Short name	T520
Test name
Test status
Simulation time	36007154211 ps
CPU time	29.63 seconds
Started	Apr 28 01:06:42 PM PDT 24
Finished	Apr 28 01:07:12 PM PDT 24
Peak memory	200440 kb
Host	smart-50f906aa-7f01-46c2-ab2a-0dd0b41d04ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4163264966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.4163264966
Directory	/workspace/26.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/26.uart_fifo_reset.2115342966
Short name	T1032
Test name
Test status
Simulation time	19531147189 ps
CPU time	29.12 seconds
Started	Apr 28 01:06:39 PM PDT 24
Finished	Apr 28 01:07:10 PM PDT 24
Peak memory	200380 kb
Host	smart-453e7298-0110-498c-9346-abe78a9ec51d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2115342966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.2115342966
Directory	/workspace/26.uart_fifo_reset/latest

Test location	/workspace/coverage/default/26.uart_intr.3281872441
Short name	T1023
Test name
Test status
Simulation time	24468278539 ps
CPU time	59.3 seconds
Started	Apr 28 01:06:39 PM PDT 24
Finished	Apr 28 01:07:40 PM PDT 24
Peak memory	200024 kb
Host	smart-a8491215-8b35-4780-82b8-803389930ea8
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281872441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.3281872441
Directory	/workspace/26.uart_intr/latest

Test location	/workspace/coverage/default/26.uart_long_xfer_wo_dly.1786446663
Short name	T869
Test name
Test status
Simulation time	60528172132 ps
CPU time	205.5 seconds
Started	Apr 28 01:06:43 PM PDT 24
Finished	Apr 28 01:10:10 PM PDT 24
Peak memory	200452 kb
Host	smart-a4c985d4-32ab-450a-91f7-606dbf015c34
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1786446663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1786446663
Directory	/workspace/26.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/26.uart_loopback.3996685566
Short name	T792
Test name
Test status
Simulation time	2190030395 ps
CPU time	5.5 seconds
Started	Apr 28 01:06:44 PM PDT 24
Finished	Apr 28 01:06:51 PM PDT 24
Peak memory	197936 kb
Host	smart-b5f84353-85e1-4099-8a0a-5671855699a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3996685566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.3996685566
Directory	/workspace/26.uart_loopback/latest

Test location	/workspace/coverage/default/26.uart_noise_filter.3682720207
Short name	T469
Test name
Test status
Simulation time	40963483413 ps
CPU time	62.2 seconds
Started	Apr 28 01:06:42 PM PDT 24
Finished	Apr 28 01:07:45 PM PDT 24
Peak memory	200516 kb
Host	smart-808aa448-e702-4fd1-aca5-5dea46e104fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3682720207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.3682720207
Directory	/workspace/26.uart_noise_filter/latest

Test location	/workspace/coverage/default/26.uart_perf.1394133430
Short name	T1045
Test name
Test status
Simulation time	27601932219 ps
CPU time	771.21 seconds
Started	Apr 28 01:06:43 PM PDT 24
Finished	Apr 28 01:19:35 PM PDT 24
Peak memory	200448 kb
Host	smart-5a38a0af-67dd-46d8-85d0-cd1b7a43aec0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1394133430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.1394133430
Directory	/workspace/26.uart_perf/latest

Test location	/workspace/coverage/default/26.uart_rx_oversample.2819295729
Short name	T988
Test name
Test status
Simulation time	1514240090 ps
CPU time	1.76 seconds
Started	Apr 28 01:06:38 PM PDT 24
Finished	Apr 28 01:06:40 PM PDT 24
Peak memory	198496 kb
Host	smart-68a131a0-e498-4353-9651-216980608da8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2819295729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.2819295729
Directory	/workspace/26.uart_rx_oversample/latest

Test location	/workspace/coverage/default/26.uart_rx_parity_err.2608763577
Short name	T273
Test name
Test status
Simulation time	122004545258 ps
CPU time	48.64 seconds
Started	Apr 28 01:06:40 PM PDT 24
Finished	Apr 28 01:07:30 PM PDT 24
Peak memory	199912 kb
Host	smart-cea24685-4813-4977-84b7-a21a160288b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2608763577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.2608763577
Directory	/workspace/26.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/26.uart_rx_start_bit_filter.1894714980
Short name	T567
Test name
Test status
Simulation time	5077563125 ps
CPU time	2.52 seconds
Started	Apr 28 01:06:42 PM PDT 24
Finished	Apr 28 01:06:46 PM PDT 24
Peak memory	196628 kb
Host	smart-0f6c4cf1-4a1c-4c80-bc2d-7b4152022411
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1894714980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.1894714980
Directory	/workspace/26.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/26.uart_smoke.2638030642
Short name	T1136
Test name
Test status
Simulation time	6079065729 ps
CPU time	7.29 seconds
Started	Apr 28 01:06:40 PM PDT 24
Finished	Apr 28 01:06:48 PM PDT 24
Peak memory	200260 kb
Host	smart-418bb85a-b409-49c5-81b5-e425fc78420a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2638030642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.2638030642
Directory	/workspace/26.uart_smoke/latest

Test location	/workspace/coverage/default/26.uart_stress_all_with_rand_reset.194859864
Short name	T705
Test name
Test status
Simulation time	146464024835 ps
CPU time	352.44 seconds
Started	Apr 28 01:06:48 PM PDT 24
Finished	Apr 28 01:12:41 PM PDT 24
Peak memory	216876 kb
Host	smart-25697a03-472e-40fc-aaef-24720fffb4dd
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194859864 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.194859864
Directory	/workspace/26.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/26.uart_tx_ovrd.3234601903
Short name	T900
Test name
Test status
Simulation time	7579428848 ps
CPU time	8.98 seconds
Started	Apr 28 01:06:44 PM PDT 24
Finished	Apr 28 01:06:54 PM PDT 24
Peak memory	199700 kb
Host	smart-8503ed4b-549e-439f-aaef-2413bc55cba0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3234601903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.3234601903
Directory	/workspace/26.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/26.uart_tx_rx.3396811717
Short name	T779
Test name
Test status
Simulation time	42079059380 ps
CPU time	38.43 seconds
Started	Apr 28 01:06:44 PM PDT 24
Finished	Apr 28 01:07:24 PM PDT 24
Peak memory	200444 kb
Host	smart-c7474046-31b5-49c8-a067-d88685835b55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3396811717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.3396811717
Directory	/workspace/26.uart_tx_rx/latest

Test location	/workspace/coverage/default/260.uart_fifo_reset.2431360348
Short name	T1010
Test name
Test status
Simulation time	33229231459 ps
CPU time	58.39 seconds
Started	Apr 28 01:10:54 PM PDT 24
Finished	Apr 28 01:11:54 PM PDT 24
Peak memory	200352 kb
Host	smart-828adc04-6fb6-4723-b502-b40c311e9262
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2431360348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2431360348
Directory	/workspace/260.uart_fifo_reset/latest

Test location	/workspace/coverage/default/262.uart_fifo_reset.993647018
Short name	T6
Test name
Test status
Simulation time	16882711136 ps
CPU time	15.35 seconds
Started	Apr 28 01:10:57 PM PDT 24
Finished	Apr 28 01:11:13 PM PDT 24
Peak memory	200208 kb
Host	smart-248baeeb-4523-445b-b8f1-25b310148310
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=993647018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.993647018
Directory	/workspace/262.uart_fifo_reset/latest

Test location	/workspace/coverage/default/263.uart_fifo_reset.2108190408
Short name	T580
Test name
Test status
Simulation time	25133724607 ps
CPU time	54.58 seconds
Started	Apr 28 01:10:54 PM PDT 24
Finished	Apr 28 01:11:50 PM PDT 24
Peak memory	200348 kb
Host	smart-63fd5d7a-d493-4675-9c68-cc5b2d414191
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2108190408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.2108190408
Directory	/workspace/263.uart_fifo_reset/latest

Test location	/workspace/coverage/default/264.uart_fifo_reset.1735065869
Short name	T1055
Test name
Test status
Simulation time	15357454164 ps
CPU time	29.03 seconds
Started	Apr 28 01:10:54 PM PDT 24
Finished	Apr 28 01:11:25 PM PDT 24
Peak memory	200368 kb
Host	smart-596a3eef-d3f5-4332-a574-e45bb07857bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1735065869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.1735065869
Directory	/workspace/264.uart_fifo_reset/latest

Test location	/workspace/coverage/default/265.uart_fifo_reset.996440364
Short name	T250
Test name
Test status
Simulation time	156978348656 ps
CPU time	62.39 seconds
Started	Apr 28 01:11:07 PM PDT 24
Finished	Apr 28 01:12:10 PM PDT 24
Peak memory	200336 kb
Host	smart-faba72ad-5499-4937-a883-a1a424f9f287
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=996440364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.996440364
Directory	/workspace/265.uart_fifo_reset/latest

Test location	/workspace/coverage/default/266.uart_fifo_reset.43910839
Short name	T828
Test name
Test status
Simulation time	81222428798 ps
CPU time	134.09 seconds
Started	Apr 28 01:10:59 PM PDT 24
Finished	Apr 28 01:13:14 PM PDT 24
Peak memory	200444 kb
Host	smart-f9c1e158-de9c-4f42-9f7a-25d7b1631fe1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=43910839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.43910839
Directory	/workspace/266.uart_fifo_reset/latest

Test location	/workspace/coverage/default/267.uart_fifo_reset.3713585116
Short name	T211
Test name
Test status
Simulation time	185671958902 ps
CPU time	72.53 seconds
Started	Apr 28 01:10:59 PM PDT 24
Finished	Apr 28 01:12:13 PM PDT 24
Peak memory	200420 kb
Host	smart-33000a59-6b33-45d7-a5d1-5c6d3c79beea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3713585116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.3713585116
Directory	/workspace/267.uart_fifo_reset/latest

Test location	/workspace/coverage/default/268.uart_fifo_reset.1529300320
Short name	T743
Test name
Test status
Simulation time	44298904261 ps
CPU time	16.86 seconds
Started	Apr 28 01:10:59 PM PDT 24
Finished	Apr 28 01:11:17 PM PDT 24
Peak memory	199724 kb
Host	smart-45b0c0eb-1f41-4c44-8b5f-9f63ef9e15d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1529300320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.1529300320
Directory	/workspace/268.uart_fifo_reset/latest

Test location	/workspace/coverage/default/269.uart_fifo_reset.674487032
Short name	T1065
Test name
Test status
Simulation time	81340402545 ps
CPU time	156.15 seconds
Started	Apr 28 01:11:00 PM PDT 24
Finished	Apr 28 01:13:37 PM PDT 24
Peak memory	200352 kb
Host	smart-4d7a2264-3eae-4eb8-ac50-8ce3052f05d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=674487032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.674487032
Directory	/workspace/269.uart_fifo_reset/latest

Test location	/workspace/coverage/default/27.uart_alert_test.2706660600
Short name	T780
Test name
Test status
Simulation time	15910777 ps
CPU time	0.54 seconds
Started	Apr 28 01:06:50 PM PDT 24
Finished	Apr 28 01:06:51 PM PDT 24
Peak memory	195708 kb
Host	smart-9bf8e325-4f97-4515-a742-1a108a90f06d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706660600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.2706660600
Directory	/workspace/27.uart_alert_test/latest

Test location	/workspace/coverage/default/27.uart_fifo_overflow.2350060407
Short name	T271
Test name
Test status
Simulation time	67906112984 ps
CPU time	112.83 seconds
Started	Apr 28 01:06:45 PM PDT 24
Finished	Apr 28 01:08:38 PM PDT 24
Peak memory	200360 kb
Host	smart-a2ab66f5-efdb-417e-92c8-55df6a8183c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2350060407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.2350060407
Directory	/workspace/27.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/27.uart_fifo_reset.431161430
Short name	T1000
Test name
Test status
Simulation time	26028480261 ps
CPU time	23.09 seconds
Started	Apr 28 01:06:45 PM PDT 24
Finished	Apr 28 01:07:09 PM PDT 24
Peak memory	200376 kb
Host	smart-ad58a018-3e8c-4e46-8889-53ce2d1462d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=431161430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.431161430
Directory	/workspace/27.uart_fifo_reset/latest

Test location	/workspace/coverage/default/27.uart_intr.3147728031
Short name	T263
Test name
Test status
Simulation time	70335652584 ps
CPU time	102.6 seconds
Started	Apr 28 01:06:46 PM PDT 24
Finished	Apr 28 01:08:29 PM PDT 24
Peak memory	200308 kb
Host	smart-d6cf061e-13b5-45b1-8fe8-3bdfd8bf0d3d
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147728031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.3147728031
Directory	/workspace/27.uart_intr/latest

Test location	/workspace/coverage/default/27.uart_long_xfer_wo_dly.3467472060
Short name	T764
Test name
Test status
Simulation time	162121650025 ps
CPU time	994.35 seconds
Started	Apr 28 01:06:48 PM PDT 24
Finished	Apr 28 01:23:23 PM PDT 24
Peak memory	200368 kb
Host	smart-64018300-7120-4ef9-9069-681d4b8e1b1c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3467472060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.3467472060
Directory	/workspace/27.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/27.uart_loopback.4105374204
Short name	T335
Test name
Test status
Simulation time	10173653366 ps
CPU time	15.91 seconds
Started	Apr 28 01:06:44 PM PDT 24
Finished	Apr 28 01:07:01 PM PDT 24
Peak memory	200304 kb
Host	smart-e43d943e-a7e2-4356-8c09-bb92e4b49ef7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4105374204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.4105374204
Directory	/workspace/27.uart_loopback/latest

Test location	/workspace/coverage/default/27.uart_noise_filter.1550719687
Short name	T621
Test name
Test status
Simulation time	50600230504 ps
CPU time	83.66 seconds
Started	Apr 28 01:06:43 PM PDT 24
Finished	Apr 28 01:08:09 PM PDT 24
Peak memory	200316 kb
Host	smart-692d6773-3011-4ab4-82f3-88ef64484bb3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1550719687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.1550719687
Directory	/workspace/27.uart_noise_filter/latest

Test location	/workspace/coverage/default/27.uart_perf.4198465989
Short name	T683
Test name
Test status
Simulation time	25381391013 ps
CPU time	372.77 seconds
Started	Apr 28 01:06:53 PM PDT 24
Finished	Apr 28 01:13:06 PM PDT 24
Peak memory	200420 kb
Host	smart-4d12c3d5-fbf3-4ca6-b71c-db8349a98dba
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4198465989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.4198465989
Directory	/workspace/27.uart_perf/latest

Test location	/workspace/coverage/default/27.uart_rx_oversample.3919428540
Short name	T67
Test name
Test status
Simulation time	8153984864 ps
CPU time	34.7 seconds
Started	Apr 28 01:06:45 PM PDT 24
Finished	Apr 28 01:07:20 PM PDT 24
Peak memory	198640 kb
Host	smart-1982c446-87ee-4261-9dbc-9b71c44bf895
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3919428540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.3919428540
Directory	/workspace/27.uart_rx_oversample/latest

Test location	/workspace/coverage/default/27.uart_rx_parity_err.1166137806
Short name	T766
Test name
Test status
Simulation time	115533480534 ps
CPU time	34.26 seconds
Started	Apr 28 01:06:43 PM PDT 24
Finished	Apr 28 01:07:18 PM PDT 24
Peak memory	200220 kb
Host	smart-3ba86443-1600-4570-a3fd-dd4b7ac476bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1166137806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.1166137806
Directory	/workspace/27.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/27.uart_rx_start_bit_filter.452773733
Short name	T598
Test name
Test status
Simulation time	6018921367 ps
CPU time	1.12 seconds
Started	Apr 28 01:06:42 PM PDT 24
Finished	Apr 28 01:06:45 PM PDT 24
Peak memory	196644 kb
Host	smart-60deabd0-ede4-47c5-af22-4077cf379c40
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=452773733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.452773733
Directory	/workspace/27.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/27.uart_smoke.1371898441
Short name	T304
Test name
Test status
Simulation time	501520552 ps
CPU time	1.77 seconds
Started	Apr 28 01:06:43 PM PDT 24
Finished	Apr 28 01:06:46 PM PDT 24
Peak memory	198632 kb
Host	smart-2eaeba1e-1e65-4dd1-8442-67e7b2ba2638
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1371898441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.1371898441
Directory	/workspace/27.uart_smoke/latest

Test location	/workspace/coverage/default/27.uart_stress_all.493215688
Short name	T815
Test name
Test status
Simulation time	122035364858 ps
CPU time	484.4 seconds
Started	Apr 28 01:06:48 PM PDT 24
Finished	Apr 28 01:14:53 PM PDT 24
Peak memory	200344 kb
Host	smart-afe042b0-db09-4ffe-bdd4-7e10bde7a14b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493215688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.493215688
Directory	/workspace/27.uart_stress_all/latest

Test location	/workspace/coverage/default/27.uart_stress_all_with_rand_reset.2948130847
Short name	T1163
Test name
Test status
Simulation time	79251998632 ps
CPU time	206.75 seconds
Started	Apr 28 01:06:49 PM PDT 24
Finished	Apr 28 01:10:16 PM PDT 24
Peak memory	215940 kb
Host	smart-7ff476c5-890e-4254-a357-8e61dd577fa6
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948130847 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.2948130847
Directory	/workspace/27.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/27.uart_tx_ovrd.1831702037
Short name	T556
Test name
Test status
Simulation time	1078168533 ps
CPU time	1.35 seconds
Started	Apr 28 01:06:44 PM PDT 24
Finished	Apr 28 01:06:47 PM PDT 24
Peak memory	199140 kb
Host	smart-23b05056-4367-428b-a12b-7d321f7031a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1831702037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.1831702037
Directory	/workspace/27.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/27.uart_tx_rx.1147549915
Short name	T468
Test name
Test status
Simulation time	68669276475 ps
CPU time	19.55 seconds
Started	Apr 28 01:06:44 PM PDT 24
Finished	Apr 28 01:07:05 PM PDT 24
Peak memory	200436 kb
Host	smart-d9a436b0-c452-49df-9fb4-443189a1edc4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1147549915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.1147549915
Directory	/workspace/27.uart_tx_rx/latest

Test location	/workspace/coverage/default/270.uart_fifo_reset.1875172868
Short name	T858
Test name
Test status
Simulation time	102373528413 ps
CPU time	160.55 seconds
Started	Apr 28 01:11:00 PM PDT 24
Finished	Apr 28 01:13:42 PM PDT 24
Peak memory	200368 kb
Host	smart-7f85b7c9-6571-4895-ba76-67115eec18a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1875172868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.1875172868
Directory	/workspace/270.uart_fifo_reset/latest

Test location	/workspace/coverage/default/271.uart_fifo_reset.2050977167
Short name	T433
Test name
Test status
Simulation time	39970248034 ps
CPU time	60.76 seconds
Started	Apr 28 01:10:59 PM PDT 24
Finished	Apr 28 01:12:01 PM PDT 24
Peak memory	200352 kb
Host	smart-6f83d802-5d5b-4eec-a28a-117c3eb582f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2050977167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.2050977167
Directory	/workspace/271.uart_fifo_reset/latest

Test location	/workspace/coverage/default/272.uart_fifo_reset.3471292864
Short name	T606
Test name
Test status
Simulation time	40853274067 ps
CPU time	61.15 seconds
Started	Apr 28 01:10:59 PM PDT 24
Finished	Apr 28 01:12:01 PM PDT 24
Peak memory	200280 kb
Host	smart-b6261a0d-4056-4dd3-9282-a444b7c9edd0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3471292864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.3471292864
Directory	/workspace/272.uart_fifo_reset/latest

Test location	/workspace/coverage/default/273.uart_fifo_reset.1625931712
Short name	T394
Test name
Test status
Simulation time	35577920019 ps
CPU time	63.36 seconds
Started	Apr 28 01:10:59 PM PDT 24
Finished	Apr 28 01:12:04 PM PDT 24
Peak memory	200084 kb
Host	smart-c19619a3-5c6a-48ae-a4df-39bbe70793e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1625931712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.1625931712
Directory	/workspace/273.uart_fifo_reset/latest

Test location	/workspace/coverage/default/274.uart_fifo_reset.4004477481
Short name	T824
Test name
Test status
Simulation time	27201530507 ps
CPU time	52.72 seconds
Started	Apr 28 01:11:01 PM PDT 24
Finished	Apr 28 01:11:55 PM PDT 24
Peak memory	200420 kb
Host	smart-333515cc-d1b5-4d90-b5e3-03c054cb1e3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4004477481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.4004477481
Directory	/workspace/274.uart_fifo_reset/latest

Test location	/workspace/coverage/default/275.uart_fifo_reset.128176231
Short name	T236
Test name
Test status
Simulation time	15116913967 ps
CPU time	13.56 seconds
Started	Apr 28 01:11:08 PM PDT 24
Finished	Apr 28 01:11:22 PM PDT 24
Peak memory	200232 kb
Host	smart-96929b51-b92a-4acd-9bd5-5aa877bbceac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=128176231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.128176231
Directory	/workspace/275.uart_fifo_reset/latest

Test location	/workspace/coverage/default/276.uart_fifo_reset.1455526082
Short name	T174
Test name
Test status
Simulation time	27069036487 ps
CPU time	32.99 seconds
Started	Apr 28 01:11:05 PM PDT 24
Finished	Apr 28 01:11:39 PM PDT 24
Peak memory	200424 kb
Host	smart-c25381e8-90e1-4181-8efb-13da9c8af1a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1455526082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.1455526082
Directory	/workspace/276.uart_fifo_reset/latest

Test location	/workspace/coverage/default/278.uart_fifo_reset.501586027
Short name	T226
Test name
Test status
Simulation time	43467127271 ps
CPU time	37.39 seconds
Started	Apr 28 01:11:04 PM PDT 24
Finished	Apr 28 01:11:42 PM PDT 24
Peak memory	200276 kb
Host	smart-67b9a20d-bc2d-49d9-83fe-66bbafb733cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=501586027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.501586027
Directory	/workspace/278.uart_fifo_reset/latest

Test location	/workspace/coverage/default/279.uart_fifo_reset.435095144
Short name	T911
Test name
Test status
Simulation time	21903389595 ps
CPU time	47.1 seconds
Started	Apr 28 01:11:11 PM PDT 24
Finished	Apr 28 01:11:59 PM PDT 24
Peak memory	200412 kb
Host	smart-7bb3ea92-8cb0-4b9a-9af1-01c792480ae4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=435095144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.435095144
Directory	/workspace/279.uart_fifo_reset/latest

Test location	/workspace/coverage/default/28.uart_alert_test.1354948462
Short name	T354
Test name
Test status
Simulation time	14096108 ps
CPU time	0.52 seconds
Started	Apr 28 01:06:53 PM PDT 24
Finished	Apr 28 01:06:54 PM PDT 24
Peak memory	195264 kb
Host	smart-9374a83e-a3ab-40ed-b6cd-8cc921132f8c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354948462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.1354948462
Directory	/workspace/28.uart_alert_test/latest

Test location	/workspace/coverage/default/28.uart_fifo_full.2099022650
Short name	T153
Test name
Test status
Simulation time	20870802367 ps
CPU time	36.75 seconds
Started	Apr 28 01:06:48 PM PDT 24
Finished	Apr 28 01:07:26 PM PDT 24
Peak memory	200384 kb
Host	smart-935bf4e2-be84-43ed-9c46-8f7f1d56239e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2099022650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.2099022650
Directory	/workspace/28.uart_fifo_full/latest

Test location	/workspace/coverage/default/28.uart_fifo_overflow.4246594586
Short name	T843
Test name
Test status
Simulation time	107013054126 ps
CPU time	65.84 seconds
Started	Apr 28 01:06:50 PM PDT 24
Finished	Apr 28 01:07:56 PM PDT 24
Peak memory	200404 kb
Host	smart-7de69b98-2bf5-4e03-81ee-110688ababff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4246594586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.4246594586
Directory	/workspace/28.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/28.uart_fifo_reset.2775961261
Short name	T187
Test name
Test status
Simulation time	161367929781 ps
CPU time	274.35 seconds
Started	Apr 28 01:06:48 PM PDT 24
Finished	Apr 28 01:11:22 PM PDT 24
Peak memory	200452 kb
Host	smart-c2b06abf-489b-42cd-a971-0052c86dfd4d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2775961261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.2775961261
Directory	/workspace/28.uart_fifo_reset/latest

Test location	/workspace/coverage/default/28.uart_intr.2145701514
Short name	T498
Test name
Test status
Simulation time	28815981657 ps
CPU time	24.68 seconds
Started	Apr 28 01:06:49 PM PDT 24
Finished	Apr 28 01:07:15 PM PDT 24
Peak memory	199692 kb
Host	smart-940f4cf5-2e0e-4b52-9cd8-09c0fcb80a3d
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145701514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.2145701514
Directory	/workspace/28.uart_intr/latest

Test location	/workspace/coverage/default/28.uart_long_xfer_wo_dly.3755799494
Short name	T935
Test name
Test status
Simulation time	129979535906 ps
CPU time	327.86 seconds
Started	Apr 28 01:06:55 PM PDT 24
Finished	Apr 28 01:12:23 PM PDT 24
Peak memory	200388 kb
Host	smart-656087ce-4042-4df9-9fe4-7d041da8f99a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3755799494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.3755799494
Directory	/workspace/28.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/28.uart_loopback.2013105231
Short name	T1095
Test name
Test status
Simulation time	7665758254 ps
CPU time	19.76 seconds
Started	Apr 28 01:06:50 PM PDT 24
Finished	Apr 28 01:07:10 PM PDT 24
Peak memory	198640 kb
Host	smart-29997ad7-2273-441e-b5c0-86d01005b65f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2013105231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2013105231
Directory	/workspace/28.uart_loopback/latest

Test location	/workspace/coverage/default/28.uart_noise_filter.3922685806
Short name	T1022
Test name
Test status
Simulation time	42560998395 ps
CPU time	70.65 seconds
Started	Apr 28 01:06:48 PM PDT 24
Finished	Apr 28 01:08:00 PM PDT 24
Peak memory	200460 kb
Host	smart-ea876e98-7ba8-4a35-89e1-b804071e2567
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3922685806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.3922685806
Directory	/workspace/28.uart_noise_filter/latest

Test location	/workspace/coverage/default/28.uart_perf.444280743
Short name	T582
Test name
Test status
Simulation time	31610929078 ps
CPU time	432.67 seconds
Started	Apr 28 01:06:49 PM PDT 24
Finished	Apr 28 01:14:02 PM PDT 24
Peak memory	200352 kb
Host	smart-9886443c-dd9c-467d-aa98-9a4202585ad0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=444280743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.444280743
Directory	/workspace/28.uart_perf/latest

Test location	/workspace/coverage/default/28.uart_rx_oversample.1348334538
Short name	T537
Test name
Test status
Simulation time	5977231325 ps
CPU time	3.89 seconds
Started	Apr 28 01:06:48 PM PDT 24
Finished	Apr 28 01:06:52 PM PDT 24
Peak memory	198568 kb
Host	smart-052bcc95-8ce8-4dc4-a5dc-195f31ea3ec9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1348334538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.1348334538
Directory	/workspace/28.uart_rx_oversample/latest

Test location	/workspace/coverage/default/28.uart_rx_parity_err.2950116387
Short name	T164
Test name
Test status
Simulation time	88425484662 ps
CPU time	110.99 seconds
Started	Apr 28 01:06:48 PM PDT 24
Finished	Apr 28 01:08:40 PM PDT 24
Peak memory	200368 kb
Host	smart-c0f10fa3-5bff-4f7a-964f-581dac89620a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2950116387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.2950116387
Directory	/workspace/28.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/28.uart_rx_start_bit_filter.2261268883
Short name	T645
Test name
Test status
Simulation time	5781098712 ps
CPU time	1.94 seconds
Started	Apr 28 01:06:53 PM PDT 24
Finished	Apr 28 01:06:55 PM PDT 24
Peak memory	196440 kb
Host	smart-33b55381-a445-4851-9036-c8697f9c5d2e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2261268883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.2261268883
Directory	/workspace/28.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/28.uart_smoke.4138474227
Short name	T917
Test name
Test status
Simulation time	717654712 ps
CPU time	1.73 seconds
Started	Apr 28 01:06:49 PM PDT 24
Finished	Apr 28 01:06:51 PM PDT 24
Peak memory	199348 kb
Host	smart-44020b61-6dcc-41fe-a8e3-82c8fb5837ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4138474227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.4138474227
Directory	/workspace/28.uart_smoke/latest

Test location	/workspace/coverage/default/28.uart_tx_ovrd.2861090151
Short name	T840
Test name
Test status
Simulation time	2009416923 ps
CPU time	2.64 seconds
Started	Apr 28 01:06:53 PM PDT 24
Finished	Apr 28 01:06:56 PM PDT 24
Peak memory	199212 kb
Host	smart-ff5c9753-bbea-4aa5-b963-1ddc4966c84d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2861090151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.2861090151
Directory	/workspace/28.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/28.uart_tx_rx.4043787358
Short name	T769
Test name
Test status
Simulation time	31468142583 ps
CPU time	16.37 seconds
Started	Apr 28 01:06:48 PM PDT 24
Finished	Apr 28 01:07:05 PM PDT 24
Peak memory	197572 kb
Host	smart-d8fe52fb-209b-4fec-89dd-ab7a0f29247f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4043787358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.4043787358
Directory	/workspace/28.uart_tx_rx/latest

Test location	/workspace/coverage/default/280.uart_fifo_reset.244451809
Short name	T234
Test name
Test status
Simulation time	193009068046 ps
CPU time	109.09 seconds
Started	Apr 28 01:11:04 PM PDT 24
Finished	Apr 28 01:12:54 PM PDT 24
Peak memory	200292 kb
Host	smart-879dca6b-39dd-45bb-8dc8-8f8a0ea59550
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=244451809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.244451809
Directory	/workspace/280.uart_fifo_reset/latest

Test location	/workspace/coverage/default/281.uart_fifo_reset.1145209190
Short name	T109
Test name
Test status
Simulation time	51491548660 ps
CPU time	24.23 seconds
Started	Apr 28 01:11:04 PM PDT 24
Finished	Apr 28 01:11:29 PM PDT 24
Peak memory	200460 kb
Host	smart-e1027a15-06bd-4a3e-851a-6475868b67c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1145209190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.1145209190
Directory	/workspace/281.uart_fifo_reset/latest

Test location	/workspace/coverage/default/282.uart_fifo_reset.1515061969
Short name	T1094
Test name
Test status
Simulation time	60644833879 ps
CPU time	29.91 seconds
Started	Apr 28 01:11:05 PM PDT 24
Finished	Apr 28 01:11:35 PM PDT 24
Peak memory	200208 kb
Host	smart-3b6edab8-26a5-4f96-84a8-bf260f0c1a73
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1515061969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.1515061969
Directory	/workspace/282.uart_fifo_reset/latest

Test location	/workspace/coverage/default/283.uart_fifo_reset.2967008684
Short name	T201
Test name
Test status
Simulation time	8228277501 ps
CPU time	13.72 seconds
Started	Apr 28 01:11:04 PM PDT 24
Finished	Apr 28 01:11:19 PM PDT 24
Peak memory	200284 kb
Host	smart-adbbfd26-be53-4e18-bb2a-b2ebe4d088ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2967008684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.2967008684
Directory	/workspace/283.uart_fifo_reset/latest

Test location	/workspace/coverage/default/285.uart_fifo_reset.2650486972
Short name	T107
Test name
Test status
Simulation time	16005337236 ps
CPU time	28.73 seconds
Started	Apr 28 01:11:04 PM PDT 24
Finished	Apr 28 01:11:33 PM PDT 24
Peak memory	200380 kb
Host	smart-56b273ea-c32f-46f2-ab4b-430eb11ea0ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2650486972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2650486972
Directory	/workspace/285.uart_fifo_reset/latest

Test location	/workspace/coverage/default/286.uart_fifo_reset.3835887286
Short name	T581
Test name
Test status
Simulation time	165820612998 ps
CPU time	301.13 seconds
Started	Apr 28 01:11:10 PM PDT 24
Finished	Apr 28 01:16:12 PM PDT 24
Peak memory	200212 kb
Host	smart-8f46bcf2-c5b0-474d-b13d-8b4cd7c3c24e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3835887286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.3835887286
Directory	/workspace/286.uart_fifo_reset/latest

Test location	/workspace/coverage/default/287.uart_fifo_reset.1233873402
Short name	T562
Test name
Test status
Simulation time	85247835011 ps
CPU time	131.56 seconds
Started	Apr 28 01:11:05 PM PDT 24
Finished	Apr 28 01:13:17 PM PDT 24
Peak memory	200428 kb
Host	smart-aa2c4de7-69a4-45e6-b9e1-e72a2bc26a26
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1233873402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.1233873402
Directory	/workspace/287.uart_fifo_reset/latest

Test location	/workspace/coverage/default/288.uart_fifo_reset.741496540
Short name	T446
Test name
Test status
Simulation time	169431520723 ps
CPU time	34.65 seconds
Started	Apr 28 01:11:10 PM PDT 24
Finished	Apr 28 01:11:46 PM PDT 24
Peak memory	200396 kb
Host	smart-04feb29a-b27b-48ab-a193-951a0499e98d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=741496540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.741496540
Directory	/workspace/288.uart_fifo_reset/latest

Test location	/workspace/coverage/default/289.uart_fifo_reset.3452040103
Short name	T444
Test name
Test status
Simulation time	25668844397 ps
CPU time	12.36 seconds
Started	Apr 28 01:11:10 PM PDT 24
Finished	Apr 28 01:11:23 PM PDT 24
Peak memory	200136 kb
Host	smart-018facd0-05d5-4641-8e8e-36c187153bc4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3452040103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.3452040103
Directory	/workspace/289.uart_fifo_reset/latest

Test location	/workspace/coverage/default/29.uart_alert_test.3436019108
Short name	T975
Test name
Test status
Simulation time	54667666 ps
CPU time	0.57 seconds
Started	Apr 28 01:07:03 PM PDT 24
Finished	Apr 28 01:07:04 PM PDT 24
Peak memory	195732 kb
Host	smart-886e7808-4ac7-4f15-9cd9-e0dffd291bff
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436019108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.3436019108
Directory	/workspace/29.uart_alert_test/latest

Test location	/workspace/coverage/default/29.uart_fifo_full.2598656901
Short name	T777
Test name
Test status
Simulation time	24719227147 ps
CPU time	34.12 seconds
Started	Apr 28 01:06:54 PM PDT 24
Finished	Apr 28 01:07:29 PM PDT 24
Peak memory	200408 kb
Host	smart-4944e729-5cb6-4c94-9639-4fb2f367a3b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2598656901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.2598656901
Directory	/workspace/29.uart_fifo_full/latest

Test location	/workspace/coverage/default/29.uart_fifo_overflow.1557597451
Short name	T713
Test name
Test status
Simulation time	302020640233 ps
CPU time	525.39 seconds
Started	Apr 28 01:06:55 PM PDT 24
Finished	Apr 28 01:15:41 PM PDT 24
Peak memory	200304 kb
Host	smart-78cbe114-8c8d-4dd9-a287-c331ba9b5a30
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1557597451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.1557597451
Directory	/workspace/29.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/29.uart_fifo_reset.322812149
Short name	T601
Test name
Test status
Simulation time	114909456084 ps
CPU time	88.04 seconds
Started	Apr 28 01:06:55 PM PDT 24
Finished	Apr 28 01:08:24 PM PDT 24
Peak memory	200328 kb
Host	smart-e11d3760-c4ec-481b-9cbd-d5c27ff5b2ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=322812149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.322812149
Directory	/workspace/29.uart_fifo_reset/latest

Test location	/workspace/coverage/default/29.uart_intr.3880838934
Short name	T629
Test name
Test status
Simulation time	5309336340 ps
CPU time	2.8 seconds
Started	Apr 28 01:06:55 PM PDT 24
Finished	Apr 28 01:06:58 PM PDT 24
Peak memory	197060 kb
Host	smart-04d526c5-e7ad-4543-9053-51635ac8b940
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880838934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.3880838934
Directory	/workspace/29.uart_intr/latest

Test location	/workspace/coverage/default/29.uart_long_xfer_wo_dly.2004543446
Short name	T405
Test name
Test status
Simulation time	142410378646 ps
CPU time	597.56 seconds
Started	Apr 28 01:07:01 PM PDT 24
Finished	Apr 28 01:16:59 PM PDT 24
Peak memory	200324 kb
Host	smart-e283bb6e-1738-421e-81d4-68f05b5d8557
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2004543446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2004543446
Directory	/workspace/29.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/29.uart_loopback.2410853972
Short name	T1132
Test name
Test status
Simulation time	3874743628 ps
CPU time	2.99 seconds
Started	Apr 28 01:07:00 PM PDT 24
Finished	Apr 28 01:07:04 PM PDT 24
Peak memory	199408 kb
Host	smart-85522976-e530-45c8-b79f-5130998d32d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2410853972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.2410853972
Directory	/workspace/29.uart_loopback/latest

Test location	/workspace/coverage/default/29.uart_noise_filter.465619783
Short name	T473
Test name
Test status
Simulation time	17600940058 ps
CPU time	29.79 seconds
Started	Apr 28 01:06:53 PM PDT 24
Finished	Apr 28 01:07:23 PM PDT 24
Peak memory	200312 kb
Host	smart-3ce6e9ab-aea3-4e1c-8740-b70efa8490c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=465619783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.465619783
Directory	/workspace/29.uart_noise_filter/latest

Test location	/workspace/coverage/default/29.uart_perf.3473678840
Short name	T253
Test name
Test status
Simulation time	20521593093 ps
CPU time	1079.83 seconds
Started	Apr 28 01:07:01 PM PDT 24
Finished	Apr 28 01:25:01 PM PDT 24
Peak memory	200376 kb
Host	smart-1a429c0d-9a3e-4dec-bb0d-39f38acae7db
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3473678840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.3473678840
Directory	/workspace/29.uart_perf/latest

Test location	/workspace/coverage/default/29.uart_rx_oversample.702419336
Short name	T650
Test name
Test status
Simulation time	1918199381 ps
CPU time	2.61 seconds
Started	Apr 28 01:06:54 PM PDT 24
Finished	Apr 28 01:06:57 PM PDT 24
Peak memory	198472 kb
Host	smart-a38020a2-574a-4796-8d38-cde42633477b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=702419336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.702419336
Directory	/workspace/29.uart_rx_oversample/latest

Test location	/workspace/coverage/default/29.uart_rx_parity_err.1523353033
Short name	T1159
Test name
Test status
Simulation time	34035617849 ps
CPU time	34.01 seconds
Started	Apr 28 01:06:54 PM PDT 24
Finished	Apr 28 01:07:29 PM PDT 24
Peak memory	200344 kb
Host	smart-c96fafbd-c1cd-40a8-9258-edf78e43662f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1523353033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1523353033
Directory	/workspace/29.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/29.uart_rx_start_bit_filter.2560550157
Short name	T611
Test name
Test status
Simulation time	3905160374 ps
CPU time	5.96 seconds
Started	Apr 28 01:06:53 PM PDT 24
Finished	Apr 28 01:07:00 PM PDT 24
Peak memory	196288 kb
Host	smart-1f729054-5c1e-4ba4-8ad1-cea89216e916
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2560550157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2560550157
Directory	/workspace/29.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/29.uart_smoke.495576289
Short name	T546
Test name
Test status
Simulation time	889081701 ps
CPU time	3.64 seconds
Started	Apr 28 01:06:52 PM PDT 24
Finished	Apr 28 01:06:56 PM PDT 24
Peak memory	200056 kb
Host	smart-c06cfae2-ea0f-410c-8e01-da297dfdb119
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=495576289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.495576289
Directory	/workspace/29.uart_smoke/latest

Test location	/workspace/coverage/default/29.uart_stress_all.1215005447
Short name	T19
Test name
Test status
Simulation time	46857431317 ps
CPU time	88.98 seconds
Started	Apr 28 01:07:03 PM PDT 24
Finished	Apr 28 01:08:33 PM PDT 24
Peak memory	200436 kb
Host	smart-17e356d3-25df-48b0-aa4c-a71d8f7602aa
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215005447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.1215005447
Directory	/workspace/29.uart_stress_all/latest

Test location	/workspace/coverage/default/29.uart_tx_ovrd.1413787240
Short name	T560
Test name
Test status
Simulation time	11540139450 ps
CPU time	8.24 seconds
Started	Apr 28 01:07:01 PM PDT 24
Finished	Apr 28 01:07:10 PM PDT 24
Peak memory	200124 kb
Host	smart-3c7789fc-b6a2-4f98-9977-fd2f84b7cec1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1413787240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1413787240
Directory	/workspace/29.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/29.uart_tx_rx.1196119357
Short name	T481
Test name
Test status
Simulation time	77506471511 ps
CPU time	122.51 seconds
Started	Apr 28 01:06:56 PM PDT 24
Finished	Apr 28 01:08:59 PM PDT 24
Peak memory	200396 kb
Host	smart-f56698b1-5c9e-4c8a-a76a-29ef721a73c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1196119357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.1196119357
Directory	/workspace/29.uart_tx_rx/latest

Test location	/workspace/coverage/default/290.uart_fifo_reset.581144342
Short name	T141
Test name
Test status
Simulation time	23969430594 ps
CPU time	13.47 seconds
Started	Apr 28 01:11:12 PM PDT 24
Finished	Apr 28 01:11:27 PM PDT 24
Peak memory	200312 kb
Host	smart-b45ae6ea-7abf-4ef2-978b-0aa50de2c005
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=581144342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.581144342
Directory	/workspace/290.uart_fifo_reset/latest

Test location	/workspace/coverage/default/291.uart_fifo_reset.3901244546
Short name	T1171
Test name
Test status
Simulation time	20047691477 ps
CPU time	28.56 seconds
Started	Apr 28 01:11:09 PM PDT 24
Finished	Apr 28 01:11:39 PM PDT 24
Peak memory	200024 kb
Host	smart-fc571b90-8f82-4ead-8693-99a4031b9d5e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3901244546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.3901244546
Directory	/workspace/291.uart_fifo_reset/latest

Test location	/workspace/coverage/default/292.uart_fifo_reset.2092399920
Short name	T358
Test name
Test status
Simulation time	16805372135 ps
CPU time	26.96 seconds
Started	Apr 28 01:11:09 PM PDT 24
Finished	Apr 28 01:11:37 PM PDT 24
Peak memory	200436 kb
Host	smart-b14ff9c3-c2cc-4e3d-ab49-c7f053ce720e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2092399920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.2092399920
Directory	/workspace/292.uart_fifo_reset/latest

Test location	/workspace/coverage/default/293.uart_fifo_reset.3572812996
Short name	T669
Test name
Test status
Simulation time	54941082845 ps
CPU time	93.09 seconds
Started	Apr 28 01:11:10 PM PDT 24
Finished	Apr 28 01:12:44 PM PDT 24
Peak memory	200424 kb
Host	smart-5ba31713-e07b-4909-96a0-62972ff0c346
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3572812996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.3572812996
Directory	/workspace/293.uart_fifo_reset/latest

Test location	/workspace/coverage/default/294.uart_fifo_reset.4156180405
Short name	T132
Test name
Test status
Simulation time	147228995405 ps
CPU time	262.69 seconds
Started	Apr 28 01:11:11 PM PDT 24
Finished	Apr 28 01:15:34 PM PDT 24
Peak memory	200328 kb
Host	smart-7ff29f3e-beca-4518-84a1-b93ca93430e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4156180405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.4156180405
Directory	/workspace/294.uart_fifo_reset/latest

Test location	/workspace/coverage/default/296.uart_fifo_reset.1560638745
Short name	T179
Test name
Test status
Simulation time	10983926303 ps
CPU time	21.47 seconds
Started	Apr 28 01:11:10 PM PDT 24
Finished	Apr 28 01:11:33 PM PDT 24
Peak memory	200336 kb
Host	smart-cb579e51-866f-433b-9e55-cf14900ec331
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1560638745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.1560638745
Directory	/workspace/296.uart_fifo_reset/latest

Test location	/workspace/coverage/default/297.uart_fifo_reset.2111868812
Short name	T711
Test name
Test status
Simulation time	62731977721 ps
CPU time	97.27 seconds
Started	Apr 28 01:11:11 PM PDT 24
Finished	Apr 28 01:12:49 PM PDT 24
Peak memory	200372 kb
Host	smart-4f7495c2-ecca-4b88-bc7d-d4ea7b680567
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2111868812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.2111868812
Directory	/workspace/297.uart_fifo_reset/latest

Test location	/workspace/coverage/default/298.uart_fifo_reset.265456406
Short name	T951
Test name
Test status
Simulation time	61113792412 ps
CPU time	60.93 seconds
Started	Apr 28 01:11:09 PM PDT 24
Finished	Apr 28 01:12:10 PM PDT 24
Peak memory	200296 kb
Host	smart-e3617530-5272-4479-9b7c-e23f5a3538be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=265456406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.265456406
Directory	/workspace/298.uart_fifo_reset/latest

Test location	/workspace/coverage/default/299.uart_fifo_reset.4110201756
Short name	T1039
Test name
Test status
Simulation time	51661651239 ps
CPU time	25.1 seconds
Started	Apr 28 01:11:10 PM PDT 24
Finished	Apr 28 01:11:36 PM PDT 24
Peak memory	200404 kb
Host	smart-40791e72-b12c-48ba-8b37-e29f9178c53a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4110201756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.4110201756
Directory	/workspace/299.uart_fifo_reset/latest

Test location	/workspace/coverage/default/3.uart_alert_test.1136788151
Short name	T894
Test name
Test status
Simulation time	14203957 ps
CPU time	0.62 seconds
Started	Apr 28 01:05:17 PM PDT 24
Finished	Apr 28 01:05:18 PM PDT 24
Peak memory	195816 kb
Host	smart-74bc74e0-cb71-4a56-933b-345adaaface4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136788151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1136788151
Directory	/workspace/3.uart_alert_test/latest

Test location	/workspace/coverage/default/3.uart_fifo_full.4179553139
Short name	T318
Test name
Test status
Simulation time	96684722894 ps
CPU time	99.34 seconds
Started	Apr 28 01:05:13 PM PDT 24
Finished	Apr 28 01:06:53 PM PDT 24
Peak memory	200288 kb
Host	smart-c40feebe-d35b-46f3-891e-de224ee3adcd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4179553139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.4179553139
Directory	/workspace/3.uart_fifo_full/latest

Test location	/workspace/coverage/default/3.uart_fifo_overflow.3212453688
Short name	T878
Test name
Test status
Simulation time	59069378313 ps
CPU time	57.09 seconds
Started	Apr 28 01:05:14 PM PDT 24
Finished	Apr 28 01:06:12 PM PDT 24
Peak memory	200396 kb
Host	smart-15db5f5b-50d7-4171-a6b2-18105d120b50
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3212453688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.3212453688
Directory	/workspace/3.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/3.uart_fifo_reset.2579799640
Short name	T879
Test name
Test status
Simulation time	71664542332 ps
CPU time	32.44 seconds
Started	Apr 28 01:05:16 PM PDT 24
Finished	Apr 28 01:05:49 PM PDT 24
Peak memory	200432 kb
Host	smart-ea9b84be-4a5e-4034-9b4d-027cc4d3cd23
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2579799640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.2579799640
Directory	/workspace/3.uart_fifo_reset/latest

Test location	/workspace/coverage/default/3.uart_intr.1239429460
Short name	T684
Test name
Test status
Simulation time	66795316307 ps
CPU time	66.82 seconds
Started	Apr 28 01:05:22 PM PDT 24
Finished	Apr 28 01:06:30 PM PDT 24
Peak memory	199284 kb
Host	smart-dbb634e2-8dbf-425e-b466-f8eaac5896ad
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239429460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.1239429460
Directory	/workspace/3.uart_intr/latest

Test location	/workspace/coverage/default/3.uart_long_xfer_wo_dly.392337096
Short name	T260
Test name
Test status
Simulation time	102017312700 ps
CPU time	239.04 seconds
Started	Apr 28 01:05:17 PM PDT 24
Finished	Apr 28 01:09:17 PM PDT 24
Peak memory	200364 kb
Host	smart-9ab9ce34-9114-4a92-8ab3-2a738c8993cd
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=392337096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.392337096
Directory	/workspace/3.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/3.uart_loopback.994107381
Short name	T121
Test name
Test status
Simulation time	8994877757 ps
CPU time	10.07 seconds
Started	Apr 28 01:05:16 PM PDT 24
Finished	Apr 28 01:05:27 PM PDT 24
Peak memory	200256 kb
Host	smart-2e72fcbe-494f-4aa5-aa4d-46d7944f4c70
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=994107381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.994107381
Directory	/workspace/3.uart_loopback/latest

Test location	/workspace/coverage/default/3.uart_noise_filter.1044223689
Short name	T934
Test name
Test status
Simulation time	131007851337 ps
CPU time	70.33 seconds
Started	Apr 28 01:05:23 PM PDT 24
Finished	Apr 28 01:06:35 PM PDT 24
Peak memory	208876 kb
Host	smart-443a76e0-8d66-4094-bd21-6684496073d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1044223689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.1044223689
Directory	/workspace/3.uart_noise_filter/latest

Test location	/workspace/coverage/default/3.uart_perf.2031213400
Short name	T615
Test name
Test status
Simulation time	21305035015 ps
CPU time	1003.22 seconds
Started	Apr 28 01:05:13 PM PDT 24
Finished	Apr 28 01:21:57 PM PDT 24
Peak memory	200436 kb
Host	smart-ba8fe791-a1ec-4dd8-9ee9-8a6f2bd19880
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2031213400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2031213400
Directory	/workspace/3.uart_perf/latest

Test location	/workspace/coverage/default/3.uart_rx_oversample.3377010260
Short name	T316
Test name
Test status
Simulation time	3366934554 ps
CPU time	13.33 seconds
Started	Apr 28 01:05:12 PM PDT 24
Finished	Apr 28 01:05:26 PM PDT 24
Peak memory	199676 kb
Host	smart-e094ab3c-01ce-40c0-80b6-f6ae5304a5c4
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3377010260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3377010260
Directory	/workspace/3.uart_rx_oversample/latest

Test location	/workspace/coverage/default/3.uart_rx_parity_err.984508738
Short name	T575
Test name
Test status
Simulation time	86328245180 ps
CPU time	126.23 seconds
Started	Apr 28 01:05:15 PM PDT 24
Finished	Apr 28 01:07:22 PM PDT 24
Peak memory	200392 kb
Host	smart-3ff4363e-1688-4787-8e15-c8b9e790b19d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=984508738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.984508738
Directory	/workspace/3.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/3.uart_rx_start_bit_filter.3994457479
Short name	T1141
Test name
Test status
Simulation time	33102022857 ps
CPU time	53.01 seconds
Started	Apr 28 01:05:13 PM PDT 24
Finished	Apr 28 01:06:07 PM PDT 24
Peak memory	196284 kb
Host	smart-701b9ec3-ca62-4d01-b554-02b259c031c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3994457479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.3994457479
Directory	/workspace/3.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/3.uart_sec_cm.2034024567
Short name	T102
Test name
Test status
Simulation time	85865580 ps
CPU time	0.85 seconds
Started	Apr 28 01:05:17 PM PDT 24
Finished	Apr 28 01:05:18 PM PDT 24
Peak memory	218528 kb
Host	smart-4f4788c3-e181-440a-9777-c119f0aa757b
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034024567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.2034024567
Directory	/workspace/3.uart_sec_cm/latest

Test location	/workspace/coverage/default/3.uart_smoke.2808981255
Short name	T1165
Test name
Test status
Simulation time	5294730778 ps
CPU time	20.32 seconds
Started	Apr 28 01:05:13 PM PDT 24
Finished	Apr 28 01:05:35 PM PDT 24
Peak memory	200156 kb
Host	smart-6f71fcd5-b7bb-45a3-b738-b2b34854b7ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2808981255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.2808981255
Directory	/workspace/3.uart_smoke/latest

Test location	/workspace/coverage/default/3.uart_stress_all.916926838
Short name	T497
Test name
Test status
Simulation time	153523074870 ps
CPU time	307.99 seconds
Started	Apr 28 01:05:22 PM PDT 24
Finished	Apr 28 01:10:30 PM PDT 24
Peak memory	208644 kb
Host	smart-d9a5fd4f-a920-4236-bc4c-4bc035abae06
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916926838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.916926838
Directory	/workspace/3.uart_stress_all/latest

Test location	/workspace/coverage/default/3.uart_tx_ovrd.671781001
Short name	T692
Test name
Test status
Simulation time	1303415515 ps
CPU time	3.14 seconds
Started	Apr 28 01:05:13 PM PDT 24
Finished	Apr 28 01:05:17 PM PDT 24
Peak memory	198600 kb
Host	smart-bd730084-5f6a-40c3-a148-7304582af938
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=671781001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.671781001
Directory	/workspace/3.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/3.uart_tx_rx.2389137711
Short name	T366
Test name
Test status
Simulation time	103833954833 ps
CPU time	11.5 seconds
Started	Apr 28 01:05:12 PM PDT 24
Finished	Apr 28 01:05:25 PM PDT 24
Peak memory	197720 kb
Host	smart-deec5e1d-4bd8-4f17-8e1e-a3de7a053146
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2389137711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.2389137711
Directory	/workspace/3.uart_tx_rx/latest

Test location	/workspace/coverage/default/30.uart_alert_test.1300230232
Short name	T476
Test name
Test status
Simulation time	18522050 ps
CPU time	0.54 seconds
Started	Apr 28 01:07:05 PM PDT 24
Finished	Apr 28 01:07:06 PM PDT 24
Peak memory	195804 kb
Host	smart-2b5bfc43-e201-4d03-8b8f-476526ed859b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300230232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.1300230232
Directory	/workspace/30.uart_alert_test/latest

Test location	/workspace/coverage/default/30.uart_fifo_full.3325484133
Short name	T171
Test name
Test status
Simulation time	124909575713 ps
CPU time	17.34 seconds
Started	Apr 28 01:07:02 PM PDT 24
Finished	Apr 28 01:07:20 PM PDT 24
Peak memory	200324 kb
Host	smart-4835b38c-32f1-4eee-afe6-ba2c48c58ea8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3325484133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3325484133
Directory	/workspace/30.uart_fifo_full/latest

Test location	/workspace/coverage/default/30.uart_fifo_overflow.1926958449
Short name	T1160
Test name
Test status
Simulation time	187668966741 ps
CPU time	132.45 seconds
Started	Apr 28 01:07:03 PM PDT 24
Finished	Apr 28 01:09:16 PM PDT 24
Peak memory	200380 kb
Host	smart-78f5efeb-d7cb-440d-b1ec-1e5c17749cfa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1926958449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.1926958449
Directory	/workspace/30.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/30.uart_fifo_reset.3036758467
Short name	T939
Test name
Test status
Simulation time	14517791064 ps
CPU time	21.61 seconds
Started	Apr 28 01:07:04 PM PDT 24
Finished	Apr 28 01:07:26 PM PDT 24
Peak memory	200384 kb
Host	smart-c8ed8bc2-d063-4d34-8370-c1e6d6ac4776
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3036758467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3036758467
Directory	/workspace/30.uart_fifo_reset/latest

Test location	/workspace/coverage/default/30.uart_intr.806234102
Short name	T453
Test name
Test status
Simulation time	231849843046 ps
CPU time	367.91 seconds
Started	Apr 28 01:07:02 PM PDT 24
Finished	Apr 28 01:13:10 PM PDT 24
Peak memory	200224 kb
Host	smart-d55230c2-5fbc-4d8d-ac6c-6e51ad45cf9a
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806234102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.806234102
Directory	/workspace/30.uart_intr/latest

Test location	/workspace/coverage/default/30.uart_loopback.507288726
Short name	T1038
Test name
Test status
Simulation time	11028536909 ps
CPU time	23.47 seconds
Started	Apr 28 01:07:07 PM PDT 24
Finished	Apr 28 01:07:31 PM PDT 24
Peak memory	199988 kb
Host	smart-aab09fee-3a29-4436-a4fc-2113b583f1c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=507288726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.507288726
Directory	/workspace/30.uart_loopback/latest

Test location	/workspace/coverage/default/30.uart_noise_filter.1435654809
Short name	T1118
Test name
Test status
Simulation time	64807883438 ps
CPU time	27.03 seconds
Started	Apr 28 01:07:04 PM PDT 24
Finished	Apr 28 01:07:31 PM PDT 24
Peak memory	195624 kb
Host	smart-43d41de4-fa3c-43c5-8a20-f823255753ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1435654809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.1435654809
Directory	/workspace/30.uart_noise_filter/latest

Test location	/workspace/coverage/default/30.uart_rx_oversample.1976199126
Short name	T1069
Test name
Test status
Simulation time	4614056748 ps
CPU time	35.83 seconds
Started	Apr 28 01:07:02 PM PDT 24
Finished	Apr 28 01:07:38 PM PDT 24
Peak memory	198568 kb
Host	smart-5fd03627-b25f-4529-b47d-1aba1673d53e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1976199126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.1976199126
Directory	/workspace/30.uart_rx_oversample/latest

Test location	/workspace/coverage/default/30.uart_rx_parity_err.3486375169
Short name	T159
Test name
Test status
Simulation time	64377245645 ps
CPU time	33.35 seconds
Started	Apr 28 01:07:01 PM PDT 24
Finished	Apr 28 01:07:35 PM PDT 24
Peak memory	200280 kb
Host	smart-35a8ffcb-f541-424e-865b-abff40b06b20
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3486375169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.3486375169
Directory	/workspace/30.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/30.uart_rx_start_bit_filter.3963811610
Short name	T1029
Test name
Test status
Simulation time	2346263755 ps
CPU time	3.28 seconds
Started	Apr 28 01:07:01 PM PDT 24
Finished	Apr 28 01:07:05 PM PDT 24
Peak memory	196408 kb
Host	smart-e688b0b5-3072-4289-b092-a62da0d92f92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3963811610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.3963811610
Directory	/workspace/30.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/30.uart_smoke.4134443775
Short name	T364
Test name
Test status
Simulation time	644341609 ps
CPU time	2.49 seconds
Started	Apr 28 01:07:00 PM PDT 24
Finished	Apr 28 01:07:03 PM PDT 24
Peak memory	199104 kb
Host	smart-03d64447-5a4b-49d4-9b47-ec1cd31db3eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4134443775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.4134443775
Directory	/workspace/30.uart_smoke/latest

Test location	/workspace/coverage/default/30.uart_stress_all.380605396
Short name	T620
Test name
Test status
Simulation time	86312582391 ps
CPU time	250.64 seconds
Started	Apr 28 01:07:09 PM PDT 24
Finished	Apr 28 01:11:20 PM PDT 24
Peak memory	200368 kb
Host	smart-ea48e9aa-29f5-4ebe-b2ef-fac90036b71d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380605396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.380605396
Directory	/workspace/30.uart_stress_all/latest

Test location	/workspace/coverage/default/30.uart_stress_all_with_rand_reset.2316072832
Short name	T855
Test name
Test status
Simulation time	1635041421743 ps
CPU time	1098.95 seconds
Started	Apr 28 01:07:09 PM PDT 24
Finished	Apr 28 01:25:28 PM PDT 24
Peak memory	227480 kb
Host	smart-e334425e-d6d7-4c2d-a55c-d161c7bd1f17
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316072832 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.2316072832
Directory	/workspace/30.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/30.uart_tx_ovrd.3273229517
Short name	T971
Test name
Test status
Simulation time	434519218 ps
CPU time	1.99 seconds
Started	Apr 28 01:07:01 PM PDT 24
Finished	Apr 28 01:07:04 PM PDT 24
Peak memory	198984 kb
Host	smart-b518b09c-8182-41d4-8eb6-40baee122242
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3273229517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.3273229517
Directory	/workspace/30.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/30.uart_tx_rx.3552428828
Short name	T755
Test name
Test status
Simulation time	40313440527 ps
CPU time	22.35 seconds
Started	Apr 28 01:07:01 PM PDT 24
Finished	Apr 28 01:07:24 PM PDT 24
Peak memory	200316 kb
Host	smart-cd3b0476-e008-4b3c-889b-27ef71a155c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3552428828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.3552428828
Directory	/workspace/30.uart_tx_rx/latest

Test location	/workspace/coverage/default/31.uart_alert_test.1601281370
Short name	T1041
Test name
Test status
Simulation time	39755132 ps
CPU time	0.55 seconds
Started	Apr 28 01:07:11 PM PDT 24
Finished	Apr 28 01:07:12 PM PDT 24
Peak memory	195792 kb
Host	smart-08d47d71-14cd-49af-a4a4-28761ac3ef88
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601281370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.1601281370
Directory	/workspace/31.uart_alert_test/latest

Test location	/workspace/coverage/default/31.uart_fifo_full.1364402173
Short name	T1027
Test name
Test status
Simulation time	121375596702 ps
CPU time	84.36 seconds
Started	Apr 28 01:07:07 PM PDT 24
Finished	Apr 28 01:08:32 PM PDT 24
Peak memory	200284 kb
Host	smart-28f6db44-9c38-433a-b926-eaeeb213f607
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1364402173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.1364402173
Directory	/workspace/31.uart_fifo_full/latest

Test location	/workspace/coverage/default/31.uart_fifo_overflow.4238369401
Short name	T138
Test name
Test status
Simulation time	86314188655 ps
CPU time	83.99 seconds
Started	Apr 28 01:07:05 PM PDT 24
Finished	Apr 28 01:08:30 PM PDT 24
Peak memory	200464 kb
Host	smart-58b56e92-8b81-4fbe-9c53-dbf4474be852
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4238369401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.4238369401
Directory	/workspace/31.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/31.uart_fifo_reset.2963929414
Short name	T525
Test name
Test status
Simulation time	71264052276 ps
CPU time	46.09 seconds
Started	Apr 28 01:07:07 PM PDT 24
Finished	Apr 28 01:07:54 PM PDT 24
Peak memory	200416 kb
Host	smart-09ef0595-ccb7-4fed-9ed4-aa91dc6d75c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2963929414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.2963929414
Directory	/workspace/31.uart_fifo_reset/latest

Test location	/workspace/coverage/default/31.uart_intr.3272659406
Short name	T1110
Test name
Test status
Simulation time	12199328833 ps
CPU time	18.75 seconds
Started	Apr 28 01:07:07 PM PDT 24
Finished	Apr 28 01:07:26 PM PDT 24
Peak memory	200360 kb
Host	smart-92faaf25-44f9-4081-8678-44f27c6a35ae
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272659406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.3272659406
Directory	/workspace/31.uart_intr/latest

Test location	/workspace/coverage/default/31.uart_long_xfer_wo_dly.1272964024
Short name	T579
Test name
Test status
Simulation time	283574595064 ps
CPU time	440.12 seconds
Started	Apr 28 01:07:12 PM PDT 24
Finished	Apr 28 01:14:33 PM PDT 24
Peak memory	200288 kb
Host	smart-8212bc79-869b-4662-96f1-9ef7c95002f0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1272964024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.1272964024
Directory	/workspace/31.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/31.uart_loopback.1008753179
Short name	T648
Test name
Test status
Simulation time	7090238625 ps
CPU time	7.02 seconds
Started	Apr 28 01:07:07 PM PDT 24
Finished	Apr 28 01:07:14 PM PDT 24
Peak memory	200200 kb
Host	smart-a394a553-2d78-4076-99ba-b6c09ba0f265
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1008753179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.1008753179
Directory	/workspace/31.uart_loopback/latest

Test location	/workspace/coverage/default/31.uart_noise_filter.1498312088
Short name	T1056
Test name
Test status
Simulation time	93898611146 ps
CPU time	133.1 seconds
Started	Apr 28 01:07:07 PM PDT 24
Finished	Apr 28 01:09:20 PM PDT 24
Peak memory	200600 kb
Host	smart-245ed6ae-52ff-4d9b-98e5-aa9ea4a7ea4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1498312088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.1498312088
Directory	/workspace/31.uart_noise_filter/latest

Test location	/workspace/coverage/default/31.uart_perf.3369291159
Short name	T750
Test name
Test status
Simulation time	14172206379 ps
CPU time	127.97 seconds
Started	Apr 28 01:07:09 PM PDT 24
Finished	Apr 28 01:09:17 PM PDT 24
Peak memory	200244 kb
Host	smart-41f2bc73-d532-4e24-89aa-2ca9f7182e7c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3369291159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.3369291159
Directory	/workspace/31.uart_perf/latest

Test location	/workspace/coverage/default/31.uart_rx_oversample.3342289383
Short name	T542
Test name
Test status
Simulation time	3467970199 ps
CPU time	14.18 seconds
Started	Apr 28 01:07:11 PM PDT 24
Finished	Apr 28 01:07:25 PM PDT 24
Peak memory	198500 kb
Host	smart-23af1266-62ce-4732-ae98-aa5cadbf0a3e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3342289383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.3342289383
Directory	/workspace/31.uart_rx_oversample/latest

Test location	/workspace/coverage/default/31.uart_rx_parity_err.2794973731
Short name	T816
Test name
Test status
Simulation time	201339529620 ps
CPU time	82.09 seconds
Started	Apr 28 01:07:07 PM PDT 24
Finished	Apr 28 01:08:29 PM PDT 24
Peak memory	200360 kb
Host	smart-3efff9a3-080d-4f07-8841-50ab3bf0a18f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2794973731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.2794973731
Directory	/workspace/31.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/31.uart_rx_start_bit_filter.3977852927
Short name	T702
Test name
Test status
Simulation time	1630194336 ps
CPU time	3.05 seconds
Started	Apr 28 01:07:09 PM PDT 24
Finished	Apr 28 01:07:12 PM PDT 24
Peak memory	196084 kb
Host	smart-2bc1a20f-1194-4f8f-a86f-160e3f715da2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3977852927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.3977852927
Directory	/workspace/31.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/31.uart_smoke.4004036479
Short name	T577
Test name
Test status
Simulation time	6128387434 ps
CPU time	4.89 seconds
Started	Apr 28 01:07:09 PM PDT 24
Finished	Apr 28 01:07:14 PM PDT 24
Peak memory	200176 kb
Host	smart-9c417dea-b215-48ea-8f91-00363cc68983
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4004036479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.4004036479
Directory	/workspace/31.uart_smoke/latest

Test location	/workspace/coverage/default/31.uart_stress_all.3478874863
Short name	T1037
Test name
Test status
Simulation time	461440061620 ps
CPU time	279.92 seconds
Started	Apr 28 01:07:11 PM PDT 24
Finished	Apr 28 01:11:52 PM PDT 24
Peak memory	216400 kb
Host	smart-53fe5855-4dcf-42d3-bd95-fffe70cad50f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478874863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.3478874863
Directory	/workspace/31.uart_stress_all/latest

Test location	/workspace/coverage/default/31.uart_stress_all_with_rand_reset.362511267
Short name	T1048
Test name
Test status
Simulation time	202113511380 ps
CPU time	1370.84 seconds
Started	Apr 28 01:07:13 PM PDT 24
Finished	Apr 28 01:30:04 PM PDT 24
Peak memory	218256 kb
Host	smart-a224db61-515f-4502-a8a5-e9982b20999f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362511267 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.362511267
Directory	/workspace/31.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/31.uart_tx_ovrd.1091972584
Short name	T283
Test name
Test status
Simulation time	6359632541 ps
CPU time	20.92 seconds
Started	Apr 28 01:07:05 PM PDT 24
Finished	Apr 28 01:07:26 PM PDT 24
Peak memory	200220 kb
Host	smart-806ee1c7-ce37-464b-919b-b915dcb6a9bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1091972584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1091972584
Directory	/workspace/31.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/31.uart_tx_rx.2362528164
Short name	T1178
Test name
Test status
Simulation time	17349502501 ps
CPU time	35.29 seconds
Started	Apr 28 01:07:05 PM PDT 24
Finished	Apr 28 01:07:41 PM PDT 24
Peak memory	200384 kb
Host	smart-8fd7e557-06d1-440c-93fb-d454cc1ba391
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2362528164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.2362528164
Directory	/workspace/31.uart_tx_rx/latest

Test location	/workspace/coverage/default/32.uart_alert_test.2914358197
Short name	T747
Test name
Test status
Simulation time	28164624 ps
CPU time	0.53 seconds
Started	Apr 28 01:07:16 PM PDT 24
Finished	Apr 28 01:07:17 PM PDT 24
Peak memory	195096 kb
Host	smart-ac0a06b0-5bf6-43df-b1cd-5b2a76c3958d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914358197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2914358197
Directory	/workspace/32.uart_alert_test/latest

Test location	/workspace/coverage/default/32.uart_fifo_full.721059577
Short name	T65
Test name
Test status
Simulation time	13426720292 ps
CPU time	15.9 seconds
Started	Apr 28 01:07:11 PM PDT 24
Finished	Apr 28 01:07:27 PM PDT 24
Peak memory	200424 kb
Host	smart-c6db60f8-e3d9-4964-b7ef-7b1abf1a78f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=721059577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.721059577
Directory	/workspace/32.uart_fifo_full/latest

Test location	/workspace/coverage/default/32.uart_fifo_overflow.1445470568
Short name	T559
Test name
Test status
Simulation time	94480657508 ps
CPU time	28.86 seconds
Started	Apr 28 01:07:12 PM PDT 24
Finished	Apr 28 01:07:41 PM PDT 24
Peak memory	200424 kb
Host	smart-181acbaf-1713-402f-abcf-6b2065ab744c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1445470568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.1445470568
Directory	/workspace/32.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/32.uart_fifo_reset.2176438314
Short name	T1008
Test name
Test status
Simulation time	52163629218 ps
CPU time	45.29 seconds
Started	Apr 28 01:07:12 PM PDT 24
Finished	Apr 28 01:07:58 PM PDT 24
Peak memory	200424 kb
Host	smart-ca93935e-d2fe-48df-b3ee-599cb07e68ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2176438314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.2176438314
Directory	/workspace/32.uart_fifo_reset/latest

Test location	/workspace/coverage/default/32.uart_intr.833677
Short name	T1180
Test name
Test status
Simulation time	166553171850 ps
CPU time	267.18 seconds
Started	Apr 28 01:07:10 PM PDT 24
Finished	Apr 28 01:11:38 PM PDT 24
Peak memory	200396 kb
Host	smart-83db44b6-307e-45fb-b194-fe2a50bd0313
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.833677
Directory	/workspace/32.uart_intr/latest

Test location	/workspace/coverage/default/32.uart_long_xfer_wo_dly.2723932136
Short name	T1070
Test name
Test status
Simulation time	162638512873 ps
CPU time	209.1 seconds
Started	Apr 28 01:07:16 PM PDT 24
Finished	Apr 28 01:10:45 PM PDT 24
Peak memory	200356 kb
Host	smart-f4a21392-04c7-4a34-90d9-e5984c5e0312
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2723932136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.2723932136
Directory	/workspace/32.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/32.uart_loopback.2682036505
Short name	T938
Test name
Test status
Simulation time	845085178 ps
CPU time	1.39 seconds
Started	Apr 28 01:07:10 PM PDT 24
Finished	Apr 28 01:07:12 PM PDT 24
Peak memory	196416 kb
Host	smart-cb8b460b-cc86-49a5-9306-d72cf5f6995d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2682036505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.2682036505
Directory	/workspace/32.uart_loopback/latest

Test location	/workspace/coverage/default/32.uart_noise_filter.1820825409
Short name	T844
Test name
Test status
Simulation time	57119708486 ps
CPU time	68.55 seconds
Started	Apr 28 01:07:11 PM PDT 24
Finished	Apr 28 01:08:20 PM PDT 24
Peak memory	198976 kb
Host	smart-4bf31e00-83fa-499b-8dd6-da4efc34296d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1820825409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.1820825409
Directory	/workspace/32.uart_noise_filter/latest

Test location	/workspace/coverage/default/32.uart_perf.3081515850
Short name	T937
Test name
Test status
Simulation time	16276043806 ps
CPU time	669.24 seconds
Started	Apr 28 01:07:10 PM PDT 24
Finished	Apr 28 01:18:20 PM PDT 24
Peak memory	200360 kb
Host	smart-5d88b19b-fcba-4e49-9d2a-dd72e0a7acb2
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3081515850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.3081515850
Directory	/workspace/32.uart_perf/latest

Test location	/workspace/coverage/default/32.uart_rx_oversample.3059125258
Short name	T483
Test name
Test status
Simulation time	3254375337 ps
CPU time	7.57 seconds
Started	Apr 28 01:07:11 PM PDT 24
Finished	Apr 28 01:07:19 PM PDT 24
Peak memory	198736 kb
Host	smart-662ccda7-6abf-43cd-8e5a-c02a9822463f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3059125258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3059125258
Directory	/workspace/32.uart_rx_oversample/latest

Test location	/workspace/coverage/default/32.uart_rx_parity_err.186719397
Short name	T565
Test name
Test status
Simulation time	350367035598 ps
CPU time	45.85 seconds
Started	Apr 28 01:07:13 PM PDT 24
Finished	Apr 28 01:07:59 PM PDT 24
Peak memory	199804 kb
Host	smart-2ea943cb-d63d-45c4-b372-4fd2464dcda8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=186719397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.186719397
Directory	/workspace/32.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/32.uart_rx_start_bit_filter.2178018619
Short name	T1058
Test name
Test status
Simulation time	2072741417 ps
CPU time	3.86 seconds
Started	Apr 28 01:07:12 PM PDT 24
Finished	Apr 28 01:07:16 PM PDT 24
Peak memory	195788 kb
Host	smart-0280fa37-8f48-486a-8afa-05cef0b2ce4d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2178018619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.2178018619
Directory	/workspace/32.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/32.uart_smoke.2663005657
Short name	T632
Test name
Test status
Simulation time	268691397 ps
CPU time	1.28 seconds
Started	Apr 28 01:07:11 PM PDT 24
Finished	Apr 28 01:07:13 PM PDT 24
Peak memory	198700 kb
Host	smart-614a8552-773a-4bad-93c0-940515622e46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2663005657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.2663005657
Directory	/workspace/32.uart_smoke/latest

Test location	/workspace/coverage/default/32.uart_stress_all.3187077274
Short name	T549
Test name
Test status
Simulation time	14777702901 ps
CPU time	12.27 seconds
Started	Apr 28 01:07:15 PM PDT 24
Finished	Apr 28 01:07:28 PM PDT 24
Peak memory	200348 kb
Host	smart-b999c96a-fe01-4b80-9df7-4d360336f893
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187077274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.3187077274
Directory	/workspace/32.uart_stress_all/latest

Test location	/workspace/coverage/default/32.uart_stress_all_with_rand_reset.2122764921
Short name	T309
Test name
Test status
Simulation time	47502713438 ps
CPU time	266.87 seconds
Started	Apr 28 01:07:18 PM PDT 24
Finished	Apr 28 01:11:45 PM PDT 24
Peak memory	216732 kb
Host	smart-479d2625-f882-491b-b845-adebca24f87f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122764921 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.2122764921
Directory	/workspace/32.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/32.uart_tx_ovrd.1406083636
Short name	T392
Test name
Test status
Simulation time	6951153833 ps
CPU time	17.92 seconds
Started	Apr 28 01:07:11 PM PDT 24
Finished	Apr 28 01:07:29 PM PDT 24
Peak memory	200180 kb
Host	smart-a910d436-81ed-41fd-9376-bd302847bd6d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1406083636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.1406083636
Directory	/workspace/32.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/32.uart_tx_rx.3066379075
Short name	T264
Test name
Test status
Simulation time	109682103000 ps
CPU time	102.16 seconds
Started	Apr 28 01:07:11 PM PDT 24
Finished	Apr 28 01:08:54 PM PDT 24
Peak memory	200372 kb
Host	smart-5840b2e7-d434-4b67-afd5-1536331aa1db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3066379075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.3066379075
Directory	/workspace/32.uart_tx_rx/latest

Test location	/workspace/coverage/default/33.uart_alert_test.78805970
Short name	T1158
Test name
Test status
Simulation time	29087740 ps
CPU time	0.52 seconds
Started	Apr 28 01:07:23 PM PDT 24
Finished	Apr 28 01:07:24 PM PDT 24
Peak memory	194780 kb
Host	smart-ee4c07a5-0599-4199-876a-1178e06ada10
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78805970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.78805970
Directory	/workspace/33.uart_alert_test/latest

Test location	/workspace/coverage/default/33.uart_fifo_full.852190957
Short name	T301
Test name
Test status
Simulation time	41194661448 ps
CPU time	35.94 seconds
Started	Apr 28 01:07:21 PM PDT 24
Finished	Apr 28 01:07:57 PM PDT 24
Peak memory	200428 kb
Host	smart-2bb41209-d4eb-4bbf-9488-5c22b6d5133a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=852190957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.852190957
Directory	/workspace/33.uart_fifo_full/latest

Test location	/workspace/coverage/default/33.uart_fifo_overflow.3810270966
Short name	T43
Test name
Test status
Simulation time	37828232085 ps
CPU time	60.43 seconds
Started	Apr 28 01:07:16 PM PDT 24
Finished	Apr 28 01:08:17 PM PDT 24
Peak memory	200108 kb
Host	smart-01ace9cb-ea9b-4113-a847-4f2dee620232
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3810270966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.3810270966
Directory	/workspace/33.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/33.uart_fifo_reset.786238773
Short name	T281
Test name
Test status
Simulation time	33676919923 ps
CPU time	12.7 seconds
Started	Apr 28 01:07:16 PM PDT 24
Finished	Apr 28 01:07:30 PM PDT 24
Peak memory	198832 kb
Host	smart-151b516e-b63b-41ff-9462-f25a768fafee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=786238773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.786238773
Directory	/workspace/33.uart_fifo_reset/latest

Test location	/workspace/coverage/default/33.uart_intr.2593895038
Short name	T397
Test name
Test status
Simulation time	153905193527 ps
CPU time	48.5 seconds
Started	Apr 28 01:07:17 PM PDT 24
Finished	Apr 28 01:08:06 PM PDT 24
Peak memory	198488 kb
Host	smart-67ff6039-fca6-4471-95d7-840afc40bc9a
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593895038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.2593895038
Directory	/workspace/33.uart_intr/latest

Test location	/workspace/coverage/default/33.uart_long_xfer_wo_dly.2437358691
Short name	T372
Test name
Test status
Simulation time	77780801890 ps
CPU time	600.43 seconds
Started	Apr 28 01:07:23 PM PDT 24
Finished	Apr 28 01:17:23 PM PDT 24
Peak memory	200364 kb
Host	smart-b48fab49-a545-4da6-a6ff-621d36ace8d0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2437358691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2437358691
Directory	/workspace/33.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/33.uart_loopback.80509270
Short name	T1062
Test name
Test status
Simulation time	9514101637 ps
CPU time	12.52 seconds
Started	Apr 28 01:07:23 PM PDT 24
Finished	Apr 28 01:07:36 PM PDT 24
Peak memory	200464 kb
Host	smart-2a0a9dc1-bfea-46a5-baed-fa6b245d8cae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=80509270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.80509270
Directory	/workspace/33.uart_loopback/latest

Test location	/workspace/coverage/default/33.uart_noise_filter.2924037760
Short name	T268
Test name
Test status
Simulation time	82437840149 ps
CPU time	95.26 seconds
Started	Apr 28 01:07:19 PM PDT 24
Finished	Apr 28 01:08:55 PM PDT 24
Peak memory	200544 kb
Host	smart-f1d3a013-8816-4d88-b549-be70bc5bad0e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2924037760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.2924037760
Directory	/workspace/33.uart_noise_filter/latest

Test location	/workspace/coverage/default/33.uart_perf.972963619
Short name	T583
Test name
Test status
Simulation time	13742614589 ps
CPU time	623.24 seconds
Started	Apr 28 01:07:22 PM PDT 24
Finished	Apr 28 01:17:46 PM PDT 24
Peak memory	200448 kb
Host	smart-876e0f60-d2be-4519-9228-2c412e8f1f44
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=972963619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.972963619
Directory	/workspace/33.uart_perf/latest

Test location	/workspace/coverage/default/33.uart_rx_oversample.3105092351
Short name	T974
Test name
Test status
Simulation time	1914168216 ps
CPU time	11.42 seconds
Started	Apr 28 01:07:16 PM PDT 24
Finished	Apr 28 01:07:28 PM PDT 24
Peak memory	198336 kb
Host	smart-1d9e678e-6bce-4583-89c9-40b094cc6a20
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3105092351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.3105092351
Directory	/workspace/33.uart_rx_oversample/latest

Test location	/workspace/coverage/default/33.uart_rx_parity_err.2385955302
Short name	T332
Test name
Test status
Simulation time	5242214293 ps
CPU time	5.84 seconds
Started	Apr 28 01:07:21 PM PDT 24
Finished	Apr 28 01:07:27 PM PDT 24
Peak memory	200324 kb
Host	smart-aed99a2f-b283-41fb-b558-785163ad933f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2385955302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.2385955302
Directory	/workspace/33.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/33.uart_rx_start_bit_filter.1781865660
Short name	T543
Test name
Test status
Simulation time	4775696310 ps
CPU time	4.11 seconds
Started	Apr 28 01:07:16 PM PDT 24
Finished	Apr 28 01:07:20 PM PDT 24
Peak memory	196732 kb
Host	smart-16b8d270-50e1-4adf-875f-6d92df37ab46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1781865660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.1781865660
Directory	/workspace/33.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/33.uart_smoke.2105204292
Short name	T984
Test name
Test status
Simulation time	256688546 ps
CPU time	1.11 seconds
Started	Apr 28 01:07:15 PM PDT 24
Finished	Apr 28 01:07:17 PM PDT 24
Peak memory	198896 kb
Host	smart-fc6553f9-4ed0-460a-9e8e-20c3cd37af43
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2105204292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.2105204292
Directory	/workspace/33.uart_smoke/latest

Test location	/workspace/coverage/default/33.uart_stress_all.1908927063
Short name	T741
Test name
Test status
Simulation time	420783556704 ps
CPU time	181.18 seconds
Started	Apr 28 01:07:22 PM PDT 24
Finished	Apr 28 01:10:23 PM PDT 24
Peak memory	208748 kb
Host	smart-4a91ad17-a4cb-444c-834c-8586b593c805
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908927063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.1908927063
Directory	/workspace/33.uart_stress_all/latest

Test location	/workspace/coverage/default/33.uart_stress_all_with_rand_reset.3775437933
Short name	T783
Test name
Test status
Simulation time	13132398368 ps
CPU time	212.79 seconds
Started	Apr 28 01:07:23 PM PDT 24
Finished	Apr 28 01:10:56 PM PDT 24
Peak memory	210232 kb
Host	smart-d09786fd-221b-4004-a046-b053f4424204
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775437933 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.3775437933
Directory	/workspace/33.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/33.uart_tx_ovrd.1234760863
Short name	T867
Test name
Test status
Simulation time	6531167874 ps
CPU time	16.31 seconds
Started	Apr 28 01:07:22 PM PDT 24
Finished	Apr 28 01:07:39 PM PDT 24
Peak memory	200244 kb
Host	smart-df9187e1-6b26-4634-a70d-c568b9e60e42
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1234760863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.1234760863
Directory	/workspace/33.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/33.uart_tx_rx.1584655595
Short name	T105
Test name
Test status
Simulation time	37971576573 ps
CPU time	19.91 seconds
Started	Apr 28 01:07:17 PM PDT 24
Finished	Apr 28 01:07:38 PM PDT 24
Peak memory	200360 kb
Host	smart-5600df2a-540f-4086-ac4c-e59e387aeb35
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1584655595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.1584655595
Directory	/workspace/33.uart_tx_rx/latest

Test location	/workspace/coverage/default/34.uart_alert_test.1064189157
Short name	T404
Test name
Test status
Simulation time	77174799 ps
CPU time	0.55 seconds
Started	Apr 28 01:07:26 PM PDT 24
Finished	Apr 28 01:07:27 PM PDT 24
Peak memory	195824 kb
Host	smart-a6bf8ff2-7624-488b-9fb3-705e6e350bdf
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064189157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1064189157
Directory	/workspace/34.uart_alert_test/latest

Test location	/workspace/coverage/default/34.uart_fifo_full.1767962932
Short name	T328
Test name
Test status
Simulation time	188044373985 ps
CPU time	124.54 seconds
Started	Apr 28 01:07:22 PM PDT 24
Finished	Apr 28 01:09:27 PM PDT 24
Peak memory	200368 kb
Host	smart-650cf955-ad92-47a5-b22a-cf64b2831183
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1767962932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.1767962932
Directory	/workspace/34.uart_fifo_full/latest

Test location	/workspace/coverage/default/34.uart_fifo_overflow.2040798922
Short name	T467
Test name
Test status
Simulation time	52883438625 ps
CPU time	21.34 seconds
Started	Apr 28 01:07:27 PM PDT 24
Finished	Apr 28 01:07:48 PM PDT 24
Peak memory	200340 kb
Host	smart-b3715eaa-905b-42ff-bc83-f44b33622073
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2040798922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.2040798922
Directory	/workspace/34.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/34.uart_intr.3626008986
Short name	T905
Test name
Test status
Simulation time	42073451874 ps
CPU time	54.42 seconds
Started	Apr 28 01:07:22 PM PDT 24
Finished	Apr 28 01:08:16 PM PDT 24
Peak memory	200404 kb
Host	smart-9c089136-93dd-4a5a-bb12-859e2498e141
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626008986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3626008986
Directory	/workspace/34.uart_intr/latest

Test location	/workspace/coverage/default/34.uart_long_xfer_wo_dly.1429491429
Short name	T720
Test name
Test status
Simulation time	153783623477 ps
CPU time	234.42 seconds
Started	Apr 28 01:07:26 PM PDT 24
Finished	Apr 28 01:11:21 PM PDT 24
Peak memory	200284 kb
Host	smart-26ee43c3-e36d-44fd-990d-882720a847c6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1429491429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.1429491429
Directory	/workspace/34.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/34.uart_loopback.1395851935
Short name	T998
Test name
Test status
Simulation time	5774193448 ps
CPU time	3.34 seconds
Started	Apr 28 01:07:28 PM PDT 24
Finished	Apr 28 01:07:32 PM PDT 24
Peak memory	199728 kb
Host	smart-56ddb8cc-70ed-45ea-85c0-71bf01efcf17
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1395851935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.1395851935
Directory	/workspace/34.uart_loopback/latest

Test location	/workspace/coverage/default/34.uart_noise_filter.3466186852
Short name	T306
Test name
Test status
Simulation time	90802310080 ps
CPU time	55.41 seconds
Started	Apr 28 01:07:20 PM PDT 24
Finished	Apr 28 01:08:16 PM PDT 24
Peak memory	199836 kb
Host	smart-befd2fdd-83e7-4077-b0a7-4ef42814c13d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3466186852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.3466186852
Directory	/workspace/34.uart_noise_filter/latest

Test location	/workspace/coverage/default/34.uart_perf.4209560624
Short name	T915
Test name
Test status
Simulation time	13806464705 ps
CPU time	108.2 seconds
Started	Apr 28 01:07:27 PM PDT 24
Finished	Apr 28 01:09:16 PM PDT 24
Peak memory	200356 kb
Host	smart-adceb82f-44fd-4cb7-8867-fb5b1b91de39
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4209560624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.4209560624
Directory	/workspace/34.uart_perf/latest

Test location	/workspace/coverage/default/34.uart_rx_oversample.1388578085
Short name	T362
Test name
Test status
Simulation time	7200038314 ps
CPU time	32.01 seconds
Started	Apr 28 01:07:22 PM PDT 24
Finished	Apr 28 01:07:54 PM PDT 24
Peak memory	199188 kb
Host	smart-2a149681-6c82-44cd-ace2-500204a45b07
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1388578085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.1388578085
Directory	/workspace/34.uart_rx_oversample/latest

Test location	/workspace/coverage/default/34.uart_rx_parity_err.2689008832
Short name	T1099
Test name
Test status
Simulation time	77029012816 ps
CPU time	115.41 seconds
Started	Apr 28 01:07:21 PM PDT 24
Finished	Apr 28 01:09:17 PM PDT 24
Peak memory	200348 kb
Host	smart-d5764df1-9a9f-4dcc-aac9-fa5e016b90e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2689008832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.2689008832
Directory	/workspace/34.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/34.uart_rx_start_bit_filter.2458197260
Short name	T944
Test name
Test status
Simulation time	3177187842 ps
CPU time	6.17 seconds
Started	Apr 28 01:07:28 PM PDT 24
Finished	Apr 28 01:07:35 PM PDT 24
Peak memory	196428 kb
Host	smart-493596a3-297f-4e58-8f7b-154032173461
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2458197260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.2458197260
Directory	/workspace/34.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/34.uart_smoke.4158240403
Short name	T913
Test name
Test status
Simulation time	265633576 ps
CPU time	1.29 seconds
Started	Apr 28 01:07:27 PM PDT 24
Finished	Apr 28 01:07:29 PM PDT 24
Peak memory	198936 kb
Host	smart-ee5f3b39-3d82-42d5-b81e-62befa3c874c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4158240403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.4158240403
Directory	/workspace/34.uart_smoke/latest

Test location	/workspace/coverage/default/34.uart_stress_all_with_rand_reset.1833871584
Short name	T925
Test name
Test status
Simulation time	861534972570 ps
CPU time	1110.82 seconds
Started	Apr 28 01:07:27 PM PDT 24
Finished	Apr 28 01:25:58 PM PDT 24
Peak memory	226312 kb
Host	smart-02648f8b-3ecd-47c4-b95e-cb8527bba806
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833871584 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.1833871584
Directory	/workspace/34.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/34.uart_tx_ovrd.3307988686
Short name	T339
Test name
Test status
Simulation time	394446290 ps
CPU time	1.03 seconds
Started	Apr 28 01:07:22 PM PDT 24
Finished	Apr 28 01:07:23 PM PDT 24
Peak memory	198412 kb
Host	smart-76a7e4dd-deee-4614-9337-36855366be82
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3307988686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.3307988686
Directory	/workspace/34.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/34.uart_tx_rx.4162448484
Short name	T385
Test name
Test status
Simulation time	35941967025 ps
CPU time	65.62 seconds
Started	Apr 28 01:07:22 PM PDT 24
Finished	Apr 28 01:08:28 PM PDT 24
Peak memory	200416 kb
Host	smart-dd1bb5ec-591e-4726-8022-693f2a7d782e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4162448484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.4162448484
Directory	/workspace/34.uart_tx_rx/latest

Test location	/workspace/coverage/default/35.uart_alert_test.1686797811
Short name	T891
Test name
Test status
Simulation time	37215397 ps
CPU time	0.53 seconds
Started	Apr 28 01:07:34 PM PDT 24
Finished	Apr 28 01:07:35 PM PDT 24
Peak memory	195656 kb
Host	smart-93e9daeb-7c2e-4b0a-8efc-d0ad721645c3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686797811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.1686797811
Directory	/workspace/35.uart_alert_test/latest

Test location	/workspace/coverage/default/35.uart_fifo_full.4079091555
Short name	T462
Test name
Test status
Simulation time	223467977161 ps
CPU time	29.29 seconds
Started	Apr 28 01:07:26 PM PDT 24
Finished	Apr 28 01:07:56 PM PDT 24
Peak memory	200440 kb
Host	smart-b058a2fa-d1fc-4f57-b195-c2101538658e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4079091555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.4079091555
Directory	/workspace/35.uart_fifo_full/latest

Test location	/workspace/coverage/default/35.uart_fifo_overflow.257615000
Short name	T806
Test name
Test status
Simulation time	23836569149 ps
CPU time	47.28 seconds
Started	Apr 28 01:07:27 PM PDT 24
Finished	Apr 28 01:08:15 PM PDT 24
Peak memory	200400 kb
Host	smart-5ba0b102-1781-401a-a9de-2b275306cdd6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=257615000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.257615000
Directory	/workspace/35.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/35.uart_fifo_reset.1089339497
Short name	T1123
Test name
Test status
Simulation time	49543967073 ps
CPU time	11.39 seconds
Started	Apr 28 01:07:28 PM PDT 24
Finished	Apr 28 01:07:40 PM PDT 24
Peak memory	200300 kb
Host	smart-f9bc4aa2-da5a-403c-bb57-9f7643a2346a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1089339497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.1089339497
Directory	/workspace/35.uart_fifo_reset/latest

Test location	/workspace/coverage/default/35.uart_intr.3141839561
Short name	T396
Test name
Test status
Simulation time	151175817883 ps
CPU time	66.23 seconds
Started	Apr 28 01:07:25 PM PDT 24
Finished	Apr 28 01:08:32 PM PDT 24
Peak memory	200312 kb
Host	smart-db93f8b6-8641-4541-a933-4c91cf4ad482
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141839561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.3141839561
Directory	/workspace/35.uart_intr/latest

Test location	/workspace/coverage/default/35.uart_long_xfer_wo_dly.4178202428
Short name	T1120
Test name
Test status
Simulation time	80871014272 ps
CPU time	489.47 seconds
Started	Apr 28 01:07:32 PM PDT 24
Finished	Apr 28 01:15:42 PM PDT 24
Peak memory	200220 kb
Host	smart-54f71552-e517-4194-a8ec-0ba78c091d91
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4178202428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.4178202428
Directory	/workspace/35.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/35.uart_loopback.360478055
Short name	T703
Test name
Test status
Simulation time	9937484631 ps
CPU time	19.59 seconds
Started	Apr 28 01:07:28 PM PDT 24
Finished	Apr 28 01:07:49 PM PDT 24
Peak memory	199020 kb
Host	smart-24db0c57-ff22-4f2b-9a63-2f326fe7497f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=360478055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.360478055
Directory	/workspace/35.uart_loopback/latest

Test location	/workspace/coverage/default/35.uart_perf.437192067
Short name	T410
Test name
Test status
Simulation time	24373879150 ps
CPU time	633.03 seconds
Started	Apr 28 01:07:25 PM PDT 24
Finished	Apr 28 01:17:59 PM PDT 24
Peak memory	200404 kb
Host	smart-a5f5f761-80c8-4db0-85af-267f1590ec59
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=437192067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.437192067
Directory	/workspace/35.uart_perf/latest

Test location	/workspace/coverage/default/35.uart_rx_oversample.3406102131
Short name	T340
Test name
Test status
Simulation time	1811294333 ps
CPU time	3.49 seconds
Started	Apr 28 01:07:28 PM PDT 24
Finished	Apr 28 01:07:32 PM PDT 24
Peak memory	198448 kb
Host	smart-14ad5a35-f3e5-4c97-9622-6fa52d0a7183
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3406102131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.3406102131
Directory	/workspace/35.uart_rx_oversample/latest

Test location	/workspace/coverage/default/35.uart_rx_parity_err.1527217257
Short name	T762
Test name
Test status
Simulation time	171085106859 ps
CPU time	242.27 seconds
Started	Apr 28 01:07:28 PM PDT 24
Finished	Apr 28 01:11:31 PM PDT 24
Peak memory	200420 kb
Host	smart-9701771f-0062-4e66-b342-6f95326daceb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1527217257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.1527217257
Directory	/workspace/35.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/35.uart_rx_start_bit_filter.2305057778
Short name	T639
Test name
Test status
Simulation time	2629766284 ps
CPU time	1.75 seconds
Started	Apr 28 01:07:27 PM PDT 24
Finished	Apr 28 01:07:29 PM PDT 24
Peak memory	196148 kb
Host	smart-895411df-ddcd-4f58-8d2d-94bb11a19620
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2305057778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.2305057778
Directory	/workspace/35.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/35.uart_smoke.3179915410
Short name	T376
Test name
Test status
Simulation time	460776503 ps
CPU time	1.27 seconds
Started	Apr 28 01:07:27 PM PDT 24
Finished	Apr 28 01:07:29 PM PDT 24
Peak memory	200248 kb
Host	smart-e1b84fae-c63a-40fc-92ee-bc75a156a80b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3179915410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.3179915410
Directory	/workspace/35.uart_smoke/latest

Test location	/workspace/coverage/default/35.uart_stress_all.992714849
Short name	T957
Test name
Test status
Simulation time	266895651635 ps
CPU time	98.66 seconds
Started	Apr 28 01:07:32 PM PDT 24
Finished	Apr 28 01:09:11 PM PDT 24
Peak memory	200368 kb
Host	smart-3cfd34c8-975a-4038-8631-044992364c5a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992714849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.992714849
Directory	/workspace/35.uart_stress_all/latest

Test location	/workspace/coverage/default/35.uart_stress_all_with_rand_reset.2710896786
Short name	T31
Test name
Test status
Simulation time	81123438269 ps
CPU time	425.79 seconds
Started	Apr 28 01:07:31 PM PDT 24
Finished	Apr 28 01:14:38 PM PDT 24
Peak memory	216764 kb
Host	smart-a1cc77dc-dbad-444f-8c10-bba622545c0d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710896786 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.2710896786
Directory	/workspace/35.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/35.uart_tx_ovrd.1548775734
Short name	T402
Test name
Test status
Simulation time	2002439342 ps
CPU time	1.78 seconds
Started	Apr 28 01:07:28 PM PDT 24
Finished	Apr 28 01:07:30 PM PDT 24
Peak memory	198880 kb
Host	smart-5083acbd-f114-4333-a686-fe3a47d52373
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1548775734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.1548775734
Directory	/workspace/35.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/35.uart_tx_rx.3728146018
Short name	T1147
Test name
Test status
Simulation time	46133548010 ps
CPU time	70.96 seconds
Started	Apr 28 01:07:28 PM PDT 24
Finished	Apr 28 01:08:39 PM PDT 24
Peak memory	200272 kb
Host	smart-30926d2a-54ac-47d7-8062-1a5a540ce111
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3728146018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.3728146018
Directory	/workspace/35.uart_tx_rx/latest

Test location	/workspace/coverage/default/36.uart_alert_test.1171443939
Short name	T95
Test name
Test status
Simulation time	18103463 ps
CPU time	0.52 seconds
Started	Apr 28 01:07:37 PM PDT 24
Finished	Apr 28 01:07:38 PM PDT 24
Peak memory	194712 kb
Host	smart-17b9dac7-e681-40b1-950a-bc4cb6d10e86
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171443939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.1171443939
Directory	/workspace/36.uart_alert_test/latest

Test location	/workspace/coverage/default/36.uart_fifo_full.656248943
Short name	T303
Test name
Test status
Simulation time	29708043036 ps
CPU time	23.69 seconds
Started	Apr 28 01:07:32 PM PDT 24
Finished	Apr 28 01:07:56 PM PDT 24
Peak memory	200332 kb
Host	smart-d2234bec-89b7-4c06-b152-371fc995ab90
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=656248943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.656248943
Directory	/workspace/36.uart_fifo_full/latest

Test location	/workspace/coverage/default/36.uart_fifo_overflow.3864819230
Short name	T519
Test name
Test status
Simulation time	16194939682 ps
CPU time	25.98 seconds
Started	Apr 28 01:07:32 PM PDT 24
Finished	Apr 28 01:07:59 PM PDT 24
Peak memory	200328 kb
Host	smart-576513a0-e2c7-4f08-ab02-21db89356d4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3864819230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.3864819230
Directory	/workspace/36.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/36.uart_fifo_reset.2764855261
Short name	T770
Test name
Test status
Simulation time	18341953850 ps
CPU time	35.04 seconds
Started	Apr 28 01:07:32 PM PDT 24
Finished	Apr 28 01:08:07 PM PDT 24
Peak memory	200456 kb
Host	smart-2a294e65-2fdc-4ba1-97a8-016cb42f80eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2764855261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.2764855261
Directory	/workspace/36.uart_fifo_reset/latest

Test location	/workspace/coverage/default/36.uart_intr.2186724223
Short name	T896
Test name
Test status
Simulation time	60289400313 ps
CPU time	100.06 seconds
Started	Apr 28 01:07:32 PM PDT 24
Finished	Apr 28 01:09:12 PM PDT 24
Peak memory	200376 kb
Host	smart-6f56097f-6f94-4522-99ea-96e9f4e39d07
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186724223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.2186724223
Directory	/workspace/36.uart_intr/latest

Test location	/workspace/coverage/default/36.uart_long_xfer_wo_dly.532649175
Short name	T695
Test name
Test status
Simulation time	117475344520 ps
CPU time	676.95 seconds
Started	Apr 28 01:07:37 PM PDT 24
Finished	Apr 28 01:18:55 PM PDT 24
Peak memory	200232 kb
Host	smart-d7a8d224-44b2-41dc-a976-ebbed5803aa1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=532649175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.532649175
Directory	/workspace/36.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/36.uart_loopback.3030507182
Short name	T717
Test name
Test status
Simulation time	1174832396 ps
CPU time	3.39 seconds
Started	Apr 28 01:07:37 PM PDT 24
Finished	Apr 28 01:07:41 PM PDT 24
Peak memory	199076 kb
Host	smart-235d0ace-6452-4dcf-af8a-181d63e75c0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3030507182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.3030507182
Directory	/workspace/36.uart_loopback/latest

Test location	/workspace/coverage/default/36.uart_noise_filter.3438508434
Short name	T965
Test name
Test status
Simulation time	85017819733 ps
CPU time	74.45 seconds
Started	Apr 28 01:07:31 PM PDT 24
Finished	Apr 28 01:08:46 PM PDT 24
Peak memory	200624 kb
Host	smart-6fd3dc70-1543-4916-bb2e-035b2d30090d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3438508434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.3438508434
Directory	/workspace/36.uart_noise_filter/latest

Test location	/workspace/coverage/default/36.uart_perf.216319024
Short name	T254
Test name
Test status
Simulation time	11517632073 ps
CPU time	547.44 seconds
Started	Apr 28 01:07:39 PM PDT 24
Finished	Apr 28 01:16:47 PM PDT 24
Peak memory	200424 kb
Host	smart-e690a28f-9e87-4cad-8c38-26b64133338b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=216319024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.216319024
Directory	/workspace/36.uart_perf/latest

Test location	/workspace/coverage/default/36.uart_rx_oversample.629714549
Short name	T1111
Test name
Test status
Simulation time	6957925279 ps
CPU time	16.27 seconds
Started	Apr 28 01:07:31 PM PDT 24
Finished	Apr 28 01:07:47 PM PDT 24
Peak memory	199616 kb
Host	smart-193b3cf9-fd65-434a-9206-c1328f35f62b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=629714549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.629714549
Directory	/workspace/36.uart_rx_oversample/latest

Test location	/workspace/coverage/default/36.uart_rx_parity_err.3865617797
Short name	T1087
Test name
Test status
Simulation time	212203417249 ps
CPU time	327.23 seconds
Started	Apr 28 01:07:31 PM PDT 24
Finished	Apr 28 01:12:59 PM PDT 24
Peak memory	200252 kb
Host	smart-9040fba6-e049-47ef-b633-558d97b28c9d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3865617797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.3865617797
Directory	/workspace/36.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/36.uart_rx_start_bit_filter.3968327357
Short name	T993
Test name
Test status
Simulation time	3287490192 ps
CPU time	5.53 seconds
Started	Apr 28 01:07:33 PM PDT 24
Finished	Apr 28 01:07:39 PM PDT 24
Peak memory	196408 kb
Host	smart-e23c3fb4-8aec-48e8-971e-a94c09bb64c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3968327357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3968327357
Directory	/workspace/36.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/36.uart_smoke.1709106950
Short name	T901
Test name
Test status
Simulation time	918441127 ps
CPU time	2.02 seconds
Started	Apr 28 01:07:32 PM PDT 24
Finished	Apr 28 01:07:35 PM PDT 24
Peak memory	199316 kb
Host	smart-017af1f9-cf1c-4061-b7ae-3da3988c91b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1709106950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.1709106950
Directory	/workspace/36.uart_smoke/latest

Test location	/workspace/coverage/default/36.uart_stress_all.1720335711
Short name	T146
Test name
Test status
Simulation time	270426873001 ps
CPU time	95.69 seconds
Started	Apr 28 01:07:39 PM PDT 24
Finished	Apr 28 01:09:15 PM PDT 24
Peak memory	200292 kb
Host	smart-e7f40fe9-4fad-42eb-94df-9c5ba1873101
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720335711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.1720335711
Directory	/workspace/36.uart_stress_all/latest

Test location	/workspace/coverage/default/36.uart_stress_all_with_rand_reset.692612750
Short name	T28
Test name
Test status
Simulation time	118328712923 ps
CPU time	363.53 seconds
Started	Apr 28 01:07:37 PM PDT 24
Finished	Apr 28 01:13:41 PM PDT 24
Peak memory	216748 kb
Host	smart-1258bfeb-9bcf-4b78-b238-63217799f417
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692612750 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.692612750
Directory	/workspace/36.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/36.uart_tx_ovrd.1695580878
Short name	T297
Test name
Test status
Simulation time	2727795749 ps
CPU time	2.04 seconds
Started	Apr 28 01:07:33 PM PDT 24
Finished	Apr 28 01:07:35 PM PDT 24
Peak memory	199160 kb
Host	smart-fcffb984-9297-4d6b-b69f-e10a6c7190c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1695580878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.1695580878
Directory	/workspace/36.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/36.uart_tx_rx.3766132200
Short name	T578
Test name
Test status
Simulation time	15531252222 ps
CPU time	26.97 seconds
Started	Apr 28 01:07:34 PM PDT 24
Finished	Apr 28 01:08:01 PM PDT 24
Peak memory	200344 kb
Host	smart-a71d87b4-4402-4ec9-b3f9-a3e148b1d33d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3766132200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.3766132200
Directory	/workspace/36.uart_tx_rx/latest

Test location	/workspace/coverage/default/37.uart_alert_test.1769309993
Short name	T948
Test name
Test status
Simulation time	67149857 ps
CPU time	0.58 seconds
Started	Apr 28 01:07:42 PM PDT 24
Finished	Apr 28 01:07:43 PM PDT 24
Peak memory	195748 kb
Host	smart-8abe40cd-486e-41e9-8d9e-28a81fa081b8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769309993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.1769309993
Directory	/workspace/37.uart_alert_test/latest

Test location	/workspace/coverage/default/37.uart_fifo_full.4189602791
Short name	T771
Test name
Test status
Simulation time	20147982090 ps
CPU time	30.65 seconds
Started	Apr 28 01:07:38 PM PDT 24
Finished	Apr 28 01:08:09 PM PDT 24
Peak memory	200440 kb
Host	smart-bb21ebe8-f77f-44bf-a2ca-6e25e1cf7207
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4189602791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.4189602791
Directory	/workspace/37.uart_fifo_full/latest

Test location	/workspace/coverage/default/37.uart_fifo_overflow.1610297955
Short name	T1100
Test name
Test status
Simulation time	116062505593 ps
CPU time	154.44 seconds
Started	Apr 28 01:07:37 PM PDT 24
Finished	Apr 28 01:10:12 PM PDT 24
Peak memory	200372 kb
Host	smart-f976df6e-11de-467e-bac8-3f06ff45502f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1610297955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.1610297955
Directory	/workspace/37.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/37.uart_fifo_reset.968700512
Short name	T803
Test name
Test status
Simulation time	27431831710 ps
CPU time	48.4 seconds
Started	Apr 28 01:07:38 PM PDT 24
Finished	Apr 28 01:08:26 PM PDT 24
Peak memory	200292 kb
Host	smart-c05d8d8d-5372-40e5-8644-cf14f57157d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=968700512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.968700512
Directory	/workspace/37.uart_fifo_reset/latest

Test location	/workspace/coverage/default/37.uart_intr.3917939652
Short name	T1106
Test name
Test status
Simulation time	15349782370 ps
CPU time	7.21 seconds
Started	Apr 28 01:07:41 PM PDT 24
Finished	Apr 28 01:07:49 PM PDT 24
Peak memory	198220 kb
Host	smart-d7b5ade6-8eb5-45c8-a908-60bcd3ae58e6
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917939652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.3917939652
Directory	/workspace/37.uart_intr/latest

Test location	/workspace/coverage/default/37.uart_long_xfer_wo_dly.2267094455
Short name	T505
Test name
Test status
Simulation time	143068839587 ps
CPU time	1387.05 seconds
Started	Apr 28 01:07:44 PM PDT 24
Finished	Apr 28 01:30:51 PM PDT 24
Peak memory	200376 kb
Host	smart-ae19c08a-7ec6-43d1-bd4a-9050225c9277
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2267094455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.2267094455
Directory	/workspace/37.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/37.uart_loopback.1278873444
Short name	T756
Test name
Test status
Simulation time	5296438590 ps
CPU time	2.68 seconds
Started	Apr 28 01:07:45 PM PDT 24
Finished	Apr 28 01:07:47 PM PDT 24
Peak memory	199748 kb
Host	smart-e1ef419a-0bbe-4ef6-b408-cc7757d75de5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1278873444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.1278873444
Directory	/workspace/37.uart_loopback/latest

Test location	/workspace/coverage/default/37.uart_noise_filter.3752650845
Short name	T681
Test name
Test status
Simulation time	29456290886 ps
CPU time	22.33 seconds
Started	Apr 28 01:07:37 PM PDT 24
Finished	Apr 28 01:08:00 PM PDT 24
Peak memory	199452 kb
Host	smart-426a6314-79cc-4f03-8daf-45c0963b72ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3752650845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.3752650845
Directory	/workspace/37.uart_noise_filter/latest

Test location	/workspace/coverage/default/37.uart_perf.1607383763
Short name	T799
Test name
Test status
Simulation time	16081814655 ps
CPU time	928.54 seconds
Started	Apr 28 01:07:44 PM PDT 24
Finished	Apr 28 01:23:13 PM PDT 24
Peak memory	200448 kb
Host	smart-6c3cb4b1-3e74-4445-ad77-8c883865ee80
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1607383763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.1607383763
Directory	/workspace/37.uart_perf/latest

Test location	/workspace/coverage/default/37.uart_rx_oversample.2643901874
Short name	T357
Test name
Test status
Simulation time	5483755579 ps
CPU time	11.8 seconds
Started	Apr 28 01:07:38 PM PDT 24
Finished	Apr 28 01:07:50 PM PDT 24
Peak memory	198756 kb
Host	smart-06bd210d-c05f-46cd-8ec5-4563f78420d9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2643901874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.2643901874
Directory	/workspace/37.uart_rx_oversample/latest

Test location	/workspace/coverage/default/37.uart_rx_parity_err.289643194
Short name	T757
Test name
Test status
Simulation time	252486326084 ps
CPU time	71.93 seconds
Started	Apr 28 01:07:43 PM PDT 24
Finished	Apr 28 01:08:55 PM PDT 24
Peak memory	200460 kb
Host	smart-465f8cca-a7e5-4c89-a137-d8d3f143a0a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=289643194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.289643194
Directory	/workspace/37.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/37.uart_rx_start_bit_filter.1795254360
Short name	T276
Test name
Test status
Simulation time	2985937132 ps
CPU time	2.78 seconds
Started	Apr 28 01:07:39 PM PDT 24
Finished	Apr 28 01:07:42 PM PDT 24
Peak memory	196368 kb
Host	smart-c66887ce-59e9-411b-9a49-c815c32c1adb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1795254360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.1795254360
Directory	/workspace/37.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/37.uart_smoke.1786194857
Short name	T613
Test name
Test status
Simulation time	6015800541 ps
CPU time	18.57 seconds
Started	Apr 28 01:07:39 PM PDT 24
Finished	Apr 28 01:07:58 PM PDT 24
Peak memory	199680 kb
Host	smart-24707615-953c-4f8c-a5e5-2dcab9516964
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1786194857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.1786194857
Directory	/workspace/37.uart_smoke/latest

Test location	/workspace/coverage/default/37.uart_stress_all.119945458
Short name	T282
Test name
Test status
Simulation time	209832549940 ps
CPU time	268.17 seconds
Started	Apr 28 01:07:42 PM PDT 24
Finished	Apr 28 01:12:11 PM PDT 24
Peak memory	200356 kb
Host	smart-8765b77c-ba32-49ff-92e0-df32b71cf2eb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119945458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.119945458
Directory	/workspace/37.uart_stress_all/latest

Test location	/workspace/coverage/default/37.uart_stress_all_with_rand_reset.1308903978
Short name	T488
Test name
Test status
Simulation time	89417364491 ps
CPU time	262.35 seconds
Started	Apr 28 01:07:43 PM PDT 24
Finished	Apr 28 01:12:06 PM PDT 24
Peak memory	217016 kb
Host	smart-d61450a4-6324-4b48-8774-3fc76ab51fcc
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308903978 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.1308903978
Directory	/workspace/37.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/37.uart_tx_ovrd.1358743697
Short name	T535
Test name
Test status
Simulation time	1298435302 ps
CPU time	1.5 seconds
Started	Apr 28 01:07:43 PM PDT 24
Finished	Apr 28 01:07:44 PM PDT 24
Peak memory	200388 kb
Host	smart-39a1eeac-80cb-4eea-b22c-be33ff6eb456
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1358743697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1358743697
Directory	/workspace/37.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/37.uart_tx_rx.3464625898
Short name	T785
Test name
Test status
Simulation time	23672872039 ps
CPU time	36.02 seconds
Started	Apr 28 01:07:38 PM PDT 24
Finished	Apr 28 01:08:14 PM PDT 24
Peak memory	200384 kb
Host	smart-70f276b8-89b6-44fd-9f4f-7f872e360d00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3464625898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.3464625898
Directory	/workspace/37.uart_tx_rx/latest

Test location	/workspace/coverage/default/38.uart_alert_test.4020255922
Short name	T979
Test name
Test status
Simulation time	68297645 ps
CPU time	0.55 seconds
Started	Apr 28 01:07:57 PM PDT 24
Finished	Apr 28 01:07:58 PM PDT 24
Peak memory	195808 kb
Host	smart-cc90088f-5c76-4982-bb03-276598eb505a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020255922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.4020255922
Directory	/workspace/38.uart_alert_test/latest

Test location	/workspace/coverage/default/38.uart_fifo_full.3658121863
Short name	T586
Test name
Test status
Simulation time	140224977834 ps
CPU time	34.69 seconds
Started	Apr 28 01:07:48 PM PDT 24
Finished	Apr 28 01:08:23 PM PDT 24
Peak memory	200324 kb
Host	smart-585a150f-722c-427f-8209-d0ade5af28b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3658121863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.3658121863
Directory	/workspace/38.uart_fifo_full/latest

Test location	/workspace/coverage/default/38.uart_fifo_overflow.3892603203
Short name	T437
Test name
Test status
Simulation time	122240960097 ps
CPU time	197.04 seconds
Started	Apr 28 01:07:48 PM PDT 24
Finished	Apr 28 01:11:06 PM PDT 24
Peak memory	200428 kb
Host	smart-665254d7-50da-4463-b772-05e11c0ebb35
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3892603203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.3892603203
Directory	/workspace/38.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/38.uart_fifo_reset.2085975382
Short name	T1042
Test name
Test status
Simulation time	54257278445 ps
CPU time	94.25 seconds
Started	Apr 28 01:07:49 PM PDT 24
Finished	Apr 28 01:09:24 PM PDT 24
Peak memory	200372 kb
Host	smart-7046385f-38cf-4f7f-8cd0-8ba6b38ee72a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2085975382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.2085975382
Directory	/workspace/38.uart_fifo_reset/latest

Test location	/workspace/coverage/default/38.uart_intr.2397539435
Short name	T377
Test name
Test status
Simulation time	3856940939 ps
CPU time	2.37 seconds
Started	Apr 28 01:07:47 PM PDT 24
Finished	Apr 28 01:07:50 PM PDT 24
Peak memory	197052 kb
Host	smart-dc19899b-526e-4643-aa26-69705db49456
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397539435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.2397539435
Directory	/workspace/38.uart_intr/latest

Test location	/workspace/coverage/default/38.uart_long_xfer_wo_dly.3420191858
Short name	T942
Test name
Test status
Simulation time	68348480208 ps
CPU time	177.97 seconds
Started	Apr 28 01:07:51 PM PDT 24
Finished	Apr 28 01:10:50 PM PDT 24
Peak memory	200448 kb
Host	smart-d04de306-139b-4d7e-8465-9b356242cdf9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3420191858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.3420191858
Directory	/workspace/38.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/38.uart_loopback.1672357948
Short name	T337
Test name
Test status
Simulation time	7497246051 ps
CPU time	12.99 seconds
Started	Apr 28 01:07:49 PM PDT 24
Finished	Apr 28 01:08:02 PM PDT 24
Peak memory	198656 kb
Host	smart-18f4d36f-73a4-4d5a-b00b-fed9cc677cf5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1672357948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1672357948
Directory	/workspace/38.uart_loopback/latest

Test location	/workspace/coverage/default/38.uart_noise_filter.500218533
Short name	T797
Test name
Test status
Simulation time	70071906561 ps
CPU time	21.51 seconds
Started	Apr 28 01:07:48 PM PDT 24
Finished	Apr 28 01:08:10 PM PDT 24
Peak memory	200600 kb
Host	smart-75a52d92-747b-418c-a9f4-fd0a768a46c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=500218533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.500218533
Directory	/workspace/38.uart_noise_filter/latest

Test location	/workspace/coverage/default/38.uart_perf.199787441
Short name	T723
Test name
Test status
Simulation time	21457903369 ps
CPU time	254.23 seconds
Started	Apr 28 01:07:49 PM PDT 24
Finished	Apr 28 01:12:04 PM PDT 24
Peak memory	200340 kb
Host	smart-173df8d3-c375-47e8-b195-25394254017b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=199787441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.199787441
Directory	/workspace/38.uart_perf/latest

Test location	/workspace/coverage/default/38.uart_rx_oversample.2157841698
Short name	T1018
Test name
Test status
Simulation time	7597625912 ps
CPU time	62.28 seconds
Started	Apr 28 01:07:50 PM PDT 24
Finished	Apr 28 01:08:52 PM PDT 24
Peak memory	199632 kb
Host	smart-9370473a-471c-4bc2-bf9d-6b4d54705688
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2157841698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.2157841698
Directory	/workspace/38.uart_rx_oversample/latest

Test location	/workspace/coverage/default/38.uart_rx_start_bit_filter.2643041932
Short name	T37
Test name
Test status
Simulation time	5060599537 ps
CPU time	2.93 seconds
Started	Apr 28 01:07:48 PM PDT 24
Finished	Apr 28 01:07:52 PM PDT 24
Peak memory	196440 kb
Host	smart-12599e4c-2df9-4149-aea7-adc54c14c6d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2643041932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.2643041932
Directory	/workspace/38.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/38.uart_smoke.4250767736
Short name	T533
Test name
Test status
Simulation time	5818424436 ps
CPU time	18.43 seconds
Started	Apr 28 01:07:43 PM PDT 24
Finished	Apr 28 01:08:02 PM PDT 24
Peak memory	199712 kb
Host	smart-29e50e0c-d86a-4676-a622-7b1cd23ca09f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4250767736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.4250767736
Directory	/workspace/38.uart_smoke/latest

Test location	/workspace/coverage/default/38.uart_stress_all.2282598751
Short name	T640
Test name
Test status
Simulation time	112109811204 ps
CPU time	161.78 seconds
Started	Apr 28 01:07:56 PM PDT 24
Finished	Apr 28 01:10:39 PM PDT 24
Peak memory	200556 kb
Host	smart-016fc49e-732f-42ce-8488-ee5225979114
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282598751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.2282598751
Directory	/workspace/38.uart_stress_all/latest

Test location	/workspace/coverage/default/38.uart_stress_all_with_rand_reset.843918966
Short name	T866
Test name
Test status
Simulation time	198962206223 ps
CPU time	715.49 seconds
Started	Apr 28 01:07:53 PM PDT 24
Finished	Apr 28 01:19:49 PM PDT 24
Peak memory	216324 kb
Host	smart-ae26d152-d791-4ba7-b3b5-c95d3c791c68
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843918966 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.843918966
Directory	/workspace/38.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/38.uart_tx_ovrd.3127048214
Short name	T1135
Test name
Test status
Simulation time	989915096 ps
CPU time	1.08 seconds
Started	Apr 28 01:07:47 PM PDT 24
Finished	Apr 28 01:07:48 PM PDT 24
Peak memory	197264 kb
Host	smart-4df0bc87-6cf3-40ec-8939-6adc63e150e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3127048214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.3127048214
Directory	/workspace/38.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/38.uart_tx_rx.2699914597
Short name	T862
Test name
Test status
Simulation time	36670821361 ps
CPU time	16.41 seconds
Started	Apr 28 01:07:48 PM PDT 24
Finished	Apr 28 01:08:05 PM PDT 24
Peak memory	200380 kb
Host	smart-bbb76e76-0e48-4cb9-bc81-29adb38c88bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2699914597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.2699914597
Directory	/workspace/38.uart_tx_rx/latest

Test location	/workspace/coverage/default/39.uart_alert_test.1010268227
Short name	T1128
Test name
Test status
Simulation time	142228684 ps
CPU time	0.53 seconds
Started	Apr 28 01:07:56 PM PDT 24
Finished	Apr 28 01:07:58 PM PDT 24
Peak memory	195204 kb
Host	smart-1180cd17-76f3-4fae-9075-bfed5ea9ddfe
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010268227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.1010268227
Directory	/workspace/39.uart_alert_test/latest

Test location	/workspace/coverage/default/39.uart_fifo_full.2894506507
Short name	T251
Test name
Test status
Simulation time	49297587760 ps
CPU time	23.22 seconds
Started	Apr 28 01:07:52 PM PDT 24
Finished	Apr 28 01:08:16 PM PDT 24
Peak memory	200432 kb
Host	smart-ec8c77cf-09a1-4891-a28d-135aeb99768b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2894506507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.2894506507
Directory	/workspace/39.uart_fifo_full/latest

Test location	/workspace/coverage/default/39.uart_fifo_overflow.1683009067
Short name	T594
Test name
Test status
Simulation time	54493315557 ps
CPU time	25.7 seconds
Started	Apr 28 01:07:53 PM PDT 24
Finished	Apr 28 01:08:19 PM PDT 24
Peak memory	200028 kb
Host	smart-b5fd0b95-f7a6-4fdb-8fcf-f8e595b34d04
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1683009067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.1683009067
Directory	/workspace/39.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/39.uart_fifo_reset.3683213520
Short name	T214
Test name
Test status
Simulation time	236744980367 ps
CPU time	580.45 seconds
Started	Apr 28 01:07:52 PM PDT 24
Finished	Apr 28 01:17:33 PM PDT 24
Peak memory	200464 kb
Host	smart-73e33701-a0b2-45c6-8c6e-f9e8676f6895
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3683213520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.3683213520
Directory	/workspace/39.uart_fifo_reset/latest

Test location	/workspace/coverage/default/39.uart_intr.1390337618
Short name	T471
Test name
Test status
Simulation time	20318230393 ps
CPU time	9.76 seconds
Started	Apr 28 01:07:52 PM PDT 24
Finished	Apr 28 01:08:03 PM PDT 24
Peak memory	199228 kb
Host	smart-7788b633-ab0d-4699-8cd7-974731564e2b
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390337618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.1390337618
Directory	/workspace/39.uart_intr/latest

Test location	/workspace/coverage/default/39.uart_long_xfer_wo_dly.775471746
Short name	T919
Test name
Test status
Simulation time	310607374109 ps
CPU time	76.48 seconds
Started	Apr 28 01:07:57 PM PDT 24
Finished	Apr 28 01:09:14 PM PDT 24
Peak memory	200376 kb
Host	smart-1e88e235-9b46-4648-bbb7-c2a323fa3e6e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=775471746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.775471746
Directory	/workspace/39.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/39.uart_loopback.2747767201
Short name	T1085
Test name
Test status
Simulation time	7778499085 ps
CPU time	12.19 seconds
Started	Apr 28 01:07:59 PM PDT 24
Finished	Apr 28 01:08:12 PM PDT 24
Peak memory	199544 kb
Host	smart-bd2c68b3-bc73-47ab-91a6-bf13c4336519
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2747767201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.2747767201
Directory	/workspace/39.uart_loopback/latest

Test location	/workspace/coverage/default/39.uart_noise_filter.3488761869
Short name	T880
Test name
Test status
Simulation time	20922565807 ps
CPU time	18.46 seconds
Started	Apr 28 01:07:56 PM PDT 24
Finished	Apr 28 01:08:15 PM PDT 24
Peak memory	200368 kb
Host	smart-9e13d3be-8e1c-4fff-9478-3a6271af8a24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3488761869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.3488761869
Directory	/workspace/39.uart_noise_filter/latest

Test location	/workspace/coverage/default/39.uart_perf.3682893569
Short name	T960
Test name
Test status
Simulation time	4252438318 ps
CPU time	241.81 seconds
Started	Apr 28 01:08:04 PM PDT 24
Finished	Apr 28 01:12:07 PM PDT 24
Peak memory	200392 kb
Host	smart-62cb294b-6730-4ac3-afd7-c3dbf155861c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3682893569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.3682893569
Directory	/workspace/39.uart_perf/latest

Test location	/workspace/coverage/default/39.uart_rx_oversample.2257621688
Short name	T540
Test name
Test status
Simulation time	5037893354 ps
CPU time	40.57 seconds
Started	Apr 28 01:07:56 PM PDT 24
Finished	Apr 28 01:08:37 PM PDT 24
Peak memory	199184 kb
Host	smart-a0ff7541-03a0-4638-82c5-49f1f08f0428
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2257621688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.2257621688
Directory	/workspace/39.uart_rx_oversample/latest

Test location	/workspace/coverage/default/39.uart_rx_parity_err.700248885
Short name	T150
Test name
Test status
Simulation time	76802553991 ps
CPU time	207.61 seconds
Started	Apr 28 01:07:58 PM PDT 24
Finished	Apr 28 01:11:26 PM PDT 24
Peak memory	200276 kb
Host	smart-5112e12a-f788-4b0d-b0ad-afb586ca4e9d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=700248885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.700248885
Directory	/workspace/39.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/39.uart_rx_start_bit_filter.2763555572
Short name	T664
Test name
Test status
Simulation time	4102982424 ps
CPU time	4.18 seconds
Started	Apr 28 01:07:57 PM PDT 24
Finished	Apr 28 01:08:02 PM PDT 24
Peak memory	196592 kb
Host	smart-6734b6d7-a926-4d98-813e-4fdf255f9677
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2763555572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.2763555572
Directory	/workspace/39.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/39.uart_smoke.4197833637
Short name	T842
Test name
Test status
Simulation time	281360795 ps
CPU time	1.21 seconds
Started	Apr 28 01:07:52 PM PDT 24
Finished	Apr 28 01:07:54 PM PDT 24
Peak memory	199028 kb
Host	smart-fa1bede4-4d98-4878-992f-202e295d2132
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4197833637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.4197833637
Directory	/workspace/39.uart_smoke/latest

Test location	/workspace/coverage/default/39.uart_stress_all_with_rand_reset.2581106066
Short name	T635
Test name
Test status
Simulation time	93177718121 ps
CPU time	487.31 seconds
Started	Apr 28 01:07:57 PM PDT 24
Finished	Apr 28 01:16:05 PM PDT 24
Peak memory	216820 kb
Host	smart-70b9a193-579e-471d-9f08-4fff43fafd91
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581106066 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.2581106066
Directory	/workspace/39.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/39.uart_tx_ovrd.4193359479
Short name	T17
Test name
Test status
Simulation time	952108812 ps
CPU time	4.8 seconds
Started	Apr 28 01:07:58 PM PDT 24
Finished	Apr 28 01:08:03 PM PDT 24
Peak memory	198712 kb
Host	smart-7268b2eb-66a7-4877-b693-78c7e7b6941a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4193359479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.4193359479
Directory	/workspace/39.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/39.uart_tx_rx.1425919846
Short name	T936
Test name
Test status
Simulation time	56098583866 ps
CPU time	27.59 seconds
Started	Apr 28 01:07:52 PM PDT 24
Finished	Apr 28 01:08:20 PM PDT 24
Peak memory	200328 kb
Host	smart-2791ce71-752d-4b5b-8b12-d75e270d8609
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1425919846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1425919846
Directory	/workspace/39.uart_tx_rx/latest

Test location	/workspace/coverage/default/4.uart_alert_test.3407056381
Short name	T610
Test name
Test status
Simulation time	12844558 ps
CPU time	0.61 seconds
Started	Apr 28 01:05:22 PM PDT 24
Finished	Apr 28 01:05:23 PM PDT 24
Peak memory	195728 kb
Host	smart-20859882-8f7b-43c3-b2b3-1145901ba999
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407056381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.3407056381
Directory	/workspace/4.uart_alert_test/latest

Test location	/workspace/coverage/default/4.uart_fifo_full.4208943628
Short name	T130
Test name
Test status
Simulation time	101081040767 ps
CPU time	25.32 seconds
Started	Apr 28 01:05:17 PM PDT 24
Finished	Apr 28 01:05:43 PM PDT 24
Peak memory	200432 kb
Host	smart-4b98c225-dccf-4704-b2b8-326ac46f8e6a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4208943628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.4208943628
Directory	/workspace/4.uart_fifo_full/latest

Test location	/workspace/coverage/default/4.uart_fifo_overflow.1477761845
Short name	T566
Test name
Test status
Simulation time	22510823398 ps
CPU time	23.2 seconds
Started	Apr 28 01:05:16 PM PDT 24
Finished	Apr 28 01:05:40 PM PDT 24
Peak memory	200284 kb
Host	smart-9feb2fa3-3439-428a-b21b-fb4bd9a86092
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1477761845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1477761845
Directory	/workspace/4.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/4.uart_fifo_reset.442091931
Short name	T228
Test name
Test status
Simulation time	93110182424 ps
CPU time	23.85 seconds
Started	Apr 28 01:05:18 PM PDT 24
Finished	Apr 28 01:05:42 PM PDT 24
Peak memory	200348 kb
Host	smart-45032109-0905-4f9a-87d6-c77dd9348c81
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=442091931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.442091931
Directory	/workspace/4.uart_fifo_reset/latest

Test location	/workspace/coverage/default/4.uart_intr.2558712684
Short name	T530
Test name
Test status
Simulation time	39997387563 ps
CPU time	30.66 seconds
Started	Apr 28 01:05:17 PM PDT 24
Finished	Apr 28 01:05:49 PM PDT 24
Peak memory	199744 kb
Host	smart-5aa5e33a-28dc-454b-9ccf-64806caa7e12
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558712684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.2558712684
Directory	/workspace/4.uart_intr/latest

Test location	/workspace/coverage/default/4.uart_long_xfer_wo_dly.2523852125
Short name	T387
Test name
Test status
Simulation time	49785991408 ps
CPU time	180.81 seconds
Started	Apr 28 01:05:24 PM PDT 24
Finished	Apr 28 01:08:25 PM PDT 24
Peak memory	200360 kb
Host	smart-9d80fea6-a572-4170-bd78-22070c3ace2c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2523852125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.2523852125
Directory	/workspace/4.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/4.uart_loopback.1082209741
Short name	T1112
Test name
Test status
Simulation time	506181379 ps
CPU time	1.12 seconds
Started	Apr 28 01:05:17 PM PDT 24
Finished	Apr 28 01:05:19 PM PDT 24
Peak memory	196028 kb
Host	smart-3680cf9a-d5ca-413c-8006-9a0cbb3b91cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1082209741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.1082209741
Directory	/workspace/4.uart_loopback/latest

Test location	/workspace/coverage/default/4.uart_noise_filter.3480390914
Short name	T982
Test name
Test status
Simulation time	53039215033 ps
CPU time	51.77 seconds
Started	Apr 28 01:05:18 PM PDT 24
Finished	Apr 28 01:06:10 PM PDT 24
Peak memory	200644 kb
Host	smart-fc110985-9617-4ca2-a772-22bdb66588bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3480390914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.3480390914
Directory	/workspace/4.uart_noise_filter/latest

Test location	/workspace/coverage/default/4.uart_perf.1284328555
Short name	T1051
Test name
Test status
Simulation time	5814965529 ps
CPU time	169 seconds
Started	Apr 28 01:05:19 PM PDT 24
Finished	Apr 28 01:08:08 PM PDT 24
Peak memory	200388 kb
Host	smart-208d14da-fb91-4171-85c3-10eaca2f9d74
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1284328555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.1284328555
Directory	/workspace/4.uart_perf/latest

Test location	/workspace/coverage/default/4.uart_rx_oversample.2169316438
Short name	T120
Test name
Test status
Simulation time	1334960064 ps
CPU time	0.67 seconds
Started	Apr 28 01:05:17 PM PDT 24
Finished	Apr 28 01:05:18 PM PDT 24
Peak memory	196112 kb
Host	smart-b2bc2147-540b-43f7-98fe-4941c0134b39
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2169316438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.2169316438
Directory	/workspace/4.uart_rx_oversample/latest

Test location	/workspace/coverage/default/4.uart_rx_parity_err.3642985483
Short name	T390
Test name
Test status
Simulation time	52330319235 ps
CPU time	84.67 seconds
Started	Apr 28 01:05:17 PM PDT 24
Finished	Apr 28 01:06:42 PM PDT 24
Peak memory	200268 kb
Host	smart-8a22f7f5-cf5b-459d-820d-1fe598350f84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3642985483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.3642985483
Directory	/workspace/4.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/4.uart_rx_start_bit_filter.2585997059
Short name	T413
Test name
Test status
Simulation time	34982793273 ps
CPU time	8.66 seconds
Started	Apr 28 01:05:16 PM PDT 24
Finished	Apr 28 01:05:25 PM PDT 24
Peak memory	196608 kb
Host	smart-2f66fb89-9b73-4ac4-b231-d75c58d0a750
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2585997059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.2585997059
Directory	/workspace/4.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/4.uart_sec_cm.4019588697
Short name	T26
Test name
Test status
Simulation time	61468128 ps
CPU time	0.85 seconds
Started	Apr 28 01:05:18 PM PDT 24
Finished	Apr 28 01:05:19 PM PDT 24
Peak memory	218464 kb
Host	smart-f5ca2fa1-030d-4497-a8f5-b3a7e7f615b6
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019588697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.4019588697
Directory	/workspace/4.uart_sec_cm/latest

Test location	/workspace/coverage/default/4.uart_smoke.2891243604
Short name	T1079
Test name
Test status
Simulation time	628328269 ps
CPU time	3.61 seconds
Started	Apr 28 01:05:17 PM PDT 24
Finished	Apr 28 01:05:21 PM PDT 24
Peak memory	198740 kb
Host	smart-1c229bef-86f8-4de3-ad9c-41643f5cbcf8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2891243604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.2891243604
Directory	/workspace/4.uart_smoke/latest

Test location	/workspace/coverage/default/4.uart_stress_all.4147213289
Short name	T123
Test name
Test status
Simulation time	7554633652 ps
CPU time	1.59 seconds
Started	Apr 28 01:05:16 PM PDT 24
Finished	Apr 28 01:05:18 PM PDT 24
Peak memory	199256 kb
Host	smart-243cd1c9-588c-4c06-8de9-3d9699220efd
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147213289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.4147213289
Directory	/workspace/4.uart_stress_all/latest

Test location	/workspace/coverage/default/4.uart_stress_all_with_rand_reset.4188005907
Short name	T1097
Test name
Test status
Simulation time	82802344095 ps
CPU time	761.14 seconds
Started	Apr 28 01:05:22 PM PDT 24
Finished	Apr 28 01:18:04 PM PDT 24
Peak memory	225204 kb
Host	smart-8128112f-9bd8-45e0-832a-b0e1325d88c7
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188005907 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.4188005907
Directory	/workspace/4.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/4.uart_tx_ovrd.1063264573
Short name	T753
Test name
Test status
Simulation time	1475672640 ps
CPU time	1.75 seconds
Started	Apr 28 01:05:17 PM PDT 24
Finished	Apr 28 01:05:20 PM PDT 24
Peak memory	199816 kb
Host	smart-ab102735-a81c-4c1f-a24a-cae74fbb6c2a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1063264573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.1063264573
Directory	/workspace/4.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/4.uart_tx_rx.3007342527
Short name	T1088
Test name
Test status
Simulation time	8800978456 ps
CPU time	13.85 seconds
Started	Apr 28 01:05:24 PM PDT 24
Finished	Apr 28 01:05:39 PM PDT 24
Peak memory	197860 kb
Host	smart-592f76fd-01e6-47c5-a28f-ae47bb7e70a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3007342527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3007342527
Directory	/workspace/4.uart_tx_rx/latest

Test location	/workspace/coverage/default/40.uart_alert_test.1055041007
Short name	T649
Test name
Test status
Simulation time	30818595 ps
CPU time	0.54 seconds
Started	Apr 28 01:08:06 PM PDT 24
Finished	Apr 28 01:08:07 PM PDT 24
Peak memory	195196 kb
Host	smart-b007cc2b-cb1d-4c8b-8104-a42de5b248a6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055041007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.1055041007
Directory	/workspace/40.uart_alert_test/latest

Test location	/workspace/coverage/default/40.uart_fifo_full.3378984141
Short name	T899
Test name
Test status
Simulation time	108060964406 ps
CPU time	26.28 seconds
Started	Apr 28 01:08:01 PM PDT 24
Finished	Apr 28 01:08:27 PM PDT 24
Peak memory	200376 kb
Host	smart-75f46c8e-6dd7-43d3-aef4-69bf39669028
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3378984141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.3378984141
Directory	/workspace/40.uart_fifo_full/latest

Test location	/workspace/coverage/default/40.uart_fifo_overflow.412588987
Short name	T69
Test name
Test status
Simulation time	52694172238 ps
CPU time	92.02 seconds
Started	Apr 28 01:08:08 PM PDT 24
Finished	Apr 28 01:09:41 PM PDT 24
Peak memory	200336 kb
Host	smart-3044d121-02d9-4a19-9231-70e56f7894ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=412588987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.412588987
Directory	/workspace/40.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/40.uart_fifo_reset.3563229321
Short name	T188
Test name
Test status
Simulation time	93833260836 ps
CPU time	84.56 seconds
Started	Apr 28 01:08:09 PM PDT 24
Finished	Apr 28 01:09:34 PM PDT 24
Peak memory	200284 kb
Host	smart-a3ba2add-3312-4866-ac46-e459eecf1093
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3563229321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.3563229321
Directory	/workspace/40.uart_fifo_reset/latest

Test location	/workspace/coverage/default/40.uart_intr.2265538054
Short name	T523
Test name
Test status
Simulation time	156678679582 ps
CPU time	267.73 seconds
Started	Apr 28 01:08:08 PM PDT 24
Finished	Apr 28 01:12:36 PM PDT 24
Peak memory	196440 kb
Host	smart-5a44ba6c-3d2c-46c9-8506-a9efcd2ffc63
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265538054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.2265538054
Directory	/workspace/40.uart_intr/latest

Test location	/workspace/coverage/default/40.uart_long_xfer_wo_dly.3013281623
Short name	T804
Test name
Test status
Simulation time	89748041068 ps
CPU time	125.02 seconds
Started	Apr 28 01:08:01 PM PDT 24
Finished	Apr 28 01:10:07 PM PDT 24
Peak memory	200356 kb
Host	smart-fd5ac9fb-10aa-4742-a328-72276cfe57af
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3013281623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.3013281623
Directory	/workspace/40.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/40.uart_loopback.1760107389
Short name	T1114
Test name
Test status
Simulation time	180088571 ps
CPU time	0.77 seconds
Started	Apr 28 01:08:08 PM PDT 24
Finished	Apr 28 01:08:10 PM PDT 24
Peak memory	197348 kb
Host	smart-e937b175-4d80-4ac1-bbcb-af052a830222
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1760107389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.1760107389
Directory	/workspace/40.uart_loopback/latest

Test location	/workspace/coverage/default/40.uart_noise_filter.1435602011
Short name	T416
Test name
Test status
Simulation time	27406164679 ps
CPU time	21.84 seconds
Started	Apr 28 01:07:57 PM PDT 24
Finished	Apr 28 01:08:19 PM PDT 24
Peak memory	199112 kb
Host	smart-b34d1fd4-61c1-4e06-b199-9b5090e5b5af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1435602011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.1435602011
Directory	/workspace/40.uart_noise_filter/latest

Test location	/workspace/coverage/default/40.uart_perf.2791727430
Short name	T612
Test name
Test status
Simulation time	7157419137 ps
CPU time	328.58 seconds
Started	Apr 28 01:08:09 PM PDT 24
Finished	Apr 28 01:13:38 PM PDT 24
Peak memory	200336 kb
Host	smart-d5a4720d-a914-4524-8447-2484e654a21e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2791727430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.2791727430
Directory	/workspace/40.uart_perf/latest

Test location	/workspace/coverage/default/40.uart_rx_oversample.3446685703
Short name	T609
Test name
Test status
Simulation time	5650424814 ps
CPU time	8.03 seconds
Started	Apr 28 01:08:04 PM PDT 24
Finished	Apr 28 01:08:13 PM PDT 24
Peak memory	199640 kb
Host	smart-3e1e24ac-d435-4a4c-944e-d6a24ad47cea
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3446685703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.3446685703
Directory	/workspace/40.uart_rx_oversample/latest

Test location	/workspace/coverage/default/40.uart_rx_parity_err.3206978879
Short name	T1021
Test name
Test status
Simulation time	111905851917 ps
CPU time	60.37 seconds
Started	Apr 28 01:08:08 PM PDT 24
Finished	Apr 28 01:09:09 PM PDT 24
Peak memory	200040 kb
Host	smart-ed232eb5-28dc-4c17-98ad-f8eebfbe3dbb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3206978879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.3206978879
Directory	/workspace/40.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/40.uart_rx_start_bit_filter.2530501873
Short name	T760
Test name
Test status
Simulation time	4365152782 ps
CPU time	2.43 seconds
Started	Apr 28 01:07:57 PM PDT 24
Finished	Apr 28 01:08:00 PM PDT 24
Peak memory	196336 kb
Host	smart-a1217fe3-4d42-41c1-ac9f-d27d03c2a960
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2530501873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.2530501873
Directory	/workspace/40.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/40.uart_smoke.1231366436
Short name	T1004
Test name
Test status
Simulation time	908294177 ps
CPU time	2.03 seconds
Started	Apr 28 01:07:58 PM PDT 24
Finished	Apr 28 01:08:01 PM PDT 24
Peak memory	200260 kb
Host	smart-66b07041-807b-4542-8245-e11e44060b1f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1231366436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.1231366436
Directory	/workspace/40.uart_smoke/latest

Test location	/workspace/coverage/default/40.uart_stress_all.549235086
Short name	T122
Test name
Test status
Simulation time	365435430334 ps
CPU time	463.14 seconds
Started	Apr 28 01:08:14 PM PDT 24
Finished	Apr 28 01:15:58 PM PDT 24
Peak memory	200372 kb
Host	smart-7423943a-2faa-46af-962d-e985d3b8e1b6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549235086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.549235086
Directory	/workspace/40.uart_stress_all/latest

Test location	/workspace/coverage/default/40.uart_stress_all_with_rand_reset.106723445
Short name	T1121
Test name
Test status
Simulation time	44495031274 ps
CPU time	729.84 seconds
Started	Apr 28 01:08:09 PM PDT 24
Finished	Apr 28 01:20:20 PM PDT 24
Peak memory	216856 kb
Host	smart-3e458803-ba7f-4b2c-89b7-6de528ce3b98
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106723445 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.106723445
Directory	/workspace/40.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/40.uart_tx_ovrd.91034870
Short name	T294
Test name
Test status
Simulation time	1522551610 ps
CPU time	2.29 seconds
Started	Apr 28 01:08:09 PM PDT 24
Finished	Apr 28 01:08:12 PM PDT 24
Peak memory	199116 kb
Host	smart-c4869d76-b65e-49c5-97bb-5746eae874bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=91034870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.91034870
Directory	/workspace/40.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/40.uart_tx_rx.1775371933
Short name	T677
Test name
Test status
Simulation time	99600930220 ps
CPU time	57.37 seconds
Started	Apr 28 01:08:01 PM PDT 24
Finished	Apr 28 01:08:58 PM PDT 24
Peak memory	200424 kb
Host	smart-93d03b10-1017-4dd9-b3da-c9c9f968016c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1775371933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.1775371933
Directory	/workspace/40.uart_tx_rx/latest

Test location	/workspace/coverage/default/41.uart_alert_test.4127329038
Short name	T374
Test name
Test status
Simulation time	165555666 ps
CPU time	0.56 seconds
Started	Apr 28 01:08:02 PM PDT 24
Finished	Apr 28 01:08:03 PM PDT 24
Peak memory	195632 kb
Host	smart-5630794d-5f91-4523-92b6-d1a0a23ee48c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127329038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.4127329038
Directory	/workspace/41.uart_alert_test/latest

Test location	/workspace/coverage/default/41.uart_fifo_full.3108670460
Short name	T500
Test name
Test status
Simulation time	11755767807 ps
CPU time	18.35 seconds
Started	Apr 28 01:08:02 PM PDT 24
Finished	Apr 28 01:08:21 PM PDT 24
Peak memory	200436 kb
Host	smart-264a5e7d-57fb-476c-b91b-58c1e498cba6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3108670460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3108670460
Directory	/workspace/41.uart_fifo_full/latest

Test location	/workspace/coverage/default/41.uart_fifo_overflow.1906930534
Short name	T557
Test name
Test status
Simulation time	149383595402 ps
CPU time	237.38 seconds
Started	Apr 28 01:08:02 PM PDT 24
Finished	Apr 28 01:12:00 PM PDT 24
Peak memory	200348 kb
Host	smart-948f9d88-ba26-4d24-b71e-4590ae1f1c7a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1906930534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.1906930534
Directory	/workspace/41.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/41.uart_intr.537409916
Short name	T371
Test name
Test status
Simulation time	30120833765 ps
CPU time	51.72 seconds
Started	Apr 28 01:08:01 PM PDT 24
Finished	Apr 28 01:08:53 PM PDT 24
Peak memory	200436 kb
Host	smart-66981ccf-b1a7-4700-8b70-592cd27db8b8
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537409916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.537409916
Directory	/workspace/41.uart_intr/latest

Test location	/workspace/coverage/default/41.uart_loopback.3920145941
Short name	T334
Test name
Test status
Simulation time	8485814423 ps
CPU time	16.8 seconds
Started	Apr 28 01:08:04 PM PDT 24
Finished	Apr 28 01:08:21 PM PDT 24
Peak memory	200372 kb
Host	smart-4ed9eacb-78f0-46c8-90c3-e95b8b5ed9f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3920145941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.3920145941
Directory	/workspace/41.uart_loopback/latest

Test location	/workspace/coverage/default/41.uart_noise_filter.2511781231
Short name	T310
Test name
Test status
Simulation time	95338682054 ps
CPU time	17.63 seconds
Started	Apr 28 01:08:02 PM PDT 24
Finished	Apr 28 01:08:20 PM PDT 24
Peak memory	200292 kb
Host	smart-5b724dd8-d842-4607-a38f-e503d392f0a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2511781231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.2511781231
Directory	/workspace/41.uart_noise_filter/latest

Test location	/workspace/coverage/default/41.uart_perf.2686877049
Short name	T1014
Test name
Test status
Simulation time	9429981014 ps
CPU time	267.25 seconds
Started	Apr 28 01:08:02 PM PDT 24
Finished	Apr 28 01:12:30 PM PDT 24
Peak memory	200224 kb
Host	smart-ee776f17-4f20-4069-8fc0-bb40480013a3
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2686877049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.2686877049
Directory	/workspace/41.uart_perf/latest

Test location	/workspace/coverage/default/41.uart_rx_oversample.3361866904
Short name	T592
Test name
Test status
Simulation time	3368271049 ps
CPU time	6.81 seconds
Started	Apr 28 01:08:06 PM PDT 24
Finished	Apr 28 01:08:13 PM PDT 24
Peak memory	199628 kb
Host	smart-2c014507-0087-4f26-8c2c-975264bc078f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3361866904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.3361866904
Directory	/workspace/41.uart_rx_oversample/latest

Test location	/workspace/coverage/default/41.uart_rx_parity_err.1722560953
Short name	T317
Test name
Test status
Simulation time	9334386107 ps
CPU time	8.83 seconds
Started	Apr 28 01:08:02 PM PDT 24
Finished	Apr 28 01:08:12 PM PDT 24
Peak memory	198380 kb
Host	smart-596a0afc-e357-423f-9f86-e3e3dda0c538
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1722560953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.1722560953
Directory	/workspace/41.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/41.uart_rx_start_bit_filter.2162802375
Short name	T1089
Test name
Test status
Simulation time	2588059474 ps
CPU time	1.65 seconds
Started	Apr 28 01:08:02 PM PDT 24
Finished	Apr 28 01:08:04 PM PDT 24
Peak memory	196068 kb
Host	smart-19618b34-ca27-40f2-963a-8a0e459e6eaa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2162802375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.2162802375
Directory	/workspace/41.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/41.uart_smoke.2021277212
Short name	T52
Test name
Test status
Simulation time	701856620 ps
CPU time	1.55 seconds
Started	Apr 28 01:08:04 PM PDT 24
Finished	Apr 28 01:08:06 PM PDT 24
Peak memory	198508 kb
Host	smart-721728f8-29b8-475c-a8a6-d0d3da66beed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2021277212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2021277212
Directory	/workspace/41.uart_smoke/latest

Test location	/workspace/coverage/default/41.uart_stress_all.4012540959
Short name	T63
Test name
Test status
Simulation time	137252762268 ps
CPU time	556.64 seconds
Started	Apr 28 01:08:03 PM PDT 24
Finished	Apr 28 01:17:21 PM PDT 24
Peak memory	200236 kb
Host	smart-df55cd5b-64a4-49e7-84d0-86326df356b3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012540959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.4012540959
Directory	/workspace/41.uart_stress_all/latest

Test location	/workspace/coverage/default/41.uart_tx_ovrd.3484172996
Short name	T545
Test name
Test status
Simulation time	1724414137 ps
CPU time	2.01 seconds
Started	Apr 28 01:08:03 PM PDT 24
Finished	Apr 28 01:08:06 PM PDT 24
Peak memory	198988 kb
Host	smart-f6ff58d7-499d-4600-ad0d-d478322ecc8f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3484172996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.3484172996
Directory	/workspace/41.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/41.uart_tx_rx.3961377076
Short name	T662
Test name
Test status
Simulation time	86918263289 ps
CPU time	134.1 seconds
Started	Apr 28 01:08:03 PM PDT 24
Finished	Apr 28 01:10:17 PM PDT 24
Peak memory	200428 kb
Host	smart-218d7504-93f1-4f4b-85f8-3beb75175d11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3961377076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.3961377076
Directory	/workspace/41.uart_tx_rx/latest

Test location	/workspace/coverage/default/42.uart_alert_test.2685174975
Short name	T761
Test name
Test status
Simulation time	10931526 ps
CPU time	0.54 seconds
Started	Apr 28 01:08:08 PM PDT 24
Finished	Apr 28 01:08:09 PM PDT 24
Peak memory	195648 kb
Host	smart-e47a2788-d78c-4910-a53b-abbfaa858df6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685174975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.2685174975
Directory	/workspace/42.uart_alert_test/latest

Test location	/workspace/coverage/default/42.uart_fifo_full.4096635262
Short name	T977
Test name
Test status
Simulation time	33992711835 ps
CPU time	26.16 seconds
Started	Apr 28 01:08:07 PM PDT 24
Finished	Apr 28 01:08:34 PM PDT 24
Peak memory	200400 kb
Host	smart-04cab74e-d41e-43cd-960f-d36c402185e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4096635262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.4096635262
Directory	/workspace/42.uart_fifo_full/latest

Test location	/workspace/coverage/default/42.uart_fifo_overflow.1599549141
Short name	T788
Test name
Test status
Simulation time	101399873793 ps
CPU time	40.79 seconds
Started	Apr 28 01:08:01 PM PDT 24
Finished	Apr 28 01:08:42 PM PDT 24
Peak memory	200360 kb
Host	smart-8f269128-4a47-4b67-975b-c0a1e3f0e979
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1599549141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.1599549141
Directory	/workspace/42.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/42.uart_fifo_reset.1043762929
Short name	T1050
Test name
Test status
Simulation time	171747910905 ps
CPU time	179.91 seconds
Started	Apr 28 01:08:07 PM PDT 24
Finished	Apr 28 01:11:08 PM PDT 24
Peak memory	200376 kb
Host	smart-59ed0c10-e702-46ad-b40a-a2fe72c77242
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1043762929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.1043762929
Directory	/workspace/42.uart_fifo_reset/latest

Test location	/workspace/coverage/default/42.uart_intr.3799513741
Short name	T431
Test name
Test status
Simulation time	43256812330 ps
CPU time	72.45 seconds
Started	Apr 28 01:08:03 PM PDT 24
Finished	Apr 28 01:09:17 PM PDT 24
Peak memory	200340 kb
Host	smart-5fe652eb-b246-457e-81ed-d5fd1d7486fa
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799513741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.3799513741
Directory	/workspace/42.uart_intr/latest

Test location	/workspace/coverage/default/42.uart_long_xfer_wo_dly.2570313429
Short name	T256
Test name
Test status
Simulation time	127655435499 ps
CPU time	616.37 seconds
Started	Apr 28 01:08:08 PM PDT 24
Finished	Apr 28 01:18:25 PM PDT 24
Peak memory	200308 kb
Host	smart-279fd3ea-31a9-4ef4-b76a-7dc705486eb3
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2570313429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.2570313429
Directory	/workspace/42.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/42.uart_loopback.644053727
Short name	T774
Test name
Test status
Simulation time	7710658937 ps
CPU time	12.8 seconds
Started	Apr 28 01:08:08 PM PDT 24
Finished	Apr 28 01:08:22 PM PDT 24
Peak memory	199828 kb
Host	smart-f56de90b-1e8c-4d2c-a1f4-77e99bb79474
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=644053727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.644053727
Directory	/workspace/42.uart_loopback/latest

Test location	/workspace/coverage/default/42.uart_noise_filter.3230079652
Short name	T999
Test name
Test status
Simulation time	110959974296 ps
CPU time	54.7 seconds
Started	Apr 28 01:08:03 PM PDT 24
Finished	Apr 28 01:08:58 PM PDT 24
Peak memory	200624 kb
Host	smart-62d23646-bcca-4956-b276-b64c4787b132
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3230079652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.3230079652
Directory	/workspace/42.uart_noise_filter/latest

Test location	/workspace/coverage/default/42.uart_perf.3277457888
Short name	T997
Test name
Test status
Simulation time	24563171898 ps
CPU time	284.62 seconds
Started	Apr 28 01:08:13 PM PDT 24
Finished	Apr 28 01:12:58 PM PDT 24
Peak memory	200424 kb
Host	smart-b11db4e4-5e63-42f8-9407-450df2b8132c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3277457888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.3277457888
Directory	/workspace/42.uart_perf/latest

Test location	/workspace/coverage/default/42.uart_rx_oversample.195467021
Short name	T929
Test name
Test status
Simulation time	1444336634 ps
CPU time	0.77 seconds
Started	Apr 28 01:08:01 PM PDT 24
Finished	Apr 28 01:08:03 PM PDT 24
Peak memory	195884 kb
Host	smart-fe3fa8aa-eca8-4754-9e84-917f6cffc163
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=195467021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.195467021
Directory	/workspace/42.uart_rx_oversample/latest

Test location	/workspace/coverage/default/42.uart_rx_parity_err.2527962659
Short name	T700
Test name
Test status
Simulation time	157733561450 ps
CPU time	82.26 seconds
Started	Apr 28 01:08:07 PM PDT 24
Finished	Apr 28 01:09:30 PM PDT 24
Peak memory	200316 kb
Host	smart-db0d7b4a-0977-4e3f-b2af-303f8eef081d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2527962659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.2527962659
Directory	/workspace/42.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/42.uart_rx_start_bit_filter.191890225
Short name	T885
Test name
Test status
Simulation time	3667910626 ps
CPU time	2.07 seconds
Started	Apr 28 01:08:08 PM PDT 24
Finished	Apr 28 01:08:11 PM PDT 24
Peak memory	196464 kb
Host	smart-04b8c9e7-7157-4e13-be54-4551c2bf9632
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=191890225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.191890225
Directory	/workspace/42.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/42.uart_smoke.1370687363
Short name	T363
Test name
Test status
Simulation time	844715924 ps
CPU time	2.64 seconds
Started	Apr 28 01:08:06 PM PDT 24
Finished	Apr 28 01:08:09 PM PDT 24
Peak memory	198676 kb
Host	smart-8a20f1e9-fdef-4d40-b2a9-ff273e61a96a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1370687363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.1370687363
Directory	/workspace/42.uart_smoke/latest

Test location	/workspace/coverage/default/42.uart_stress_all.2260838873
Short name	T300
Test name
Test status
Simulation time	33562988425 ps
CPU time	21.35 seconds
Started	Apr 28 01:08:08 PM PDT 24
Finished	Apr 28 01:08:30 PM PDT 24
Peak memory	200428 kb
Host	smart-c04e4469-cf6b-4ebb-b0ae-78f223fa4335
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260838873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.2260838873
Directory	/workspace/42.uart_stress_all/latest

Test location	/workspace/coverage/default/42.uart_stress_all_with_rand_reset.2211928461
Short name	T116
Test name
Test status
Simulation time	75611049277 ps
CPU time	295.62 seconds
Started	Apr 28 01:08:07 PM PDT 24
Finished	Apr 28 01:13:03 PM PDT 24
Peak memory	216404 kb
Host	smart-e892dbde-d9bd-44ae-8711-c1da6dc95457
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211928461 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.2211928461
Directory	/workspace/42.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/42.uart_tx_ovrd.3213793203
Short name	T412
Test name
Test status
Simulation time	6287085912 ps
CPU time	20.18 seconds
Started	Apr 28 01:08:09 PM PDT 24
Finished	Apr 28 01:08:30 PM PDT 24
Peak memory	200276 kb
Host	smart-25227489-c1a5-48a3-bee9-ebf5265f7089
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3213793203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.3213793203
Directory	/workspace/42.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/42.uart_tx_rx.648558539
Short name	T714
Test name
Test status
Simulation time	10382257752 ps
CPU time	5.75 seconds
Started	Apr 28 01:08:04 PM PDT 24
Finished	Apr 28 01:08:11 PM PDT 24
Peak memory	200232 kb
Host	smart-e13754bb-3b3d-46bf-8bf3-fd232bd210e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=648558539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.648558539
Directory	/workspace/42.uart_tx_rx/latest

Test location	/workspace/coverage/default/43.uart_alert_test.13636904
Short name	T902
Test name
Test status
Simulation time	31547424 ps
CPU time	0.52 seconds
Started	Apr 28 01:08:18 PM PDT 24
Finished	Apr 28 01:08:19 PM PDT 24
Peak memory	195644 kb
Host	smart-47852305-526a-4bbc-aaff-99e5d0277518
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13636904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.13636904
Directory	/workspace/43.uart_alert_test/latest

Test location	/workspace/coverage/default/43.uart_fifo_full.542945413
Short name	T749
Test name
Test status
Simulation time	264048313165 ps
CPU time	44.99 seconds
Started	Apr 28 01:08:11 PM PDT 24
Finished	Apr 28 01:08:57 PM PDT 24
Peak memory	200436 kb
Host	smart-955043c8-85c8-4841-913a-70d52ca3b283
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=542945413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.542945413
Directory	/workspace/43.uart_fifo_full/latest

Test location	/workspace/coverage/default/43.uart_fifo_overflow.2048548580
Short name	T415
Test name
Test status
Simulation time	62692871870 ps
CPU time	53.75 seconds
Started	Apr 28 01:08:15 PM PDT 24
Finished	Apr 28 01:09:09 PM PDT 24
Peak memory	200380 kb
Host	smart-a1935c1d-64d3-4b9f-b5fa-af0b4d79167e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2048548580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.2048548580
Directory	/workspace/43.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/43.uart_fifo_reset.2353364425
Short name	T8
Test name
Test status
Simulation time	7577747457 ps
CPU time	19.28 seconds
Started	Apr 28 01:08:12 PM PDT 24
Finished	Apr 28 01:08:32 PM PDT 24
Peak memory	200404 kb
Host	smart-5a24d16c-9b56-46be-949c-951511c84d84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2353364425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.2353364425
Directory	/workspace/43.uart_fifo_reset/latest

Test location	/workspace/coverage/default/43.uart_intr.2827330408
Short name	T563
Test name
Test status
Simulation time	68594206509 ps
CPU time	28.49 seconds
Started	Apr 28 01:08:13 PM PDT 24
Finished	Apr 28 01:08:42 PM PDT 24
Peak memory	199888 kb
Host	smart-c3d4c974-932c-4687-bb34-4ec06d0e9a17
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827330408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.2827330408
Directory	/workspace/43.uart_intr/latest

Test location	/workspace/coverage/default/43.uart_long_xfer_wo_dly.1262377548
Short name	T1017
Test name
Test status
Simulation time	77394168341 ps
CPU time	280.61 seconds
Started	Apr 28 01:08:13 PM PDT 24
Finished	Apr 28 01:12:54 PM PDT 24
Peak memory	200352 kb
Host	smart-6babe025-898d-4fc9-8b35-c23abdd20876
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1262377548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.1262377548
Directory	/workspace/43.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/43.uart_loopback.2074923969
Short name	T342
Test name
Test status
Simulation time	3126380089 ps
CPU time	2.82 seconds
Started	Apr 28 01:08:14 PM PDT 24
Finished	Apr 28 01:08:18 PM PDT 24
Peak memory	198876 kb
Host	smart-15a50378-875e-44b3-b173-b2ed68ac13cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2074923969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.2074923969
Directory	/workspace/43.uart_loopback/latest

Test location	/workspace/coverage/default/43.uart_noise_filter.674451714
Short name	T558
Test name
Test status
Simulation time	482468100788 ps
CPU time	137.19 seconds
Started	Apr 28 01:08:16 PM PDT 24
Finished	Apr 28 01:10:34 PM PDT 24
Peak memory	200584 kb
Host	smart-431cba9c-c11f-4e69-939b-d23a4064d674
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=674451714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.674451714
Directory	/workspace/43.uart_noise_filter/latest

Test location	/workspace/coverage/default/43.uart_perf.4033729601
Short name	T1176
Test name
Test status
Simulation time	7844349480 ps
CPU time	82.96 seconds
Started	Apr 28 01:08:15 PM PDT 24
Finished	Apr 28 01:09:38 PM PDT 24
Peak memory	200380 kb
Host	smart-23371b51-ecd2-4c6d-ad6e-2013962c8c35
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4033729601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.4033729601
Directory	/workspace/43.uart_perf/latest

Test location	/workspace/coverage/default/43.uart_rx_oversample.2301614055
Short name	T1013
Test name
Test status
Simulation time	5401632211 ps
CPU time	12.49 seconds
Started	Apr 28 01:08:11 PM PDT 24
Finished	Apr 28 01:08:24 PM PDT 24
Peak memory	198532 kb
Host	smart-40dd4707-ce06-4cd5-818d-cc5f1d9335e9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2301614055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.2301614055
Directory	/workspace/43.uart_rx_oversample/latest

Test location	/workspace/coverage/default/43.uart_rx_parity_err.926307236
Short name	T1043
Test name
Test status
Simulation time	153487819370 ps
CPU time	117.53 seconds
Started	Apr 28 01:08:12 PM PDT 24
Finished	Apr 28 01:10:10 PM PDT 24
Peak memory	200260 kb
Host	smart-964a14f4-ccf1-4379-b0cc-1b31b7ba56c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=926307236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.926307236
Directory	/workspace/43.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/43.uart_rx_start_bit_filter.1286354908
Short name	T447
Test name
Test status
Simulation time	41132874967 ps
CPU time	65.4 seconds
Started	Apr 28 01:08:13 PM PDT 24
Finished	Apr 28 01:09:19 PM PDT 24
Peak memory	196696 kb
Host	smart-f3e4ace7-e630-4e09-817c-3afae076a0bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1286354908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.1286354908
Directory	/workspace/43.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/43.uart_smoke.590006121
Short name	T53
Test name
Test status
Simulation time	5449472625 ps
CPU time	11.53 seconds
Started	Apr 28 01:08:08 PM PDT 24
Finished	Apr 28 01:08:20 PM PDT 24
Peak memory	199576 kb
Host	smart-86f88103-a28d-455a-b765-b1483c5a6766
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=590006121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.590006121
Directory	/workspace/43.uart_smoke/latest

Test location	/workspace/coverage/default/43.uart_stress_all.960227265
Short name	T3
Test name
Test status
Simulation time	143502129535 ps
CPU time	302.93 seconds
Started	Apr 28 01:08:18 PM PDT 24
Finished	Apr 28 01:13:22 PM PDT 24
Peak memory	200204 kb
Host	smart-46efa81f-593d-4ca1-ba9d-2b709a545446
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960227265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.960227265
Directory	/workspace/43.uart_stress_all/latest

Test location	/workspace/coverage/default/43.uart_stress_all_with_rand_reset.2777835615
Short name	T492
Test name
Test status
Simulation time	28816394213 ps
CPU time	316.1 seconds
Started	Apr 28 01:08:11 PM PDT 24
Finished	Apr 28 01:13:28 PM PDT 24
Peak memory	216848 kb
Host	smart-8b0c822b-1d1e-408b-9615-870ff4ff4c1f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777835615 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.2777835615
Directory	/workspace/43.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/43.uart_tx_ovrd.4026352040
Short name	T399
Test name
Test status
Simulation time	5275889069 ps
CPU time	2.07 seconds
Started	Apr 28 01:08:13 PM PDT 24
Finished	Apr 28 01:08:16 PM PDT 24
Peak memory	199056 kb
Host	smart-5cba939a-48ef-4fbe-b340-fc85ab8899db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4026352040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.4026352040
Directory	/workspace/43.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/44.uart_alert_test.3524059489
Short name	T823
Test name
Test status
Simulation time	21678591 ps
CPU time	0.54 seconds
Started	Apr 28 01:08:28 PM PDT 24
Finished	Apr 28 01:08:29 PM PDT 24
Peak memory	195692 kb
Host	smart-3bc12ab8-0877-4d82-81d6-baef55997e48
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524059489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.3524059489
Directory	/workspace/44.uart_alert_test/latest

Test location	/workspace/coverage/default/44.uart_fifo_overflow.3718966785
Short name	T169
Test name
Test status
Simulation time	71633814690 ps
CPU time	25.78 seconds
Started	Apr 28 01:08:22 PM PDT 24
Finished	Apr 28 01:08:48 PM PDT 24
Peak memory	200424 kb
Host	smart-5a1dece4-bce9-4355-90da-1177accd0b7d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3718966785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3718966785
Directory	/workspace/44.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/44.uart_fifo_reset.1354206919
Short name	T1162
Test name
Test status
Simulation time	20893050391 ps
CPU time	22.45 seconds
Started	Apr 28 01:08:19 PM PDT 24
Finished	Apr 28 01:08:42 PM PDT 24
Peak memory	200364 kb
Host	smart-7d62377c-b5e8-4076-b4e4-ef1a656e86ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1354206919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.1354206919
Directory	/workspace/44.uart_fifo_reset/latest

Test location	/workspace/coverage/default/44.uart_intr.346385163
Short name	T1181
Test name
Test status
Simulation time	8191357140 ps
CPU time	15 seconds
Started	Apr 28 01:08:27 PM PDT 24
Finished	Apr 28 01:08:43 PM PDT 24
Peak memory	200384 kb
Host	smart-1654c87d-277f-4014-b635-2649444bbdce
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346385163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.346385163
Directory	/workspace/44.uart_intr/latest

Test location	/workspace/coverage/default/44.uart_long_xfer_wo_dly.2980167534
Short name	T1117
Test name
Test status
Simulation time	114847819156 ps
CPU time	246.56 seconds
Started	Apr 28 01:08:27 PM PDT 24
Finished	Apr 28 01:12:35 PM PDT 24
Peak memory	200404 kb
Host	smart-9da5642e-f3af-42fa-9c06-973620bfabb6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2980167534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.2980167534
Directory	/workspace/44.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/44.uart_loopback.231287932
Short name	T1066
Test name
Test status
Simulation time	6538004679 ps
CPU time	8.27 seconds
Started	Apr 28 01:08:22 PM PDT 24
Finished	Apr 28 01:08:31 PM PDT 24
Peak memory	200368 kb
Host	smart-39e20cc1-1bee-4624-bc36-094c1855da8d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=231287932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.231287932
Directory	/workspace/44.uart_loopback/latest

Test location	/workspace/coverage/default/44.uart_noise_filter.3107362239
Short name	T954
Test name
Test status
Simulation time	17964344572 ps
CPU time	32.19 seconds
Started	Apr 28 01:08:19 PM PDT 24
Finished	Apr 28 01:08:52 PM PDT 24
Peak memory	200544 kb
Host	smart-396a51e9-29cd-403e-8ffd-ed455ad4b4b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3107362239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.3107362239
Directory	/workspace/44.uart_noise_filter/latest

Test location	/workspace/coverage/default/44.uart_perf.465318072
Short name	T625
Test name
Test status
Simulation time	20987979090 ps
CPU time	570.9 seconds
Started	Apr 28 01:08:27 PM PDT 24
Finished	Apr 28 01:17:59 PM PDT 24
Peak memory	200448 kb
Host	smart-165a7190-f555-4001-919b-b15f87fa6d9d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=465318072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.465318072
Directory	/workspace/44.uart_perf/latest

Test location	/workspace/coverage/default/44.uart_rx_oversample.833590572
Short name	T661
Test name
Test status
Simulation time	5944845546 ps
CPU time	13.86 seconds
Started	Apr 28 01:08:29 PM PDT 24
Finished	Apr 28 01:08:44 PM PDT 24
Peak memory	198612 kb
Host	smart-ed9e8f3b-6bb5-41f3-81aa-4a3c3339737d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=833590572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.833590572
Directory	/workspace/44.uart_rx_oversample/latest

Test location	/workspace/coverage/default/44.uart_rx_parity_err.1306261725
Short name	T496
Test name
Test status
Simulation time	58819636405 ps
CPU time	96.05 seconds
Started	Apr 28 01:08:26 PM PDT 24
Finished	Apr 28 01:10:02 PM PDT 24
Peak memory	200204 kb
Host	smart-ff3d4576-0596-411b-b965-3f7dbd22e4b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1306261725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.1306261725
Directory	/workspace/44.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/44.uart_rx_start_bit_filter.1258084628
Short name	T45
Test name
Test status
Simulation time	3645398021 ps
CPU time	2.39 seconds
Started	Apr 28 01:08:26 PM PDT 24
Finished	Apr 28 01:08:29 PM PDT 24
Peak memory	196248 kb
Host	smart-a1c1fe6a-6d10-4a0e-a879-4810b585fc59
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1258084628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.1258084628
Directory	/workspace/44.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/44.uart_smoke.3419815147
Short name	T751
Test name
Test status
Simulation time	6274489289 ps
CPU time	12.61 seconds
Started	Apr 28 01:08:17 PM PDT 24
Finished	Apr 28 01:08:30 PM PDT 24
Peak memory	200228 kb
Host	smart-a49ca8e1-592f-470e-9d55-81c0f207b213
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3419815147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.3419815147
Directory	/workspace/44.uart_smoke/latest

Test location	/workspace/coverage/default/44.uart_stress_all.982245078
Short name	T180
Test name
Test status
Simulation time	766052534897 ps
CPU time	296.02 seconds
Started	Apr 28 01:08:33 PM PDT 24
Finished	Apr 28 01:13:29 PM PDT 24
Peak memory	200408 kb
Host	smart-3160aca0-44e4-42af-881f-bccdbfe14f1b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982245078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.982245078
Directory	/workspace/44.uart_stress_all/latest

Test location	/workspace/coverage/default/44.uart_stress_all_with_rand_reset.640381641
Short name	T1102
Test name
Test status
Simulation time	75505619724 ps
CPU time	733.65 seconds
Started	Apr 28 01:08:27 PM PDT 24
Finished	Apr 28 01:20:42 PM PDT 24
Peak memory	216940 kb
Host	smart-4fa13975-b7dd-4998-9ca2-01c93fb28f26
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640381641 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.640381641
Directory	/workspace/44.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.uart_tx_ovrd.3604057614
Short name	T972
Test name
Test status
Simulation time	1516275062 ps
CPU time	1.75 seconds
Started	Apr 28 01:08:27 PM PDT 24
Finished	Apr 28 01:08:30 PM PDT 24
Peak memory	198860 kb
Host	smart-d6396947-cf63-4352-b0f0-bcbf9cf7a39f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3604057614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.3604057614
Directory	/workspace/44.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/44.uart_tx_rx.176907591
Short name	T383
Test name
Test status
Simulation time	55387955360 ps
CPU time	47.98 seconds
Started	Apr 28 01:08:19 PM PDT 24
Finished	Apr 28 01:09:07 PM PDT 24
Peak memory	200332 kb
Host	smart-5e60b6f8-c340-4b6e-916c-f1420bb8670d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=176907591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.176907591
Directory	/workspace/44.uart_tx_rx/latest

Test location	/workspace/coverage/default/45.uart_alert_test.618271773
Short name	T550
Test name
Test status
Simulation time	35802387 ps
CPU time	0.55 seconds
Started	Apr 28 01:08:30 PM PDT 24
Finished	Apr 28 01:08:32 PM PDT 24
Peak memory	195784 kb
Host	smart-98078b8a-9fa6-46f2-9c69-35a5788663a0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618271773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.618271773
Directory	/workspace/45.uart_alert_test/latest

Test location	/workspace/coverage/default/45.uart_fifo_full.3859981241
Short name	T812
Test name
Test status
Simulation time	13692386945 ps
CPU time	23.2 seconds
Started	Apr 28 01:08:29 PM PDT 24
Finished	Apr 28 01:08:53 PM PDT 24
Peak memory	200196 kb
Host	smart-93ddbc45-d88e-4a61-9e7c-9cb833db4b72
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3859981241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.3859981241
Directory	/workspace/45.uart_fifo_full/latest

Test location	/workspace/coverage/default/45.uart_fifo_overflow.3522823631
Short name	T626
Test name
Test status
Simulation time	27135799154 ps
CPU time	44.94 seconds
Started	Apr 28 01:08:27 PM PDT 24
Finished	Apr 28 01:09:13 PM PDT 24
Peak memory	200340 kb
Host	smart-3c1a758d-9f0c-4faf-a1b2-5a4be0079e62
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3522823631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.3522823631
Directory	/workspace/45.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/45.uart_fifo_reset.2625757591
Short name	T1169
Test name
Test status
Simulation time	42106741258 ps
CPU time	35.53 seconds
Started	Apr 28 01:08:27 PM PDT 24
Finished	Apr 28 01:09:03 PM PDT 24
Peak memory	200452 kb
Host	smart-ba3c1680-55cf-4c9d-9683-54069cae6ed6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2625757591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2625757591
Directory	/workspace/45.uart_fifo_reset/latest

Test location	/workspace/coverage/default/45.uart_intr.1321454922
Short name	T884
Test name
Test status
Simulation time	16989076484 ps
CPU time	6.53 seconds
Started	Apr 28 01:08:26 PM PDT 24
Finished	Apr 28 01:08:33 PM PDT 24
Peak memory	199628 kb
Host	smart-21bce8f2-d230-48c0-ac66-627670e7eefb
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321454922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.1321454922
Directory	/workspace/45.uart_intr/latest

Test location	/workspace/coverage/default/45.uart_long_xfer_wo_dly.1492517817
Short name	T641
Test name
Test status
Simulation time	106990637437 ps
CPU time	151.77 seconds
Started	Apr 28 01:08:31 PM PDT 24
Finished	Apr 28 01:11:03 PM PDT 24
Peak memory	200460 kb
Host	smart-630fd0f0-4d93-4614-baf5-6f3f82c0a672
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1492517817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.1492517817
Directory	/workspace/45.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/45.uart_loopback.2984302665
Short name	T1036
Test name
Test status
Simulation time	4517721992 ps
CPU time	10.71 seconds
Started	Apr 28 01:08:32 PM PDT 24
Finished	Apr 28 01:08:43 PM PDT 24
Peak memory	200060 kb
Host	smart-4be1c688-8bcd-4057-a44f-f977de934d2e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2984302665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.2984302665
Directory	/workspace/45.uart_loopback/latest

Test location	/workspace/coverage/default/45.uart_noise_filter.3716320517
Short name	T791
Test name
Test status
Simulation time	29942372587 ps
CPU time	53.25 seconds
Started	Apr 28 01:08:26 PM PDT 24
Finished	Apr 28 01:09:20 PM PDT 24
Peak memory	198628 kb
Host	smart-bdfc951a-24e1-4906-bfc7-6ddc3f7e53dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3716320517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.3716320517
Directory	/workspace/45.uart_noise_filter/latest

Test location	/workspace/coverage/default/45.uart_perf.2571304180
Short name	T694
Test name
Test status
Simulation time	27123711142 ps
CPU time	643.26 seconds
Started	Apr 28 01:08:31 PM PDT 24
Finished	Apr 28 01:19:15 PM PDT 24
Peak memory	200372 kb
Host	smart-89a302fe-1364-4468-9793-eaabe247d03c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2571304180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.2571304180
Directory	/workspace/45.uart_perf/latest

Test location	/workspace/coverage/default/45.uart_rx_oversample.2587227335
Short name	T343
Test name
Test status
Simulation time	4371869521 ps
CPU time	39.7 seconds
Started	Apr 28 01:08:25 PM PDT 24
Finished	Apr 28 01:09:05 PM PDT 24
Peak memory	199500 kb
Host	smart-1de96a66-ab3c-4f8c-a7c4-d7b46c79b75f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2587227335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.2587227335
Directory	/workspace/45.uart_rx_oversample/latest

Test location	/workspace/coverage/default/45.uart_rx_parity_err.174386649
Short name	T850
Test name
Test status
Simulation time	64907479015 ps
CPU time	21.4 seconds
Started	Apr 28 01:08:29 PM PDT 24
Finished	Apr 28 01:08:51 PM PDT 24
Peak memory	200340 kb
Host	smart-521f9f10-af6c-414f-b90f-2332f1b8b7d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=174386649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.174386649
Directory	/workspace/45.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/45.uart_rx_start_bit_filter.1396479291
Short name	T1047
Test name
Test status
Simulation time	3574901999 ps
CPU time	3.36 seconds
Started	Apr 28 01:08:28 PM PDT 24
Finished	Apr 28 01:08:32 PM PDT 24
Peak memory	196300 kb
Host	smart-e9b31c47-f665-4e1b-b974-f119f33684f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1396479291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.1396479291
Directory	/workspace/45.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/45.uart_smoke.3755477323
Short name	T1172
Test name
Test status
Simulation time	844947644 ps
CPU time	3.47 seconds
Started	Apr 28 01:08:22 PM PDT 24
Finished	Apr 28 01:08:26 PM PDT 24
Peak memory	198892 kb
Host	smart-d092459c-5c1c-48ce-ad60-bcfaa6a5eae0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3755477323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.3755477323
Directory	/workspace/45.uart_smoke/latest

Test location	/workspace/coverage/default/45.uart_stress_all.3923084517
Short name	T400
Test name
Test status
Simulation time	440731002992 ps
CPU time	795.38 seconds
Started	Apr 28 01:08:31 PM PDT 24
Finished	Apr 28 01:21:47 PM PDT 24
Peak memory	208752 kb
Host	smart-765ad9e3-96c2-40dc-aa9e-eb07cde940de
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923084517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.3923084517
Directory	/workspace/45.uart_stress_all/latest

Test location	/workspace/coverage/default/45.uart_stress_all_with_rand_reset.1058594105
Short name	T1127
Test name
Test status
Simulation time	228580969689 ps
CPU time	830.89 seconds
Started	Apr 28 01:08:31 PM PDT 24
Finished	Apr 28 01:22:23 PM PDT 24
Peak memory	217100 kb
Host	smart-0ac30f1f-f67f-4d78-825a-e84c15d6641a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058594105 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.1058594105
Directory	/workspace/45.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.uart_tx_ovrd.3447633251
Short name	T735
Test name
Test status
Simulation time	1483895224 ps
CPU time	3.18 seconds
Started	Apr 28 01:08:32 PM PDT 24
Finished	Apr 28 01:08:36 PM PDT 24
Peak memory	199628 kb
Host	smart-351525be-af79-4944-b823-462e5d32e7aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3447633251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.3447633251
Directory	/workspace/45.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/45.uart_tx_rx.3778261514
Short name	T930
Test name
Test status
Simulation time	96807001160 ps
CPU time	41.72 seconds
Started	Apr 28 01:08:27 PM PDT 24
Finished	Apr 28 01:09:10 PM PDT 24
Peak memory	200372 kb
Host	smart-f5cc635f-22bc-4beb-ac16-431d4d3badbf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3778261514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.3778261514
Directory	/workspace/45.uart_tx_rx/latest

Test location	/workspace/coverage/default/46.uart_alert_test.1760853937
Short name	T830
Test name
Test status
Simulation time	33502101 ps
CPU time	0.54 seconds
Started	Apr 28 01:08:39 PM PDT 24
Finished	Apr 28 01:08:40 PM PDT 24
Peak memory	195760 kb
Host	smart-de170d8c-3af9-482f-a60e-51e02ab90645
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760853937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.1760853937
Directory	/workspace/46.uart_alert_test/latest

Test location	/workspace/coverage/default/46.uart_fifo_full.3897398577
Short name	T255
Test name
Test status
Simulation time	130884259438 ps
CPU time	315.92 seconds
Started	Apr 28 01:08:32 PM PDT 24
Finished	Apr 28 01:13:49 PM PDT 24
Peak memory	200344 kb
Host	smart-8d17cd8a-da9f-4053-95a8-116222f703e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3897398577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.3897398577
Directory	/workspace/46.uart_fifo_full/latest

Test location	/workspace/coverage/default/46.uart_fifo_overflow.3362325867
Short name	T466
Test name
Test status
Simulation time	29385942121 ps
CPU time	25.53 seconds
Started	Apr 28 01:08:32 PM PDT 24
Finished	Apr 28 01:08:58 PM PDT 24
Peak memory	200300 kb
Host	smart-7ca574bb-c90f-4c01-adb4-7c95f032a14d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3362325867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.3362325867
Directory	/workspace/46.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/46.uart_fifo_reset.3837150043
Short name	T207
Test name
Test status
Simulation time	7464027283 ps
CPU time	11.82 seconds
Started	Apr 28 01:08:31 PM PDT 24
Finished	Apr 28 01:08:44 PM PDT 24
Peak memory	200108 kb
Host	smart-8103ab08-5952-47ce-a8f6-10e378185a45
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3837150043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.3837150043
Directory	/workspace/46.uart_fifo_reset/latest

Test location	/workspace/coverage/default/46.uart_intr.2123699149
Short name	T831
Test name
Test status
Simulation time	30495011329 ps
CPU time	30.28 seconds
Started	Apr 28 01:08:32 PM PDT 24
Finished	Apr 28 01:09:03 PM PDT 24
Peak memory	200308 kb
Host	smart-6060f482-ae6f-4772-9e02-b8c3ca1631a6
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123699149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.2123699149
Directory	/workspace/46.uart_intr/latest

Test location	/workspace/coverage/default/46.uart_long_xfer_wo_dly.307275315
Short name	T807
Test name
Test status
Simulation time	99394996310 ps
CPU time	347.36 seconds
Started	Apr 28 01:08:35 PM PDT 24
Finished	Apr 28 01:14:24 PM PDT 24
Peak memory	200252 kb
Host	smart-c20cccf2-6621-431b-8f7e-f4d00c797ffd
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=307275315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.307275315
Directory	/workspace/46.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/46.uart_loopback.1205033879
Short name	T465
Test name
Test status
Simulation time	4951507996 ps
CPU time	9.43 seconds
Started	Apr 28 01:08:35 PM PDT 24
Finished	Apr 28 01:08:45 PM PDT 24
Peak memory	199152 kb
Host	smart-c98c2a0d-27d3-45eb-87df-700056644881
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1205033879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.1205033879
Directory	/workspace/46.uart_loopback/latest

Test location	/workspace/coverage/default/46.uart_noise_filter.2730783890
Short name	T587
Test name
Test status
Simulation time	52856293230 ps
CPU time	83.49 seconds
Started	Apr 28 01:08:31 PM PDT 24
Finished	Apr 28 01:09:55 PM PDT 24
Peak memory	199548 kb
Host	smart-b5f4823b-1778-4ac7-b9e2-b7d1ea993a1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2730783890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.2730783890
Directory	/workspace/46.uart_noise_filter/latest

Test location	/workspace/coverage/default/46.uart_perf.1366147694
Short name	T835
Test name
Test status
Simulation time	16707785884 ps
CPU time	328.04 seconds
Started	Apr 28 01:08:34 PM PDT 24
Finished	Apr 28 01:14:03 PM PDT 24
Peak memory	200380 kb
Host	smart-6d735966-d691-475e-857e-77faf575bd95
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1366147694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.1366147694
Directory	/workspace/46.uart_perf/latest

Test location	/workspace/coverage/default/46.uart_rx_oversample.3512446510
Short name	T554
Test name
Test status
Simulation time	3860941165 ps
CPU time	7 seconds
Started	Apr 28 01:08:32 PM PDT 24
Finished	Apr 28 01:08:40 PM PDT 24
Peak memory	199320 kb
Host	smart-4d1db452-b683-45bb-820c-6bc7a7fdea45
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3512446510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.3512446510
Directory	/workspace/46.uart_rx_oversample/latest

Test location	/workspace/coverage/default/46.uart_rx_parity_err.286764508
Short name	T389
Test name
Test status
Simulation time	181835286504 ps
CPU time	334.13 seconds
Started	Apr 28 01:08:35 PM PDT 24
Finished	Apr 28 01:14:10 PM PDT 24
Peak memory	200420 kb
Host	smart-7878a106-ccb6-4502-b4f3-ccec94fe50b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=286764508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.286764508
Directory	/workspace/46.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/46.uart_rx_start_bit_filter.668383125
Short name	T1122
Test name
Test status
Simulation time	5093738992 ps
CPU time	2.82 seconds
Started	Apr 28 01:08:32 PM PDT 24
Finished	Apr 28 01:08:36 PM PDT 24
Peak memory	196440 kb
Host	smart-de9601fb-7d66-4a8c-960c-da416a1ebd61
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=668383125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.668383125
Directory	/workspace/46.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/46.uart_smoke.3148077265
Short name	T382
Test name
Test status
Simulation time	910487536 ps
CPU time	2.07 seconds
Started	Apr 28 01:08:32 PM PDT 24
Finished	Apr 28 01:08:35 PM PDT 24
Peak memory	199240 kb
Host	smart-a8b72ad6-1d56-408d-8145-dc76747dae00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3148077265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.3148077265
Directory	/workspace/46.uart_smoke/latest

Test location	/workspace/coverage/default/46.uart_stress_all.2817896293
Short name	T509
Test name
Test status
Simulation time	338377972427 ps
CPU time	321.64 seconds
Started	Apr 28 01:08:37 PM PDT 24
Finished	Apr 28 01:13:59 PM PDT 24
Peak memory	208676 kb
Host	smart-b9fbba32-9bb7-47f9-8901-8d7c4819946c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817896293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.2817896293
Directory	/workspace/46.uart_stress_all/latest

Test location	/workspace/coverage/default/46.uart_stress_all_with_rand_reset.1347004212
Short name	T34
Test name
Test status
Simulation time	50308078251 ps
CPU time	191.28 seconds
Started	Apr 28 01:08:34 PM PDT 24
Finished	Apr 28 01:11:46 PM PDT 24
Peak memory	216964 kb
Host	smart-e3c4fe5e-c4db-427b-99a8-3c32d50336ed
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347004212 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.1347004212
Directory	/workspace/46.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/46.uart_tx_ovrd.390589673
Short name	T914
Test name
Test status
Simulation time	8890155365 ps
CPU time	10.19 seconds
Started	Apr 28 01:08:35 PM PDT 24
Finished	Apr 28 01:08:46 PM PDT 24
Peak memory	200184 kb
Host	smart-87a50a09-a9af-42ef-81a8-ae1617e5529f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=390589673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.390589673
Directory	/workspace/46.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/46.uart_tx_rx.2466201351
Short name	T508
Test name
Test status
Simulation time	33770997883 ps
CPU time	48.17 seconds
Started	Apr 28 01:08:32 PM PDT 24
Finished	Apr 28 01:09:21 PM PDT 24
Peak memory	200360 kb
Host	smart-71483830-5d38-41b0-9de6-35c7789868c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2466201351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.2466201351
Directory	/workspace/46.uart_tx_rx/latest

Test location	/workspace/coverage/default/47.uart_alert_test.1779064852
Short name	T1026
Test name
Test status
Simulation time	28197498 ps
CPU time	0.54 seconds
Started	Apr 28 01:08:42 PM PDT 24
Finished	Apr 28 01:08:43 PM PDT 24
Peak memory	195812 kb
Host	smart-88a3a8de-665b-4915-87d0-9a76ce309730
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779064852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.1779064852
Directory	/workspace/47.uart_alert_test/latest

Test location	/workspace/coverage/default/47.uart_fifo_full.1704510492
Short name	T809
Test name
Test status
Simulation time	19541285210 ps
CPU time	43.3 seconds
Started	Apr 28 01:08:38 PM PDT 24
Finished	Apr 28 01:09:21 PM PDT 24
Peak memory	200368 kb
Host	smart-5d3cadd9-5b2a-4a52-b29c-5bc7fafb8999
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1704510492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.1704510492
Directory	/workspace/47.uart_fifo_full/latest

Test location	/workspace/coverage/default/47.uart_fifo_overflow.3289310831
Short name	T441
Test name
Test status
Simulation time	144101775883 ps
CPU time	83.36 seconds
Started	Apr 28 01:08:35 PM PDT 24
Finished	Apr 28 01:09:59 PM PDT 24
Peak memory	200412 kb
Host	smart-99a9301a-2a8c-430d-a3fc-933bac5f4234
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3289310831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.3289310831
Directory	/workspace/47.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/47.uart_fifo_reset.1498358617
Short name	T628
Test name
Test status
Simulation time	16238417694 ps
CPU time	19.31 seconds
Started	Apr 28 01:08:35 PM PDT 24
Finished	Apr 28 01:08:55 PM PDT 24
Peak memory	200284 kb
Host	smart-1d63f769-6d2c-41ba-8260-e5c2f82267d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1498358617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.1498358617
Directory	/workspace/47.uart_fifo_reset/latest

Test location	/workspace/coverage/default/47.uart_intr.1908501663
Short name	T682
Test name
Test status
Simulation time	38128199631 ps
CPU time	63.59 seconds
Started	Apr 28 01:08:35 PM PDT 24
Finished	Apr 28 01:09:39 PM PDT 24
Peak memory	199424 kb
Host	smart-1085a0d4-8b27-43d4-8caf-63295c736188
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908501663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.1908501663
Directory	/workspace/47.uart_intr/latest

Test location	/workspace/coverage/default/47.uart_long_xfer_wo_dly.126783983
Short name	T724
Test name
Test status
Simulation time	162215523569 ps
CPU time	912.73 seconds
Started	Apr 28 01:08:41 PM PDT 24
Finished	Apr 28 01:23:55 PM PDT 24
Peak memory	200436 kb
Host	smart-4a70f22f-3b52-4aa7-83bc-38adf6893d0d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=126783983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.126783983
Directory	/workspace/47.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/47.uart_loopback.689633967
Short name	T836
Test name
Test status
Simulation time	11034255651 ps
CPU time	18.65 seconds
Started	Apr 28 01:08:41 PM PDT 24
Finished	Apr 28 01:09:00 PM PDT 24
Peak memory	199172 kb
Host	smart-05b43f48-8d66-4b0e-b2e7-870fbc68c642
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=689633967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.689633967
Directory	/workspace/47.uart_loopback/latest

Test location	/workspace/coverage/default/47.uart_noise_filter.2585255192
Short name	T653
Test name
Test status
Simulation time	139217821977 ps
CPU time	143.51 seconds
Started	Apr 28 01:08:37 PM PDT 24
Finished	Apr 28 01:11:02 PM PDT 24
Peak memory	199664 kb
Host	smart-964abe8b-5a50-4cc5-acd7-dfb3069b8e78
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2585255192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.2585255192
Directory	/workspace/47.uart_noise_filter/latest

Test location	/workspace/coverage/default/47.uart_perf.2460318860
Short name	T663
Test name
Test status
Simulation time	18347793667 ps
CPU time	269.76 seconds
Started	Apr 28 01:08:41 PM PDT 24
Finished	Apr 28 01:13:12 PM PDT 24
Peak memory	200236 kb
Host	smart-3083aba2-7a91-42e3-a742-dc777fe7055b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2460318860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.2460318860
Directory	/workspace/47.uart_perf/latest

Test location	/workspace/coverage/default/47.uart_rx_oversample.1084302613
Short name	T889
Test name
Test status
Simulation time	3073671542 ps
CPU time	19.24 seconds
Started	Apr 28 01:08:36 PM PDT 24
Finished	Apr 28 01:08:56 PM PDT 24
Peak memory	198848 kb
Host	smart-ebda1262-6ac5-4fd7-bc1e-39f3cf0b9f54
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1084302613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.1084302613
Directory	/workspace/47.uart_rx_oversample/latest

Test location	/workspace/coverage/default/47.uart_rx_parity_err.3296538025
Short name	T585
Test name
Test status
Simulation time	35841232941 ps
CPU time	57.42 seconds
Started	Apr 28 01:08:39 PM PDT 24
Finished	Apr 28 01:09:37 PM PDT 24
Peak memory	199864 kb
Host	smart-9987fd65-5a10-48ac-b117-8259b8747483
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3296538025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3296538025
Directory	/workspace/47.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/47.uart_rx_start_bit_filter.1703138225
Short name	T272
Test name
Test status
Simulation time	5190739929 ps
CPU time	8.59 seconds
Started	Apr 28 01:08:40 PM PDT 24
Finished	Apr 28 01:08:49 PM PDT 24
Peak memory	196556 kb
Host	smart-d248a05e-9a15-40d6-b609-df375ab3fd50
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1703138225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.1703138225
Directory	/workspace/47.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/47.uart_smoke.4138976538
Short name	T795
Test name
Test status
Simulation time	941730835 ps
CPU time	4.42 seconds
Started	Apr 28 01:08:36 PM PDT 24
Finished	Apr 28 01:08:41 PM PDT 24
Peak memory	199908 kb
Host	smart-5fbf1787-327a-40c6-b28a-193f7b992e33
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4138976538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.4138976538
Directory	/workspace/47.uart_smoke/latest

Test location	/workspace/coverage/default/47.uart_stress_all.3872360894
Short name	T1077
Test name
Test status
Simulation time	145060805267 ps
CPU time	75.2 seconds
Started	Apr 28 01:08:42 PM PDT 24
Finished	Apr 28 01:09:58 PM PDT 24
Peak memory	216084 kb
Host	smart-fa48ca79-ecc3-4243-8c9d-7d20f2f19a6d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872360894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.3872360894
Directory	/workspace/47.uart_stress_all/latest

Test location	/workspace/coverage/default/47.uart_stress_all_with_rand_reset.437082531
Short name	T534
Test name
Test status
Simulation time	31231623738 ps
CPU time	645.05 seconds
Started	Apr 28 01:08:41 PM PDT 24
Finished	Apr 28 01:19:27 PM PDT 24
Peak memory	208764 kb
Host	smart-6eaba018-7a11-46dd-a735-3f3d93e86762
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437082531 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.437082531
Directory	/workspace/47.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/47.uart_tx_ovrd.894254240
Short name	T513
Test name
Test status
Simulation time	2334998568 ps
CPU time	2.62 seconds
Started	Apr 28 01:08:46 PM PDT 24
Finished	Apr 28 01:08:49 PM PDT 24
Peak memory	199132 kb
Host	smart-a13533e0-1110-41e2-bb86-aa5ab2fa068d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=894254240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.894254240
Directory	/workspace/47.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/47.uart_tx_rx.2885771574
Short name	T463
Test name
Test status
Simulation time	6681294249 ps
CPU time	2.9 seconds
Started	Apr 28 01:08:35 PM PDT 24
Finished	Apr 28 01:08:39 PM PDT 24
Peak memory	198456 kb
Host	smart-279c1f0a-4306-483c-a6e6-38942c2fe684
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2885771574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.2885771574
Directory	/workspace/47.uart_tx_rx/latest

Test location	/workspace/coverage/default/48.uart_alert_test.959441945
Short name	T1019
Test name
Test status
Simulation time	49255424 ps
CPU time	0.53 seconds
Started	Apr 28 01:08:48 PM PDT 24
Finished	Apr 28 01:08:49 PM PDT 24
Peak memory	195820 kb
Host	smart-99789ee3-82f8-4be0-a016-f81b746672cd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959441945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.959441945
Directory	/workspace/48.uart_alert_test/latest

Test location	/workspace/coverage/default/48.uart_fifo_full.3510941025
Short name	T375
Test name
Test status
Simulation time	74534906112 ps
CPU time	50.22 seconds
Started	Apr 28 01:08:41 PM PDT 24
Finished	Apr 28 01:09:32 PM PDT 24
Peak memory	200360 kb
Host	smart-ed307dce-90c7-4065-a6b0-0142b2a9e64b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3510941025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.3510941025
Directory	/workspace/48.uart_fifo_full/latest

Test location	/workspace/coverage/default/48.uart_fifo_overflow.200437334
Short name	T623
Test name
Test status
Simulation time	249956012773 ps
CPU time	62.93 seconds
Started	Apr 28 01:08:42 PM PDT 24
Finished	Apr 28 01:09:45 PM PDT 24
Peak memory	200364 kb
Host	smart-d326cd06-a70d-44fb-b288-efece1fe85a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=200437334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.200437334
Directory	/workspace/48.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/48.uart_intr.3399513324
Short name	T368
Test name
Test status
Simulation time	28509805948 ps
CPU time	12.39 seconds
Started	Apr 28 01:08:43 PM PDT 24
Finished	Apr 28 01:08:56 PM PDT 24
Peak memory	199384 kb
Host	smart-1b7f3685-5cd8-4084-a292-4772201a5260
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399513324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.3399513324
Directory	/workspace/48.uart_intr/latest

Test location	/workspace/coverage/default/48.uart_long_xfer_wo_dly.2294317443
Short name	T633
Test name
Test status
Simulation time	123097377449 ps
CPU time	177.01 seconds
Started	Apr 28 01:08:48 PM PDT 24
Finished	Apr 28 01:11:46 PM PDT 24
Peak memory	200452 kb
Host	smart-0b92f462-a21d-4e13-845e-56140c9ba67b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2294317443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.2294317443
Directory	/workspace/48.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/48.uart_loopback.4219917876
Short name	T712
Test name
Test status
Simulation time	3916911579 ps
CPU time	2.09 seconds
Started	Apr 28 01:08:48 PM PDT 24
Finished	Apr 28 01:08:51 PM PDT 24
Peak memory	198560 kb
Host	smart-aac88c54-3a91-47d4-9d81-1f8da1e5bfc7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4219917876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.4219917876
Directory	/workspace/48.uart_loopback/latest

Test location	/workspace/coverage/default/48.uart_noise_filter.177132738
Short name	T992
Test name
Test status
Simulation time	48545174333 ps
CPU time	43.89 seconds
Started	Apr 28 01:08:48 PM PDT 24
Finished	Apr 28 01:09:32 PM PDT 24
Peak memory	199000 kb
Host	smart-6e5bbd60-7712-45fd-bcfb-0e448133cfd5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=177132738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.177132738
Directory	/workspace/48.uart_noise_filter/latest

Test location	/workspace/coverage/default/48.uart_perf.3105266165
Short name	T1074
Test name
Test status
Simulation time	6300039207 ps
CPU time	195.71 seconds
Started	Apr 28 01:08:46 PM PDT 24
Finished	Apr 28 01:12:02 PM PDT 24
Peak memory	200148 kb
Host	smart-5d839ce2-ebb0-48a6-aa90-5d47b4f63d40
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3105266165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.3105266165
Directory	/workspace/48.uart_perf/latest

Test location	/workspace/coverage/default/48.uart_rx_oversample.2446521805
Short name	T652
Test name
Test status
Simulation time	1816035253 ps
CPU time	6.85 seconds
Started	Apr 28 01:08:41 PM PDT 24
Finished	Apr 28 01:08:49 PM PDT 24
Peak memory	198564 kb
Host	smart-9469433e-17cb-4928-bb7f-a82914c4cdc3
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2446521805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.2446521805
Directory	/workspace/48.uart_rx_oversample/latest

Test location	/workspace/coverage/default/48.uart_rx_parity_err.2012367007
Short name	T693
Test name
Test status
Simulation time	23603533658 ps
CPU time	44.41 seconds
Started	Apr 28 01:08:46 PM PDT 24
Finished	Apr 28 01:09:31 PM PDT 24
Peak memory	200404 kb
Host	smart-f6ba3fc4-9e15-4441-90c7-3f075009e7a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2012367007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.2012367007
Directory	/workspace/48.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/48.uart_rx_start_bit_filter.173265625
Short name	T778
Test name
Test status
Simulation time	42941535484 ps
CPU time	18.1 seconds
Started	Apr 28 01:08:46 PM PDT 24
Finished	Apr 28 01:09:05 PM PDT 24
Peak memory	196180 kb
Host	smart-46337f4c-e446-4e93-a5d5-50f839631449
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=173265625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.173265625
Directory	/workspace/48.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/48.uart_smoke.3715071065
Short name	T576
Test name
Test status
Simulation time	469671605 ps
CPU time	1.35 seconds
Started	Apr 28 01:08:40 PM PDT 24
Finished	Apr 28 01:08:42 PM PDT 24
Peak memory	199132 kb
Host	smart-81f932b0-7b03-47ac-bb01-9bbb288e0c24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3715071065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3715071065
Directory	/workspace/48.uart_smoke/latest

Test location	/workspace/coverage/default/48.uart_stress_all_with_rand_reset.1148071749
Short name	T56
Test name
Test status
Simulation time	112254255895 ps
CPU time	1617.58 seconds
Started	Apr 28 01:08:48 PM PDT 24
Finished	Apr 28 01:35:46 PM PDT 24
Peak memory	216792 kb
Host	smart-5fac3198-2d40-4c06-9a60-3ccf59bf35a8
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148071749 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.1148071749
Directory	/workspace/48.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.uart_tx_ovrd.24867073
Short name	T767
Test name
Test status
Simulation time	1121957201 ps
CPU time	2.29 seconds
Started	Apr 28 01:08:48 PM PDT 24
Finished	Apr 28 01:08:51 PM PDT 24
Peak memory	199004 kb
Host	smart-15c1a16e-bcb1-4d24-9c6b-06956c028e07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=24867073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.24867073
Directory	/workspace/48.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/48.uart_tx_rx.3383574956
Short name	T893
Test name
Test status
Simulation time	36198383463 ps
CPU time	54.33 seconds
Started	Apr 28 01:08:43 PM PDT 24
Finished	Apr 28 01:09:38 PM PDT 24
Peak memory	200268 kb
Host	smart-130858a7-127e-4108-b9cc-9237bb7094f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3383574956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.3383574956
Directory	/workspace/48.uart_tx_rx/latest

Test location	/workspace/coverage/default/49.uart_alert_test.2658211495
Short name	T1145
Test name
Test status
Simulation time	11859239 ps
CPU time	0.55 seconds
Started	Apr 28 01:08:51 PM PDT 24
Finished	Apr 28 01:08:52 PM PDT 24
Peak memory	195692 kb
Host	smart-bd5ff625-04c0-44fd-866c-c1806631d73e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658211495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.2658211495
Directory	/workspace/49.uart_alert_test/latest

Test location	/workspace/coverage/default/49.uart_fifo_full.1630763692
Short name	T44
Test name
Test status
Simulation time	31699051439 ps
CPU time	78.95 seconds
Started	Apr 28 01:08:46 PM PDT 24
Finished	Apr 28 01:10:05 PM PDT 24
Peak memory	200332 kb
Host	smart-3ad5a061-18b8-4ed4-8f24-bb652a1f9c41
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1630763692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.1630763692
Directory	/workspace/49.uart_fifo_full/latest

Test location	/workspace/coverage/default/49.uart_fifo_overflow.1059562994
Short name	T668
Test name
Test status
Simulation time	184229118365 ps
CPU time	88.39 seconds
Started	Apr 28 01:08:47 PM PDT 24
Finished	Apr 28 01:10:16 PM PDT 24
Peak memory	200472 kb
Host	smart-0f1d2d12-553a-4193-8f50-f3a4c726c771
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1059562994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.1059562994
Directory	/workspace/49.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/49.uart_fifo_reset.2415668935
Short name	T685
Test name
Test status
Simulation time	13105215102 ps
CPU time	12.43 seconds
Started	Apr 28 01:08:46 PM PDT 24
Finished	Apr 28 01:08:59 PM PDT 24
Peak memory	200368 kb
Host	smart-e495bdff-6405-4093-b76d-a44be898f278
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2415668935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.2415668935
Directory	/workspace/49.uart_fifo_reset/latest

Test location	/workspace/coverage/default/49.uart_intr.2501244111
Short name	T1015
Test name
Test status
Simulation time	21092409324 ps
CPU time	37.78 seconds
Started	Apr 28 01:08:48 PM PDT 24
Finished	Apr 28 01:09:26 PM PDT 24
Peak memory	198048 kb
Host	smart-203ce4d4-50cd-49b0-a9ee-ce5bf7ae8a2d
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501244111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.2501244111
Directory	/workspace/49.uart_intr/latest

Test location	/workspace/coverage/default/49.uart_long_xfer_wo_dly.703851814
Short name	T401
Test name
Test status
Simulation time	93068322328 ps
CPU time	613.24 seconds
Started	Apr 28 01:08:51 PM PDT 24
Finished	Apr 28 01:19:05 PM PDT 24
Peak memory	200472 kb
Host	smart-602f7d1e-f486-4142-9d1a-adec62cf1a75
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=703851814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.703851814
Directory	/workspace/49.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/49.uart_loopback.1631710107
Short name	T966
Test name
Test status
Simulation time	20921879 ps
CPU time	0.61 seconds
Started	Apr 28 01:08:51 PM PDT 24
Finished	Apr 28 01:08:52 PM PDT 24
Peak memory	196296 kb
Host	smart-b52bb104-3c7d-4647-9920-5c4425e26f3c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1631710107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1631710107
Directory	/workspace/49.uart_loopback/latest

Test location	/workspace/coverage/default/49.uart_noise_filter.2086132873
Short name	T541
Test name
Test status
Simulation time	32311477107 ps
CPU time	11.59 seconds
Started	Apr 28 01:08:47 PM PDT 24
Finished	Apr 28 01:08:59 PM PDT 24
Peak memory	195052 kb
Host	smart-d656940a-ba76-44d5-baee-e5d56c58f1c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2086132873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.2086132873
Directory	/workspace/49.uart_noise_filter/latest

Test location	/workspace/coverage/default/49.uart_perf.3636798372
Short name	T46
Test name
Test status
Simulation time	14110041528 ps
CPU time	378 seconds
Started	Apr 28 01:08:50 PM PDT 24
Finished	Apr 28 01:15:09 PM PDT 24
Peak memory	200448 kb
Host	smart-772753db-8363-4556-bf7d-289a7b5ede96
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3636798372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.3636798372
Directory	/workspace/49.uart_perf/latest

Test location	/workspace/coverage/default/49.uart_rx_oversample.1189027886
Short name	T1179
Test name
Test status
Simulation time	3135569368 ps
CPU time	9.3 seconds
Started	Apr 28 01:08:46 PM PDT 24
Finished	Apr 28 01:08:56 PM PDT 24
Peak memory	199260 kb
Host	smart-dd574d81-d8f8-4c17-b616-b1022e995870
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1189027886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.1189027886
Directory	/workspace/49.uart_rx_oversample/latest

Test location	/workspace/coverage/default/49.uart_rx_parity_err.2241108120
Short name	T428
Test name
Test status
Simulation time	20781140650 ps
CPU time	11.43 seconds
Started	Apr 28 01:08:52 PM PDT 24
Finished	Apr 28 01:09:04 PM PDT 24
Peak memory	200172 kb
Host	smart-af7f1d04-3270-4b63-8c11-db3dff86234f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2241108120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.2241108120
Directory	/workspace/49.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/49.uart_rx_start_bit_filter.1972454512
Short name	T436
Test name
Test status
Simulation time	3375646686 ps
CPU time	4.03 seconds
Started	Apr 28 01:08:46 PM PDT 24
Finished	Apr 28 01:08:50 PM PDT 24
Peak memory	196432 kb
Host	smart-99c3accd-b4ec-437f-9b6d-9dd9ecf3c494
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1972454512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.1972454512
Directory	/workspace/49.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/49.uart_smoke.3664917282
Short name	T528
Test name
Test status
Simulation time	516259739 ps
CPU time	1.26 seconds
Started	Apr 28 01:08:46 PM PDT 24
Finished	Apr 28 01:08:48 PM PDT 24
Peak memory	199112 kb
Host	smart-0fb2f227-ca88-4f1a-bfec-0809d3b0d8a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3664917282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.3664917282
Directory	/workspace/49.uart_smoke/latest

Test location	/workspace/coverage/default/49.uart_stress_all.40487293
Short name	T1142
Test name
Test status
Simulation time	295034963969 ps
CPU time	173.03 seconds
Started	Apr 28 01:08:51 PM PDT 24
Finished	Apr 28 01:11:45 PM PDT 24
Peak memory	200356 kb
Host	smart-de1ca581-a933-4a48-89be-4d64af96d80b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40487293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.40487293
Directory	/workspace/49.uart_stress_all/latest

Test location	/workspace/coverage/default/49.uart_stress_all_with_rand_reset.1249100710
Short name	T1154
Test name
Test status
Simulation time	24394021391 ps
CPU time	207.22 seconds
Started	Apr 28 01:08:50 PM PDT 24
Finished	Apr 28 01:12:18 PM PDT 24
Peak memory	217004 kb
Host	smart-341a9c55-80e2-49e2-bf8c-933f6b34ca52
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249100710 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.1249100710
Directory	/workspace/49.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/49.uart_tx_ovrd.1072778778
Short name	T986
Test name
Test status
Simulation time	968626197 ps
CPU time	3.18 seconds
Started	Apr 28 01:08:51 PM PDT 24
Finished	Apr 28 01:08:55 PM PDT 24
Peak memory	199024 kb
Host	smart-3ce44133-77b8-4654-9a35-a8f93b7127d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1072778778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.1072778778
Directory	/workspace/49.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/49.uart_tx_rx.904161853
Short name	T667
Test name
Test status
Simulation time	93261719469 ps
CPU time	78.34 seconds
Started	Apr 28 01:08:47 PM PDT 24
Finished	Apr 28 01:10:06 PM PDT 24
Peak memory	200384 kb
Host	smart-19ad1206-e4e5-4d7f-99a5-e07772b5d4bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=904161853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.904161853
Directory	/workspace/49.uart_tx_rx/latest

Test location	/workspace/coverage/default/5.uart_alert_test.3509776002
Short name	T445
Test name
Test status
Simulation time	70944944 ps
CPU time	0.54 seconds
Started	Apr 28 01:05:25 PM PDT 24
Finished	Apr 28 01:05:26 PM PDT 24
Peak memory	195808 kb
Host	smart-950b2557-50ad-43e3-aaea-a904a5262c7f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509776002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.3509776002
Directory	/workspace/5.uart_alert_test/latest

Test location	/workspace/coverage/default/5.uart_fifo_full.3376748641
Short name	T521
Test name
Test status
Simulation time	140941200013 ps
CPU time	344 seconds
Started	Apr 28 01:05:15 PM PDT 24
Finished	Apr 28 01:11:00 PM PDT 24
Peak memory	200456 kb
Host	smart-eb845059-1702-45a7-9ba2-a3d3e6c5533c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3376748641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.3376748641
Directory	/workspace/5.uart_fifo_full/latest

Test location	/workspace/coverage/default/5.uart_fifo_overflow.1958028881
Short name	T507
Test name
Test status
Simulation time	72048757877 ps
CPU time	74.23 seconds
Started	Apr 28 01:05:21 PM PDT 24
Finished	Apr 28 01:06:36 PM PDT 24
Peak memory	200340 kb
Host	smart-0d135e2e-4536-4f3e-84f7-a1cab45380f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1958028881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.1958028881
Directory	/workspace/5.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/5.uart_fifo_reset.813071142
Short name	T501
Test name
Test status
Simulation time	29257592101 ps
CPU time	41.62 seconds
Started	Apr 28 01:05:21 PM PDT 24
Finished	Apr 28 01:06:03 PM PDT 24
Peak memory	200344 kb
Host	smart-2a20b2a2-f704-4d10-8118-9fcbc03bc1a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=813071142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.813071142
Directory	/workspace/5.uart_fifo_reset/latest

Test location	/workspace/coverage/default/5.uart_intr.832500388
Short name	T434
Test name
Test status
Simulation time	251303357893 ps
CPU time	380.89 seconds
Started	Apr 28 01:05:20 PM PDT 24
Finished	Apr 28 01:11:41 PM PDT 24
Peak memory	200148 kb
Host	smart-e044f8be-090f-465a-83a7-3ede65e9a111
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832500388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.832500388
Directory	/workspace/5.uart_intr/latest

Test location	/workspace/coverage/default/5.uart_long_xfer_wo_dly.3847879891
Short name	T950
Test name
Test status
Simulation time	97894355579 ps
CPU time	248.36 seconds
Started	Apr 28 01:05:24 PM PDT 24
Finished	Apr 28 01:09:33 PM PDT 24
Peak memory	200420 kb
Host	smart-40a81f82-f5b9-4734-acb8-db8525ab38f8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3847879891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.3847879891
Directory	/workspace/5.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/5.uart_loopback.535770898
Short name	T345
Test name
Test status
Simulation time	8281950809 ps
CPU time	18.91 seconds
Started	Apr 28 01:05:24 PM PDT 24
Finished	Apr 28 01:05:44 PM PDT 24
Peak memory	199036 kb
Host	smart-b8f37b12-af28-4ebf-bdf5-71aa72284c21
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=535770898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.535770898
Directory	/workspace/5.uart_loopback/latest

Test location	/workspace/coverage/default/5.uart_noise_filter.1864706442
Short name	T1092
Test name
Test status
Simulation time	95402690353 ps
CPU time	96.24 seconds
Started	Apr 28 01:05:23 PM PDT 24
Finished	Apr 28 01:07:00 PM PDT 24
Peak memory	199160 kb
Host	smart-56dab196-327d-4519-bf33-3be7b0d62088
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1864706442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.1864706442
Directory	/workspace/5.uart_noise_filter/latest

Test location	/workspace/coverage/default/5.uart_perf.3257480916
Short name	T66
Test name
Test status
Simulation time	9762675562 ps
CPU time	124.77 seconds
Started	Apr 28 01:05:18 PM PDT 24
Finished	Apr 28 01:07:23 PM PDT 24
Peak memory	200480 kb
Host	smart-4276d6c5-55d6-48f0-8ac6-5b9f5fcd0bd0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3257480916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.3257480916
Directory	/workspace/5.uart_perf/latest

Test location	/workspace/coverage/default/5.uart_rx_oversample.3934398134
Short name	T811
Test name
Test status
Simulation time	5697158587 ps
CPU time	13.56 seconds
Started	Apr 28 01:05:23 PM PDT 24
Finished	Apr 28 01:05:37 PM PDT 24
Peak memory	199756 kb
Host	smart-7b791fae-6e63-40c0-a147-efbd029d3784
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3934398134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.3934398134
Directory	/workspace/5.uart_rx_oversample/latest

Test location	/workspace/coverage/default/5.uart_rx_parity_err.3043917130
Short name	T527
Test name
Test status
Simulation time	115155370491 ps
CPU time	45.16 seconds
Started	Apr 28 01:05:23 PM PDT 24
Finished	Apr 28 01:06:09 PM PDT 24
Peak memory	200448 kb
Host	smart-b7d4e886-b761-4c5f-993b-e0fab264949c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3043917130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.3043917130
Directory	/workspace/5.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/5.uart_rx_start_bit_filter.4116544019
Short name	T370
Test name
Test status
Simulation time	41790257850 ps
CPU time	37.09 seconds
Started	Apr 28 01:05:22 PM PDT 24
Finished	Apr 28 01:06:00 PM PDT 24
Peak memory	196244 kb
Host	smart-265e8ce3-6e2a-4cb3-b1f6-c5bd7d079c61
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4116544019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.4116544019
Directory	/workspace/5.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/5.uart_smoke.98965224
Short name	T1166
Test name
Test status
Simulation time	6068143480 ps
CPU time	21.44 seconds
Started	Apr 28 01:05:17 PM PDT 24
Finished	Apr 28 01:05:39 PM PDT 24
Peak memory	200360 kb
Host	smart-55817114-cdad-4d18-aac4-a37fcd89e8eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=98965224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.98965224
Directory	/workspace/5.uart_smoke/latest

Test location	/workspace/coverage/default/5.uart_stress_all.3181695049
Short name	T166
Test name
Test status
Simulation time	247935762939 ps
CPU time	160.87 seconds
Started	Apr 28 01:05:21 PM PDT 24
Finished	Apr 28 01:08:02 PM PDT 24
Peak memory	200392 kb
Host	smart-5a469924-6636-4f88-ac5f-32ed30bd2af3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181695049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3181695049
Directory	/workspace/5.uart_stress_all/latest

Test location	/workspace/coverage/default/5.uart_stress_all_with_rand_reset.409531649
Short name	T58
Test name
Test status
Simulation time	188997718656 ps
CPU time	796.05 seconds
Started	Apr 28 01:05:19 PM PDT 24
Finished	Apr 28 01:18:35 PM PDT 24
Peak memory	226916 kb
Host	smart-2b6ce5b5-7070-4498-ab14-8e2f93640204
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409531649 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.409531649
Directory	/workspace/5.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/5.uart_tx_ovrd.509934253
Short name	T430
Test name
Test status
Simulation time	6466552143 ps
CPU time	2.17 seconds
Started	Apr 28 01:05:24 PM PDT 24
Finished	Apr 28 01:05:27 PM PDT 24
Peak memory	199968 kb
Host	smart-6c09e4d9-367d-40b7-a7a9-d9a7542df445
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=509934253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.509934253
Directory	/workspace/5.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/5.uart_tx_rx.3879201516
Short name	T479
Test name
Test status
Simulation time	85947230736 ps
CPU time	18.04 seconds
Started	Apr 28 01:05:19 PM PDT 24
Finished	Apr 28 01:05:38 PM PDT 24
Peak memory	197788 kb
Host	smart-6a1290a1-4499-4d42-82fe-14480d983344
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3879201516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.3879201516
Directory	/workspace/5.uart_tx_rx/latest

Test location	/workspace/coverage/default/50.uart_fifo_reset.533180212
Short name	T249
Test name
Test status
Simulation time	38037381470 ps
CPU time	18.44 seconds
Started	Apr 28 01:08:51 PM PDT 24
Finished	Apr 28 01:09:10 PM PDT 24
Peak memory	200384 kb
Host	smart-76508e59-c887-4b1c-9a0d-25a6bc07bec4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=533180212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.533180212
Directory	/workspace/50.uart_fifo_reset/latest

Test location	/workspace/coverage/default/50.uart_stress_all_with_rand_reset.2248254105
Short name	T860
Test name
Test status
Simulation time	24082572931 ps
CPU time	243.84 seconds
Started	Apr 28 01:08:50 PM PDT 24
Finished	Apr 28 01:12:55 PM PDT 24
Peak memory	208692 kb
Host	smart-045f944d-7904-4078-82a5-c090ad631385
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248254105 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.2248254105
Directory	/workspace/50.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/51.uart_fifo_reset.1919894364
Short name	T801
Test name
Test status
Simulation time	35345169138 ps
CPU time	17.96 seconds
Started	Apr 28 01:08:52 PM PDT 24
Finished	Apr 28 01:09:10 PM PDT 24
Peak memory	200284 kb
Host	smart-8d02b6dd-3d56-4de9-a88c-d0d08a2a0251
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1919894364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.1919894364
Directory	/workspace/51.uart_fifo_reset/latest

Test location	/workspace/coverage/default/51.uart_stress_all_with_rand_reset.194991371
Short name	T981
Test name
Test status
Simulation time	450924994365 ps
CPU time	1269.85 seconds
Started	Apr 28 01:08:51 PM PDT 24
Finished	Apr 28 01:30:01 PM PDT 24
Peak memory	227636 kb
Host	smart-463fcda6-2d3d-4af5-a430-8aca8bbe8abb
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194991371 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.194991371
Directory	/workspace/51.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/52.uart_fifo_reset.1138628974
Short name	T1052
Test name
Test status
Simulation time	114668618197 ps
CPU time	468.12 seconds
Started	Apr 28 01:08:55 PM PDT 24
Finished	Apr 28 01:16:43 PM PDT 24
Peak memory	200352 kb
Host	smart-2929431c-fcc0-4c09-999d-e8642a78a4bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1138628974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.1138628974
Directory	/workspace/52.uart_fifo_reset/latest

Test location	/workspace/coverage/default/52.uart_stress_all_with_rand_reset.2327795928
Short name	T1093
Test name
Test status
Simulation time	107745809945 ps
CPU time	1080.29 seconds
Started	Apr 28 01:08:57 PM PDT 24
Finished	Apr 28 01:26:57 PM PDT 24
Peak memory	216848 kb
Host	smart-4de884ce-f04b-4eb1-a059-b9dc395b3e38
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327795928 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.2327795928
Directory	/workspace/52.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/53.uart_fifo_reset.1394525065
Short name	T220
Test name
Test status
Simulation time	49885335282 ps
CPU time	27.5 seconds
Started	Apr 28 01:08:59 PM PDT 24
Finished	Apr 28 01:09:27 PM PDT 24
Peak memory	200420 kb
Host	smart-c84bfbe1-893b-448d-a0d6-2e3ae244866f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1394525065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1394525065
Directory	/workspace/53.uart_fifo_reset/latest

Test location	/workspace/coverage/default/53.uart_stress_all_with_rand_reset.2310177083
Short name	T59
Test name
Test status
Simulation time	138767176032 ps
CPU time	2083.8 seconds
Started	Apr 28 01:08:56 PM PDT 24
Finished	Apr 28 01:43:40 PM PDT 24
Peak memory	229468 kb
Host	smart-1b762a78-ac3a-4874-b457-a36df70f5a0b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310177083 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.2310177083
Directory	/workspace/53.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/54.uart_stress_all_with_rand_reset.443646648
Short name	T62
Test name
Test status
Simulation time	111437636008 ps
CPU time	2101.7 seconds
Started	Apr 28 01:08:55 PM PDT 24
Finished	Apr 28 01:43:57 PM PDT 24
Peak memory	225000 kb
Host	smart-4fd2ea32-fad8-4990-8015-058fdfdcbb27
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443646648 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.443646648
Directory	/workspace/54.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/55.uart_fifo_reset.1987801512
Short name	T996
Test name
Test status
Simulation time	135294113884 ps
CPU time	185.42 seconds
Started	Apr 28 01:08:55 PM PDT 24
Finished	Apr 28 01:12:01 PM PDT 24
Peak memory	200364 kb
Host	smart-a4e6e243-5d86-4397-ab89-65834b75cfff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1987801512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.1987801512
Directory	/workspace/55.uart_fifo_reset/latest

Test location	/workspace/coverage/default/56.uart_fifo_reset.1311177957
Short name	T1068
Test name
Test status
Simulation time	16087631916 ps
CPU time	17.29 seconds
Started	Apr 28 01:08:55 PM PDT 24
Finished	Apr 28 01:09:13 PM PDT 24
Peak memory	200360 kb
Host	smart-f8d8894b-6f8d-45d6-9170-54bb41ef8ed4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1311177957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1311177957
Directory	/workspace/56.uart_fifo_reset/latest

Test location	/workspace/coverage/default/56.uart_stress_all_with_rand_reset.1813525292
Short name	T223
Test name
Test status
Simulation time	194429508548 ps
CPU time	835.5 seconds
Started	Apr 28 01:08:56 PM PDT 24
Finished	Apr 28 01:22:52 PM PDT 24
Peak memory	216804 kb
Host	smart-61df4e4f-b46c-4cac-b8fc-2d9c0670f39d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813525292 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.1813525292
Directory	/workspace/56.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/57.uart_stress_all_with_rand_reset.1346357415
Short name	T595
Test name
Test status
Simulation time	88050151376 ps
CPU time	296.43 seconds
Started	Apr 28 01:09:00 PM PDT 24
Finished	Apr 28 01:13:57 PM PDT 24
Peak memory	216256 kb
Host	smart-5eda0c35-1048-47a3-a864-b62166d35d66
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346357415 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.1346357415
Directory	/workspace/57.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/58.uart_stress_all_with_rand_reset.701410803
Short name	T482
Test name
Test status
Simulation time	40848217925 ps
CPU time	473.75 seconds
Started	Apr 28 01:09:00 PM PDT 24
Finished	Apr 28 01:16:55 PM PDT 24
Peak memory	215936 kb
Host	smart-5fb13920-a1c8-419c-b613-e5ac6351ede3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701410803 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.701410803
Directory	/workspace/58.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/59.uart_fifo_reset.1749833175
Short name	T454
Test name
Test status
Simulation time	15521284837 ps
CPU time	30.55 seconds
Started	Apr 28 01:09:04 PM PDT 24
Finished	Apr 28 01:09:35 PM PDT 24
Peak memory	200212 kb
Host	smart-7113dcc7-286c-464c-9697-e07b4a67def8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1749833175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1749833175
Directory	/workspace/59.uart_fifo_reset/latest

Test location	/workspace/coverage/default/59.uart_stress_all_with_rand_reset.3199745529
Short name	T111
Test name
Test status
Simulation time	87964336203 ps
CPU time	183.3 seconds
Started	Apr 28 01:09:04 PM PDT 24
Finished	Apr 28 01:12:07 PM PDT 24
Peak memory	217040 kb
Host	smart-d8d3f6aa-2967-49b4-8363-f2522aac57b4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199745529 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.3199745529
Directory	/workspace/59.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.uart_alert_test.1061416180
Short name	T1107
Test name
Test status
Simulation time	11630318 ps
CPU time	0.54 seconds
Started	Apr 28 01:05:25 PM PDT 24
Finished	Apr 28 01:05:26 PM PDT 24
Peak memory	195820 kb
Host	smart-9dacb87c-1506-43ae-8e2f-365bebb4ce6b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061416180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.1061416180
Directory	/workspace/6.uart_alert_test/latest

Test location	/workspace/coverage/default/6.uart_fifo_full.394880418
Short name	T665
Test name
Test status
Simulation time	103092066663 ps
CPU time	207.2 seconds
Started	Apr 28 01:05:26 PM PDT 24
Finished	Apr 28 01:08:54 PM PDT 24
Peak memory	200276 kb
Host	smart-0031a853-9eea-4357-990f-2cfa79ef2652
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=394880418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.394880418
Directory	/workspace/6.uart_fifo_full/latest

Test location	/workspace/coverage/default/6.uart_fifo_overflow.3279180862
Short name	T1133
Test name
Test status
Simulation time	22562815553 ps
CPU time	44.43 seconds
Started	Apr 28 01:05:21 PM PDT 24
Finished	Apr 28 01:06:06 PM PDT 24
Peak memory	200368 kb
Host	smart-45353ff8-3c50-4238-b92b-3419cdae98c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3279180862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.3279180862
Directory	/workspace/6.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/6.uart_fifo_reset.2870333512
Short name	T759
Test name
Test status
Simulation time	61788728726 ps
CPU time	61.49 seconds
Started	Apr 28 01:05:22 PM PDT 24
Finished	Apr 28 01:06:24 PM PDT 24
Peak memory	200412 kb
Host	smart-6c9e008c-333f-444a-a3e5-0095f5cb71af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2870333512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.2870333512
Directory	/workspace/6.uart_fifo_reset/latest

Test location	/workspace/coverage/default/6.uart_intr.1006440894
Short name	T802
Test name
Test status
Simulation time	17672779423 ps
CPU time	21.75 seconds
Started	Apr 28 01:05:21 PM PDT 24
Finished	Apr 28 01:05:44 PM PDT 24
Peak memory	199204 kb
Host	smart-cf6607d5-e092-4a08-a70c-de0033d22251
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006440894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1006440894
Directory	/workspace/6.uart_intr/latest

Test location	/workspace/coverage/default/6.uart_long_xfer_wo_dly.134888450
Short name	T701
Test name
Test status
Simulation time	87939833578 ps
CPU time	212.18 seconds
Started	Apr 28 01:05:21 PM PDT 24
Finished	Apr 28 01:08:54 PM PDT 24
Peak memory	200368 kb
Host	smart-6787b6f1-49ab-4348-aa2a-4feeeef41bf0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=134888450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.134888450
Directory	/workspace/6.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/6.uart_loopback.654452716
Short name	T455
Test name
Test status
Simulation time	4190995150 ps
CPU time	7.09 seconds
Started	Apr 28 01:05:22 PM PDT 24
Finished	Apr 28 01:05:30 PM PDT 24
Peak memory	198472 kb
Host	smart-88d0ac16-7fac-4530-bb07-853b531e37e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=654452716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.654452716
Directory	/workspace/6.uart_loopback/latest

Test location	/workspace/coverage/default/6.uart_noise_filter.1104418988
Short name	T439
Test name
Test status
Simulation time	54428770564 ps
CPU time	88.87 seconds
Started	Apr 28 01:05:23 PM PDT 24
Finished	Apr 28 01:06:53 PM PDT 24
Peak memory	200524 kb
Host	smart-191a671e-5f11-4b05-9e6d-9f8b8548599d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1104418988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.1104418988
Directory	/workspace/6.uart_noise_filter/latest

Test location	/workspace/coverage/default/6.uart_perf.3880817504
Short name	T40
Test name
Test status
Simulation time	14964830894 ps
CPU time	169.88 seconds
Started	Apr 28 01:05:22 PM PDT 24
Finished	Apr 28 01:08:12 PM PDT 24
Peak memory	200308 kb
Host	smart-684ad411-9d49-41af-9151-f3e0dcea44bb
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3880817504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.3880817504
Directory	/workspace/6.uart_perf/latest

Test location	/workspace/coverage/default/6.uart_rx_oversample.2007523666
Short name	T570
Test name
Test status
Simulation time	4914067350 ps
CPU time	48.36 seconds
Started	Apr 28 01:05:23 PM PDT 24
Finished	Apr 28 01:06:12 PM PDT 24
Peak memory	198528 kb
Host	smart-05b24856-a7c3-42f1-bc8e-9d7a4dd0f509
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2007523666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.2007523666
Directory	/workspace/6.uart_rx_oversample/latest

Test location	/workspace/coverage/default/6.uart_rx_parity_err.1593012035
Short name	T526
Test name
Test status
Simulation time	185201646299 ps
CPU time	54.17 seconds
Started	Apr 28 01:05:23 PM PDT 24
Finished	Apr 28 01:06:18 PM PDT 24
Peak memory	200260 kb
Host	smart-32987734-e385-46aa-9a1a-0f246eac67fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1593012035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.1593012035
Directory	/workspace/6.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/6.uart_rx_start_bit_filter.2226630835
Short name	T480
Test name
Test status
Simulation time	5684382364 ps
CPU time	7.07 seconds
Started	Apr 28 01:05:23 PM PDT 24
Finished	Apr 28 01:05:31 PM PDT 24
Peak memory	196656 kb
Host	smart-f77d1506-68e4-4537-b240-6c6d0dee995a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2226630835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.2226630835
Directory	/workspace/6.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/6.uart_smoke.3872833283
Short name	T969
Test name
Test status
Simulation time	315439251 ps
CPU time	0.98 seconds
Started	Apr 28 01:05:23 PM PDT 24
Finished	Apr 28 01:05:25 PM PDT 24
Peak memory	198824 kb
Host	smart-438aa1bf-a47f-494c-845d-dc8a3fbdd208
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3872833283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.3872833283
Directory	/workspace/6.uart_smoke/latest

Test location	/workspace/coverage/default/6.uart_stress_all.1905491936
Short name	T847
Test name
Test status
Simulation time	242079851291 ps
CPU time	1702.57 seconds
Started	Apr 28 01:05:23 PM PDT 24
Finished	Apr 28 01:33:47 PM PDT 24
Peak memory	208868 kb
Host	smart-2e5017c9-c65b-42d8-bf98-e8b618a495fd
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905491936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.1905491936
Directory	/workspace/6.uart_stress_all/latest

Test location	/workspace/coverage/default/6.uart_stress_all_with_rand_reset.39121081
Short name	T115
Test name
Test status
Simulation time	36239802540 ps
CPU time	296.6 seconds
Started	Apr 28 01:05:26 PM PDT 24
Finished	Apr 28 01:10:23 PM PDT 24
Peak memory	216884 kb
Host	smart-fac161c2-16d0-4977-a80e-ec864b6d95bc
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39121081 -assert nopostpro c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.39121081
Directory	/workspace/6.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.uart_tx_ovrd.2807095297
Short name	T336
Test name
Test status
Simulation time	821073018 ps
CPU time	4.31 seconds
Started	Apr 28 01:05:23 PM PDT 24
Finished	Apr 28 01:05:28 PM PDT 24
Peak memory	199932 kb
Host	smart-2f551b3d-1164-46ef-b77b-c8c4d1767ae1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2807095297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.2807095297
Directory	/workspace/6.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/6.uart_tx_rx.2580716184
Short name	T1076
Test name
Test status
Simulation time	98045960259 ps
CPU time	46.05 seconds
Started	Apr 28 01:05:20 PM PDT 24
Finished	Apr 28 01:06:06 PM PDT 24
Peak memory	200380 kb
Host	smart-516af740-f7e7-4ee8-86d9-64d2f9705cdc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2580716184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.2580716184
Directory	/workspace/6.uart_tx_rx/latest

Test location	/workspace/coverage/default/60.uart_fifo_reset.3047839632
Short name	T231
Test name
Test status
Simulation time	20775493560 ps
CPU time	10.26 seconds
Started	Apr 28 01:09:00 PM PDT 24
Finished	Apr 28 01:09:11 PM PDT 24
Peak memory	200168 kb
Host	smart-57bdcc57-0ef2-4fa2-b8af-f934b4a5efe2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3047839632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.3047839632
Directory	/workspace/60.uart_fifo_reset/latest

Test location	/workspace/coverage/default/60.uart_stress_all_with_rand_reset.3648602200
Short name	T958
Test name
Test status
Simulation time	26619182777 ps
CPU time	322.5 seconds
Started	Apr 28 01:09:03 PM PDT 24
Finished	Apr 28 01:14:26 PM PDT 24
Peak memory	215960 kb
Host	smart-5c057ed1-1e6d-43fc-9451-5149e6343af5
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648602200 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.3648602200
Directory	/workspace/60.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/61.uart_fifo_reset.2083110380
Short name	T137
Test name
Test status
Simulation time	13440695913 ps
CPU time	21.57 seconds
Started	Apr 28 01:09:00 PM PDT 24
Finished	Apr 28 01:09:22 PM PDT 24
Peak memory	200424 kb
Host	smart-2eacd7d0-4b6a-4a32-beda-7f6a21928d6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2083110380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.2083110380
Directory	/workspace/61.uart_fifo_reset/latest

Test location	/workspace/coverage/default/61.uart_stress_all_with_rand_reset.473245761
Short name	T33
Test name
Test status
Simulation time	17077950047 ps
CPU time	213.35 seconds
Started	Apr 28 01:09:02 PM PDT 24
Finished	Apr 28 01:12:36 PM PDT 24
Peak memory	212408 kb
Host	smart-1c7a13eb-4826-44f7-8b9a-f3787f819acb
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473245761 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.473245761
Directory	/workspace/61.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/62.uart_fifo_reset.2397693453
Short name	T1060
Test name
Test status
Simulation time	141380285880 ps
CPU time	117.55 seconds
Started	Apr 28 01:09:05 PM PDT 24
Finished	Apr 28 01:11:03 PM PDT 24
Peak memory	199976 kb
Host	smart-c0bd4336-62cf-4a3e-9751-f953fb7df9f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2397693453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.2397693453
Directory	/workspace/62.uart_fifo_reset/latest

Test location	/workspace/coverage/default/62.uart_stress_all_with_rand_reset.2530996974
Short name	T671
Test name
Test status
Simulation time	22449647237 ps
CPU time	162.54 seconds
Started	Apr 28 01:09:04 PM PDT 24
Finished	Apr 28 01:11:47 PM PDT 24
Peak memory	216484 kb
Host	smart-ee4ea08a-1419-4c1c-b547-aaa4fddb6329
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530996974 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.2530996974
Directory	/workspace/62.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/63.uart_fifo_reset.24806038
Short name	T1148
Test name
Test status
Simulation time	175223952661 ps
CPU time	45.23 seconds
Started	Apr 28 01:09:00 PM PDT 24
Finished	Apr 28 01:09:46 PM PDT 24
Peak memory	200268 kb
Host	smart-932c5933-7fee-42b7-923a-cbc0276a8597
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=24806038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.24806038
Directory	/workspace/63.uart_fifo_reset/latest

Test location	/workspace/coverage/default/63.uart_stress_all_with_rand_reset.2730654109
Short name	T503
Test name
Test status
Simulation time	104497163603 ps
CPU time	916.37 seconds
Started	Apr 28 01:09:00 PM PDT 24
Finished	Apr 28 01:24:17 PM PDT 24
Peak memory	225260 kb
Host	smart-7c87bd85-6a35-44ce-ab15-3eb1c68cf8e3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730654109 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.2730654109
Directory	/workspace/63.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/64.uart_fifo_reset.2078153591
Short name	T1174
Test name
Test status
Simulation time	22608777004 ps
CPU time	24.14 seconds
Started	Apr 28 01:09:02 PM PDT 24
Finished	Apr 28 01:09:26 PM PDT 24
Peak memory	200380 kb
Host	smart-dbcdbb89-dc62-4271-ab7f-3b6bc79df202
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2078153591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.2078153591
Directory	/workspace/64.uart_fifo_reset/latest

Test location	/workspace/coverage/default/64.uart_stress_all_with_rand_reset.4189006893
Short name	T895
Test name
Test status
Simulation time	154308693655 ps
CPU time	980.06 seconds
Started	Apr 28 01:09:05 PM PDT 24
Finished	Apr 28 01:25:25 PM PDT 24
Peak memory	225020 kb
Host	smart-b99f4dbf-fb79-4a19-a6d1-71b679ae05d5
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189006893 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.4189006893
Directory	/workspace/64.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/65.uart_fifo_reset.4251536452
Short name	T522
Test name
Test status
Simulation time	38986378648 ps
CPU time	11.84 seconds
Started	Apr 28 01:09:01 PM PDT 24
Finished	Apr 28 01:09:14 PM PDT 24
Peak memory	200452 kb
Host	smart-d0869a24-5084-43ce-aa9d-76cb2a607dfd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4251536452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.4251536452
Directory	/workspace/65.uart_fifo_reset/latest

Test location	/workspace/coverage/default/65.uart_stress_all_with_rand_reset.2978886606
Short name	T314
Test name
Test status
Simulation time	79017117977 ps
CPU time	1215.3 seconds
Started	Apr 28 01:09:02 PM PDT 24
Finished	Apr 28 01:29:18 PM PDT 24
Peak memory	216976 kb
Host	smart-85a0ef74-a709-4137-a524-2f3b9d5c05e8
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978886606 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.2978886606
Directory	/workspace/65.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/66.uart_fifo_reset.2446908558
Short name	T435
Test name
Test status
Simulation time	35852164525 ps
CPU time	54.86 seconds
Started	Apr 28 01:09:02 PM PDT 24
Finished	Apr 28 01:09:57 PM PDT 24
Peak memory	200228 kb
Host	smart-43692478-8e2d-4e4f-8286-8bb55c4c0ef8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2446908558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.2446908558
Directory	/workspace/66.uart_fifo_reset/latest

Test location	/workspace/coverage/default/66.uart_stress_all_with_rand_reset.1011850172
Short name	T1126
Test name
Test status
Simulation time	171020184709 ps
CPU time	503.62 seconds
Started	Apr 28 01:09:02 PM PDT 24
Finished	Apr 28 01:17:27 PM PDT 24
Peak memory	216876 kb
Host	smart-4449068e-01b7-4ebe-8635-37cf3c66c4e2
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011850172 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.1011850172
Directory	/workspace/66.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/67.uart_fifo_reset.1180802728
Short name	T261
Test name
Test status
Simulation time	18676424803 ps
CPU time	29.91 seconds
Started	Apr 28 01:09:13 PM PDT 24
Finished	Apr 28 01:09:43 PM PDT 24
Peak memory	200436 kb
Host	smart-bbd2b4f7-68e4-4059-a30e-eeec72f65e4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1180802728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.1180802728
Directory	/workspace/67.uart_fifo_reset/latest

Test location	/workspace/coverage/default/67.uart_stress_all_with_rand_reset.4114415983
Short name	T852
Test name
Test status
Simulation time	70081862676 ps
CPU time	224.46 seconds
Started	Apr 28 01:09:12 PM PDT 24
Finished	Apr 28 01:12:57 PM PDT 24
Peak memory	216884 kb
Host	smart-7dfd1e32-9f45-405f-a53d-cfe2f88d92f2
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114415983 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.4114415983
Directory	/workspace/67.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/68.uart_fifo_reset.3603871948
Short name	T152
Test name
Test status
Simulation time	89548205078 ps
CPU time	130.22 seconds
Started	Apr 28 01:09:04 PM PDT 24
Finished	Apr 28 01:11:15 PM PDT 24
Peak memory	200268 kb
Host	smart-ecf8f697-6863-4bb3-a4e0-2a24ab59ea8a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3603871948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.3603871948
Directory	/workspace/68.uart_fifo_reset/latest

Test location	/workspace/coverage/default/68.uart_stress_all_with_rand_reset.2426283006
Short name	T302
Test name
Test status
Simulation time	48040578142 ps
CPU time	145.99 seconds
Started	Apr 28 01:09:04 PM PDT 24
Finished	Apr 28 01:11:31 PM PDT 24
Peak memory	208540 kb
Host	smart-8a5ea1a9-1d43-40bf-993b-29e1acef1662
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426283006 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.2426283006
Directory	/workspace/68.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/69.uart_fifo_reset.2424578495
Short name	T588
Test name
Test status
Simulation time	32014651729 ps
CPU time	44.34 seconds
Started	Apr 28 01:09:05 PM PDT 24
Finished	Apr 28 01:09:50 PM PDT 24
Peak memory	200432 kb
Host	smart-8cf10efa-c729-4636-88d9-52c3d50ac53a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2424578495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.2424578495
Directory	/workspace/69.uart_fifo_reset/latest

Test location	/workspace/coverage/default/7.uart_alert_test.2515022606
Short name	T348
Test name
Test status
Simulation time	64047622 ps
CPU time	0.58 seconds
Started	Apr 28 01:05:28 PM PDT 24
Finished	Apr 28 01:05:29 PM PDT 24
Peak memory	195656 kb
Host	smart-e57a85b7-907b-40e8-8462-9624454f5112
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515022606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2515022606
Directory	/workspace/7.uart_alert_test/latest

Test location	/workspace/coverage/default/7.uart_fifo_full.1239315453
Short name	T1067
Test name
Test status
Simulation time	70955213308 ps
CPU time	31.83 seconds
Started	Apr 28 01:05:25 PM PDT 24
Finished	Apr 28 01:05:58 PM PDT 24
Peak memory	200392 kb
Host	smart-bb0df5fa-701d-4aeb-9151-7ab2e590d261
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1239315453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.1239315453
Directory	/workspace/7.uart_fifo_full/latest

Test location	/workspace/coverage/default/7.uart_fifo_overflow.2905848293
Short name	T819
Test name
Test status
Simulation time	51957280069 ps
CPU time	21.14 seconds
Started	Apr 28 01:05:22 PM PDT 24
Finished	Apr 28 01:05:44 PM PDT 24
Peak memory	199592 kb
Host	smart-29ec20c2-0af2-40e7-b4d4-2f5478cbfd26
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2905848293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2905848293
Directory	/workspace/7.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/7.uart_fifo_reset.1565171386
Short name	T532
Test name
Test status
Simulation time	23747233724 ps
CPU time	22.56 seconds
Started	Apr 28 01:05:22 PM PDT 24
Finished	Apr 28 01:05:45 PM PDT 24
Peak memory	200192 kb
Host	smart-a8a20dd5-467d-4c02-9146-ce6c4540a261
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1565171386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.1565171386
Directory	/workspace/7.uart_fifo_reset/latest

Test location	/workspace/coverage/default/7.uart_intr.2366143609
Short name	T1101
Test name
Test status
Simulation time	6506102884 ps
CPU time	11.33 seconds
Started	Apr 28 01:05:20 PM PDT 24
Finished	Apr 28 01:05:32 PM PDT 24
Peak memory	197096 kb
Host	smart-3e2514cd-27c1-4384-b1be-4196fe79a6c7
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366143609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.2366143609
Directory	/workspace/7.uart_intr/latest

Test location	/workspace/coverage/default/7.uart_long_xfer_wo_dly.369765685
Short name	T745
Test name
Test status
Simulation time	133994212354 ps
CPU time	94.12 seconds
Started	Apr 28 01:05:25 PM PDT 24
Finished	Apr 28 01:07:00 PM PDT 24
Peak memory	200428 kb
Host	smart-e545f729-8d98-43e9-9e70-6c9ef3c9a265
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=369765685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.369765685
Directory	/workspace/7.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/7.uart_loopback.1414211246
Short name	T906
Test name
Test status
Simulation time	7125012471 ps
CPU time	10.51 seconds
Started	Apr 28 01:05:24 PM PDT 24
Finished	Apr 28 01:05:35 PM PDT 24
Peak memory	200316 kb
Host	smart-d1e7d050-ba2d-4cb8-bafb-8fb04dafda6d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1414211246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.1414211246
Directory	/workspace/7.uart_loopback/latest

Test location	/workspace/coverage/default/7.uart_noise_filter.1601430480
Short name	T320
Test name
Test status
Simulation time	13845917646 ps
CPU time	13.07 seconds
Started	Apr 28 01:05:22 PM PDT 24
Finished	Apr 28 01:05:36 PM PDT 24
Peak memory	200236 kb
Host	smart-e725b1e7-0877-4afd-8b3f-648edd9da4cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1601430480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.1601430480
Directory	/workspace/7.uart_noise_filter/latest

Test location	/workspace/coverage/default/7.uart_perf.515084265
Short name	T600
Test name
Test status
Simulation time	9400869448 ps
CPU time	114.71 seconds
Started	Apr 28 01:05:26 PM PDT 24
Finished	Apr 28 01:07:22 PM PDT 24
Peak memory	200272 kb
Host	smart-5636a17f-2750-4d39-8aa9-3d12467331c7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=515084265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.515084265
Directory	/workspace/7.uart_perf/latest

Test location	/workspace/coverage/default/7.uart_rx_oversample.3116272150
Short name	T1155
Test name
Test status
Simulation time	2754776054 ps
CPU time	22.57 seconds
Started	Apr 28 01:05:21 PM PDT 24
Finished	Apr 28 01:05:44 PM PDT 24
Peak memory	198444 kb
Host	smart-45da50b1-9642-4661-ac0b-b21a1759679a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3116272150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.3116272150
Directory	/workspace/7.uart_rx_oversample/latest

Test location	/workspace/coverage/default/7.uart_rx_parity_err.3713125087
Short name	T1075
Test name
Test status
Simulation time	147785251396 ps
CPU time	249.76 seconds
Started	Apr 28 01:05:24 PM PDT 24
Finished	Apr 28 01:09:35 PM PDT 24
Peak memory	200276 kb
Host	smart-ac5e653c-844a-4214-93a4-0b5563952e6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3713125087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.3713125087
Directory	/workspace/7.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/7.uart_rx_start_bit_filter.2125146062
Short name	T406
Test name
Test status
Simulation time	1969564031 ps
CPU time	3.81 seconds
Started	Apr 28 01:05:26 PM PDT 24
Finished	Apr 28 01:05:30 PM PDT 24
Peak memory	195812 kb
Host	smart-e8393746-9e53-44b3-ad43-d60caf93cf26
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2125146062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.2125146062
Directory	/workspace/7.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/7.uart_smoke.3572812299
Short name	T296
Test name
Test status
Simulation time	265574765 ps
CPU time	1.51 seconds
Started	Apr 28 01:05:24 PM PDT 24
Finished	Apr 28 01:05:26 PM PDT 24
Peak memory	198880 kb
Host	smart-6fcc9a32-6053-4af9-8c8c-e0806ebf0c80
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3572812299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.3572812299
Directory	/workspace/7.uart_smoke/latest

Test location	/workspace/coverage/default/7.uart_stress_all.73305639
Short name	T499
Test name
Test status
Simulation time	89666488128 ps
CPU time	1245.9 seconds
Started	Apr 28 01:05:21 PM PDT 24
Finished	Apr 28 01:26:07 PM PDT 24
Peak memory	200320 kb
Host	smart-1f22772d-8d49-4cb0-8f13-a0ccfa87f478
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73305639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.73305639
Directory	/workspace/7.uart_stress_all/latest

Test location	/workspace/coverage/default/7.uart_stress_all_with_rand_reset.1603135886
Short name	T888
Test name
Test status
Simulation time	29714068467 ps
CPU time	604.42 seconds
Started	Apr 28 01:05:25 PM PDT 24
Finished	Apr 28 01:15:31 PM PDT 24
Peak memory	216064 kb
Host	smart-31959993-384c-4f9e-bd4b-566f54025263
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603135886 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.1603135886
Directory	/workspace/7.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.uart_tx_ovrd.1249678613
Short name	T863
Test name
Test status
Simulation time	771931733 ps
CPU time	1.85 seconds
Started	Apr 28 01:05:25 PM PDT 24
Finished	Apr 28 01:05:27 PM PDT 24
Peak memory	199180 kb
Host	smart-5aca8294-123a-4bb8-bd7b-ab4f601c35ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1249678613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.1249678613
Directory	/workspace/7.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/7.uart_tx_rx.1580885215
Short name	T691
Test name
Test status
Simulation time	90879957170 ps
CPU time	122.82 seconds
Started	Apr 28 01:05:25 PM PDT 24
Finished	Apr 28 01:07:29 PM PDT 24
Peak memory	200284 kb
Host	smart-2323872e-4945-491a-8f5d-bec1a6edbff5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1580885215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.1580885215
Directory	/workspace/7.uart_tx_rx/latest

Test location	/workspace/coverage/default/70.uart_fifo_reset.506461610
Short name	T733
Test name
Test status
Simulation time	34869773812 ps
CPU time	17.71 seconds
Started	Apr 28 01:09:13 PM PDT 24
Finished	Apr 28 01:09:32 PM PDT 24
Peak memory	200376 kb
Host	smart-18f7e9b6-e50a-43c2-b800-f831e86bee6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=506461610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.506461610
Directory	/workspace/70.uart_fifo_reset/latest

Test location	/workspace/coverage/default/70.uart_stress_all_with_rand_reset.2619675924
Short name	T859
Test name
Test status
Simulation time	215423545092 ps
CPU time	827.71 seconds
Started	Apr 28 01:09:12 PM PDT 24
Finished	Apr 28 01:23:00 PM PDT 24
Peak memory	217060 kb
Host	smart-1202bbfd-46e2-4c1e-b462-110aa5048967
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619675924 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.2619675924
Directory	/workspace/70.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/71.uart_fifo_reset.2146373884
Short name	T928
Test name
Test status
Simulation time	34623133556 ps
CPU time	17.18 seconds
Started	Apr 28 01:09:05 PM PDT 24
Finished	Apr 28 01:09:23 PM PDT 24
Peak memory	200440 kb
Host	smart-5f4f7c5e-0ff4-4fbe-bbb3-c8d1eb171d90
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2146373884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.2146373884
Directory	/workspace/71.uart_fifo_reset/latest

Test location	/workspace/coverage/default/71.uart_stress_all_with_rand_reset.751908812
Short name	T30
Test name
Test status
Simulation time	15493428842 ps
CPU time	141.02 seconds
Started	Apr 28 01:09:05 PM PDT 24
Finished	Apr 28 01:11:26 PM PDT 24
Peak memory	216420 kb
Host	smart-186ddde0-5bfa-4168-bbe1-8ca375cd67e1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751908812 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.751908812
Directory	/workspace/71.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/72.uart_fifo_reset.4282970514
Short name	T227
Test name
Test status
Simulation time	100068763331 ps
CPU time	107.81 seconds
Started	Apr 28 01:09:06 PM PDT 24
Finished	Apr 28 01:10:54 PM PDT 24
Peak memory	200384 kb
Host	smart-67258223-af64-4650-99d5-39b231fcdd08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4282970514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.4282970514
Directory	/workspace/72.uart_fifo_reset/latest

Test location	/workspace/coverage/default/72.uart_stress_all_with_rand_reset.598022564
Short name	T29
Test name
Test status
Simulation time	69152992041 ps
CPU time	1132.75 seconds
Started	Apr 28 01:09:05 PM PDT 24
Finished	Apr 28 01:27:59 PM PDT 24
Peak memory	217028 kb
Host	smart-9b138c4c-4bf1-409a-8e2e-a4cf9d88a677
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598022564 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.598022564
Directory	/workspace/72.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/73.uart_fifo_reset.2891921689
Short name	T672
Test name
Test status
Simulation time	75165562496 ps
CPU time	107.3 seconds
Started	Apr 28 01:09:05 PM PDT 24
Finished	Apr 28 01:10:53 PM PDT 24
Peak memory	200480 kb
Host	smart-407edfc7-1cbf-4d15-bb99-895bf3b6936b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2891921689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2891921689
Directory	/workspace/73.uart_fifo_reset/latest

Test location	/workspace/coverage/default/73.uart_stress_all_with_rand_reset.3346438199
Short name	T502
Test name
Test status
Simulation time	51316769313 ps
CPU time	273.8 seconds
Started	Apr 28 01:09:05 PM PDT 24
Finished	Apr 28 01:13:40 PM PDT 24
Peak memory	208740 kb
Host	smart-aa8717d5-6607-41bb-bf50-b576fbc2bfec
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346438199 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.3346438199
Directory	/workspace/73.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/74.uart_fifo_reset.2344581352
Short name	T442
Test name
Test status
Simulation time	30394088055 ps
CPU time	17.93 seconds
Started	Apr 28 01:09:13 PM PDT 24
Finished	Apr 28 01:09:32 PM PDT 24
Peak memory	200276 kb
Host	smart-4fb5aa96-b5fc-4392-b65b-436ce8ea5707
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2344581352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.2344581352
Directory	/workspace/74.uart_fifo_reset/latest

Test location	/workspace/coverage/default/74.uart_stress_all_with_rand_reset.3452662804
Short name	T636
Test name
Test status
Simulation time	26951648937 ps
CPU time	378.56 seconds
Started	Apr 28 01:09:13 PM PDT 24
Finished	Apr 28 01:15:32 PM PDT 24
Peak memory	216832 kb
Host	smart-4f56b883-c507-4402-889b-ebad170a0c24
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452662804 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.3452662804
Directory	/workspace/74.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/75.uart_fifo_reset.313686257
Short name	T205
Test name
Test status
Simulation time	20360354214 ps
CPU time	34 seconds
Started	Apr 28 01:09:12 PM PDT 24
Finished	Apr 28 01:09:47 PM PDT 24
Peak memory	200344 kb
Host	smart-ccb8f837-b996-4eeb-a71c-5c97cac2de17
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=313686257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.313686257
Directory	/workspace/75.uart_fifo_reset/latest

Test location	/workspace/coverage/default/75.uart_stress_all_with_rand_reset.926677768
Short name	T110
Test name
Test status
Simulation time	76652616462 ps
CPU time	848.67 seconds
Started	Apr 28 01:09:14 PM PDT 24
Finished	Apr 28 01:23:23 PM PDT 24
Peak memory	225108 kb
Host	smart-066766d4-3f29-4537-ae69-c02ea809e75d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926677768 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.926677768
Directory	/workspace/75.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/76.uart_fifo_reset.2892614603
Short name	T1007
Test name
Test status
Simulation time	24304836100 ps
CPU time	36.23 seconds
Started	Apr 28 01:09:13 PM PDT 24
Finished	Apr 28 01:09:50 PM PDT 24
Peak memory	200436 kb
Host	smart-3720748f-8596-4fa3-8f8f-401290039d0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2892614603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.2892614603
Directory	/workspace/76.uart_fifo_reset/latest

Test location	/workspace/coverage/default/76.uart_stress_all_with_rand_reset.2539108324
Short name	T112
Test name
Test status
Simulation time	29199212039 ps
CPU time	298.71 seconds
Started	Apr 28 01:09:12 PM PDT 24
Finished	Apr 28 01:14:12 PM PDT 24
Peak memory	216476 kb
Host	smart-e5f1f22f-f7fd-4399-96da-b6bebf043338
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539108324 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.2539108324
Directory	/workspace/76.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/77.uart_fifo_reset.687976163
Short name	T670
Test name
Test status
Simulation time	5775128442 ps
CPU time	12.56 seconds
Started	Apr 28 01:09:15 PM PDT 24
Finished	Apr 28 01:09:28 PM PDT 24
Peak memory	200356 kb
Host	smart-2ac91be6-b76f-4c49-9b05-7b41cb4032f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=687976163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.687976163
Directory	/workspace/77.uart_fifo_reset/latest

Test location	/workspace/coverage/default/77.uart_stress_all_with_rand_reset.25239260
Short name	T237
Test name
Test status
Simulation time	409547177280 ps
CPU time	488.07 seconds
Started	Apr 28 01:09:16 PM PDT 24
Finished	Apr 28 01:17:25 PM PDT 24
Peak memory	229064 kb
Host	smart-a8797a57-a1f7-4699-9ea9-50aabf125583
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25239260 -assert nopostpro c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.25239260
Directory	/workspace/77.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/78.uart_fifo_reset.810147253
Short name	T322
Test name
Test status
Simulation time	181472522974 ps
CPU time	37.82 seconds
Started	Apr 28 01:09:12 PM PDT 24
Finished	Apr 28 01:09:50 PM PDT 24
Peak memory	200264 kb
Host	smart-3960fa4f-03b8-44f4-9ab5-531014214ba0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=810147253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.810147253
Directory	/workspace/78.uart_fifo_reset/latest

Test location	/workspace/coverage/default/78.uart_stress_all_with_rand_reset.269022326
Short name	T313
Test name
Test status
Simulation time	16366602936 ps
CPU time	199.04 seconds
Started	Apr 28 01:09:13 PM PDT 24
Finished	Apr 28 01:12:32 PM PDT 24
Peak memory	217000 kb
Host	smart-bd5e7de7-5090-49a2-998b-06924ea33679
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269022326 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.269022326
Directory	/workspace/78.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/79.uart_fifo_reset.287812427
Short name	T1072
Test name
Test status
Simulation time	13558929425 ps
CPU time	23.53 seconds
Started	Apr 28 01:09:15 PM PDT 24
Finished	Apr 28 01:09:39 PM PDT 24
Peak memory	200392 kb
Host	smart-fa1a223d-9fdf-4467-851a-9d2943033807
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=287812427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.287812427
Directory	/workspace/79.uart_fifo_reset/latest

Test location	/workspace/coverage/default/79.uart_stress_all_with_rand_reset.4183888518
Short name	T248
Test name
Test status
Simulation time	70942965901 ps
CPU time	883.22 seconds
Started	Apr 28 01:09:17 PM PDT 24
Finished	Apr 28 01:24:01 PM PDT 24
Peak memory	216720 kb
Host	smart-b0572f6d-7bd1-4256-8a85-8338ad46c34b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183888518 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.4183888518
Directory	/workspace/79.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/8.uart_alert_test.2572565662
Short name	T1078
Test name
Test status
Simulation time	14219928 ps
CPU time	0.54 seconds
Started	Apr 28 01:05:27 PM PDT 24
Finished	Apr 28 01:05:28 PM PDT 24
Peak memory	195700 kb
Host	smart-b2514412-bf38-468a-9d6b-9871faae9fec
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572565662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.2572565662
Directory	/workspace/8.uart_alert_test/latest

Test location	/workspace/coverage/default/8.uart_fifo_full.754264050
Short name	T876
Test name
Test status
Simulation time	139235703153 ps
CPU time	26.83 seconds
Started	Apr 28 01:05:30 PM PDT 24
Finished	Apr 28 01:05:57 PM PDT 24
Peak memory	200224 kb
Host	smart-bbcf5e01-f345-4c45-8fa8-91ae6f1b729d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=754264050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.754264050
Directory	/workspace/8.uart_fifo_full/latest

Test location	/workspace/coverage/default/8.uart_fifo_overflow.3893136232
Short name	T659
Test name
Test status
Simulation time	61382110532 ps
CPU time	29.4 seconds
Started	Apr 28 01:05:28 PM PDT 24
Finished	Apr 28 01:05:58 PM PDT 24
Peak memory	200368 kb
Host	smart-f838ce5d-7d85-4403-b264-a51566195dfd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3893136232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.3893136232
Directory	/workspace/8.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/8.uart_fifo_reset.843456692
Short name	T846
Test name
Test status
Simulation time	20417813972 ps
CPU time	35.24 seconds
Started	Apr 28 01:05:27 PM PDT 24
Finished	Apr 28 01:06:03 PM PDT 24
Peak memory	200332 kb
Host	smart-69b875fc-ed49-4eab-a397-0a1e1bb059fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=843456692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.843456692
Directory	/workspace/8.uart_fifo_reset/latest

Test location	/workspace/coverage/default/8.uart_intr.4071924501
Short name	T732
Test name
Test status
Simulation time	156991335749 ps
CPU time	233.9 seconds
Started	Apr 28 01:05:27 PM PDT 24
Finished	Apr 28 01:09:21 PM PDT 24
Peak memory	197248 kb
Host	smart-d6e2e2ea-d5a3-4274-b3f9-961751c5a449
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071924501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.4071924501
Directory	/workspace/8.uart_intr/latest

Test location	/workspace/coverage/default/8.uart_long_xfer_wo_dly.2492215267
Short name	T257
Test name
Test status
Simulation time	116217397767 ps
CPU time	271.31 seconds
Started	Apr 28 01:05:27 PM PDT 24
Finished	Apr 28 01:09:59 PM PDT 24
Peak memory	200436 kb
Host	smart-2c5dd5e2-41b2-44a6-a39a-bfe4ef653905
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2492215267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.2492215267
Directory	/workspace/8.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/8.uart_loopback.2926618044
Short name	T422
Test name
Test status
Simulation time	6000430540 ps
CPU time	6.28 seconds
Started	Apr 28 01:05:28 PM PDT 24
Finished	Apr 28 01:05:35 PM PDT 24
Peak memory	200376 kb
Host	smart-817e6619-71b7-445b-994a-7162342872fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2926618044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.2926618044
Directory	/workspace/8.uart_loopback/latest

Test location	/workspace/coverage/default/8.uart_noise_filter.2492957673
Short name	T826
Test name
Test status
Simulation time	55139632334 ps
CPU time	24.45 seconds
Started	Apr 28 01:05:25 PM PDT 24
Finished	Apr 28 01:05:50 PM PDT 24
Peak memory	199508 kb
Host	smart-2cc6729e-6cd4-415c-aef3-cf5d3524c4af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2492957673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.2492957673
Directory	/workspace/8.uart_noise_filter/latest

Test location	/workspace/coverage/default/8.uart_perf.3327024611
Short name	T1035
Test name
Test status
Simulation time	17206690415 ps
CPU time	196.04 seconds
Started	Apr 28 01:05:27 PM PDT 24
Finished	Apr 28 01:08:44 PM PDT 24
Peak memory	200300 kb
Host	smart-bd5da6f9-e3c9-41a1-a79c-1e68edd5c781
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3327024611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3327024611
Directory	/workspace/8.uart_perf/latest

Test location	/workspace/coverage/default/8.uart_rx_oversample.3940264411
Short name	T786
Test name
Test status
Simulation time	3685179735 ps
CPU time	36.04 seconds
Started	Apr 28 01:05:29 PM PDT 24
Finished	Apr 28 01:06:06 PM PDT 24
Peak memory	198640 kb
Host	smart-15505f46-57ff-4f75-97ca-ccca0fd3ac20
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3940264411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.3940264411
Directory	/workspace/8.uart_rx_oversample/latest

Test location	/workspace/coverage/default/8.uart_rx_parity_err.4238275887
Short name	T868
Test name
Test status
Simulation time	52446505656 ps
CPU time	79.02 seconds
Started	Apr 28 01:05:29 PM PDT 24
Finished	Apr 28 01:06:49 PM PDT 24
Peak memory	199212 kb
Host	smart-a91ee465-9627-4497-b32f-2243c75a7eb2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4238275887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.4238275887
Directory	/workspace/8.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/8.uart_rx_start_bit_filter.1264623123
Short name	T872
Test name
Test status
Simulation time	2080731439 ps
CPU time	2.75 seconds
Started	Apr 28 01:05:29 PM PDT 24
Finished	Apr 28 01:05:32 PM PDT 24
Peak memory	195832 kb
Host	smart-539d3de1-90ac-484e-927e-0a329f3e38ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1264623123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1264623123
Directory	/workspace/8.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/8.uart_smoke.3040391035
Short name	T355
Test name
Test status
Simulation time	147398472 ps
CPU time	0.87 seconds
Started	Apr 28 01:05:29 PM PDT 24
Finished	Apr 28 01:05:30 PM PDT 24
Peak memory	197436 kb
Host	smart-bef58a8b-45c7-4d4b-8199-1c3caf81abbc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3040391035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.3040391035
Directory	/workspace/8.uart_smoke/latest

Test location	/workspace/coverage/default/8.uart_stress_all_with_rand_reset.2318460614
Short name	T266
Test name
Test status
Simulation time	122158692797 ps
CPU time	1255.23 seconds
Started	Apr 28 01:05:30 PM PDT 24
Finished	Apr 28 01:26:26 PM PDT 24
Peak memory	225328 kb
Host	smart-16b8f662-f8b4-4703-963e-e46a865bbd5c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318460614 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.2318460614
Directory	/workspace/8.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/8.uart_tx_ovrd.2996849556
Short name	T742
Test name
Test status
Simulation time	1263538759 ps
CPU time	2.42 seconds
Started	Apr 28 01:05:28 PM PDT 24
Finished	Apr 28 01:05:31 PM PDT 24
Peak memory	200332 kb
Host	smart-96f53060-7d7e-4814-afd9-b2ba0874b609
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2996849556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.2996849556
Directory	/workspace/8.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/8.uart_tx_rx.427301824
Short name	T1109
Test name
Test status
Simulation time	32046368661 ps
CPU time	11.54 seconds
Started	Apr 28 01:05:26 PM PDT 24
Finished	Apr 28 01:05:38 PM PDT 24
Peak memory	198676 kb
Host	smart-c3ee74f4-5308-402d-9207-f8f8e2daa4ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=427301824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.427301824
Directory	/workspace/8.uart_tx_rx/latest

Test location	/workspace/coverage/default/80.uart_fifo_reset.864161962
Short name	T933
Test name
Test status
Simulation time	12898603695 ps
CPU time	23.7 seconds
Started	Apr 28 01:09:16 PM PDT 24
Finished	Apr 28 01:09:41 PM PDT 24
Peak memory	200444 kb
Host	smart-d61fb609-a411-4ec9-b6e0-9cd16fa7e46d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=864161962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.864161962
Directory	/workspace/80.uart_fifo_reset/latest

Test location	/workspace/coverage/default/81.uart_fifo_reset.1942671155
Short name	T192
Test name
Test status
Simulation time	61941341229 ps
CPU time	94.64 seconds
Started	Apr 28 01:09:14 PM PDT 24
Finished	Apr 28 01:10:50 PM PDT 24
Peak memory	200400 kb
Host	smart-612b3aff-82a0-46ee-b6d3-f718627ce487
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1942671155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.1942671155
Directory	/workspace/81.uart_fifo_reset/latest

Test location	/workspace/coverage/default/81.uart_stress_all_with_rand_reset.2580460744
Short name	T176
Test name
Test status
Simulation time	195137849474 ps
CPU time	480.41 seconds
Started	Apr 28 01:09:18 PM PDT 24
Finished	Apr 28 01:17:19 PM PDT 24
Peak memory	225228 kb
Host	smart-9c634808-e186-457f-8b7d-916c750809b8
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580460744 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.2580460744
Directory	/workspace/81.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/82.uart_fifo_reset.3846777336
Short name	T183
Test name
Test status
Simulation time	45820960570 ps
CPU time	80.12 seconds
Started	Apr 28 01:09:15 PM PDT 24
Finished	Apr 28 01:10:36 PM PDT 24
Peak memory	200444 kb
Host	smart-ccb22e1f-fe30-4da6-b077-27d310f8afd7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3846777336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.3846777336
Directory	/workspace/82.uart_fifo_reset/latest

Test location	/workspace/coverage/default/83.uart_fifo_reset.2658668960
Short name	T571
Test name
Test status
Simulation time	48131846953 ps
CPU time	55.74 seconds
Started	Apr 28 01:09:21 PM PDT 24
Finished	Apr 28 01:10:17 PM PDT 24
Peak memory	200432 kb
Host	smart-8056845f-421a-47f2-84fd-aba08fa08898
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2658668960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.2658668960
Directory	/workspace/83.uart_fifo_reset/latest

Test location	/workspace/coverage/default/83.uart_stress_all_with_rand_reset.3228306335
Short name	T373
Test name
Test status
Simulation time	50418104437 ps
CPU time	798.41 seconds
Started	Apr 28 01:09:16 PM PDT 24
Finished	Apr 28 01:22:35 PM PDT 24
Peak memory	216988 kb
Host	smart-998cb66b-3280-4f9d-8c01-c9884ee67be1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228306335 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.3228306335
Directory	/workspace/83.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/84.uart_fifo_reset.3916618435
Short name	T765
Test name
Test status
Simulation time	130440486821 ps
CPU time	105.17 seconds
Started	Apr 28 01:09:16 PM PDT 24
Finished	Apr 28 01:11:02 PM PDT 24
Peak memory	200368 kb
Host	smart-efd2e7a0-f9e1-478d-8c03-f801cd28aa72
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3916618435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.3916618435
Directory	/workspace/84.uart_fifo_reset/latest

Test location	/workspace/coverage/default/84.uart_stress_all_with_rand_reset.3568015347
Short name	T736
Test name
Test status
Simulation time	31652715955 ps
CPU time	251.95 seconds
Started	Apr 28 01:09:21 PM PDT 24
Finished	Apr 28 01:13:34 PM PDT 24
Peak memory	215148 kb
Host	smart-43326782-dc2e-48fe-8eb7-8989618661a4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568015347 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.3568015347
Directory	/workspace/84.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/85.uart_fifo_reset.216006404
Short name	T959
Test name
Test status
Simulation time	65789302112 ps
CPU time	111.34 seconds
Started	Apr 28 01:09:19 PM PDT 24
Finished	Apr 28 01:11:11 PM PDT 24
Peak memory	200364 kb
Host	smart-3e9a4c75-0ed5-41cf-a2ea-4f6a76fa45b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=216006404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.216006404
Directory	/workspace/85.uart_fifo_reset/latest

Test location	/workspace/coverage/default/86.uart_fifo_reset.64430338
Short name	T51
Test name
Test status
Simulation time	18326521054 ps
CPU time	28.2 seconds
Started	Apr 28 01:09:15 PM PDT 24
Finished	Apr 28 01:09:43 PM PDT 24
Peak memory	200376 kb
Host	smart-c40ad973-8ad5-465f-8fe1-d98e2464d3fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=64430338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.64430338
Directory	/workspace/86.uart_fifo_reset/latest

Test location	/workspace/coverage/default/86.uart_stress_all_with_rand_reset.1886312319
Short name	T60
Test name
Test status
Simulation time	52649119255 ps
CPU time	535.5 seconds
Started	Apr 28 01:09:22 PM PDT 24
Finished	Apr 28 01:18:18 PM PDT 24
Peak memory	225196 kb
Host	smart-e46755d7-118f-4c69-9299-f0925f7f4465
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886312319 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.1886312319
Directory	/workspace/86.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/87.uart_fifo_reset.111501163
Short name	T197
Test name
Test status
Simulation time	119450264117 ps
CPU time	117.54 seconds
Started	Apr 28 01:09:16 PM PDT 24
Finished	Apr 28 01:11:14 PM PDT 24
Peak memory	200448 kb
Host	smart-554ae943-4998-4ab8-b0ae-7eceec2a53d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=111501163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.111501163
Directory	/workspace/87.uart_fifo_reset/latest

Test location	/workspace/coverage/default/87.uart_stress_all_with_rand_reset.1192515988
Short name	T949
Test name
Test status
Simulation time	16720911370 ps
CPU time	364.03 seconds
Started	Apr 28 01:09:19 PM PDT 24
Finished	Apr 28 01:15:24 PM PDT 24
Peak memory	216164 kb
Host	smart-8cdc22c1-1672-4345-9c2e-de648d32fdc3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192515988 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.1192515988
Directory	/workspace/87.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/88.uart_fifo_reset.1754753147
Short name	T616
Test name
Test status
Simulation time	8250285080 ps
CPU time	16.11 seconds
Started	Apr 28 01:09:19 PM PDT 24
Finished	Apr 28 01:09:35 PM PDT 24
Peak memory	200360 kb
Host	smart-b2c1a86b-ff61-4712-a7c7-7646ccf1c57c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1754753147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.1754753147
Directory	/workspace/88.uart_fifo_reset/latest

Test location	/workspace/coverage/default/88.uart_stress_all_with_rand_reset.2587989790
Short name	T1096
Test name
Test status
Simulation time	50179276233 ps
CPU time	551.54 seconds
Started	Apr 28 01:09:18 PM PDT 24
Finished	Apr 28 01:18:30 PM PDT 24
Peak memory	217060 kb
Host	smart-8bdc5601-3236-483b-89c7-bf9174f83b4b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587989790 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.2587989790
Directory	/workspace/88.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/89.uart_fifo_reset.402418834
Short name	T790
Test name
Test status
Simulation time	167335794282 ps
CPU time	200.77 seconds
Started	Apr 28 01:09:19 PM PDT 24
Finished	Apr 28 01:12:40 PM PDT 24
Peak memory	200396 kb
Host	smart-8739a9f4-421c-488a-a642-ab7dd7d58120
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=402418834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.402418834
Directory	/workspace/89.uart_fifo_reset/latest

Test location	/workspace/coverage/default/9.uart_alert_test.3380735393
Short name	T833
Test name
Test status
Simulation time	60389657 ps
CPU time	0.55 seconds
Started	Apr 28 01:05:32 PM PDT 24
Finished	Apr 28 01:05:34 PM PDT 24
Peak memory	195812 kb
Host	smart-6b1326d5-6cb7-4d89-aa24-4e1e3e0a6888
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380735393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.3380735393
Directory	/workspace/9.uart_alert_test/latest

Test location	/workspace/coverage/default/9.uart_fifo_full.3397865740
Short name	T890
Test name
Test status
Simulation time	180967046587 ps
CPU time	189.49 seconds
Started	Apr 28 01:05:27 PM PDT 24
Finished	Apr 28 01:08:37 PM PDT 24
Peak memory	200428 kb
Host	smart-c345e0ed-6678-44c9-9849-036163ea6766
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3397865740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.3397865740
Directory	/workspace/9.uart_fifo_full/latest

Test location	/workspace/coverage/default/9.uart_fifo_overflow.1872718576
Short name	T13
Test name
Test status
Simulation time	70781761517 ps
CPU time	25.27 seconds
Started	Apr 28 01:05:28 PM PDT 24
Finished	Apr 28 01:05:54 PM PDT 24
Peak memory	200364 kb
Host	smart-801a203c-2aa2-4bcb-9e72-bf71c42d70b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1872718576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1872718576
Directory	/workspace/9.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/9.uart_fifo_reset.3196863184
Short name	T514
Test name
Test status
Simulation time	50866669603 ps
CPU time	88.62 seconds
Started	Apr 28 01:05:33 PM PDT 24
Finished	Apr 28 01:07:02 PM PDT 24
Peak memory	200364 kb
Host	smart-36fb8c23-e7d7-4a00-bcb8-8cd93856d79f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3196863184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.3196863184
Directory	/workspace/9.uart_fifo_reset/latest

Test location	/workspace/coverage/default/9.uart_intr.3547143241
Short name	T637
Test name
Test status
Simulation time	41204491998 ps
CPU time	32.5 seconds
Started	Apr 28 01:05:35 PM PDT 24
Finished	Apr 28 01:06:07 PM PDT 24
Peak memory	200376 kb
Host	smart-8a66f2cf-fe8f-4e64-9380-5ee46bf63fb4
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547143241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.3547143241
Directory	/workspace/9.uart_intr/latest

Test location	/workspace/coverage/default/9.uart_long_xfer_wo_dly.2710516058
Short name	T739
Test name
Test status
Simulation time	53346771572 ps
CPU time	106.79 seconds
Started	Apr 28 01:05:31 PM PDT 24
Finished	Apr 28 01:07:18 PM PDT 24
Peak memory	200436 kb
Host	smart-d2829c93-a29a-4ed0-9c93-ef53ea58f1e6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2710516058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2710516058
Directory	/workspace/9.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/9.uart_loopback.30695451
Short name	T341
Test name
Test status
Simulation time	5751611471 ps
CPU time	7.83 seconds
Started	Apr 28 01:05:32 PM PDT 24
Finished	Apr 28 01:05:40 PM PDT 24
Peak memory	200316 kb
Host	smart-f4cc73bc-5d27-4c29-a03e-99b788a737ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=30695451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.30695451
Directory	/workspace/9.uart_loopback/latest

Test location	/workspace/coverage/default/9.uart_noise_filter.2101360888
Short name	T119
Test name
Test status
Simulation time	57988874492 ps
CPU time	48.95 seconds
Started	Apr 28 01:05:31 PM PDT 24
Finished	Apr 28 01:06:20 PM PDT 24
Peak memory	200544 kb
Host	smart-8029c2aa-867d-457f-8a4d-b26985ae80ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2101360888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.2101360888
Directory	/workspace/9.uart_noise_filter/latest

Test location	/workspace/coverage/default/9.uart_perf.3046385766
Short name	T845
Test name
Test status
Simulation time	18456927028 ps
CPU time	1080.55 seconds
Started	Apr 28 01:05:32 PM PDT 24
Finished	Apr 28 01:23:33 PM PDT 24
Peak memory	200448 kb
Host	smart-38d55756-b43c-40c2-b00b-9396084aa8b1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3046385766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.3046385766
Directory	/workspace/9.uart_perf/latest

Test location	/workspace/coverage/default/9.uart_rx_oversample.2854407002
Short name	T773
Test name
Test status
Simulation time	3251742060 ps
CPU time	27.64 seconds
Started	Apr 28 01:05:35 PM PDT 24
Finished	Apr 28 01:06:03 PM PDT 24
Peak memory	198460 kb
Host	smart-05afdc61-2d9c-4146-8cba-03228e7dd1d4
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2854407002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.2854407002
Directory	/workspace/9.uart_rx_oversample/latest

Test location	/workspace/coverage/default/9.uart_rx_parity_err.3910127835
Short name	T956
Test name
Test status
Simulation time	47671981811 ps
CPU time	65.65 seconds
Started	Apr 28 01:05:34 PM PDT 24
Finished	Apr 28 01:06:40 PM PDT 24
Peak memory	200344 kb
Host	smart-55c2b033-9e15-4126-8520-1c9fa4a8e6e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3910127835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.3910127835
Directory	/workspace/9.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/9.uart_rx_start_bit_filter.4098944479
Short name	T420
Test name
Test status
Simulation time	2083779508 ps
CPU time	1.44 seconds
Started	Apr 28 01:05:34 PM PDT 24
Finished	Apr 28 01:05:36 PM PDT 24
Peak memory	196000 kb
Host	smart-43836186-ed60-44b8-89cd-7198e46538a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4098944479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.4098944479
Directory	/workspace/9.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/9.uart_smoke.3524321144
Short name	T1028
Test name
Test status
Simulation time	5815044349 ps
CPU time	9.22 seconds
Started	Apr 28 01:05:27 PM PDT 24
Finished	Apr 28 01:05:37 PM PDT 24
Peak memory	199520 kb
Host	smart-69eb5431-8550-4d29-8ae5-599027fd12a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3524321144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.3524321144
Directory	/workspace/9.uart_smoke/latest

Test location	/workspace/coverage/default/9.uart_stress_all_with_rand_reset.4259890813
Short name	T113
Test name
Test status
Simulation time	23710830138 ps
CPU time	107.19 seconds
Started	Apr 28 01:05:32 PM PDT 24
Finished	Apr 28 01:07:20 PM PDT 24
Peak memory	208656 kb
Host	smart-69819e6c-c296-4810-aca3-aea64f2c505a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259890813 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.4259890813
Directory	/workspace/9.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.uart_tx_ovrd.1536428516
Short name	T553
Test name
Test status
Simulation time	910173779 ps
CPU time	3.1 seconds
Started	Apr 28 01:05:33 PM PDT 24
Finished	Apr 28 01:05:37 PM PDT 24
Peak memory	199616 kb
Host	smart-572936b3-e58b-424e-9001-83c47eba8248
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1536428516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.1536428516
Directory	/workspace/9.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/9.uart_tx_rx.580422435
Short name	T352
Test name
Test status
Simulation time	109927204402 ps
CPU time	17.82 seconds
Started	Apr 28 01:05:27 PM PDT 24
Finished	Apr 28 01:05:46 PM PDT 24
Peak memory	198180 kb
Host	smart-54731b35-b33b-4c14-9b51-7e3417cf4168
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=580422435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.580422435
Directory	/workspace/9.uart_tx_rx/latest

Test location	/workspace/coverage/default/90.uart_fifo_reset.3966478401
Short name	T820
Test name
Test status
Simulation time	105476624437 ps
CPU time	53.76 seconds
Started	Apr 28 01:09:19 PM PDT 24
Finished	Apr 28 01:10:13 PM PDT 24
Peak memory	200460 kb
Host	smart-a0977af2-7f19-4d98-85ef-9aad51ac2d71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3966478401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.3966478401
Directory	/workspace/90.uart_fifo_reset/latest

Test location	/workspace/coverage/default/90.uart_stress_all_with_rand_reset.2540581841
Short name	T740
Test name
Test status
Simulation time	28909743677 ps
CPU time	149.33 seconds
Started	Apr 28 01:09:21 PM PDT 24
Finished	Apr 28 01:11:51 PM PDT 24
Peak memory	208636 kb
Host	smart-236b8323-5368-4d6c-8d9d-d39f6eb45e4f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540581841 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.2540581841
Directory	/workspace/90.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/91.uart_fifo_reset.2154603737
Short name	T391
Test name
Test status
Simulation time	140270686604 ps
CPU time	58.9 seconds
Started	Apr 28 01:09:19 PM PDT 24
Finished	Apr 28 01:10:19 PM PDT 24
Peak memory	200424 kb
Host	smart-ae0e6b9f-b9bb-4eb6-91a1-894618fcfbd2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2154603737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.2154603737
Directory	/workspace/91.uart_fifo_reset/latest

Test location	/workspace/coverage/default/91.uart_stress_all_with_rand_reset.1278046431
Short name	T607
Test name
Test status
Simulation time	101547651339 ps
CPU time	602.32 seconds
Started	Apr 28 01:09:18 PM PDT 24
Finished	Apr 28 01:19:21 PM PDT 24
Peak memory	225120 kb
Host	smart-a5ded172-174f-4268-af8d-904ce63982b7
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278046431 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.1278046431
Directory	/workspace/91.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/92.uart_fifo_reset.117552066
Short name	T458
Test name
Test status
Simulation time	31053176079 ps
CPU time	18.62 seconds
Started	Apr 28 01:09:21 PM PDT 24
Finished	Apr 28 01:09:39 PM PDT 24
Peak memory	200416 kb
Host	smart-5db0b6d6-2d43-4458-a0b4-ec4c6247a7fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=117552066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.117552066
Directory	/workspace/92.uart_fifo_reset/latest

Test location	/workspace/coverage/default/92.uart_stress_all_with_rand_reset.2651560482
Short name	T808
Test name
Test status
Simulation time	199050479292 ps
CPU time	750.96 seconds
Started	Apr 28 01:09:24 PM PDT 24
Finished	Apr 28 01:21:55 PM PDT 24
Peak memory	216060 kb
Host	smart-cc559eda-faa2-4f5b-a63f-10c54452dfa0
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651560482 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.2651560482
Directory	/workspace/92.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/93.uart_fifo_reset.2764493404
Short name	T438
Test name
Test status
Simulation time	21364565426 ps
CPU time	9.33 seconds
Started	Apr 28 01:09:25 PM PDT 24
Finished	Apr 28 01:09:34 PM PDT 24
Peak memory	200332 kb
Host	smart-65f84b54-0e97-48a8-9c27-9ccc37936574
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2764493404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.2764493404
Directory	/workspace/93.uart_fifo_reset/latest

Test location	/workspace/coverage/default/93.uart_stress_all_with_rand_reset.43017726
Short name	T71
Test name
Test status
Simulation time	126748286391 ps
CPU time	250.98 seconds
Started	Apr 28 01:09:27 PM PDT 24
Finished	Apr 28 01:13:38 PM PDT 24
Peak memory	216920 kb
Host	smart-010888dc-29e8-4d65-b2e2-8792be79848a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43017726 -assert nopostpro c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.43017726
Directory	/workspace/93.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/94.uart_fifo_reset.11337577
Short name	T1046
Test name
Test status
Simulation time	190782478689 ps
CPU time	296.47 seconds
Started	Apr 28 01:09:26 PM PDT 24
Finished	Apr 28 01:14:22 PM PDT 24
Peak memory	200272 kb
Host	smart-0696e614-f0b2-4870-912a-e6f626d98a05
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=11337577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.11337577
Directory	/workspace/94.uart_fifo_reset/latest

Test location	/workspace/coverage/default/94.uart_stress_all_with_rand_reset.3163694733
Short name	T449
Test name
Test status
Simulation time	22008237820 ps
CPU time	260.99 seconds
Started	Apr 28 01:09:27 PM PDT 24
Finished	Apr 28 01:13:48 PM PDT 24
Peak memory	216976 kb
Host	smart-0f80909b-68ea-49f6-a57a-cd4dfd7404af
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163694733 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.3163694733
Directory	/workspace/94.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/95.uart_fifo_reset.1453539492
Short name	T716
Test name
Test status
Simulation time	74267271610 ps
CPU time	22.93 seconds
Started	Apr 28 01:09:24 PM PDT 24
Finished	Apr 28 01:09:47 PM PDT 24
Peak memory	200024 kb
Host	smart-8c45ccdd-653e-4455-a359-81df2ac90659
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1453539492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.1453539492
Directory	/workspace/95.uart_fifo_reset/latest

Test location	/workspace/coverage/default/95.uart_stress_all_with_rand_reset.2096769700
Short name	T315
Test name
Test status
Simulation time	160299600602 ps
CPU time	426.39 seconds
Started	Apr 28 01:09:24 PM PDT 24
Finished	Apr 28 01:16:31 PM PDT 24
Peak memory	217052 kb
Host	smart-89a5e385-5ebe-4f31-bcd8-5fa2cc1f0394
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096769700 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.2096769700
Directory	/workspace/95.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/96.uart_fifo_reset.3106942150
Short name	T212
Test name
Test status
Simulation time	87812407072 ps
CPU time	13.89 seconds
Started	Apr 28 01:09:23 PM PDT 24
Finished	Apr 28 01:09:37 PM PDT 24
Peak memory	200340 kb
Host	smart-da32ca8c-e07b-44c0-b692-f3f03b084313
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3106942150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3106942150
Directory	/workspace/96.uart_fifo_reset/latest

Test location	/workspace/coverage/default/96.uart_stress_all_with_rand_reset.3672008894
Short name	T222
Test name
Test status
Simulation time	34880397525 ps
CPU time	417.53 seconds
Started	Apr 28 01:09:25 PM PDT 24
Finished	Apr 28 01:16:23 PM PDT 24
Peak memory	217016 kb
Host	smart-00e14baa-8784-454f-80b9-e61d7faf5f08
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672008894 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.3672008894
Directory	/workspace/96.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/97.uart_fifo_reset.285388680
Short name	T135
Test name
Test status
Simulation time	31941008510 ps
CPU time	8.57 seconds
Started	Apr 28 01:09:24 PM PDT 24
Finished	Apr 28 01:09:33 PM PDT 24
Peak memory	200212 kb
Host	smart-5b54061c-858d-471c-ba2b-13013676c65a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=285388680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.285388680
Directory	/workspace/97.uart_fifo_reset/latest

Test location	/workspace/coverage/default/97.uart_stress_all_with_rand_reset.4214489008
Short name	T57
Test name
Test status
Simulation time	167100483630 ps
CPU time	1407.71 seconds
Started	Apr 28 01:09:24 PM PDT 24
Finished	Apr 28 01:32:52 PM PDT 24
Peak memory	225456 kb
Host	smart-3eafe8b5-4186-41f3-b77b-b9bb34d6e67e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214489008 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.4214489008
Directory	/workspace/97.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/98.uart_fifo_reset.1481608589
Short name	T1150
Test name
Test status
Simulation time	48656695536 ps
CPU time	70.73 seconds
Started	Apr 28 01:09:22 PM PDT 24
Finished	Apr 28 01:10:34 PM PDT 24
Peak memory	200448 kb
Host	smart-538e41f9-63d3-46ff-9fc9-943a635a8663
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1481608589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.1481608589
Directory	/workspace/98.uart_fifo_reset/latest

Test location	/workspace/coverage/default/98.uart_stress_all_with_rand_reset.3769681442
Short name	T477
Test name
Test status
Simulation time	132406859653 ps
CPU time	661.57 seconds
Started	Apr 28 01:09:24 PM PDT 24
Finished	Apr 28 01:20:26 PM PDT 24
Peak memory	214840 kb
Host	smart-39a2e1ae-2be0-4740-98ed-e6f7edd80266
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769681442 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.3769681442
Directory	/workspace/98.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/99.uart_fifo_reset.1027505049
Short name	T539
Test name
Test status
Simulation time	31079905279 ps
CPU time	18.69 seconds
Started	Apr 28 01:09:29 PM PDT 24
Finished	Apr 28 01:09:49 PM PDT 24
Peak memory	200288 kb
Host	smart-13663a97-63e2-4113-98da-da2f39f0a91b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1027505049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.1027505049
Directory	/workspace/99.uart_fifo_reset/latest

Test location	/workspace/coverage/default/99.uart_stress_all_with_rand_reset.2812680087
Short name	T856
Test name
Test status
Simulation time	85203119494 ps
CPU time	289.49 seconds
Started	Apr 28 01:09:29 PM PDT 24
Finished	Apr 28 01:14:20 PM PDT 24
Peak memory	216696 kb
Host	smart-353ae779-23f5-4824-8517-5d7bce774ab3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812680087 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.2812680087
Directory	/workspace/99.uart_stress_all_with_rand_reset/latest