Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	109158	1			T1	44		T2	228		T3	50
all_values[1]	109158	1			T1	44		T2	228		T3	50
all_values[2]	109158	1			T1	44		T2	228		T3	50
all_values[3]	109158	1			T1	44		T2	228		T3	50
all_values[4]	109158	1			T1	44		T2	228		T3	50
all_values[5]	109158	1			T1	44		T2	228		T3	50
all_values[6]	109158	1			T1	44		T2	228		T3	50
all_values[7]	109158	1			T1	44		T2	228		T3	50

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

439043

1

T1

260

T2

880

T3

149

auto[1]

434221

1

T1

92

T2

944

T3

251

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

814994

1

T1

326

T2

1605

T3

350

auto[1]

58270

1

T1

26

T2

219

T3

50

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	31382	1			T1	25		T2	14		T3	7
all_values[0]	auto[0]	auto[1]	23156	1			T1	18		T2	73		T3	3
all_values[0]	auto[1]	auto[0]	31480	1			T1	1		T2	59		T3	24
all_values[0]	auto[1]	auto[1]	23140	1			T2	82		T3	16		T4	4
all_values[1]	auto[0]	auto[0]	51984	1			T1	37		T2	98		T3	7
all_values[1]	auto[0]	auto[1]	1744	1			T2	2		T11	2		T12	11
all_values[1]	auto[1]	auto[0]	53826	1			T1	7		T2	107		T3	19
all_values[1]	auto[1]	auto[1]	1604	1			T2	21		T3	24		T4	18
all_values[2]	auto[0]	auto[0]	49829	1			T1	36		T2	102		T3	32
all_values[2]	auto[0]	auto[1]	2779	1			T1	8		T2	4		T3	2
all_values[2]	auto[1]	auto[0]	53919	1			T2	117		T3	12		T4	20
all_values[2]	auto[1]	auto[1]	2631	1			T2	5		T3	4		T4	2
all_values[3]	auto[0]	auto[0]	57013	1			T1	7		T2	118		T3	1
all_values[3]	auto[0]	auto[1]	325	1			T2	1		T4	1		T12	2
all_values[3]	auto[1]	auto[0]	51477	1			T1	37		T2	107		T3	48
all_values[3]	auto[1]	auto[1]	343	1			T2	2		T3	1		T86	1
all_values[4]	auto[0]	auto[0]	56405	1			T1	42		T2	60		T3	19
all_values[4]	auto[0]	auto[1]	490	1			T2	5		T85	1		T124	5
all_values[4]	auto[1]	auto[0]	51727	1			T1	2		T2	143		T3	31
all_values[4]	auto[1]	auto[1]	536	1			T2	20		T12	6		T18	14
all_values[5]	auto[0]	auto[0]	58211	1			T1	41		T2	130		T3	40
all_values[5]	auto[0]	auto[1]	199	1			T12	3		T14	2		T85	2
all_values[5]	auto[1]	auto[0]	50575	1			T1	3		T2	98		T3	10
all_values[5]	auto[1]	auto[1]	173	1			T12	2		T14	1		T85	2
all_values[6]	auto[0]	auto[0]	52825	1			T1	43		T2	145		T3	28
all_values[6]	auto[0]	auto[1]	180	1			T12	2		T14	2		T29	4
all_values[6]	auto[1]	auto[0]	55965	1			T1	1		T2	83		T3	22
all_values[6]	auto[1]	auto[1]	188	1			T12	4		T14	2		T85	3
all_values[7]	auto[0]	auto[0]	52123	1			T1	3		T2	128		T3	10
all_values[7]	auto[0]	auto[1]	398	1			T12	2		T15	7		T14	1
all_values[7]	auto[1]	auto[0]	56253	1			T1	41		T2	96		T3	40
all_values[7]	auto[1]	auto[1]	384	1			T2	4		T85	3		T192	7