Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2569

1

T1

1

T2

11

T3

1

auto[UartRx]

2569

1

T1

1

T2

11

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4560	1			T1	2		T2	14		T3	2
values[1]	55	1			T2	2		T29	1		T30	2
values[2]	38	1			T2	1		T12	1		T14	1
values[3]	46	1			T2	1		T12	1		T14	1
values[4]	59	1			T30	1		T32	1		T33	1
values[5]	48	1			T2	1		T30	1		T31	1
values[6]	51	1			T33	2		T328	1		T54	1
values[7]	61	1			T2	1		T20	2		T12	1
values[8]	53	1			T20	1		T30	1		T34	1
values[9]	65	1			T2	1		T29	1		T31	3
values[10]	60	1			T2	1		T20	2		T14	2

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2374	1			T1	1		T2	9		T3	1
auto[UartTx]	values[1]	16	1			T29	1		T30	1		T328	1
auto[UartTx]	values[2]	14	1			T2	1		T43	1		T329	1
auto[UartTx]	values[3]	15	1			T14	1		T31	1		T52	1
auto[UartTx]	values[4]	23	1			T30	1		T329	1		T54	3
auto[UartTx]	values[5]	20	1			T34	1		T119	1		T53	1
auto[UartTx]	values[6]	21	1			T33	1		T302	1		T99	1
auto[UartTx]	values[7]	18	1			T20	1		T12	1		T29	1
auto[UartTx]	values[8]	17	1			T330	1		T331	1		T55	2
auto[UartTx]	values[9]	23	1			T2	1		T29	1		T31	1
auto[UartTx]	values[10]	10	1			T109	1		T332	1		T333	1
auto[UartRx]	values[0]	2186	1			T1	1		T2	5		T3	1
auto[UartRx]	values[1]	39	1			T2	2		T30	1		T34	1
auto[UartRx]	values[2]	24	1			T12	1		T14	1		T29	1
auto[UartRx]	values[3]	31	1			T2	1		T12	1		T30	1
auto[UartRx]	values[4]	36	1			T32	1		T33	1		T52	1
auto[UartRx]	values[5]	28	1			T2	1		T30	1		T31	1
auto[UartRx]	values[6]	30	1			T33	1		T328	1		T54	1
auto[UartRx]	values[7]	43	1			T2	1		T20	1		T29	1
auto[UartRx]	values[8]	36	1			T20	1		T30	1		T34	1
auto[UartRx]	values[9]	42	1			T31	2		T32	1		T328	1
auto[UartRx]	values[10]	50	1			T2	1		T20	2		T14	2