Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2397	1			T1	3		T2	10		T3	1
auto[BaudRate115200]	2206	1			T1	1		T2	6		T3	2
auto[BaudRate230400]	2255	1			T1	1		T2	11		T3	2
auto[BaudRate128Kbps]	2266	1			T1	1		T2	11		T3	1
auto[BaudRate256Kbps]	2277	1			T1	2		T2	17		T6	3
auto[BaudRate1Mbps]	1883	1			T1	1		T3	3		T4	2
auto[BaudRate1p5Mbps]	1413	1			T3	1		T9	1		T11	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1784	1			T3	10		T7	3		T35	9
freqs[25]	1318	1			T11	10		T303	2		T289	5
freqs[48]	694	1			T334	21		T126	5		T140	8
freqs[50]	517	1			T324	1		T315	2		T125	17
freqs[100]	1353	1			T36	10		T271	13		T30	60

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	289	1			T3	1		T7	3		T35	2
auto[BaudRate9600]	freqs[25]	250	1			T11	3		T325	1		T327	2
auto[BaudRate9600]	freqs[48]	114	1			T126	1		T140	1		T277	1
auto[BaudRate9600]	freqs[50]	63	1			T324	1		T335	2		T336	1
auto[BaudRate9600]	freqs[100]	206	1			T36	1		T271	1		T30	15
auto[BaudRate115200]	freqs[24]	252	1			T3	2		T35	1		T22	1
auto[BaudRate115200]	freqs[25]	222	1			T11	3		T303	1		T327	1
auto[BaudRate115200]	freqs[48]	102	1			T126	2		T140	2		T219	1
auto[BaudRate115200]	freqs[50]	76	1			T125	1		T34	3		T335	2
auto[BaudRate115200]	freqs[100]	195	1			T36	1		T30	8		T145	3
auto[BaudRate230400]	freqs[24]	278	1			T3	2		T35	1		T86	1
auto[BaudRate230400]	freqs[25]	171	1			T327	3		T294	1		T172	2
auto[BaudRate230400]	freqs[48]	101	1			T334	6		T126	1		T140	2
auto[BaudRate230400]	freqs[50]	75	1			T125	4		T34	6		T335	3
auto[BaudRate230400]	freqs[100]	204	1			T36	1		T271	2		T30	5
auto[BaudRate128Kbps]	freqs[24]	256	1			T3	1		T35	2		T86	1
auto[BaudRate128Kbps]	freqs[25]	199	1			T289	4		T325	1		T172	2
auto[BaudRate128Kbps]	freqs[48]	91	1			T277	1		T219	2		T321	1
auto[BaudRate128Kbps]	freqs[50]	83	1			T125	2		T34	3		T335	3
auto[BaudRate128Kbps]	freqs[100]	203	1			T36	2		T271	3		T30	7
auto[BaudRate256Kbps]	freqs[24]	281	1			T35	1		T86	1		T39	2
auto[BaudRate256Kbps]	freqs[25]	162	1			T11	1		T303	1		T293	1
auto[BaudRate256Kbps]	freqs[48]	84	1			T334	6		T140	1		T321	1
auto[BaudRate256Kbps]	freqs[50]	82	1			T315	1		T125	2		T267	2
auto[BaudRate256Kbps]	freqs[100]	186	1			T36	1		T271	3		T30	8
auto[BaudRate1Mbps]	freqs[24]	291	1			T3	3		T35	1		T86	1
auto[BaudRate1Mbps]	freqs[25]	202	1			T11	2		T289	1		T293	1
auto[BaudRate1Mbps]	freqs[48]	109	1			T334	6		T219	1		T321	1
auto[BaudRate1Mbps]	freqs[50]	69	1			T315	1		T125	4		T267	3
auto[BaudRate1Mbps]	freqs[100]	159	1			T36	1		T271	2		T30	9
auto[BaudRate1p5Mbps]	freqs[25]	112	1			T11	1		T293	3		T284	1
auto[BaudRate1p5Mbps]	freqs[48]	93	1			T334	3		T126	1		T140	2
auto[BaudRate1p5Mbps]	freqs[50]	69	1			T125	4		T267	3		T34	5
auto[BaudRate1p5Mbps]	freqs[100]	200	1			T36	3		T271	2		T30	8

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded