Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.92	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	10	120	92.31

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	10	120	92.31	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	29872844	1			T1	210		T2	23336		T3	18
all_levels[1]	187981	1			T1	3		T2	1330		T8	18
all_levels[2]	2446	1			T3	1		T4	1		T8	1
all_levels[3]	1131	1			T8	1		T9	5		T35	3
all_levels[4]	783	1			T8	1		T9	2		T35	1
all_levels[5]	549	1			T9	1		T35	4		T84	1
all_levels[6]	454	1			T8	1		T84	1		T137	2
all_levels[7]	393	1			T1	2		T2	2		T8	1
all_levels[8]	299	1			T12	1		T138	2		T127	1
all_levels[9]	301	1			T84	1		T86	1		T12	3
all_levels[10]	228	1			T3	1		T139	1		T39	2
all_levels[11]	212	1			T84	1		T137	1		T85	1
all_levels[12]	176	1			T11	3		T140	2		T141	1
all_levels[13]	169	1			T3	1		T84	1		T137	1
all_levels[14]	149	1			T2	1		T138	1		T127	2
all_levels[15]	148	1			T84	1		T126	1		T127	1
all_levels[16]	121	1			T35	1		T141	1		T29	2
all_levels[17]	114	1			T84	3		T142	1		T29	1
all_levels[18]	105	1			T1	1		T11	2		T141	1
all_levels[19]	102	1			T3	1		T85	1		T141	3
all_levels[20]	91	1			T29	1		T143	1		T124	1
all_levels[21]	61	1			T84	1		T142	2		T144	2
all_levels[22]	82	1			T2	1		T3	1		T12	1
all_levels[23]	60	1			T12	1		T143	2		T145	2
all_levels[24]	74	1			T3	1		T4	3		T141	1
all_levels[25]	61	1			T1	1		T4	1		T86	1
all_levels[26]	67	1			T1	1		T36	2		T138	1
all_levels[27]	40	1			T3	1		T36	1		T84	2
all_levels[28]	45	1			T12	1		T141	2		T146	1
all_levels[29]	35	1			T84	1		T12	1		T141	1
all_levels[30]	31	1			T2	1		T3	2		T12	1
all_levels[31]	41	1			T31	1		T147	1		T34	1
all_levels[32]	44	1			T4	1		T148	1		T147	1
all_levels[33]	27	1			T84	1		T142	1		T30	1
all_levels[34]	34	1			T84	1		T142	2		T141	1
all_levels[35]	21	1			T12	1		T149	1		T150	1
all_levels[36]	23	1			T3	1		T35	1		T137	1
all_levels[37]	27	1			T29	1		T151	1		T152	1
all_levels[38]	22	1			T3	3		T145	2		T153	1
all_levels[39]	15	1			T29	1		T154	1		T155	1
all_levels[40]	25	1			T142	1		T156	1		T31	1
all_levels[41]	13	1			T41	2		T157	1		T158	1
all_levels[42]	21	1			T142	1		T159	1		T33	1
all_levels[43]	14	1			T160	1		T161	1		T121	1
all_levels[44]	14	1			T162	1		T55	1		T163	1
all_levels[45]	22	1			T32	1		T33	1		T164	1
all_levels[46]	10	1			T32	2		T165	1		T166	1
all_levels[47]	16	1			T137	2		T159	2		T157	1
all_levels[48]	18	1			T159	1		T157	1		T114	1
all_levels[49]	13	1			T167	1		T168	2		T169	1
all_levels[50]	3	1			T141	1		T170	1		T171	1
all_levels[51]	16	1			T172	3		T173	1		T174	2
all_levels[52]	16	1			T15	1		T175	5		T176	1
all_levels[53]	10	1			T177	2		T178	1		T179	1
all_levels[54]	8	1			T142	1		T180	1		T181	1
all_levels[55]	5	1			T182	1		T183	2		T99	1
all_levels[56]	7	1			T31	1		T155	1		T184	1
all_levels[57]	5	1			T31	1		T185	1		T186	1
all_levels[58]	8	1			T85	2		T165	1		T187	2
all_levels[59]	4	1			T85	1		T141	1		T188	1
all_levels[60]	10	1			T121	1		T189	4		T186	2
all_levels[61]	8	1			T165	1		T176	2		T190	1
all_levels[62]	3	1			T33	1		T155	1		T114	1
all_levels[63]	7	1			T35	1		T167	1		T191	1
all_levels[64]	117	1			T86	1		T85	1		T192	3

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30064771

1

T1

218

T2

24617

T3

24

auto[1]

5228

1

T2

54

T3

7

T4

3

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	10	120	92.31	10

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[33]]	[auto[1]]	0	1	1
[all_levels[36] , all_levels[37]]	[auto[1]]	--	--	2
[all_levels[46]]	[auto[1]]	0	1	1
[all_levels[50]]	[auto[1]]	0	1	1
[all_levels[54]]	[auto[1]]	0	1	1
[all_levels[57] , all_levels[58] , all_levels[59]]	[auto[1]]	--	--	3
[all_levels[62]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	29868130	1			T1	210		T2	23282		T3	13
all_levels[0]	auto[1]	4714	1			T2	54		T3	5		T4	1
all_levels[1]	auto[0]	187896	1			T1	3		T2	1330		T8	18
all_levels[1]	auto[1]	85	1			T35	1		T86	1		T142	1
all_levels[2]	auto[0]	2406	1			T3	1		T4	1		T8	1
all_levels[2]	auto[1]	40	1			T137	1		T193	1		T108	1
all_levels[3]	auto[0]	1110	1			T8	1		T9	5		T35	3
all_levels[3]	auto[1]	21	1			T144	2		T194	3		T33	1
all_levels[4]	auto[0]	755	1			T8	1		T9	2		T35	1
all_levels[4]	auto[1]	28	1			T160	1		T195	2		T108	2
all_levels[5]	auto[0]	526	1			T9	1		T35	4		T84	1
all_levels[5]	auto[1]	23	1			T196	4		T197	1		T198	1
all_levels[6]	auto[0]	445	1			T8	1		T84	1		T137	2
all_levels[6]	auto[1]	9	1			T183	4		T199	4		T200	1
all_levels[7]	auto[0]	377	1			T1	2		T2	2		T8	1
all_levels[7]	auto[1]	16	1			T142	1		T137	1		T114	1
all_levels[8]	auto[0]	290	1			T12	1		T138	2		T127	1
all_levels[8]	auto[1]	9	1			T162	1		T201	2		T202	3
all_levels[9]	auto[0]	287	1			T84	1		T86	1		T12	3
all_levels[9]	auto[1]	14	1			T31	1		T203	1		T204	1
all_levels[10]	auto[0]	219	1			T3	1		T139	1		T39	2
all_levels[10]	auto[1]	9	1			T159	1		T149	2		T205	1
all_levels[11]	auto[0]	205	1			T84	1		T137	1		T85	1
all_levels[11]	auto[1]	7	1			T206	1		T197	1		T207	1
all_levels[12]	auto[0]	157	1			T11	1		T140	1		T141	1
all_levels[12]	auto[1]	19	1			T11	2		T140	1		T208	1
all_levels[13]	auto[0]	157	1			T3	1		T84	1		T137	1
all_levels[13]	auto[1]	12	1			T209	3		T210	1		T211	1
all_levels[14]	auto[0]	136	1			T2	1		T138	1		T127	1
all_levels[14]	auto[1]	13	1			T127	1		T212	1		T213	1
all_levels[15]	auto[0]	137	1			T84	1		T126	1		T127	1
all_levels[15]	auto[1]	11	1			T140	1		T31	1		T214	2
all_levels[16]	auto[0]	109	1			T35	1		T141	1		T29	2
all_levels[16]	auto[1]	12	1			T215	1		T216	1		T217	1
all_levels[17]	auto[0]	106	1			T84	3		T142	1		T29	1
all_levels[17]	auto[1]	8	1			T118	1		T218	1		T196	1
all_levels[18]	auto[0]	96	1			T1	1		T11	1		T141	1
all_levels[18]	auto[1]	9	1			T11	1		T219	1		T220	2
all_levels[19]	auto[0]	97	1			T3	1		T85	1		T141	3
all_levels[19]	auto[1]	5	1			T221	1		T222	1		T223	1
all_levels[20]	auto[0]	81	1			T29	1		T143	1		T124	1
all_levels[20]	auto[1]	10	1			T164	1		T224	1		T225	2
all_levels[21]	auto[0]	55	1			T84	1		T142	2		T144	1
all_levels[21]	auto[1]	6	1			T144	1		T114	1		T226	1
all_levels[22]	auto[0]	74	1			T2	1		T3	1		T12	1
all_levels[22]	auto[1]	8	1			T227	1		T228	2		T229	1
all_levels[23]	auto[0]	51	1			T12	1		T143	1		T145	1
all_levels[23]	auto[1]	9	1			T143	1		T145	1		T230	3
all_levels[24]	auto[0]	60	1			T3	1		T4	1		T141	1
all_levels[24]	auto[1]	14	1			T4	2		T231	7		T175	1
all_levels[25]	auto[0]	53	1			T1	1		T4	1		T86	1
all_levels[25]	auto[1]	8	1			T232	1		T233	1		T234	1
all_levels[26]	auto[0]	55	1			T1	1		T36	1		T138	1
all_levels[26]	auto[1]	12	1			T36	1		T235	1		T236	1
all_levels[27]	auto[0]	35	1			T3	1		T36	1		T84	2
all_levels[27]	auto[1]	5	1			T127	1		T237	2		T238	1
all_levels[28]	auto[0]	41	1			T12	1		T141	2		T146	1
all_levels[28]	auto[1]	4	1			T209	2		T239	1		T240	1
all_levels[29]	auto[0]	31	1			T84	1		T12	1		T141	1
all_levels[29]	auto[1]	4	1			T114	2		T241	1		T234	1
all_levels[30]	auto[0]	27	1			T2	1		T3	2		T12	1
all_levels[30]	auto[1]	4	1			T242	2		T243	2		-	-
all_levels[31]	auto[0]	39	1			T31	1		T147	1		T34	1
all_levels[31]	auto[1]	2	1			T244	2		-	-		-	-
all_levels[32]	auto[0]	41	1			T4	1		T148	1		T147	1
all_levels[32]	auto[1]	3	1			T178	1		T199	2		-	-
all_levels[33]	auto[0]	27	1			T84	1		T142	1		T30	1
all_levels[34]	auto[0]	30	1			T84	1		T142	1		T141	1
all_levels[34]	auto[1]	4	1			T142	1		T197	1		T245	1
all_levels[35]	auto[0]	17	1			T12	1		T149	1		T150	1
all_levels[35]	auto[1]	4	1			T246	3		T247	1		-	-
all_levels[36]	auto[0]	23	1			T3	1		T35	1		T137	1
all_levels[37]	auto[0]	27	1			T29	1		T151	1		T152	1
all_levels[38]	auto[0]	15	1			T3	1		T145	1		T153	1
all_levels[38]	auto[1]	7	1			T3	2		T145	1		T218	1
all_levels[39]	auto[0]	14	1			T29	1		T154	1		T155	1
all_levels[39]	auto[1]	1	1			T248	1		-	-		-	-
all_levels[40]	auto[0]	23	1			T142	1		T156	1		T31	1
all_levels[40]	auto[1]	2	1			T249	1		T250	1		-	-
all_levels[41]	auto[0]	12	1			T41	1		T157	1		T158	1
all_levels[41]	auto[1]	1	1			T41	1		-	-		-	-
all_levels[42]	auto[0]	20	1			T142	1		T159	1		T33	1
all_levels[42]	auto[1]	1	1			T251	1		-	-		-	-
all_levels[43]	auto[0]	13	1			T160	1		T161	1		T121	1
all_levels[43]	auto[1]	1	1			T111	1		-	-		-	-
all_levels[44]	auto[0]	13	1			T162	1		T55	1		T163	1
all_levels[44]	auto[1]	1	1			T252	1		-	-		-	-
all_levels[45]	auto[0]	18	1			T32	1		T33	1		T164	1
all_levels[45]	auto[1]	4	1			T253	1		T254	1		T255	2
all_levels[46]	auto[0]	10	1			T32	2		T165	1		T166	1
all_levels[47]	auto[0]	11	1			T137	1		T159	1		T157	1
all_levels[47]	auto[1]	5	1			T137	1		T159	1		T256	1
all_levels[48]	auto[0]	16	1			T159	1		T157	1		T114	1
all_levels[48]	auto[1]	2	1			T48	2		-	-		-	-
all_levels[49]	auto[0]	12	1			T167	1		T168	1		T169	1
all_levels[49]	auto[1]	1	1			T168	1		-	-		-	-
all_levels[50]	auto[0]	3	1			T141	1		T170	1		T171	1
all_levels[51]	auto[0]	13	1			T172	1		T173	1		T174	1
all_levels[51]	auto[1]	3	1			T172	2		T174	1		-	-
all_levels[52]	auto[0]	12	1			T15	1		T175	1		T176	1
all_levels[52]	auto[1]	4	1			T175	4		-	-		-	-
all_levels[53]	auto[0]	9	1			T177	1		T178	1		T179	1
all_levels[53]	auto[1]	1	1			T177	1		-	-		-	-
all_levels[54]	auto[0]	8	1			T142	1		T180	1		T181	1
all_levels[55]	auto[0]	4	1			T182	1		T183	1		T99	1
all_levels[55]	auto[1]	1	1			T183	1		-	-		-	-
all_levels[56]	auto[0]	6	1			T31	1		T155	1		T184	1
all_levels[56]	auto[1]	1	1			T257	1		-	-		-	-
all_levels[57]	auto[0]	5	1			T31	1		T185	1		T186	1
all_levels[58]	auto[0]	8	1			T85	2		T165	1		T187	2
all_levels[59]	auto[0]	4	1			T85	1		T141	1		T188	1
all_levels[60]	auto[0]	6	1			T121	1		T189	1		T186	1
all_levels[60]	auto[1]	4	1			T189	3		T186	1		-	-
all_levels[61]	auto[0]	7	1			T165	1		T176	1		T190	1
all_levels[61]	auto[1]	1	1			T176	1		-	-		-	-
all_levels[62]	auto[0]	3	1			T33	1		T155	1		T114	1
all_levels[63]	auto[0]	6	1			T35	1		T167	1		T191	1
all_levels[63]	auto[1]	1	1			T258	1		-	-		-	-
all_levels[64]	auto[0]	92	1			T86	1		T85	1		T192	3
all_levels[64]	auto[1]	25	1			T143	1		T31	2		T177	1