Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	109158	1			T1	44		T2	228		T3	50
all_pins[1]	109158	1			T1	44		T2	228		T3	50
all_pins[2]	109158	1			T1	44		T2	228		T3	50
all_pins[3]	109158	1			T1	44		T2	228		T3	50
all_pins[4]	109158	1			T1	44		T2	228		T3	50
all_pins[5]	109158	1			T1	44		T2	228		T3	50
all_pins[6]	109158	1			T1	44		T2	228		T3	50
all_pins[7]	109158	1			T1	44		T2	228		T3	50

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	843352	1			T1	352		T2	1681		T3	355
values[0x1]	29912	1			T2	143		T3	45		T4	24
transitions[0x0=>0x1]	28766	1			T2	127		T3	45		T4	24
transitions[0x1=>0x0]	28330	1			T2	127		T3	45		T4	23

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	85956	1			T1	44		T2	145		T3	34
all_pins[0]	values[0x1]	23202	1			T2	83		T3	16		T4	4
all_pins[0]	transitions[0x0=>0x1]	22661	1			T2	74		T3	16		T4	4
all_pins[0]	transitions[0x1=>0x0]	1059	1			T2	12		T3	24		T4	18
all_pins[1]	values[0x0]	107558	1			T1	44		T2	207		T3	26
all_pins[1]	values[0x1]	1600	1			T2	21		T3	24		T4	18
all_pins[1]	transitions[0x0=>0x1]	1477	1			T2	21		T3	24		T4	18
all_pins[1]	transitions[0x1=>0x0]	2565	1			T2	5		T3	4		T4	2
all_pins[2]	values[0x0]	106470	1			T1	44		T2	223		T3	46
all_pins[2]	values[0x1]	2688	1			T2	5		T3	4		T4	2
all_pins[2]	transitions[0x0=>0x1]	2608	1			T2	5		T3	4		T4	2
all_pins[2]	transitions[0x1=>0x0]	263	1			T2	2		T3	1		T86	1
all_pins[3]	values[0x0]	108815	1			T1	44		T2	226		T3	49
all_pins[3]	values[0x1]	343	1			T2	2		T3	1		T86	1
all_pins[3]	transitions[0x0=>0x1]	298	1			T2	2		T3	1		T86	1
all_pins[3]	transitions[0x1=>0x0]	491	1			T2	20		T12	6		T18	14
all_pins[4]	values[0x0]	108622	1			T1	44		T2	208		T3	50
all_pins[4]	values[0x1]	536	1			T2	20		T12	6		T18	14
all_pins[4]	transitions[0x0=>0x1]	459	1			T2	17		T12	3		T18	11
all_pins[4]	transitions[0x1=>0x0]	159	1			T2	1		T14	1		T85	2
all_pins[5]	values[0x0]	108922	1			T1	44		T2	224		T3	50
all_pins[5]	values[0x1]	236	1			T2	4		T12	3		T14	1
all_pins[5]	transitions[0x0=>0x1]	189	1			T2	4		T12	1		T85	1
all_pins[5]	transitions[0x1=>0x0]	876	1			T2	4		T9	1		T12	2
all_pins[6]	values[0x0]	108235	1			T1	44		T2	224		T3	50
all_pins[6]	values[0x1]	923	1			T2	4		T9	1		T12	4
all_pins[6]	transitions[0x0=>0x1]	872	1			T2	4		T9	1		T12	4
all_pins[6]	transitions[0x1=>0x0]	333	1			T2	4		T192	7		T259	14
all_pins[7]	values[0x0]	108774	1			T1	44		T2	224		T3	50
all_pins[7]	values[0x1]	384	1			T2	4		T85	3		T192	7
all_pins[7]	transitions[0x0=>0x1]	202	1			T85	3		T192	7		T259	13
all_pins[7]	transitions[0x1=>0x0]	22584	1			T2	79		T3	16		T4	3