Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	8929402	1			T1	120		T2	6030		T3	18
all_levels[1]	624974	1			T1	25		T2	4396		T8	5
all_levels[2]	254939	1			T1	8		T2	30		T8	4
all_levels[3]	413246	1			T1	7		T2	34		T5	3
all_levels[4]	232040	1			T1	7		T2	22		T9	1
all_levels[5]	202395	1			T1	10		T2	23		T3	1
all_levels[6]	242698	1			T1	10		T2	25		T11	1
all_levels[7]	221188	1			T1	3		T2	38		T8	2
all_levels[8]	260788	1			T1	7		T2	27		T8	3
all_levels[9]	226154	1			T1	7		T2	32		T37	69
all_levels[10]	237889	1			T1	1		T2	27		T37	62
all_levels[11]	440561	1			T1	3		T2	21		T8	17
all_levels[12]	214067	1			T1	1		T2	25		T8	61
all_levels[13]	226992	1			T1	7		T2	27		T37	61
all_levels[14]	231062	1			T2	29		T8	2		T11	2
all_levels[15]	184631	1			T2	25		T35	2		T37	65
all_levels[16]	291288	1			T2	32		T11	2		T86	1
all_levels[17]	189746	1			T2	32		T36	1		T37	73
all_levels[18]	215480	1			T2	30		T35	1		T86	5
all_levels[19]	251667	1			T2	24		T9	2		T35	1
all_levels[20]	191073	1			T2	24		T4	4		T8	11
all_levels[21]	171241	1			T2	31		T35	1		T86	1
all_levels[22]	266908	1			T2	29		T4	3		T11	1
all_levels[23]	176998	1			T2	34		T35	8		T37	54
all_levels[24]	214556	1			T2	31		T11	2		T35	5
all_levels[25]	262559	1			T2	22		T11	1		T37	62
all_levels[26]	286042	1			T2	27		T3	1		T35	1
all_levels[27]	409189	1			T2	23		T11	1		T35	1
all_levels[28]	196366	1			T2	24		T4	4		T37	64
all_levels[29]	188350	1			T2	27		T11	3		T35	8
all_levels[30]	294990	1			T2	25		T139	4		T37	60
all_levels[31]	574746	1			T2	445		T35	3		T139	3
all_levels[32]	12745130	1			T1	2		T2	12989		T3	12

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30064771

1

T1

218

T2

24617

T3

24

auto[1]

4584

1

T2

43

T3

8

T4

7

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	8926823	1			T1	120		T2	5987		T3	13
all_levels[0]	auto[1]	2579	1			T2	43		T3	5		T4	2
all_levels[1]	auto[0]	624651	1			T1	25		T2	4396		T8	5
all_levels[1]	auto[1]	323	1			T11	2		T35	2		T142	1
all_levels[2]	auto[0]	254903	1			T1	8		T2	30		T8	4
all_levels[2]	auto[1]	36	1			T276	1		T338	1		T339	1
all_levels[3]	auto[0]	413080	1			T1	7		T2	34		T5	2
all_levels[3]	auto[1]	166	1			T5	1		T209	30		T165	5
all_levels[4]	auto[0]	232014	1			T1	7		T2	22		T9	1
all_levels[4]	auto[1]	26	1			T128	1		T143	1		T327	2
all_levels[5]	auto[0]	202368	1			T1	10		T2	23		T3	1
all_levels[5]	auto[1]	27	1			T5	1		T36	1		T126	1
all_levels[6]	auto[0]	242658	1			T1	10		T2	25		T11	1
all_levels[6]	auto[1]	40	1			T142	2		T126	2		T145	1
all_levels[7]	auto[0]	221056	1			T1	3		T2	38		T8	2
all_levels[7]	auto[1]	132	1			T266	1		T263	1		T107	13
all_levels[8]	auto[0]	260757	1			T1	7		T2	27		T8	2
all_levels[8]	auto[1]	31	1			T8	1		T264	1		T174	1
all_levels[9]	auto[0]	226137	1			T1	7		T2	32		T37	69
all_levels[9]	auto[1]	17	1			T219	2		T118	1		T149	1
all_levels[10]	auto[0]	237863	1			T1	1		T2	27		T37	62
all_levels[10]	auto[1]	26	1			T114	1		T340	1		T207	1
all_levels[11]	auto[0]	440527	1			T1	3		T2	21		T8	17
all_levels[11]	auto[1]	34	1			T232	1		T48	1		T109	1
all_levels[12]	auto[0]	214036	1			T1	1		T2	25		T8	61
all_levels[12]	auto[1]	31	1			T11	1		T39	1		T260	1
all_levels[13]	auto[0]	226962	1			T1	7		T2	27		T37	61
all_levels[13]	auto[1]	30	1			T137	1		T165	1		T341	1
all_levels[14]	auto[0]	231037	1			T2	29		T8	2		T11	2
all_levels[14]	auto[1]	25	1			T31	1		T162	1		T196	1
all_levels[15]	auto[0]	184454	1			T2	25		T35	2		T37	65
all_levels[15]	auto[1]	177	1			T140	1		T143	1		T157	2
all_levels[16]	auto[0]	291247	1			T2	32		T11	2		T86	1
all_levels[16]	auto[1]	41	1			T159	1		T206	1		T290	1
all_levels[17]	auto[0]	189729	1			T2	32		T36	1		T37	73
all_levels[17]	auto[1]	17	1			T342	1		T227	2		T178	2
all_levels[18]	auto[0]	215465	1			T2	30		T35	1		T86	3
all_levels[18]	auto[1]	15	1			T86	2		T142	1		T140	1
all_levels[19]	auto[0]	251634	1			T2	24		T9	2		T35	1
all_levels[19]	auto[1]	33	1			T232	1		T177	1		T121	1
all_levels[20]	auto[0]	191058	1			T2	24		T4	2		T8	11
all_levels[20]	auto[1]	15	1			T4	2		T137	1		T278	1
all_levels[21]	auto[0]	171218	1			T2	31		T35	1		T86	1
all_levels[21]	auto[1]	23	1			T120	3		T46	4		T343	1
all_levels[22]	auto[0]	266899	1			T2	29		T4	2		T11	1
all_levels[22]	auto[1]	9	1			T4	1		T193	1		T270	1
all_levels[23]	auto[0]	176974	1			T2	34		T35	8		T37	54
all_levels[23]	auto[1]	24	1			T295	1		T336	1		T235	1
all_levels[24]	auto[0]	214534	1			T2	31		T11	2		T35	5
all_levels[24]	auto[1]	22	1			T264	4		T34	1		T114	1
all_levels[25]	auto[0]	262546	1			T2	22		T11	1		T37	62
all_levels[25]	auto[1]	13	1			T118	2		T344	2		T339	1
all_levels[26]	auto[0]	286024	1			T2	27		T3	1		T35	1
all_levels[26]	auto[1]	18	1			T36	2		T86	1		T137	1
all_levels[27]	auto[0]	409164	1			T2	23		T11	1		T35	1
all_levels[27]	auto[1]	25	1			T31	1		T195	2		T188	1
all_levels[28]	auto[0]	196337	1			T2	24		T4	2		T37	64
all_levels[28]	auto[1]	29	1			T4	2		T172	2		T290	2
all_levels[29]	auto[0]	188334	1			T2	27		T11	3		T35	8
all_levels[29]	auto[1]	16	1			T291	1		T300	1		T178	1
all_levels[30]	auto[0]	294972	1			T2	25		T139	4		T37	60
all_levels[30]	auto[1]	18	1			T114	1		T162	1		T237	2
all_levels[31]	auto[0]	574736	1			T2	445		T35	3		T139	3
all_levels[31]	auto[1]	10	1			T206	1		T227	1		T220	1
all_levels[32]	auto[0]	12744574	1			T1	2		T2	12989		T3	9
all_levels[32]	auto[1]	556	1			T3	3		T9	1		T36	4