Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	783	1			T12	7		T14	4		T85	4
all_values[1]	783	1			T12	7		T14	4		T85	4
all_values[2]	783	1			T12	7		T14	4		T85	4
all_values[3]	783	1			T12	7		T14	4		T85	4
all_values[4]	783	1			T12	7		T14	4		T85	4
all_values[5]	783	1			T12	7		T14	4		T85	4
all_values[6]	783	1			T12	7		T14	4		T85	4
all_values[7]	783	1			T12	7		T14	4		T85	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3381

1

T12

30

T14

12

T85

18

auto[1]

2883

1

T12

26

T14

20

T85

14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2282

1

T12

20

T14

14

T85

11

auto[1]

3982

1

T12

36

T14

18

T85

21

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3662

1

T12

34

T14

22

T85

21

auto[1]

2602

1

T12

22

T14

10

T85

11

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	4	44	91.67	4
Automatically Generated Cross Bins	48	4	44	91.67	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	245	1			T12	3		T14	2		T85	3
all_values[0]	auto[0]	auto[1]	auto[1]	210	1			T12	1		T14	1		T29	3
all_values[0]	auto[1]	auto[0]	auto[1]	175	1			T12	2		T29	4		T124	1
all_values[0]	auto[1]	auto[1]	auto[1]	153	1			T12	1		T14	1		T85	1
all_values[1]	auto[0]	auto[0]	auto[0]	210	1			T12	5		T85	2		T29	1
all_values[1]	auto[0]	auto[1]	auto[0]	240	1			T14	2		T85	1		T29	8
all_values[1]	auto[1]	auto[0]	auto[1]	180	1			T12	2		T85	1		T29	1
all_values[1]	auto[1]	auto[1]	auto[1]	153	1			T14	2		T29	2		T124	4
all_values[2]	auto[0]	auto[0]	auto[0]	168	1			T12	1		T32	1		T34	2
all_values[2]	auto[0]	auto[0]	auto[1]	92	1			T85	1		T29	4		T124	1
all_values[2]	auto[0]	auto[1]	auto[0]	122	1			T14	2		T85	2		T124	1
all_values[2]	auto[0]	auto[1]	auto[1]	76	1			T12	2		T29	2		T124	2
all_values[2]	auto[1]	auto[0]	auto[1]	163	1			T14	2		T29	6		T124	3
all_values[2]	auto[1]	auto[1]	auto[1]	162	1			T12	4		T85	1		T124	4
all_values[3]	auto[0]	auto[0]	auto[0]	177	1			T12	1		T85	4		T29	6
all_values[3]	auto[0]	auto[0]	auto[1]	69	1			T29	1		T124	1		T31	3
all_values[3]	auto[0]	auto[1]	auto[0]	138	1			T12	2		T14	2		T29	2
all_values[3]	auto[0]	auto[1]	auto[1]	68	1			T14	1		T34	1		T107	2
all_values[3]	auto[1]	auto[0]	auto[1]	182	1			T12	4		T29	2		T124	5
all_values[3]	auto[1]	auto[1]	auto[1]	149	1			T14	1		T29	1		T124	1
all_values[4]	auto[0]	auto[0]	auto[0]	199	1			T12	2		T14	2		T85	1
all_values[4]	auto[0]	auto[0]	auto[1]	74	1			T85	1		T124	1		T31	1
all_values[4]	auto[0]	auto[1]	auto[0]	128	1			T12	3		T14	2		T29	5
all_values[4]	auto[0]	auto[1]	auto[1]	66	1			T12	1		T29	1		T34	3
all_values[4]	auto[1]	auto[0]	auto[1]	170	1			T85	1		T124	7		T31	1
all_values[4]	auto[1]	auto[1]	auto[1]	146	1			T12	1		T85	1		T29	1
all_values[5]	auto[0]	auto[0]	auto[0]	164	1			T12	1		T124	6		T32	1
all_values[5]	auto[0]	auto[0]	auto[1]	73	1			T12	2		T14	1		T85	1
all_values[5]	auto[0]	auto[1]	auto[0]	139	1			T124	2		T31	1		T32	1
all_values[5]	auto[0]	auto[1]	auto[1]	82	1			T12	2		T14	1		T85	1
all_values[5]	auto[1]	auto[0]	auto[1]	179	1			T12	2		T14	1		T85	1
all_values[5]	auto[1]	auto[1]	auto[1]	146	1			T14	1		T85	1		T29	1
all_values[6]	auto[0]	auto[0]	auto[0]	185	1			T85	1		T29	3		T124	2
all_values[6]	auto[0]	auto[0]	auto[1]	83	1			T14	1		T29	1		T31	1
all_values[6]	auto[0]	auto[1]	auto[0]	128	1			T29	2		T124	3		T32	1
all_values[6]	auto[0]	auto[1]	auto[1]	70	1			T12	2		T14	1		T85	2
all_values[6]	auto[1]	auto[0]	auto[1]	165	1			T12	2		T14	1		T29	4
all_values[6]	auto[1]	auto[1]	auto[1]	152	1			T12	3		T14	1		T85	1
all_values[7]	auto[0]	auto[0]	auto[0]	152	1			T12	1		T14	2		T29	2
all_values[7]	auto[0]	auto[0]	auto[1]	95	1			T12	1		T29	4		T32	1
all_values[7]	auto[0]	auto[1]	auto[0]	132	1			T12	4		T14	2		T124	3
all_values[7]	auto[0]	auto[1]	auto[1]	77	1			T85	1		T29	1		T32	2
all_values[7]	auto[1]	auto[0]	auto[1]	181	1			T12	1		T85	1		T29	4
all_values[7]	auto[1]	auto[1]	auto[1]	146	1			T85	2		T29	1		T124	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal