Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.27 99.27 97.95 100.00 98.80 100.00 99.59


Total test records in report: 1317
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T68 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.610477895 Apr 30 03:06:08 PM PDT 24 Apr 30 03:06:09 PM PDT 24 35537303 ps
T1258 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1545601161 Apr 30 03:06:30 PM PDT 24 Apr 30 03:06:31 PM PDT 24 72000966 ps
T1259 /workspace/coverage/cover_reg_top/20.uart_intr_test.1133882248 Apr 30 03:06:57 PM PDT 24 Apr 30 03:06:58 PM PDT 24 35213994 ps
T1260 /workspace/coverage/cover_reg_top/44.uart_intr_test.2939974123 Apr 30 03:07:01 PM PDT 24 Apr 30 03:07:02 PM PDT 24 45480207 ps
T1261 /workspace/coverage/cover_reg_top/0.uart_tl_errors.3030422613 Apr 30 03:06:07 PM PDT 24 Apr 30 03:06:10 PM PDT 24 105057222 ps
T1262 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.664235613 Apr 30 03:06:50 PM PDT 24 Apr 30 03:06:51 PM PDT 24 60433972 ps
T1263 /workspace/coverage/cover_reg_top/47.uart_intr_test.3446294109 Apr 30 03:07:01 PM PDT 24 Apr 30 03:07:02 PM PDT 24 22564714 ps
T1264 /workspace/coverage/cover_reg_top/29.uart_intr_test.20512319 Apr 30 03:06:59 PM PDT 24 Apr 30 03:07:00 PM PDT 24 25018630 ps
T1265 /workspace/coverage/cover_reg_top/48.uart_intr_test.2913336664 Apr 30 03:07:00 PM PDT 24 Apr 30 03:07:01 PM PDT 24 38978836 ps
T1266 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1489794779 Apr 30 03:06:58 PM PDT 24 Apr 30 03:06:59 PM PDT 24 22609897 ps
T1267 /workspace/coverage/cover_reg_top/21.uart_intr_test.32817794 Apr 30 03:06:57 PM PDT 24 Apr 30 03:06:58 PM PDT 24 53159948 ps
T1268 /workspace/coverage/cover_reg_top/6.uart_csr_rw.2334626929 Apr 30 03:06:31 PM PDT 24 Apr 30 03:06:32 PM PDT 24 16304047 ps
T1269 /workspace/coverage/cover_reg_top/1.uart_tl_errors.2513047705 Apr 30 03:06:07 PM PDT 24 Apr 30 03:06:09 PM PDT 24 41094200 ps
T1270 /workspace/coverage/cover_reg_top/8.uart_intr_test.353932611 Apr 30 03:06:39 PM PDT 24 Apr 30 03:06:40 PM PDT 24 31534874 ps
T69 /workspace/coverage/cover_reg_top/1.uart_csr_rw.87474384 Apr 30 03:06:09 PM PDT 24 Apr 30 03:06:10 PM PDT 24 13968311 ps
T1271 /workspace/coverage/cover_reg_top/18.uart_intr_test.3388842455 Apr 30 03:06:58 PM PDT 24 Apr 30 03:06:59 PM PDT 24 50692647 ps
T1272 /workspace/coverage/cover_reg_top/19.uart_intr_test.556638592 Apr 30 03:06:56 PM PDT 24 Apr 30 03:06:57 PM PDT 24 27714483 ps
T70 /workspace/coverage/cover_reg_top/17.uart_csr_rw.2556910230 Apr 30 03:06:58 PM PDT 24 Apr 30 03:06:59 PM PDT 24 14442144 ps
T133 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3128524675 Apr 30 03:06:16 PM PDT 24 Apr 30 03:06:18 PM PDT 24 97382399 ps
T1273 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1668040038 Apr 30 03:06:46 PM PDT 24 Apr 30 03:06:48 PM PDT 24 82437781 ps
T1274 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3014035670 Apr 30 03:06:50 PM PDT 24 Apr 30 03:06:52 PM PDT 24 42354248 ps
T1275 /workspace/coverage/cover_reg_top/13.uart_intr_test.1671325406 Apr 30 03:06:44 PM PDT 24 Apr 30 03:06:45 PM PDT 24 41845211 ps
T1276 /workspace/coverage/cover_reg_top/1.uart_intr_test.4063898388 Apr 30 03:06:09 PM PDT 24 Apr 30 03:06:10 PM PDT 24 28329338 ps
T1277 /workspace/coverage/cover_reg_top/19.uart_csr_rw.244980503 Apr 30 03:06:57 PM PDT 24 Apr 30 03:06:58 PM PDT 24 15443848 ps
T1278 /workspace/coverage/cover_reg_top/35.uart_intr_test.2471197069 Apr 30 03:07:01 PM PDT 24 Apr 30 03:07:02 PM PDT 24 61946871 ps
T1279 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.597461924 Apr 30 03:06:06 PM PDT 24 Apr 30 03:06:08 PM PDT 24 197142552 ps
T1280 /workspace/coverage/cover_reg_top/14.uart_intr_test.3114050795 Apr 30 03:06:53 PM PDT 24 Apr 30 03:06:54 PM PDT 24 53352815 ps
T1281 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1903683141 Apr 30 03:06:46 PM PDT 24 Apr 30 03:06:47 PM PDT 24 37505174 ps
T1282 /workspace/coverage/cover_reg_top/10.uart_tl_errors.1808223064 Apr 30 03:06:45 PM PDT 24 Apr 30 03:06:47 PM PDT 24 27729899 ps
T1283 /workspace/coverage/cover_reg_top/0.uart_intr_test.290604106 Apr 30 03:06:07 PM PDT 24 Apr 30 03:06:08 PM PDT 24 100675650 ps
T1284 /workspace/coverage/cover_reg_top/24.uart_intr_test.3896324182 Apr 30 03:06:54 PM PDT 24 Apr 30 03:06:56 PM PDT 24 14632506 ps
T1285 /workspace/coverage/cover_reg_top/17.uart_tl_errors.1887964160 Apr 30 03:06:49 PM PDT 24 Apr 30 03:06:51 PM PDT 24 47285572 ps
T1286 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.345747269 Apr 30 03:06:30 PM PDT 24 Apr 30 03:06:32 PM PDT 24 61200146 ps
T1287 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2687155604 Apr 30 03:06:51 PM PDT 24 Apr 30 03:06:52 PM PDT 24 34424322 ps
T1288 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.459285747 Apr 30 03:06:45 PM PDT 24 Apr 30 03:06:47 PM PDT 24 18295532 ps
T1289 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.620873014 Apr 30 03:06:58 PM PDT 24 Apr 30 03:07:00 PM PDT 24 37017847 ps
T1290 /workspace/coverage/cover_reg_top/11.uart_csr_rw.464129861 Apr 30 03:06:45 PM PDT 24 Apr 30 03:06:47 PM PDT 24 24716447 ps
T1291 /workspace/coverage/cover_reg_top/26.uart_intr_test.190042849 Apr 30 03:06:55 PM PDT 24 Apr 30 03:06:56 PM PDT 24 12065506 ps
T1292 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1652237990 Apr 30 03:06:38 PM PDT 24 Apr 30 03:06:40 PM PDT 24 108040730 ps
T1293 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2859005529 Apr 30 03:06:26 PM PDT 24 Apr 30 03:06:28 PM PDT 24 45454926 ps
T1294 /workspace/coverage/cover_reg_top/37.uart_intr_test.2700130084 Apr 30 03:07:02 PM PDT 24 Apr 30 03:07:03 PM PDT 24 15725763 ps
T71 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.341177196 Apr 30 03:06:23 PM PDT 24 Apr 30 03:06:24 PM PDT 24 49435717 ps
T1295 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3108779875 Apr 30 03:06:45 PM PDT 24 Apr 30 03:06:46 PM PDT 24 49645337 ps
T96 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.1457708420 Apr 30 03:06:51 PM PDT 24 Apr 30 03:06:52 PM PDT 24 92017342 ps
T1296 /workspace/coverage/cover_reg_top/4.uart_tl_errors.4017854663 Apr 30 03:06:26 PM PDT 24 Apr 30 03:06:28 PM PDT 24 308919891 ps
T1297 /workspace/coverage/cover_reg_top/5.uart_intr_test.2263251723 Apr 30 03:06:33 PM PDT 24 Apr 30 03:06:34 PM PDT 24 11093294 ps
T1298 /workspace/coverage/cover_reg_top/42.uart_intr_test.151268605 Apr 30 03:07:03 PM PDT 24 Apr 30 03:07:05 PM PDT 24 13143493 ps
T1299 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.938254176 Apr 30 03:06:42 PM PDT 24 Apr 30 03:06:44 PM PDT 24 191273514 ps
T1300 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.795099067 Apr 30 03:06:51 PM PDT 24 Apr 30 03:06:53 PM PDT 24 109949667 ps
T1301 /workspace/coverage/cover_reg_top/46.uart_intr_test.1152426365 Apr 30 03:07:04 PM PDT 24 Apr 30 03:07:05 PM PDT 24 187786556 ps
T1302 /workspace/coverage/cover_reg_top/9.uart_csr_rw.2757860741 Apr 30 03:06:40 PM PDT 24 Apr 30 03:06:41 PM PDT 24 18092845 ps
T1303 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.404697430 Apr 30 03:06:32 PM PDT 24 Apr 30 03:06:33 PM PDT 24 97300190 ps
T72 /workspace/coverage/cover_reg_top/14.uart_csr_rw.2048313399 Apr 30 03:06:51 PM PDT 24 Apr 30 03:06:52 PM PDT 24 21247661 ps
T1304 /workspace/coverage/cover_reg_top/2.uart_csr_rw.3063170340 Apr 30 03:06:15 PM PDT 24 Apr 30 03:06:16 PM PDT 24 38912826 ps
T1305 /workspace/coverage/cover_reg_top/45.uart_intr_test.65473699 Apr 30 03:07:01 PM PDT 24 Apr 30 03:07:02 PM PDT 24 14319870 ps
T1306 /workspace/coverage/cover_reg_top/16.uart_intr_test.4215843583 Apr 30 03:06:49 PM PDT 24 Apr 30 03:06:50 PM PDT 24 24539452 ps
T1307 /workspace/coverage/cover_reg_top/12.uart_csr_rw.1079873543 Apr 30 03:06:46 PM PDT 24 Apr 30 03:06:48 PM PDT 24 14434285 ps
T1308 /workspace/coverage/cover_reg_top/49.uart_intr_test.1719160567 Apr 30 03:07:02 PM PDT 24 Apr 30 03:07:04 PM PDT 24 55837793 ps
T1309 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.538306485 Apr 30 03:06:35 PM PDT 24 Apr 30 03:06:37 PM PDT 24 172935639 ps
T1310 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3315748549 Apr 30 03:06:07 PM PDT 24 Apr 30 03:06:08 PM PDT 24 43134970 ps
T1311 /workspace/coverage/cover_reg_top/2.uart_intr_test.3053053454 Apr 30 03:06:16 PM PDT 24 Apr 30 03:06:17 PM PDT 24 41995109 ps
T1312 /workspace/coverage/cover_reg_top/0.uart_csr_rw.1740000276 Apr 30 03:06:09 PM PDT 24 Apr 30 03:06:10 PM PDT 24 17232121 ps
T1313 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2941634521 Apr 30 03:06:36 PM PDT 24 Apr 30 03:06:37 PM PDT 24 40788977 ps
T1314 /workspace/coverage/cover_reg_top/13.uart_csr_rw.3925359223 Apr 30 03:06:45 PM PDT 24 Apr 30 03:06:46 PM PDT 24 12106197 ps
T1315 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3485238732 Apr 30 03:06:24 PM PDT 24 Apr 30 03:06:27 PM PDT 24 327415022 ps
T1316 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.4083123156 Apr 30 03:06:07 PM PDT 24 Apr 30 03:06:08 PM PDT 24 106043364 ps
T1317 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3638080853 Apr 30 03:06:29 PM PDT 24 Apr 30 03:06:30 PM PDT 24 29607740 ps

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.2204234092
Short name T2
Test name
Test status
Simulation time 490486932733 ps
CPU time 691.01 seconds
Started Apr 30 03:16:03 PM PDT 24
Finished Apr 30 03:27:35 PM PDT 24
Peak memory 216860 kb
Host smart-ef6324ac-212f-4f3b-a1b9-c1fc78fc33e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204234092 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.2204234092
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.3573701527
Short name T32
Test name
Test status
Simulation time 374527918168 ps
CPU time 1505.35 seconds
Started Apr 30 03:15:29 PM PDT 24
Finished Apr 30 03:40:35 PM PDT 24
Peak memory 225252 kb
Host smart-63029972-5e65-4037-8f26-21ca2b867e35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573701527 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.3573701527
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.4047395796
Short name T20
Test name
Test status
Simulation time 132244587303 ps
CPU time 552.03 seconds
Started Apr 30 03:16:17 PM PDT 24
Finished Apr 30 03:25:30 PM PDT 24
Peak memory 217036 kb
Host smart-cb1d987c-6ff6-4ae6-9220-2675ad06d102
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047395796 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.4047395796
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.2935285859
Short name T262
Test name
Test status
Simulation time 65195432961 ps
CPU time 310.6 seconds
Started Apr 30 03:14:40 PM PDT 24
Finished Apr 30 03:19:52 PM PDT 24
Peak memory 200436 kb
Host smart-f695a66c-0a28-4256-8ca6-7ddb2ef1588c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2935285859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.2935285859
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.894683471
Short name T29
Test name
Test status
Simulation time 311410253499 ps
CPU time 1091.76 seconds
Started Apr 30 03:15:58 PM PDT 24
Finished Apr 30 03:34:10 PM PDT 24
Peak memory 226252 kb
Host smart-888a0aaf-33a0-456e-9a48-c681679a93fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894683471 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.894683471
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.755692314
Short name T192
Test name
Test status
Simulation time 211971436337 ps
CPU time 44.25 seconds
Started Apr 30 03:13:17 PM PDT 24
Finished Apr 30 03:14:02 PM PDT 24
Peak memory 200388 kb
Host smart-921ddd2f-332d-4e02-b7a0-5b57bd63306d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755692314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.755692314
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.890276455
Short name T107
Test name
Test status
Simulation time 353510158049 ps
CPU time 449.92 seconds
Started Apr 30 03:15:44 PM PDT 24
Finished Apr 30 03:23:14 PM PDT 24
Peak memory 217076 kb
Host smart-33571344-00d9-412a-9d1c-9cd0fbb2459e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890276455 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.890276455
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.1116696863
Short name T54
Test name
Test status
Simulation time 348666033144 ps
CPU time 1135.78 seconds
Started Apr 30 03:16:03 PM PDT 24
Finished Apr 30 03:35:00 PM PDT 24
Peak memory 217128 kb
Host smart-b8618052-f227-4d03-89a5-0209bfc15297
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116696863 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.1116696863
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.319741744
Short name T5
Test name
Test status
Simulation time 57572390563 ps
CPU time 24.7 seconds
Started Apr 30 03:17:20 PM PDT 24
Finished Apr 30 03:17:45 PM PDT 24
Peak memory 200440 kb
Host smart-f3d1794f-6545-4980-8dbd-4f7820f42378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319741744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.319741744
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_sec_cm.808542496
Short name T98
Test name
Test status
Simulation time 112900199 ps
CPU time 0.83 seconds
Started Apr 30 03:11:00 PM PDT 24
Finished Apr 30 03:11:02 PM PDT 24
Peak memory 218500 kb
Host smart-294d1dce-d08f-4f66-adce-d714d030e1b2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808542496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.808542496
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/14.uart_alert_test.2845852871
Short name T348
Test name
Test status
Simulation time 30424217 ps
CPU time 0.55 seconds
Started Apr 30 03:12:39 PM PDT 24
Finished Apr 30 03:12:40 PM PDT 24
Peak memory 195824 kb
Host smart-26cd6b77-550b-4e44-beb7-1fa150293648
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845852871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.2845852871
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_stress_all.2974355320
Short name T209
Test name
Test status
Simulation time 316929449904 ps
CPU time 546.94 seconds
Started Apr 30 03:14:39 PM PDT 24
Finished Apr 30 03:23:46 PM PDT 24
Peak memory 200460 kb
Host smart-7396400c-34ed-4c78-8c9d-ceb5916467d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974355320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.2974355320
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all.2535909989
Short name T124
Test name
Test status
Simulation time 235485288773 ps
CPU time 44.31 seconds
Started Apr 30 03:13:42 PM PDT 24
Finished Apr 30 03:14:26 PM PDT 24
Peak memory 200424 kb
Host smart-a2bdc6a2-a0f1-4527-b3a4-8ce1b759424d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535909989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.2535909989
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all.1559985855
Short name T165
Test name
Test status
Simulation time 312473390650 ps
CPU time 1430.85 seconds
Started Apr 30 03:15:43 PM PDT 24
Finished Apr 30 03:39:35 PM PDT 24
Peak memory 200448 kb
Host smart-b64c1f07-39c7-4ace-88f4-302ff0706092
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559985855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.1559985855
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.3026437577
Short name T35
Test name
Test status
Simulation time 184302423816 ps
CPU time 145.4 seconds
Started Apr 30 03:17:42 PM PDT 24
Finished Apr 30 03:20:08 PM PDT 24
Peak memory 200364 kb
Host smart-3c2232cd-8926-4d36-86fd-744c3f8759bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026437577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.3026437577
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_fifo_full.450830866
Short name T116
Test name
Test status
Simulation time 372631530359 ps
CPU time 120.57 seconds
Started Apr 30 03:14:29 PM PDT 24
Finished Apr 30 03:16:30 PM PDT 24
Peak memory 200368 kb
Host smart-8ade43b1-013b-4d57-bea2-0a79480115ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450830866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.450830866
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.845762679
Short name T33
Test name
Test status
Simulation time 45682575902 ps
CPU time 515.28 seconds
Started Apr 30 03:13:20 PM PDT 24
Finished Apr 30 03:21:56 PM PDT 24
Peak memory 217048 kb
Host smart-2a50866b-ac4b-4ceb-87d0-a5ee468430fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845762679 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.845762679
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.449832750
Short name T89
Test name
Test status
Simulation time 303686888 ps
CPU time 1.25 seconds
Started Apr 30 03:06:09 PM PDT 24
Finished Apr 30 03:06:10 PM PDT 24
Peak memory 199544 kb
Host smart-9110447f-ad11-4cfb-a14f-61b9f18e26ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449832750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.449832750
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.634721351
Short name T31
Test name
Test status
Simulation time 145055406521 ps
CPU time 422.5 seconds
Started Apr 30 03:13:33 PM PDT 24
Finished Apr 30 03:20:36 PM PDT 24
Peak memory 227996 kb
Host smart-b4feccd1-f990-431c-a0b7-514468730a6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634721351 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.634721351
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_fifo_full.160449066
Short name T141
Test name
Test status
Simulation time 292895854733 ps
CPU time 96.99 seconds
Started Apr 30 03:15:20 PM PDT 24
Finished Apr 30 03:16:58 PM PDT 24
Peak memory 200408 kb
Host smart-b87c998e-c0f4-45cc-bdcc-9fcbeaf50d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160449066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.160449066
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_full.1852923660
Short name T155
Test name
Test status
Simulation time 131204849878 ps
CPU time 59.95 seconds
Started Apr 30 03:11:58 PM PDT 24
Finished Apr 30 03:12:59 PM PDT 24
Peak memory 200456 kb
Host smart-72c19f83-12ce-46f2-9d83-3e1d2a4167db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852923660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.1852923660
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_stress_all.2312541737
Short name T121
Test name
Test status
Simulation time 275105995700 ps
CPU time 1006.36 seconds
Started Apr 30 03:14:44 PM PDT 24
Finished Apr 30 03:31:31 PM PDT 24
Peak memory 208796 kb
Host smart-6ab48091-4b30-4328-b707-f3d84807ef86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312541737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.2312541737
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_fifo_full.537664280
Short name T285
Test name
Test status
Simulation time 95029626250 ps
CPU time 173.12 seconds
Started Apr 30 03:11:14 PM PDT 24
Finished Apr 30 03:14:07 PM PDT 24
Peak memory 200368 kb
Host smart-831b2b5f-8088-4ebd-a12c-c71a4851a02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537664280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.537664280
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.1319554538
Short name T52
Test name
Test status
Simulation time 117958561024 ps
CPU time 1187.02 seconds
Started Apr 30 03:14:59 PM PDT 24
Finished Apr 30 03:34:47 PM PDT 24
Peak memory 216864 kb
Host smart-9199ab30-315d-4826-bb95-c081ab99aedb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319554538 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.1319554538
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2973807338
Short name T63
Test name
Test status
Simulation time 98149010 ps
CPU time 0.76 seconds
Started Apr 30 03:06:08 PM PDT 24
Finished Apr 30 03:06:09 PM PDT 24
Peak memory 196820 kb
Host smart-eb767ee6-36e4-4897-b161-be7a7e169522
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973807338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.2973807338
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.544558581
Short name T77
Test name
Test status
Simulation time 55866144 ps
CPU time 0.72 seconds
Started Apr 30 03:06:17 PM PDT 24
Finished Apr 30 03:06:18 PM PDT 24
Peak memory 198212 kb
Host smart-7c38d6de-244d-45d1-934f-7f8d3d802b4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544558581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr_
outstanding.544558581
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.646287866
Short name T34
Test name
Test status
Simulation time 77675938046 ps
CPU time 392.14 seconds
Started Apr 30 03:14:54 PM PDT 24
Finished Apr 30 03:21:27 PM PDT 24
Peak memory 216932 kb
Host smart-01264af2-92bb-4cd8-854a-a538f76f1932
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646287866 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.646287866
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.567212119
Short name T172
Test name
Test status
Simulation time 50336722328 ps
CPU time 25.95 seconds
Started Apr 30 03:17:39 PM PDT 24
Finished Apr 30 03:18:05 PM PDT 24
Peak memory 200376 kb
Host smart-1bb09c7c-9aca-4894-bc2f-806bcd385821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567212119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.567212119
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.3524934252
Short name T142
Test name
Test status
Simulation time 15512229799 ps
CPU time 17.12 seconds
Started Apr 30 03:16:36 PM PDT 24
Finished Apr 30 03:16:53 PM PDT 24
Peak memory 200432 kb
Host smart-ed33120b-65a5-4f5f-b7cd-1ec77d5f8336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524934252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.3524934252
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.1030873097
Short name T118
Test name
Test status
Simulation time 237404506187 ps
CPU time 176 seconds
Started Apr 30 03:16:48 PM PDT 24
Finished Apr 30 03:19:45 PM PDT 24
Peak memory 200320 kb
Host smart-db2baca9-d03f-449d-ba82-6a1f83b013c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030873097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.1030873097
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.725012802
Short name T144
Test name
Test status
Simulation time 209366371306 ps
CPU time 225.29 seconds
Started Apr 30 03:11:01 PM PDT 24
Finished Apr 30 03:14:47 PM PDT 24
Peak memory 200188 kb
Host smart-50cc53bd-848a-47be-97d9-20a71f2a22d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725012802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.725012802
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.1457708420
Short name T96
Test name
Test status
Simulation time 92017342 ps
CPU time 0.88 seconds
Started Apr 30 03:06:51 PM PDT 24
Finished Apr 30 03:06:52 PM PDT 24
Peak memory 198924 kb
Host smart-40beb727-d9f5-4689-9a9f-3b1b20611d13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457708420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.1457708420
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.649389522
Short name T291
Test name
Test status
Simulation time 84753232871 ps
CPU time 130.49 seconds
Started Apr 30 03:11:02 PM PDT 24
Finished Apr 30 03:13:13 PM PDT 24
Peak memory 200416 kb
Host smart-2dc26022-7c7c-4ff7-b4a7-010273b55a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649389522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.649389522
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.636196202
Short name T567
Test name
Test status
Simulation time 75669305085 ps
CPU time 34.55 seconds
Started Apr 30 03:12:05 PM PDT 24
Finished Apr 30 03:12:40 PM PDT 24
Peak memory 200396 kb
Host smart-64a45801-fce8-4fdd-8774-0ca6038a7580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636196202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.636196202
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.2983413628
Short name T3
Test name
Test status
Simulation time 109192235109 ps
CPU time 50.52 seconds
Started Apr 30 03:16:35 PM PDT 24
Finished Apr 30 03:17:26 PM PDT 24
Peak memory 200504 kb
Host smart-e9ebf981-cdd2-4f03-bdbe-56aa7535326b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983413628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.2983413628
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1750641464
Short name T91
Test name
Test status
Simulation time 51525461 ps
CPU time 0.92 seconds
Started Apr 30 03:06:07 PM PDT 24
Finished Apr 30 03:06:09 PM PDT 24
Peak memory 199148 kb
Host smart-4ee61c99-7804-4c6f-8d7a-af42a6383672
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750641464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.1750641464
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.2913832963
Short name T227
Test name
Test status
Simulation time 226459405153 ps
CPU time 102.57 seconds
Started Apr 30 03:16:44 PM PDT 24
Finished Apr 30 03:18:27 PM PDT 24
Peak memory 200432 kb
Host smart-ba405120-2234-47fd-afa7-3e125246c3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913832963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.2913832963
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.302310502
Short name T198
Test name
Test status
Simulation time 231119444791 ps
CPU time 87.46 seconds
Started Apr 30 03:13:05 PM PDT 24
Finished Apr 30 03:14:33 PM PDT 24
Peak memory 200320 kb
Host smart-ea05f64a-7b93-4cd8-8422-ec9c111b174b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302310502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.302310502
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_stress_all.12161780
Short name T162
Test name
Test status
Simulation time 364947898895 ps
CPU time 1156.66 seconds
Started Apr 30 03:13:18 PM PDT 24
Finished Apr 30 03:32:35 PM PDT 24
Peak memory 200604 kb
Host smart-dde834c0-b381-47a9-ae7f-269fe808e617
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12161780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.12161780
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.22034710
Short name T183
Test name
Test status
Simulation time 45104482726 ps
CPU time 19.16 seconds
Started Apr 30 03:17:12 PM PDT 24
Finished Apr 30 03:17:32 PM PDT 24
Peak memory 200416 kb
Host smart-56f8fe4b-7620-4c11-9449-b0b68aaa222e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22034710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.22034710
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.2098747566
Short name T175
Test name
Test status
Simulation time 70832212905 ps
CPU time 45.46 seconds
Started Apr 30 03:16:25 PM PDT 24
Finished Apr 30 03:17:10 PM PDT 24
Peak memory 200404 kb
Host smart-4561fd5b-afbe-426a-93d4-d83320e0b106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098747566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.2098747566
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.482453459
Short name T193
Test name
Test status
Simulation time 88400522624 ps
CPU time 194.32 seconds
Started Apr 30 03:16:32 PM PDT 24
Finished Apr 30 03:19:46 PM PDT 24
Peak memory 200488 kb
Host smart-0ae689d4-f218-4681-bff3-ef4de3035bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482453459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.482453459
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.530853543
Short name T11
Test name
Test status
Simulation time 119078685953 ps
CPU time 63.07 seconds
Started Apr 30 03:14:59 PM PDT 24
Finished Apr 30 03:16:02 PM PDT 24
Peak memory 200464 kb
Host smart-8c0faf7c-3832-41dd-8eab-43e6650713ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530853543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.530853543
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.253391053
Short name T167
Test name
Test status
Simulation time 93482230870 ps
CPU time 143.09 seconds
Started Apr 30 03:15:01 PM PDT 24
Finished Apr 30 03:17:25 PM PDT 24
Peak memory 200416 kb
Host smart-58c71329-59e5-4c72-840a-f7e887797875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253391053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.253391053
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_stress_all.1574858811
Short name T85
Test name
Test status
Simulation time 163854760405 ps
CPU time 78.14 seconds
Started Apr 30 03:15:21 PM PDT 24
Finished Apr 30 03:16:40 PM PDT 24
Peak memory 200408 kb
Host smart-cac9e4ca-2f44-4bf9-af15-1166e99640bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574858811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.1574858811
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.1418246890
Short name T59
Test name
Test status
Simulation time 95379215705 ps
CPU time 869.41 seconds
Started Apr 30 03:15:43 PM PDT 24
Finished Apr 30 03:30:13 PM PDT 24
Peak memory 216908 kb
Host smart-eb81f4db-9dee-4516-978c-a8679154c15b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418246890 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.1418246890
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.2590119029
Short name T759
Test name
Test status
Simulation time 95367253137 ps
CPU time 804.06 seconds
Started Apr 30 03:12:13 PM PDT 24
Finished Apr 30 03:25:38 PM PDT 24
Peak memory 225292 kb
Host smart-25b6e7ca-aa9a-4c23-8460-9abcd128434a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590119029 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.2590119029
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_stress_all.1838744004
Short name T514
Test name
Test status
Simulation time 343116528369 ps
CPU time 596.83 seconds
Started Apr 30 03:13:02 PM PDT 24
Finished Apr 30 03:22:59 PM PDT 24
Peak memory 200432 kb
Host smart-a3997f3e-076a-4aef-8043-17a73c3c5ca3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838744004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.1838744004
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.2716606502
Short name T251
Test name
Test status
Simulation time 27129626184 ps
CPU time 25.91 seconds
Started Apr 30 03:16:26 PM PDT 24
Finished Apr 30 03:16:53 PM PDT 24
Peak memory 200352 kb
Host smart-9a015181-0b91-4231-878a-758079931ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716606502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.2716606502
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.2868757335
Short name T232
Test name
Test status
Simulation time 64402919025 ps
CPU time 51.97 seconds
Started Apr 30 03:17:04 PM PDT 24
Finished Apr 30 03:17:57 PM PDT 24
Peak memory 200340 kb
Host smart-f37c518a-51d1-40c5-9567-e6b24185b806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868757335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.2868757335
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.2513611509
Short name T250
Test name
Test status
Simulation time 49648112437 ps
CPU time 19.87 seconds
Started Apr 30 03:17:04 PM PDT 24
Finished Apr 30 03:17:25 PM PDT 24
Peak memory 200380 kb
Host smart-4d7edf3e-d8d8-4e87-bf3d-6d1a347d637b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513611509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.2513611509
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.2393083399
Short name T224
Test name
Test status
Simulation time 64704474314 ps
CPU time 51.49 seconds
Started Apr 30 03:17:29 PM PDT 24
Finished Apr 30 03:18:22 PM PDT 24
Peak memory 200376 kb
Host smart-78ffbda3-7de5-4e56-812b-2b6cbdcb6b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393083399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.2393083399
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.3688896903
Short name T272
Test name
Test status
Simulation time 215852776024 ps
CPU time 56.99 seconds
Started Apr 30 03:17:44 PM PDT 24
Finished Apr 30 03:18:41 PM PDT 24
Peak memory 200320 kb
Host smart-0e60d710-cfeb-42da-8c37-e212c311962c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688896903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.3688896903
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.4179158860
Short name T199
Test name
Test status
Simulation time 220839427739 ps
CPU time 548.91 seconds
Started Apr 30 03:16:01 PM PDT 24
Finished Apr 30 03:25:10 PM PDT 24
Peak memory 217116 kb
Host smart-36d02843-e6bc-40ff-a5ae-26ed33e71041
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179158860 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.4179158860
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_smoke.3226279853
Short name T45
Test name
Test status
Simulation time 890484661 ps
CPU time 3.3 seconds
Started Apr 30 03:10:51 PM PDT 24
Finished Apr 30 03:10:55 PM PDT 24
Peak memory 199172 kb
Host smart-4cbc7dac-aa8d-4435-89d2-dbacf33f8141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226279853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.3226279853
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.943052800
Short name T205
Test name
Test status
Simulation time 39091442257 ps
CPU time 78.83 seconds
Started Apr 30 03:16:39 PM PDT 24
Finished Apr 30 03:17:58 PM PDT 24
Peak memory 200444 kb
Host smart-d1de955c-344e-4cc6-a26a-7a5f930313bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943052800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.943052800
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.3509208016
Short name T186
Test name
Test status
Simulation time 29259894426 ps
CPU time 43.72 seconds
Started Apr 30 03:16:33 PM PDT 24
Finished Apr 30 03:17:18 PM PDT 24
Peak memory 200352 kb
Host smart-6dde0e9f-dfc5-4edd-a215-9442e6e56477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509208016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.3509208016
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.1528049067
Short name T215
Test name
Test status
Simulation time 83313297876 ps
CPU time 48.32 seconds
Started Apr 30 03:16:44 PM PDT 24
Finished Apr 30 03:17:33 PM PDT 24
Peak memory 200436 kb
Host smart-35f469bd-fb05-4427-8cea-b21244d153e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528049067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.1528049067
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.2826292116
Short name T254
Test name
Test status
Simulation time 275030432249 ps
CPU time 44.27 seconds
Started Apr 30 03:16:43 PM PDT 24
Finished Apr 30 03:17:28 PM PDT 24
Peak memory 200380 kb
Host smart-a3592fe0-9d0c-4148-b5ce-ffec48961844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826292116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.2826292116
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.1772172123
Short name T258
Test name
Test status
Simulation time 91337901371 ps
CPU time 146.45 seconds
Started Apr 30 03:16:41 PM PDT 24
Finished Apr 30 03:19:08 PM PDT 24
Peak memory 200184 kb
Host smart-430e9c39-2c9b-4898-9fc1-9540898f69c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772172123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1772172123
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.4030280428
Short name T523
Test name
Test status
Simulation time 27460590694 ps
CPU time 34.96 seconds
Started Apr 30 03:16:49 PM PDT 24
Finished Apr 30 03:17:24 PM PDT 24
Peak memory 200432 kb
Host smart-24320b79-0d4b-4786-a0da-af2e9d05674e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030280428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.4030280428
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.1404357627
Short name T252
Test name
Test status
Simulation time 27920020328 ps
CPU time 45.45 seconds
Started Apr 30 03:17:05 PM PDT 24
Finished Apr 30 03:17:51 PM PDT 24
Peak memory 200344 kb
Host smart-b22a359a-3086-4b07-9647-4c04f43a133a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404357627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1404357627
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.4025485567
Short name T244
Test name
Test status
Simulation time 76096655637 ps
CPU time 72.34 seconds
Started Apr 30 03:17:07 PM PDT 24
Finished Apr 30 03:18:20 PM PDT 24
Peak memory 200368 kb
Host smart-a7996d1f-b850-4ecd-b911-6a484aaeead8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025485567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.4025485567
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.1001733924
Short name T127
Test name
Test status
Simulation time 62270269091 ps
CPU time 107.78 seconds
Started Apr 30 03:17:13 PM PDT 24
Finished Apr 30 03:19:02 PM PDT 24
Peak memory 200380 kb
Host smart-0b18ab1e-f706-400c-b7d1-fbe7b9ccbd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001733924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.1001733924
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.3613941335
Short name T241
Test name
Test status
Simulation time 91815428470 ps
CPU time 137.84 seconds
Started Apr 30 03:17:13 PM PDT 24
Finished Apr 30 03:19:31 PM PDT 24
Peak memory 200352 kb
Host smart-1cd0c917-3f27-4850-b575-93f7e8552169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613941335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.3613941335
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.318242603
Short name T247
Test name
Test status
Simulation time 159331230096 ps
CPU time 84.97 seconds
Started Apr 30 03:17:32 PM PDT 24
Finished Apr 30 03:18:58 PM PDT 24
Peak memory 200312 kb
Host smart-9f4106cc-fc2c-43aa-bd3b-e64ceb323c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318242603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.318242603
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.2044874540
Short name T257
Test name
Test status
Simulation time 16265205700 ps
CPU time 29.01 seconds
Started Apr 30 03:17:32 PM PDT 24
Finished Apr 30 03:18:02 PM PDT 24
Peak memory 200288 kb
Host smart-4fd333db-c9e8-417d-a727-c118191c8141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044874540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2044874540
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.481054925
Short name T221
Test name
Test status
Simulation time 24451658289 ps
CPU time 23.55 seconds
Started Apr 30 03:17:31 PM PDT 24
Finished Apr 30 03:17:55 PM PDT 24
Peak memory 200444 kb
Host smart-fecc1dd3-bbc5-413f-8df8-e67d2ecf6bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481054925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.481054925
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.2721588958
Short name T242
Test name
Test status
Simulation time 89452291996 ps
CPU time 34.77 seconds
Started Apr 30 03:17:31 PM PDT 24
Finished Apr 30 03:18:06 PM PDT 24
Peak memory 200392 kb
Host smart-a1cbf16e-5aac-42e9-84a5-5bfa272595f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721588958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2721588958
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.781391241
Short name T41
Test name
Test status
Simulation time 40932291309 ps
CPU time 57.1 seconds
Started Apr 30 03:17:40 PM PDT 24
Finished Apr 30 03:18:37 PM PDT 24
Peak memory 200532 kb
Host smart-f44baff3-9b85-457a-971d-854f83cf867d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781391241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.781391241
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.948747038
Short name T176
Test name
Test status
Simulation time 50273239618 ps
CPU time 49.03 seconds
Started Apr 30 03:17:41 PM PDT 24
Finished Apr 30 03:18:31 PM PDT 24
Peak memory 200436 kb
Host smart-6331add4-ab11-42ed-aca3-f8b497b67bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948747038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.948747038
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.1371862730
Short name T48
Test name
Test status
Simulation time 65448781060 ps
CPU time 29.29 seconds
Started Apr 30 03:17:40 PM PDT 24
Finished Apr 30 03:18:10 PM PDT 24
Peak memory 200436 kb
Host smart-de043880-5656-41c1-adde-4a9dc03e77e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371862730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.1371862730
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.2130100780
Short name T248
Test name
Test status
Simulation time 307699588103 ps
CPU time 66.18 seconds
Started Apr 30 03:17:46 PM PDT 24
Finished Apr 30 03:18:53 PM PDT 24
Peak memory 200388 kb
Host smart-dac23d64-ae04-446b-9ef6-bb7e9fd14915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130100780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.2130100780
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.2135686097
Short name T177
Test name
Test status
Simulation time 219059904403 ps
CPU time 28.08 seconds
Started Apr 30 03:14:37 PM PDT 24
Finished Apr 30 03:15:05 PM PDT 24
Peak memory 200400 kb
Host smart-db17b255-7848-4243-afca-c760b357573a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135686097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.2135686097
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.3974424203
Short name T168
Test name
Test status
Simulation time 276694304801 ps
CPU time 63.64 seconds
Started Apr 30 03:16:12 PM PDT 24
Finished Apr 30 03:17:17 PM PDT 24
Peak memory 200316 kb
Host smart-382b5a2d-d9f6-4286-8a95-26bf9608272a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974424203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.3974424203
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.2941558017
Short name T111
Test name
Test status
Simulation time 443580219558 ps
CPU time 526.26 seconds
Started Apr 30 03:16:13 PM PDT 24
Finished Apr 30 03:25:00 PM PDT 24
Peak memory 231172 kb
Host smart-74b3f88a-3be4-49e6-8ac2-d1d3bdb57ffa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941558017 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.2941558017
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.256231872
Short name T1207
Test name
Test status
Simulation time 125932457 ps
CPU time 1.41 seconds
Started Apr 30 03:06:07 PM PDT 24
Finished Apr 30 03:06:09 PM PDT 24
Peak memory 198324 kb
Host smart-4b3d3f86-7a35-459f-bcf1-77d2bc44f897
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256231872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.256231872
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3315748549
Short name T1310
Test name
Test status
Simulation time 43134970 ps
CPU time 0.54 seconds
Started Apr 30 03:06:07 PM PDT 24
Finished Apr 30 03:06:08 PM PDT 24
Peak memory 195628 kb
Host smart-8fee8bed-a96e-4b63-af27-e21182c00926
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315748549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.3315748549
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.597461924
Short name T1279
Test name
Test status
Simulation time 197142552 ps
CPU time 1.46 seconds
Started Apr 30 03:06:06 PM PDT 24
Finished Apr 30 03:06:08 PM PDT 24
Peak memory 200380 kb
Host smart-52753bd5-b972-47bb-9cc1-ed8f080d94a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597461924 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.597461924
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.1740000276
Short name T1312
Test name
Test status
Simulation time 17232121 ps
CPU time 0.62 seconds
Started Apr 30 03:06:09 PM PDT 24
Finished Apr 30 03:06:10 PM PDT 24
Peak memory 195912 kb
Host smart-39ae9415-3500-41ca-8556-72fb34d9d2c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740000276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.1740000276
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.290604106
Short name T1283
Test name
Test status
Simulation time 100675650 ps
CPU time 0.54 seconds
Started Apr 30 03:06:07 PM PDT 24
Finished Apr 30 03:06:08 PM PDT 24
Peak memory 194584 kb
Host smart-200d2e51-2716-48a2-b17a-46a0d00d6547
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290604106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.290604106
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.4083123156
Short name T1316
Test name
Test status
Simulation time 106043364 ps
CPU time 0.73 seconds
Started Apr 30 03:06:07 PM PDT 24
Finished Apr 30 03:06:08 PM PDT 24
Peak memory 198364 kb
Host smart-f0858b70-8868-474a-bfa0-085bdbda461e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083123156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.4083123156
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.3030422613
Short name T1261
Test name
Test status
Simulation time 105057222 ps
CPU time 2.09 seconds
Started Apr 30 03:06:07 PM PDT 24
Finished Apr 30 03:06:10 PM PDT 24
Peak memory 200380 kb
Host smart-6614f185-3238-4fd0-a3e6-78ea3b242c45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030422613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.3030422613
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.610477895
Short name T68
Test name
Test status
Simulation time 35537303 ps
CPU time 0.63 seconds
Started Apr 30 03:06:08 PM PDT 24
Finished Apr 30 03:06:09 PM PDT 24
Peak memory 195104 kb
Host smart-5d564748-f3b5-4825-b9a7-a76dd09f1840
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610477895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.610477895
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.4158917460
Short name T66
Test name
Test status
Simulation time 978871355 ps
CPU time 2.58 seconds
Started Apr 30 03:06:08 PM PDT 24
Finished Apr 30 03:06:11 PM PDT 24
Peak memory 197980 kb
Host smart-17889fb0-73b4-470c-b811-8d8c39eb4057
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158917460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.4158917460
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2162280510
Short name T64
Test name
Test status
Simulation time 49758484 ps
CPU time 0.6 seconds
Started Apr 30 03:06:09 PM PDT 24
Finished Apr 30 03:06:10 PM PDT 24
Peak memory 195768 kb
Host smart-7c7a163c-27ef-418f-8e28-f245b36cbc54
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162280510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.2162280510
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3164000054
Short name T1222
Test name
Test status
Simulation time 56360257 ps
CPU time 0.85 seconds
Started Apr 30 03:06:17 PM PDT 24
Finished Apr 30 03:06:18 PM PDT 24
Peak memory 200148 kb
Host smart-10da6833-80b0-4853-a31d-d0621e3335e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164000054 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.3164000054
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.87474384
Short name T69
Test name
Test status
Simulation time 13968311 ps
CPU time 0.59 seconds
Started Apr 30 03:06:09 PM PDT 24
Finished Apr 30 03:06:10 PM PDT 24
Peak memory 195888 kb
Host smart-c7e2a000-a923-4d6c-a9e9-78729883789c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87474384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.87474384
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.4063898388
Short name T1276
Test name
Test status
Simulation time 28329338 ps
CPU time 0.56 seconds
Started Apr 30 03:06:09 PM PDT 24
Finished Apr 30 03:06:10 PM PDT 24
Peak memory 194676 kb
Host smart-50b66fe4-6fd4-41ad-acc8-64bb2a2bab86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063898388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.4063898388
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.2513047705
Short name T1269
Test name
Test status
Simulation time 41094200 ps
CPU time 1.03 seconds
Started Apr 30 03:06:07 PM PDT 24
Finished Apr 30 03:06:09 PM PDT 24
Peak memory 200220 kb
Host smart-056b7b80-c60a-45e9-821b-511fae13e408
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513047705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.2513047705
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.4240352855
Short name T1225
Test name
Test status
Simulation time 45905981 ps
CPU time 0.75 seconds
Started Apr 30 03:06:46 PM PDT 24
Finished Apr 30 03:06:48 PM PDT 24
Peak memory 199272 kb
Host smart-7e8a7899-16b1-4b5f-ab52-10cfbc9f8dd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240352855 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.4240352855
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.3071543982
Short name T1219
Test name
Test status
Simulation time 33314695 ps
CPU time 0.56 seconds
Started Apr 30 03:06:43 PM PDT 24
Finished Apr 30 03:06:44 PM PDT 24
Peak memory 195772 kb
Host smart-c2e54d7a-dfd2-4441-8b5f-453f4dc0f1c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071543982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.3071543982
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.596792935
Short name T1234
Test name
Test status
Simulation time 14272914 ps
CPU time 0.57 seconds
Started Apr 30 03:06:44 PM PDT 24
Finished Apr 30 03:06:46 PM PDT 24
Peak memory 194728 kb
Host smart-8b065122-655e-4186-bdc3-28dbb971c4c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596792935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.596792935
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.473494291
Short name T80
Test name
Test status
Simulation time 64506645 ps
CPU time 0.64 seconds
Started Apr 30 03:06:44 PM PDT 24
Finished Apr 30 03:06:45 PM PDT 24
Peak memory 195096 kb
Host smart-71ef15e7-31f9-4225-9cee-8d45f05b02c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473494291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr
_outstanding.473494291
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.1808223064
Short name T1282
Test name
Test status
Simulation time 27729899 ps
CPU time 1.28 seconds
Started Apr 30 03:06:45 PM PDT 24
Finished Apr 30 03:06:47 PM PDT 24
Peak memory 200320 kb
Host smart-484e6643-d0fd-4f3e-a942-7b54a63df913
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808223064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.1808223064
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1668040038
Short name T1273
Test name
Test status
Simulation time 82437781 ps
CPU time 1.32 seconds
Started Apr 30 03:06:46 PM PDT 24
Finished Apr 30 03:06:48 PM PDT 24
Peak memory 199612 kb
Host smart-16cd2c49-b135-4e2d-b8a4-2f78dbe1bc06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668040038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.1668040038
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3108779875
Short name T1295
Test name
Test status
Simulation time 49645337 ps
CPU time 0.81 seconds
Started Apr 30 03:06:45 PM PDT 24
Finished Apr 30 03:06:46 PM PDT 24
Peak memory 200140 kb
Host smart-a46954e8-289c-4732-8f9c-2b09c393e7f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108779875 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.3108779875
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.464129861
Short name T1290
Test name
Test status
Simulation time 24716447 ps
CPU time 0.59 seconds
Started Apr 30 03:06:45 PM PDT 24
Finished Apr 30 03:06:47 PM PDT 24
Peak memory 195632 kb
Host smart-1a47c0a1-51a1-4d74-86bc-b8488c788473
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464129861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.464129861
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.288811832
Short name T1241
Test name
Test status
Simulation time 21963474 ps
CPU time 0.55 seconds
Started Apr 30 03:06:44 PM PDT 24
Finished Apr 30 03:06:45 PM PDT 24
Peak memory 194672 kb
Host smart-45e3409d-7451-459d-9cb6-d61d7f83804e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288811832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.288811832
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.459285747
Short name T1288
Test name
Test status
Simulation time 18295532 ps
CPU time 0.73 seconds
Started Apr 30 03:06:45 PM PDT 24
Finished Apr 30 03:06:47 PM PDT 24
Peak memory 197456 kb
Host smart-85477b0a-541e-4f01-87d1-8da85bf8d97b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459285747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr
_outstanding.459285747
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.3524354706
Short name T1208
Test name
Test status
Simulation time 81590681 ps
CPU time 1.23 seconds
Started Apr 30 03:06:44 PM PDT 24
Finished Apr 30 03:06:46 PM PDT 24
Peak memory 200420 kb
Host smart-7cfde24a-b85e-4583-89f7-f1b8d02e719c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524354706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3524354706
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.763920118
Short name T1226
Test name
Test status
Simulation time 169593560 ps
CPU time 0.93 seconds
Started Apr 30 03:06:43 PM PDT 24
Finished Apr 30 03:06:45 PM PDT 24
Peak memory 199256 kb
Host smart-4602ec1a-a3b5-4793-991d-9f6a9aa5b047
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763920118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.763920118
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2850630098
Short name T1244
Test name
Test status
Simulation time 47595388 ps
CPU time 0.79 seconds
Started Apr 30 03:06:46 PM PDT 24
Finished Apr 30 03:06:47 PM PDT 24
Peak memory 199916 kb
Host smart-56895aa1-77df-4844-bdae-ce8c1b9882d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850630098 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.2850630098
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.1079873543
Short name T1307
Test name
Test status
Simulation time 14434285 ps
CPU time 0.59 seconds
Started Apr 30 03:06:46 PM PDT 24
Finished Apr 30 03:06:48 PM PDT 24
Peak memory 195648 kb
Host smart-cf8a2f0d-7010-4677-b226-2c65872c31b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079873543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.1079873543
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.3321812763
Short name T1224
Test name
Test status
Simulation time 18485555 ps
CPU time 0.54 seconds
Started Apr 30 03:06:44 PM PDT 24
Finished Apr 30 03:06:45 PM PDT 24
Peak memory 194808 kb
Host smart-beb424e9-048e-480d-8779-809945aae102
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321812763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.3321812763
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.289554231
Short name T1248
Test name
Test status
Simulation time 47514325 ps
CPU time 0.73 seconds
Started Apr 30 03:06:44 PM PDT 24
Finished Apr 30 03:06:46 PM PDT 24
Peak memory 197320 kb
Host smart-646c1533-47d7-4d79-b70b-8a23ab1159b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289554231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_csr
_outstanding.289554231
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.11197371
Short name T1217
Test name
Test status
Simulation time 44205314 ps
CPU time 2.12 seconds
Started Apr 30 03:06:46 PM PDT 24
Finished Apr 30 03:06:49 PM PDT 24
Peak memory 200356 kb
Host smart-2a34d379-e40a-4ff9-809b-81459e796c1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11197371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.11197371
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3693800391
Short name T93
Test name
Test status
Simulation time 46423983 ps
CPU time 0.94 seconds
Started Apr 30 03:06:44 PM PDT 24
Finished Apr 30 03:06:45 PM PDT 24
Peak memory 199304 kb
Host smart-609f9f1f-c302-4190-a826-6e678e50ef35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693800391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3693800391
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1387853680
Short name T1189
Test name
Test status
Simulation time 28852557 ps
CPU time 1.2 seconds
Started Apr 30 03:06:53 PM PDT 24
Finished Apr 30 03:06:55 PM PDT 24
Peak memory 200320 kb
Host smart-1b04c978-f168-4e7e-9525-6bd2d7dc50c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387853680 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.1387853680
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.3925359223
Short name T1314
Test name
Test status
Simulation time 12106197 ps
CPU time 0.6 seconds
Started Apr 30 03:06:45 PM PDT 24
Finished Apr 30 03:06:46 PM PDT 24
Peak memory 195696 kb
Host smart-3ef64711-f275-430c-9ff3-5fc0a6161dd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925359223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.3925359223
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.1671325406
Short name T1275
Test name
Test status
Simulation time 41845211 ps
CPU time 0.55 seconds
Started Apr 30 03:06:44 PM PDT 24
Finished Apr 30 03:06:45 PM PDT 24
Peak memory 194716 kb
Host smart-3e00c6e5-3a08-4157-9bc3-f14830127d0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671325406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.1671325406
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2206596837
Short name T1238
Test name
Test status
Simulation time 38668501 ps
CPU time 0.73 seconds
Started Apr 30 03:06:53 PM PDT 24
Finished Apr 30 03:06:55 PM PDT 24
Peak memory 197228 kb
Host smart-d5554364-c375-44f0-90f4-21e8b931ff64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206596837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.2206596837
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.2582413489
Short name T1246
Test name
Test status
Simulation time 104792631 ps
CPU time 1.54 seconds
Started Apr 30 03:06:46 PM PDT 24
Finished Apr 30 03:06:48 PM PDT 24
Peak memory 200356 kb
Host smart-16f98a7f-4466-4349-a9da-0fc8724e3889
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582413489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.2582413489
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2038950005
Short name T136
Test name
Test status
Simulation time 48172104 ps
CPU time 0.96 seconds
Started Apr 30 03:06:45 PM PDT 24
Finished Apr 30 03:06:47 PM PDT 24
Peak memory 199304 kb
Host smart-1199617b-1430-4c9f-a4ff-abf89e804c88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038950005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.2038950005
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.664235613
Short name T1262
Test name
Test status
Simulation time 60433972 ps
CPU time 0.73 seconds
Started Apr 30 03:06:50 PM PDT 24
Finished Apr 30 03:06:51 PM PDT 24
Peak memory 198840 kb
Host smart-b481d8e2-23f7-44cf-af2b-aae7065a7fe9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664235613 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.664235613
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.2048313399
Short name T72
Test name
Test status
Simulation time 21247661 ps
CPU time 0.58 seconds
Started Apr 30 03:06:51 PM PDT 24
Finished Apr 30 03:06:52 PM PDT 24
Peak memory 195700 kb
Host smart-7527b415-3278-42c1-bfe8-f467e73fb3da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048313399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.2048313399
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.3114050795
Short name T1280
Test name
Test status
Simulation time 53352815 ps
CPU time 0.57 seconds
Started Apr 30 03:06:53 PM PDT 24
Finished Apr 30 03:06:54 PM PDT 24
Peak memory 194624 kb
Host smart-44ced33f-524b-4426-abb8-8386bcbd52a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114050795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.3114050795
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3875195803
Short name T1237
Test name
Test status
Simulation time 113781849 ps
CPU time 0.65 seconds
Started Apr 30 03:06:49 PM PDT 24
Finished Apr 30 03:06:50 PM PDT 24
Peak memory 194876 kb
Host smart-fc588c2a-828a-451b-840f-6578e7790cd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875195803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.3875195803
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.3338561174
Short name T1201
Test name
Test status
Simulation time 42064276 ps
CPU time 2.04 seconds
Started Apr 30 03:06:51 PM PDT 24
Finished Apr 30 03:06:53 PM PDT 24
Peak memory 200448 kb
Host smart-67146d2c-3670-495c-a85c-ecad6f3562f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338561174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.3338561174
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2687155604
Short name T1287
Test name
Test status
Simulation time 34424322 ps
CPU time 0.66 seconds
Started Apr 30 03:06:51 PM PDT 24
Finished Apr 30 03:06:52 PM PDT 24
Peak memory 198688 kb
Host smart-b66e0c34-b4b6-4707-a330-b0335edb551e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687155604 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.2687155604
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.916074694
Short name T1215
Test name
Test status
Simulation time 35533407 ps
CPU time 0.59 seconds
Started Apr 30 03:06:52 PM PDT 24
Finished Apr 30 03:06:53 PM PDT 24
Peak memory 195716 kb
Host smart-fbf985e1-ecf1-4f85-b3cf-f19c55e3980f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916074694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.916074694
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.2049412263
Short name T1218
Test name
Test status
Simulation time 12781558 ps
CPU time 0.6 seconds
Started Apr 30 03:06:53 PM PDT 24
Finished Apr 30 03:06:54 PM PDT 24
Peak memory 194720 kb
Host smart-2d6d2972-30dd-4e38-8685-f1bb6a674351
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049412263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.2049412263
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2649695302
Short name T82
Test name
Test status
Simulation time 40656124 ps
CPU time 0.64 seconds
Started Apr 30 03:06:49 PM PDT 24
Finished Apr 30 03:06:50 PM PDT 24
Peak memory 195872 kb
Host smart-6614ecd1-0828-4c8c-b052-190789d6ab1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649695302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.2649695302
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.1503121936
Short name T1256
Test name
Test status
Simulation time 35858750 ps
CPU time 1.63 seconds
Started Apr 30 03:06:53 PM PDT 24
Finished Apr 30 03:06:55 PM PDT 24
Peak memory 200408 kb
Host smart-97523cde-af4d-4d75-baaf-0c864ed3e9d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503121936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.1503121936
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.795099067
Short name T1300
Test name
Test status
Simulation time 109949667 ps
CPU time 0.98 seconds
Started Apr 30 03:06:51 PM PDT 24
Finished Apr 30 03:06:53 PM PDT 24
Peak memory 199536 kb
Host smart-cba70d15-2afc-4d42-9ae5-3f375e060ea4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795099067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.795099067
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3014035670
Short name T1274
Test name
Test status
Simulation time 42354248 ps
CPU time 1.12 seconds
Started Apr 30 03:06:50 PM PDT 24
Finished Apr 30 03:06:52 PM PDT 24
Peak memory 200332 kb
Host smart-a124ff52-6f79-413d-a626-0f3eb4424d21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014035670 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.3014035670
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.4058812014
Short name T1195
Test name
Test status
Simulation time 19244991 ps
CPU time 0.56 seconds
Started Apr 30 03:06:52 PM PDT 24
Finished Apr 30 03:06:53 PM PDT 24
Peak memory 195720 kb
Host smart-251ce60a-fe5e-4984-892f-b34c48220b43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058812014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.4058812014
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.4215843583
Short name T1306
Test name
Test status
Simulation time 24539452 ps
CPU time 0.54 seconds
Started Apr 30 03:06:49 PM PDT 24
Finished Apr 30 03:06:50 PM PDT 24
Peak memory 194592 kb
Host smart-5ab55d39-2846-4fbb-ad46-a822cfcdcb53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215843583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.4215843583
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1433430158
Short name T79
Test name
Test status
Simulation time 26930508 ps
CPU time 0.76 seconds
Started Apr 30 03:06:53 PM PDT 24
Finished Apr 30 03:06:55 PM PDT 24
Peak memory 197144 kb
Host smart-252a91d3-febb-49e4-b858-e2809c9be02d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433430158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.1433430158
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.3388451761
Short name T1202
Test name
Test status
Simulation time 48298713 ps
CPU time 1.2 seconds
Started Apr 30 03:06:49 PM PDT 24
Finished Apr 30 03:06:51 PM PDT 24
Peak memory 200420 kb
Host smart-5858d7d5-78eb-4804-8837-c56dfa461e35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388451761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.3388451761
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.4042193888
Short name T87
Test name
Test status
Simulation time 52104516 ps
CPU time 0.94 seconds
Started Apr 30 03:06:50 PM PDT 24
Finished Apr 30 03:06:52 PM PDT 24
Peak memory 199312 kb
Host smart-aac9efd7-9aa8-4ffc-b469-b0e3235b0a5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042193888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.4042193888
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1489794779
Short name T1266
Test name
Test status
Simulation time 22609897 ps
CPU time 1.12 seconds
Started Apr 30 03:06:58 PM PDT 24
Finished Apr 30 03:06:59 PM PDT 24
Peak memory 200328 kb
Host smart-9d5eca3a-3363-4a5f-85d1-c3b151be4ddf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489794779 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.1489794779
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.2556910230
Short name T70
Test name
Test status
Simulation time 14442144 ps
CPU time 0.6 seconds
Started Apr 30 03:06:58 PM PDT 24
Finished Apr 30 03:06:59 PM PDT 24
Peak memory 195676 kb
Host smart-cb13b662-60e2-4de9-8b7d-d0c26b2dfa2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556910230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.2556910230
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.3819539859
Short name T1221
Test name
Test status
Simulation time 12343719 ps
CPU time 0.58 seconds
Started Apr 30 03:06:50 PM PDT 24
Finished Apr 30 03:06:51 PM PDT 24
Peak memory 194688 kb
Host smart-4bbbe9de-21fe-4bf8-a083-3bcb11e7b1bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819539859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.3819539859
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.379688923
Short name T81
Test name
Test status
Simulation time 21474902 ps
CPU time 0.6 seconds
Started Apr 30 03:06:56 PM PDT 24
Finished Apr 30 03:06:57 PM PDT 24
Peak memory 195828 kb
Host smart-c9957c66-643d-43d5-9651-f03a9e796808
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379688923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr
_outstanding.379688923
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.1887964160
Short name T1285
Test name
Test status
Simulation time 47285572 ps
CPU time 1.28 seconds
Started Apr 30 03:06:49 PM PDT 24
Finished Apr 30 03:06:51 PM PDT 24
Peak memory 200332 kb
Host smart-653e33b3-fe62-4bfe-b687-3a74821356b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887964160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.1887964160
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.841215691
Short name T92
Test name
Test status
Simulation time 670585819 ps
CPU time 1.33 seconds
Started Apr 30 03:06:48 PM PDT 24
Finished Apr 30 03:06:50 PM PDT 24
Peak memory 199612 kb
Host smart-dd22d2bd-ab46-4b80-a70f-266054ed7006
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841215691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.841215691
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1337775186
Short name T1220
Test name
Test status
Simulation time 59356337 ps
CPU time 0.85 seconds
Started Apr 30 03:06:57 PM PDT 24
Finished Apr 30 03:06:59 PM PDT 24
Peak memory 200140 kb
Host smart-e94f276d-4df4-436f-9fd4-f0df7831c1c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337775186 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.1337775186
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.3173812330
Short name T75
Test name
Test status
Simulation time 36141840 ps
CPU time 0.56 seconds
Started Apr 30 03:06:56 PM PDT 24
Finished Apr 30 03:06:57 PM PDT 24
Peak memory 195688 kb
Host smart-eb7f43a1-e61f-4a07-9c5d-ca94fe0c3192
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173812330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3173812330
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3388842455
Short name T1271
Test name
Test status
Simulation time 50692647 ps
CPU time 0.55 seconds
Started Apr 30 03:06:58 PM PDT 24
Finished Apr 30 03:06:59 PM PDT 24
Peak memory 194648 kb
Host smart-b5357c61-fcac-48ab-8b80-08443fedecdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388842455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3388842455
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2060194132
Short name T1251
Test name
Test status
Simulation time 26167974 ps
CPU time 0.63 seconds
Started Apr 30 03:06:58 PM PDT 24
Finished Apr 30 03:07:00 PM PDT 24
Peak memory 195820 kb
Host smart-f4ab0149-ed97-405b-9ff5-961150259a89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060194132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.2060194132
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.701240658
Short name T1198
Test name
Test status
Simulation time 166769980 ps
CPU time 1.24 seconds
Started Apr 30 03:06:58 PM PDT 24
Finished Apr 30 03:07:00 PM PDT 24
Peak memory 200400 kb
Host smart-9caafafe-90ef-434b-a6cd-a3cc2f138991
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701240658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.701240658
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1415393108
Short name T90
Test name
Test status
Simulation time 97798382 ps
CPU time 0.93 seconds
Started Apr 30 03:06:57 PM PDT 24
Finished Apr 30 03:06:59 PM PDT 24
Peak memory 199364 kb
Host smart-ae9d1e60-36a9-40e6-afe3-73b764de3ee5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415393108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1415393108
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.36253055
Short name T1235
Test name
Test status
Simulation time 82379963 ps
CPU time 0.74 seconds
Started Apr 30 03:07:00 PM PDT 24
Finished Apr 30 03:07:01 PM PDT 24
Peak memory 198456 kb
Host smart-a53ecd78-3c6e-4ec1-9c4d-3ba4f7ba0a37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36253055 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.36253055
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.244980503
Short name T1277
Test name
Test status
Simulation time 15443848 ps
CPU time 0.6 seconds
Started Apr 30 03:06:57 PM PDT 24
Finished Apr 30 03:06:58 PM PDT 24
Peak memory 195640 kb
Host smart-c9bac473-f4d4-4e68-9419-c2fb5b405802
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244980503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.244980503
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.556638592
Short name T1272
Test name
Test status
Simulation time 27714483 ps
CPU time 0.55 seconds
Started Apr 30 03:06:56 PM PDT 24
Finished Apr 30 03:06:57 PM PDT 24
Peak memory 194668 kb
Host smart-c2010a40-85a2-44c5-8cdc-68aa2aed823c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556638592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.556638592
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.620873014
Short name T1289
Test name
Test status
Simulation time 37017847 ps
CPU time 0.76 seconds
Started Apr 30 03:06:58 PM PDT 24
Finished Apr 30 03:07:00 PM PDT 24
Peak memory 198380 kb
Host smart-1fdee84b-6e5a-410d-986c-acafab83b92b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620873014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr
_outstanding.620873014
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.2638697858
Short name T1249
Test name
Test status
Simulation time 93484533 ps
CPU time 1.9 seconds
Started Apr 30 03:06:58 PM PDT 24
Finished Apr 30 03:07:01 PM PDT 24
Peak memory 200424 kb
Host smart-a080fcc7-e03c-4c11-a76d-0f672a185b3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638697858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.2638697858
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2928186459
Short name T135
Test name
Test status
Simulation time 140766559 ps
CPU time 0.88 seconds
Started Apr 30 03:06:59 PM PDT 24
Finished Apr 30 03:07:00 PM PDT 24
Peak memory 199244 kb
Host smart-135e1a93-4e0e-4f08-b460-962effd02750
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928186459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.2928186459
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2137075150
Short name T1229
Test name
Test status
Simulation time 67059063 ps
CPU time 0.65 seconds
Started Apr 30 03:06:18 PM PDT 24
Finished Apr 30 03:06:19 PM PDT 24
Peak memory 195780 kb
Host smart-35775048-7891-439e-909f-3de134df927a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137075150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.2137075150
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3707746079
Short name T67
Test name
Test status
Simulation time 221943423 ps
CPU time 2.24 seconds
Started Apr 30 03:06:17 PM PDT 24
Finished Apr 30 03:06:20 PM PDT 24
Peak memory 197884 kb
Host smart-f2008817-4390-4264-afd2-d9fc0a7cd135
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707746079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.3707746079
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.30145487
Short name T1194
Test name
Test status
Simulation time 36089992 ps
CPU time 0.57 seconds
Started Apr 30 03:06:18 PM PDT 24
Finished Apr 30 03:06:19 PM PDT 24
Peak memory 195660 kb
Host smart-786c0765-ed09-45d1-90f3-c7aaeb4c4433
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30145487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.30145487
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.636970764
Short name T1223
Test name
Test status
Simulation time 237595622 ps
CPU time 0.84 seconds
Started Apr 30 03:06:17 PM PDT 24
Finished Apr 30 03:06:18 PM PDT 24
Peak memory 200208 kb
Host smart-e5a9c755-f2a0-40c9-86c4-4718b8a0d8e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636970764 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.636970764
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.3063170340
Short name T1304
Test name
Test status
Simulation time 38912826 ps
CPU time 0.55 seconds
Started Apr 30 03:06:15 PM PDT 24
Finished Apr 30 03:06:16 PM PDT 24
Peak memory 195724 kb
Host smart-be263191-20a6-4768-a49b-d9c9990b0637
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063170340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.3063170340
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.3053053454
Short name T1311
Test name
Test status
Simulation time 41995109 ps
CPU time 0.55 seconds
Started Apr 30 03:06:16 PM PDT 24
Finished Apr 30 03:06:17 PM PDT 24
Peak memory 194620 kb
Host smart-723e82e6-5462-499f-9a82-b2003fa642c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053053454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3053053454
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2816746346
Short name T76
Test name
Test status
Simulation time 31166390 ps
CPU time 0.73 seconds
Started Apr 30 03:06:15 PM PDT 24
Finished Apr 30 03:06:17 PM PDT 24
Peak memory 196196 kb
Host smart-b2f13f12-2b0f-47c9-b529-21e08ddc7fd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816746346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.2816746346
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.1672607405
Short name T1204
Test name
Test status
Simulation time 39889583 ps
CPU time 0.98 seconds
Started Apr 30 03:06:16 PM PDT 24
Finished Apr 30 03:06:17 PM PDT 24
Peak memory 200100 kb
Host smart-03aabf3b-aec4-406a-bedf-e35737041ce2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672607405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.1672607405
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1319383439
Short name T134
Test name
Test status
Simulation time 80181820 ps
CPU time 0.91 seconds
Started Apr 30 03:06:17 PM PDT 24
Finished Apr 30 03:06:19 PM PDT 24
Peak memory 199140 kb
Host smart-709b5d6b-80e9-4380-93ef-4b2f1da2ec4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319383439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.1319383439
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.1133882248
Short name T1259
Test name
Test status
Simulation time 35213994 ps
CPU time 0.55 seconds
Started Apr 30 03:06:57 PM PDT 24
Finished Apr 30 03:06:58 PM PDT 24
Peak memory 194656 kb
Host smart-6acb55f9-8f77-4e8a-858f-5e62b2f1fe7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133882248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.1133882248
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.32817794
Short name T1267
Test name
Test status
Simulation time 53159948 ps
CPU time 0.55 seconds
Started Apr 30 03:06:57 PM PDT 24
Finished Apr 30 03:06:58 PM PDT 24
Peak memory 194648 kb
Host smart-e8e4ce41-48a6-46ca-99b3-dc73850557a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32817794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.32817794
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.2978659336
Short name T1197
Test name
Test status
Simulation time 14334232 ps
CPU time 0.55 seconds
Started Apr 30 03:06:55 PM PDT 24
Finished Apr 30 03:06:56 PM PDT 24
Peak memory 194624 kb
Host smart-f3d18dfa-f671-4fe8-8a32-f1734daca4cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978659336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.2978659336
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.3282694307
Short name T1196
Test name
Test status
Simulation time 15937048 ps
CPU time 0.57 seconds
Started Apr 30 03:06:57 PM PDT 24
Finished Apr 30 03:06:58 PM PDT 24
Peak memory 194776 kb
Host smart-5e73f93d-ee9c-4279-b9c8-28e4315f337b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282694307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.3282694307
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.3896324182
Short name T1284
Test name
Test status
Simulation time 14632506 ps
CPU time 0.57 seconds
Started Apr 30 03:06:54 PM PDT 24
Finished Apr 30 03:06:56 PM PDT 24
Peak memory 194700 kb
Host smart-28e0e6f2-18fe-4ba4-9852-acd4680da6bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896324182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.3896324182
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.3537281372
Short name T1211
Test name
Test status
Simulation time 18432579 ps
CPU time 0.55 seconds
Started Apr 30 03:06:58 PM PDT 24
Finished Apr 30 03:06:59 PM PDT 24
Peak memory 194660 kb
Host smart-a303507b-492b-43e0-b614-b1994532fdd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537281372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.3537281372
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.190042849
Short name T1291
Test name
Test status
Simulation time 12065506 ps
CPU time 0.6 seconds
Started Apr 30 03:06:55 PM PDT 24
Finished Apr 30 03:06:56 PM PDT 24
Peak memory 194680 kb
Host smart-8a118c98-b70b-405a-940e-afdb257f05fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190042849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.190042849
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.376627183
Short name T1190
Test name
Test status
Simulation time 37346235 ps
CPU time 0.55 seconds
Started Apr 30 03:07:00 PM PDT 24
Finished Apr 30 03:07:01 PM PDT 24
Peak memory 194728 kb
Host smart-7f819ffd-9e78-4999-9ce9-7064ce80fb74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376627183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.376627183
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.1016166205
Short name T1253
Test name
Test status
Simulation time 32600481 ps
CPU time 0.57 seconds
Started Apr 30 03:06:56 PM PDT 24
Finished Apr 30 03:06:57 PM PDT 24
Peak memory 194652 kb
Host smart-c10730d1-a7f8-4cd1-a7f3-bd6900ec712f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016166205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.1016166205
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.20512319
Short name T1264
Test name
Test status
Simulation time 25018630 ps
CPU time 0.57 seconds
Started Apr 30 03:06:59 PM PDT 24
Finished Apr 30 03:07:00 PM PDT 24
Peak memory 194728 kb
Host smart-4c97f108-3ede-4c19-9617-e5d934bade63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20512319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.20512319
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3282143727
Short name T1203
Test name
Test status
Simulation time 23808319 ps
CPU time 0.68 seconds
Started Apr 30 03:06:24 PM PDT 24
Finished Apr 30 03:06:25 PM PDT 24
Peak memory 195848 kb
Host smart-5f801556-a9b1-4411-9a84-efba804336fd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282143727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.3282143727
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3485238732
Short name T1315
Test name
Test status
Simulation time 327415022 ps
CPU time 2.51 seconds
Started Apr 30 03:06:24 PM PDT 24
Finished Apr 30 03:06:27 PM PDT 24
Peak memory 197932 kb
Host smart-b55a7d44-4c36-4416-b8b0-e1f8a8d987cc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485238732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.3485238732
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.341177196
Short name T71
Test name
Test status
Simulation time 49435717 ps
CPU time 0.57 seconds
Started Apr 30 03:06:23 PM PDT 24
Finished Apr 30 03:06:24 PM PDT 24
Peak memory 195628 kb
Host smart-8bbaf5ea-be21-4861-880d-7408ac95839e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341177196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.341177196
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2121983012
Short name T1199
Test name
Test status
Simulation time 52300607 ps
CPU time 0.75 seconds
Started Apr 30 03:06:24 PM PDT 24
Finished Apr 30 03:06:25 PM PDT 24
Peak memory 199288 kb
Host smart-98875094-c3f2-4ef8-b9a0-893eea7b29f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121983012 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.2121983012
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.886304372
Short name T73
Test name
Test status
Simulation time 53005219 ps
CPU time 0.58 seconds
Started Apr 30 03:06:26 PM PDT 24
Finished Apr 30 03:06:27 PM PDT 24
Peak memory 195756 kb
Host smart-855479fe-7954-4e64-80cd-98f299df7632
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886304372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.886304372
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.479372548
Short name T1254
Test name
Test status
Simulation time 30902081 ps
CPU time 0.56 seconds
Started Apr 30 03:06:16 PM PDT 24
Finished Apr 30 03:06:17 PM PDT 24
Peak memory 194796 kb
Host smart-fc97f80b-9f3c-43e9-89b1-1db97e9a5ab8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479372548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.479372548
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2859005529
Short name T1293
Test name
Test status
Simulation time 45454926 ps
CPU time 0.65 seconds
Started Apr 30 03:06:26 PM PDT 24
Finished Apr 30 03:06:28 PM PDT 24
Peak memory 195916 kb
Host smart-92861ae9-9725-482b-9db8-b84ea09ff019
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859005529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.2859005529
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.2306691060
Short name T1228
Test name
Test status
Simulation time 142437232 ps
CPU time 2.12 seconds
Started Apr 30 03:06:16 PM PDT 24
Finished Apr 30 03:06:19 PM PDT 24
Peak memory 200428 kb
Host smart-45aa776d-cf3c-4e19-af1a-782bd71cf205
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306691060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2306691060
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3128524675
Short name T133
Test name
Test status
Simulation time 97382399 ps
CPU time 1.28 seconds
Started Apr 30 03:06:16 PM PDT 24
Finished Apr 30 03:06:18 PM PDT 24
Peak memory 199600 kb
Host smart-5577692e-3926-4fab-b4d6-c517194a0850
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128524675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3128524675
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.3111497585
Short name T1242
Test name
Test status
Simulation time 13105260 ps
CPU time 0.57 seconds
Started Apr 30 03:06:58 PM PDT 24
Finished Apr 30 03:07:00 PM PDT 24
Peak memory 194700 kb
Host smart-d5669fea-bb3b-4c7f-88c0-c0fba19c22cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111497585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.3111497585
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.1243936646
Short name T1205
Test name
Test status
Simulation time 19085079 ps
CPU time 0.57 seconds
Started Apr 30 03:07:03 PM PDT 24
Finished Apr 30 03:07:04 PM PDT 24
Peak memory 194640 kb
Host smart-73cb9ff0-44e4-4c57-8c48-11da590c99d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243936646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.1243936646
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.2377055825
Short name T1200
Test name
Test status
Simulation time 20402137 ps
CPU time 0.59 seconds
Started Apr 30 03:07:03 PM PDT 24
Finished Apr 30 03:07:04 PM PDT 24
Peak memory 194676 kb
Host smart-fe4b09f6-d082-4b38-8479-6fe79ce0715c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377055825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.2377055825
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.4276662483
Short name T1240
Test name
Test status
Simulation time 45532234 ps
CPU time 0.59 seconds
Started Apr 30 03:07:02 PM PDT 24
Finished Apr 30 03:07:04 PM PDT 24
Peak memory 194688 kb
Host smart-dbf82ad5-06ee-4a41-94f8-67204bef7a1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276662483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.4276662483
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.567199213
Short name T1255
Test name
Test status
Simulation time 14906758 ps
CPU time 0.61 seconds
Started Apr 30 03:07:01 PM PDT 24
Finished Apr 30 03:07:02 PM PDT 24
Peak memory 194860 kb
Host smart-2c719bdd-706c-48b0-bf53-8d9d6a18e9c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567199213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.567199213
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.2471197069
Short name T1278
Test name
Test status
Simulation time 61946871 ps
CPU time 0.54 seconds
Started Apr 30 03:07:01 PM PDT 24
Finished Apr 30 03:07:02 PM PDT 24
Peak memory 194792 kb
Host smart-947acba4-24bb-4306-be0d-0bd3c6d1b5a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471197069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.2471197069
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.3972301161
Short name T1247
Test name
Test status
Simulation time 13887116 ps
CPU time 0.62 seconds
Started Apr 30 03:07:02 PM PDT 24
Finished Apr 30 03:07:03 PM PDT 24
Peak memory 194704 kb
Host smart-65c95a7f-0a6d-41cf-95ac-d6cc4cbdfc78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972301161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.3972301161
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.2700130084
Short name T1294
Test name
Test status
Simulation time 15725763 ps
CPU time 0.56 seconds
Started Apr 30 03:07:02 PM PDT 24
Finished Apr 30 03:07:03 PM PDT 24
Peak memory 194640 kb
Host smart-7a4fb513-9ac4-40a3-b098-90e2429b2b01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700130084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.2700130084
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.2629548368
Short name T1214
Test name
Test status
Simulation time 14323779 ps
CPU time 0.57 seconds
Started Apr 30 03:07:02 PM PDT 24
Finished Apr 30 03:07:04 PM PDT 24
Peak memory 194680 kb
Host smart-a535b449-bfe4-4cea-853e-229b4e9a90f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629548368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.2629548368
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.2743745902
Short name T1231
Test name
Test status
Simulation time 42814397 ps
CPU time 0.55 seconds
Started Apr 30 03:07:03 PM PDT 24
Finished Apr 30 03:07:04 PM PDT 24
Peak memory 194612 kb
Host smart-56e63aba-c9d9-447f-8736-6112081a2905
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743745902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.2743745902
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3638080853
Short name T1317
Test name
Test status
Simulation time 29607740 ps
CPU time 0.75 seconds
Started Apr 30 03:06:29 PM PDT 24
Finished Apr 30 03:06:30 PM PDT 24
Peak memory 196588 kb
Host smart-047556c4-f2d8-4bfe-a309-1c632e4a0e9c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638080853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.3638080853
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.529955658
Short name T1193
Test name
Test status
Simulation time 2729249460 ps
CPU time 2.55 seconds
Started Apr 30 03:06:24 PM PDT 24
Finished Apr 30 03:06:27 PM PDT 24
Peak memory 198296 kb
Host smart-6e47e39a-21b1-4609-89f1-d18dea5afeda
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529955658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.529955658
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.3619863318
Short name T1206
Test name
Test status
Simulation time 16861086 ps
CPU time 0.59 seconds
Started Apr 30 03:06:25 PM PDT 24
Finished Apr 30 03:06:26 PM PDT 24
Peak memory 195676 kb
Host smart-7f487591-a1d1-4ec9-8840-c925bf78cb05
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619863318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.3619863318
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.345747269
Short name T1286
Test name
Test status
Simulation time 61200146 ps
CPU time 0.71 seconds
Started Apr 30 03:06:30 PM PDT 24
Finished Apr 30 03:06:32 PM PDT 24
Peak memory 198448 kb
Host smart-2806da1d-d085-4c89-81d4-073fe49f3096
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345747269 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.345747269
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.1157486924
Short name T1232
Test name
Test status
Simulation time 23287843 ps
CPU time 0.57 seconds
Started Apr 30 03:06:26 PM PDT 24
Finished Apr 30 03:06:27 PM PDT 24
Peak memory 195704 kb
Host smart-f848198d-0dc8-453e-8243-a4d7cbb2a728
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157486924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.1157486924
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.2280440865
Short name T1210
Test name
Test status
Simulation time 22116228 ps
CPU time 0.57 seconds
Started Apr 30 03:06:25 PM PDT 24
Finished Apr 30 03:06:26 PM PDT 24
Peak memory 194736 kb
Host smart-9edcbc94-7502-489c-8476-14bea7c31846
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280440865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.2280440865
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.3680162981
Short name T74
Test name
Test status
Simulation time 93654060 ps
CPU time 0.7 seconds
Started Apr 30 03:06:33 PM PDT 24
Finished Apr 30 03:06:34 PM PDT 24
Peak memory 197396 kb
Host smart-3d1f14c7-6e6d-4685-a4bf-00240daa463f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680162981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.3680162981
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.4017854663
Short name T1296
Test name
Test status
Simulation time 308919891 ps
CPU time 1.52 seconds
Started Apr 30 03:06:26 PM PDT 24
Finished Apr 30 03:06:28 PM PDT 24
Peak memory 200356 kb
Host smart-f5d302f3-acc1-4675-be9a-ce71ffc0a39f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017854663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.4017854663
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3096066346
Short name T95
Test name
Test status
Simulation time 73649895 ps
CPU time 1.28 seconds
Started Apr 30 03:06:26 PM PDT 24
Finished Apr 30 03:06:28 PM PDT 24
Peak memory 199456 kb
Host smart-e20f4998-935e-4d31-b51c-44f96321daa1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096066346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.3096066346
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.3670499907
Short name T1230
Test name
Test status
Simulation time 20601015 ps
CPU time 0.57 seconds
Started Apr 30 03:07:04 PM PDT 24
Finished Apr 30 03:07:05 PM PDT 24
Peak memory 194632 kb
Host smart-2de1dd00-b9f7-4393-8143-96f330a6cf0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670499907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.3670499907
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.3167800727
Short name T1209
Test name
Test status
Simulation time 12874211 ps
CPU time 0.56 seconds
Started Apr 30 03:07:01 PM PDT 24
Finished Apr 30 03:07:02 PM PDT 24
Peak memory 194692 kb
Host smart-5fc8b958-cc59-4562-8515-f6a6f2dd78c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167800727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.3167800727
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.151268605
Short name T1298
Test name
Test status
Simulation time 13143493 ps
CPU time 0.57 seconds
Started Apr 30 03:07:03 PM PDT 24
Finished Apr 30 03:07:05 PM PDT 24
Peak memory 194644 kb
Host smart-cd137c17-3763-490a-96a5-5a970b677005
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151268605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.151268605
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.3751805373
Short name T1227
Test name
Test status
Simulation time 36274487 ps
CPU time 0.56 seconds
Started Apr 30 03:07:03 PM PDT 24
Finished Apr 30 03:07:04 PM PDT 24
Peak memory 194720 kb
Host smart-aee277a9-e919-41f0-bd29-2ec67e8dd3a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751805373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.3751805373
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.2939974123
Short name T1260
Test name
Test status
Simulation time 45480207 ps
CPU time 0.56 seconds
Started Apr 30 03:07:01 PM PDT 24
Finished Apr 30 03:07:02 PM PDT 24
Peak memory 194636 kb
Host smart-e911d368-b51b-49e5-8b8f-96ba2cacc7e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939974123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.2939974123
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.65473699
Short name T1305
Test name
Test status
Simulation time 14319870 ps
CPU time 0.56 seconds
Started Apr 30 03:07:01 PM PDT 24
Finished Apr 30 03:07:02 PM PDT 24
Peak memory 194628 kb
Host smart-1bb92541-6afa-48da-9618-61b702079eb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65473699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.65473699
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.1152426365
Short name T1301
Test name
Test status
Simulation time 187786556 ps
CPU time 0.56 seconds
Started Apr 30 03:07:04 PM PDT 24
Finished Apr 30 03:07:05 PM PDT 24
Peak memory 194648 kb
Host smart-470bbf0b-9496-4bda-8e69-037649ed32f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152426365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.1152426365
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.3446294109
Short name T1263
Test name
Test status
Simulation time 22564714 ps
CPU time 0.65 seconds
Started Apr 30 03:07:01 PM PDT 24
Finished Apr 30 03:07:02 PM PDT 24
Peak memory 194696 kb
Host smart-09c8d715-b3f9-4fe3-a171-bc2ef47ee2cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446294109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.3446294109
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.2913336664
Short name T1265
Test name
Test status
Simulation time 38978836 ps
CPU time 0.56 seconds
Started Apr 30 03:07:00 PM PDT 24
Finished Apr 30 03:07:01 PM PDT 24
Peak memory 194740 kb
Host smart-6f255f55-2d72-470a-b0de-8681debf0097
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913336664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2913336664
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.1719160567
Short name T1308
Test name
Test status
Simulation time 55837793 ps
CPU time 0.62 seconds
Started Apr 30 03:07:02 PM PDT 24
Finished Apr 30 03:07:04 PM PDT 24
Peak memory 194648 kb
Host smart-7ca4e808-665e-4a0a-963a-7330227c5ab2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719160567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.1719160567
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.253718828
Short name T1233
Test name
Test status
Simulation time 90229534 ps
CPU time 1.14 seconds
Started Apr 30 03:06:30 PM PDT 24
Finished Apr 30 03:06:32 PM PDT 24
Peak memory 200332 kb
Host smart-8208fec4-423e-48a9-bcf3-84fb3def24db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253718828 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.253718828
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.4453171
Short name T65
Test name
Test status
Simulation time 28591294 ps
CPU time 0.58 seconds
Started Apr 30 03:06:33 PM PDT 24
Finished Apr 30 03:06:34 PM PDT 24
Peak memory 195752 kb
Host smart-6fd2781c-d6e3-42dd-a95e-c409d87f532b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4453171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.4453171
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.2263251723
Short name T1297
Test name
Test status
Simulation time 11093294 ps
CPU time 0.57 seconds
Started Apr 30 03:06:33 PM PDT 24
Finished Apr 30 03:06:34 PM PDT 24
Peak memory 194708 kb
Host smart-a1bd01c8-fe47-4dac-a2e6-c499965ea772
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263251723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.2263251723
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.404697430
Short name T1303
Test name
Test status
Simulation time 97300190 ps
CPU time 0.69 seconds
Started Apr 30 03:06:32 PM PDT 24
Finished Apr 30 03:06:33 PM PDT 24
Peak memory 197032 kb
Host smart-a7280891-5656-429e-83a7-973997f57000
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404697430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_
outstanding.404697430
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.2386649756
Short name T1252
Test name
Test status
Simulation time 34542416 ps
CPU time 0.96 seconds
Started Apr 30 03:06:31 PM PDT 24
Finished Apr 30 03:06:32 PM PDT 24
Peak memory 200204 kb
Host smart-e9e7f90b-bee3-4fad-b771-86a5c6355a0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386649756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.2386649756
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.538306485
Short name T1309
Test name
Test status
Simulation time 172935639 ps
CPU time 1.37 seconds
Started Apr 30 03:06:35 PM PDT 24
Finished Apr 30 03:06:37 PM PDT 24
Peak memory 199700 kb
Host smart-58fa6a10-2814-4247-a39e-823be30f0f09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538306485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.538306485
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1545601161
Short name T1258
Test name
Test status
Simulation time 72000966 ps
CPU time 0.69 seconds
Started Apr 30 03:06:30 PM PDT 24
Finished Apr 30 03:06:31 PM PDT 24
Peak memory 198604 kb
Host smart-95ea42c6-2d9d-475b-9376-1477f0436a0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545601161 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.1545601161
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.2334626929
Short name T1268
Test name
Test status
Simulation time 16304047 ps
CPU time 0.58 seconds
Started Apr 30 03:06:31 PM PDT 24
Finished Apr 30 03:06:32 PM PDT 24
Peak memory 195700 kb
Host smart-5f70973d-c612-4de5-92ba-9facbccc0068
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334626929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.2334626929
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.1087587935
Short name T1257
Test name
Test status
Simulation time 40205643 ps
CPU time 0.59 seconds
Started Apr 30 03:06:36 PM PDT 24
Finished Apr 30 03:06:37 PM PDT 24
Peak memory 194404 kb
Host smart-af32139b-29f3-486b-9d29-9baf94dee76e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087587935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.1087587935
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2941634521
Short name T1313
Test name
Test status
Simulation time 40788977 ps
CPU time 0.67 seconds
Started Apr 30 03:06:36 PM PDT 24
Finished Apr 30 03:06:37 PM PDT 24
Peak memory 194484 kb
Host smart-ba121f60-e87c-4110-a01d-b7a3f732ccc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941634521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.2941634521
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.1238842350
Short name T1212
Test name
Test status
Simulation time 414987437 ps
CPU time 1.46 seconds
Started Apr 30 03:06:29 PM PDT 24
Finished Apr 30 03:06:31 PM PDT 24
Peak memory 200404 kb
Host smart-15935204-7cdf-42e7-b6bd-ed12a15e0fa0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238842350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1238842350
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2343612118
Short name T94
Test name
Test status
Simulation time 176532016 ps
CPU time 1.28 seconds
Started Apr 30 03:06:31 PM PDT 24
Finished Apr 30 03:06:33 PM PDT 24
Peak memory 199700 kb
Host smart-a0701b08-fb47-4eba-af95-0197f4ce4f81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343612118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.2343612118
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2220990328
Short name T1213
Test name
Test status
Simulation time 24202608 ps
CPU time 0.81 seconds
Started Apr 30 03:06:38 PM PDT 24
Finished Apr 30 03:06:39 PM PDT 24
Peak memory 199180 kb
Host smart-88f02dcd-66a9-4214-a99e-ab5922854942
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220990328 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.2220990328
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.2436999427
Short name T1191
Test name
Test status
Simulation time 16690074 ps
CPU time 0.6 seconds
Started Apr 30 03:06:38 PM PDT 24
Finished Apr 30 03:06:40 PM PDT 24
Peak memory 195700 kb
Host smart-4f77d83b-d3ce-47d4-a08e-2a5e4c6cbeb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436999427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.2436999427
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.1722823048
Short name T1216
Test name
Test status
Simulation time 57228836 ps
CPU time 0.54 seconds
Started Apr 30 03:06:39 PM PDT 24
Finished Apr 30 03:06:40 PM PDT 24
Peak memory 194720 kb
Host smart-2fb40afc-9076-47b2-a662-cea6925769fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722823048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.1722823048
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.3106626712
Short name T78
Test name
Test status
Simulation time 37744914 ps
CPU time 0.65 seconds
Started Apr 30 03:06:38 PM PDT 24
Finished Apr 30 03:06:40 PM PDT 24
Peak memory 195960 kb
Host smart-cbfefe49-a7ee-49cc-a340-f26f9f550d34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106626712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.3106626712
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.128999528
Short name T1250
Test name
Test status
Simulation time 46607358 ps
CPU time 1.21 seconds
Started Apr 30 03:06:35 PM PDT 24
Finished Apr 30 03:06:36 PM PDT 24
Peak memory 200384 kb
Host smart-2fe3073e-78f4-45f0-aa1e-b2f2327e3eeb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128999528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.128999528
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.4038920742
Short name T88
Test name
Test status
Simulation time 929637860 ps
CPU time 1.19 seconds
Started Apr 30 03:06:38 PM PDT 24
Finished Apr 30 03:06:40 PM PDT 24
Peak memory 199524 kb
Host smart-090661d0-2d42-4659-bebd-2f65782ce5df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038920742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.4038920742
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1652237990
Short name T1292
Test name
Test status
Simulation time 108040730 ps
CPU time 0.83 seconds
Started Apr 30 03:06:38 PM PDT 24
Finished Apr 30 03:06:40 PM PDT 24
Peak memory 200188 kb
Host smart-0d8ad2a4-0fe1-46ef-9bb3-df9d424c8fd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652237990 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1652237990
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.3058043798
Short name T1245
Test name
Test status
Simulation time 11686855 ps
CPU time 0.59 seconds
Started Apr 30 03:06:38 PM PDT 24
Finished Apr 30 03:06:40 PM PDT 24
Peak memory 195704 kb
Host smart-14059633-31eb-4f49-bf88-423c13ae18e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058043798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.3058043798
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.353932611
Short name T1270
Test name
Test status
Simulation time 31534874 ps
CPU time 0.56 seconds
Started Apr 30 03:06:39 PM PDT 24
Finished Apr 30 03:06:40 PM PDT 24
Peak memory 194676 kb
Host smart-c4bb2f81-821c-4d40-8bde-efe780ee1647
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353932611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.353932611
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.2491152024
Short name T1243
Test name
Test status
Simulation time 18324014 ps
CPU time 0.6 seconds
Started Apr 30 03:06:38 PM PDT 24
Finished Apr 30 03:06:39 PM PDT 24
Peak memory 195888 kb
Host smart-4d1a3424-f7c2-4598-9eef-af249c2f613c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491152024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.2491152024
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.501920041
Short name T1239
Test name
Test status
Simulation time 49043248 ps
CPU time 1.18 seconds
Started Apr 30 03:06:41 PM PDT 24
Finished Apr 30 03:06:42 PM PDT 24
Peak memory 200148 kb
Host smart-514d9aef-eead-4d9e-90a9-a6b3322e9a44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501920041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.501920041
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1333313549
Short name T132
Test name
Test status
Simulation time 342916321 ps
CPU time 1.26 seconds
Started Apr 30 03:06:38 PM PDT 24
Finished Apr 30 03:06:41 PM PDT 24
Peak memory 199700 kb
Host smart-a7bc4bec-db4c-49c2-b8e3-b28aa8c6d3dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333313549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.1333313549
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1903683141
Short name T1281
Test name
Test status
Simulation time 37505174 ps
CPU time 1.11 seconds
Started Apr 30 03:06:46 PM PDT 24
Finished Apr 30 03:06:47 PM PDT 24
Peak memory 200136 kb
Host smart-ab24edb7-99ed-4921-901b-d4ccba5c8d9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903683141 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.1903683141
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.2757860741
Short name T1302
Test name
Test status
Simulation time 18092845 ps
CPU time 0.61 seconds
Started Apr 30 03:06:40 PM PDT 24
Finished Apr 30 03:06:41 PM PDT 24
Peak memory 195720 kb
Host smart-cc7b0972-bb9d-4788-b4dc-2f79f029d055
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757860741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.2757860741
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.1545408582
Short name T1236
Test name
Test status
Simulation time 19920818 ps
CPU time 0.64 seconds
Started Apr 30 03:06:39 PM PDT 24
Finished Apr 30 03:06:40 PM PDT 24
Peak memory 194644 kb
Host smart-4872b304-693c-4846-ba0e-7bcb958a4edb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545408582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1545408582
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.3565540578
Short name T83
Test name
Test status
Simulation time 12479094 ps
CPU time 0.66 seconds
Started Apr 30 03:06:45 PM PDT 24
Finished Apr 30 03:06:47 PM PDT 24
Peak memory 196972 kb
Host smart-20716d00-f543-469e-8000-bf915f54d22a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565540578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.3565540578
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.3929174812
Short name T1192
Test name
Test status
Simulation time 71996636 ps
CPU time 1.66 seconds
Started Apr 30 03:06:40 PM PDT 24
Finished Apr 30 03:06:42 PM PDT 24
Peak memory 200292 kb
Host smart-61fd97e8-6141-4ccf-8c1b-5bd48a356979
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929174812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.3929174812
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.938254176
Short name T1299
Test name
Test status
Simulation time 191273514 ps
CPU time 0.93 seconds
Started Apr 30 03:06:42 PM PDT 24
Finished Apr 30 03:06:44 PM PDT 24
Peak memory 199152 kb
Host smart-000a78fc-ed98-4bee-a8e9-ec40b06d74ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938254176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.938254176
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.1883932640
Short name T462
Test name
Test status
Simulation time 13079970 ps
CPU time 0.55 seconds
Started Apr 30 03:10:54 PM PDT 24
Finished Apr 30 03:10:55 PM PDT 24
Peak memory 195776 kb
Host smart-d459afbc-9a9a-428f-8ea2-89ad27282252
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883932640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.1883932640
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.1426063495
Short name T1148
Test name
Test status
Simulation time 91736038237 ps
CPU time 69.7 seconds
Started Apr 30 03:10:48 PM PDT 24
Finished Apr 30 03:11:59 PM PDT 24
Peak memory 200432 kb
Host smart-219303a1-2762-4379-8f23-a464c22d92a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426063495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.1426063495
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.3081108470
Short name T182
Test name
Test status
Simulation time 103943924439 ps
CPU time 45.9 seconds
Started Apr 30 03:10:49 PM PDT 24
Finished Apr 30 03:11:36 PM PDT 24
Peak memory 200256 kb
Host smart-2467e022-3c1f-4b1b-bf5b-215ec788ce8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081108470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.3081108470
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.1539911654
Short name T279
Test name
Test status
Simulation time 81266232919 ps
CPU time 122.69 seconds
Started Apr 30 03:10:49 PM PDT 24
Finished Apr 30 03:12:53 PM PDT 24
Peak memory 200320 kb
Host smart-5c085e41-0250-4e1f-a87a-0fbcb4d2932d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539911654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.1539911654
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.897031290
Short name T613
Test name
Test status
Simulation time 23987359995 ps
CPU time 35.33 seconds
Started Apr 30 03:10:49 PM PDT 24
Finished Apr 30 03:11:25 PM PDT 24
Peak memory 200104 kb
Host smart-3c6d17ef-cf3c-41a9-8c3c-5e7cfdb65a6e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897031290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.897031290
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.800216842
Short name T563
Test name
Test status
Simulation time 119129594049 ps
CPU time 289.57 seconds
Started Apr 30 03:10:55 PM PDT 24
Finished Apr 30 03:15:45 PM PDT 24
Peak memory 200484 kb
Host smart-dbf8c287-a406-4d7f-8025-a25f1c147025
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=800216842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.800216842
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.2643256574
Short name T513
Test name
Test status
Simulation time 4900241646 ps
CPU time 8.69 seconds
Started Apr 30 03:10:55 PM PDT 24
Finished Apr 30 03:11:05 PM PDT 24
Peak memory 200440 kb
Host smart-f86be132-7a71-47d9-b94b-a38334365ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643256574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.2643256574
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.3616274210
Short name T301
Test name
Test status
Simulation time 467225834103 ps
CPU time 71.8 seconds
Started Apr 30 03:10:50 PM PDT 24
Finished Apr 30 03:12:02 PM PDT 24
Peak memory 200640 kb
Host smart-5d52f2ae-fa08-41f2-81ac-692dd94eef2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616274210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.3616274210
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.177893427
Short name T943
Test name
Test status
Simulation time 13194747002 ps
CPU time 629.83 seconds
Started Apr 30 03:10:55 PM PDT 24
Finished Apr 30 03:21:26 PM PDT 24
Peak memory 200476 kb
Host smart-4a17dd85-3c55-4218-9030-48d18db28320
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=177893427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.177893427
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.821170454
Short name T677
Test name
Test status
Simulation time 2189200494 ps
CPU time 15.37 seconds
Started Apr 30 03:10:50 PM PDT 24
Finished Apr 30 03:11:06 PM PDT 24
Peak memory 198576 kb
Host smart-948dc7b2-e34e-457b-91fd-39abf99ae3f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=821170454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.821170454
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.1727674601
Short name T49
Test name
Test status
Simulation time 13903359610 ps
CPU time 8.92 seconds
Started Apr 30 03:10:49 PM PDT 24
Finished Apr 30 03:10:59 PM PDT 24
Peak memory 200392 kb
Host smart-9b54685e-1af2-48c2-abf4-e9da8e9a7991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727674601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.1727674601
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.3896847846
Short name T443
Test name
Test status
Simulation time 3724658928 ps
CPU time 6.65 seconds
Started Apr 30 03:10:51 PM PDT 24
Finished Apr 30 03:10:58 PM PDT 24
Peak memory 196420 kb
Host smart-ab33976e-e74f-4179-afba-fd4be35f5fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896847846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.3896847846
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_stress_all.81110133
Short name T973
Test name
Test status
Simulation time 38241566304 ps
CPU time 164.72 seconds
Started Apr 30 03:10:57 PM PDT 24
Finished Apr 30 03:13:42 PM PDT 24
Peak memory 200440 kb
Host smart-b1509111-7c6a-46b8-90fb-30021222e4fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81110133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.81110133
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.972311874
Short name T200
Test name
Test status
Simulation time 48602835213 ps
CPU time 416.16 seconds
Started Apr 30 03:11:00 PM PDT 24
Finished Apr 30 03:17:58 PM PDT 24
Peak memory 217084 kb
Host smart-8549822f-558b-49ad-81c6-0be558032f0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972311874 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.972311874
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.3651699902
Short name T560
Test name
Test status
Simulation time 1385169301 ps
CPU time 1.84 seconds
Started Apr 30 03:10:50 PM PDT 24
Finished Apr 30 03:10:52 PM PDT 24
Peak memory 199280 kb
Host smart-09f657dc-72ba-46f7-bc5e-b3e015c8d0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651699902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.3651699902
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.4026552215
Short name T532
Test name
Test status
Simulation time 10422793356 ps
CPU time 18.65 seconds
Started Apr 30 03:10:51 PM PDT 24
Finished Apr 30 03:11:10 PM PDT 24
Peak memory 200416 kb
Host smart-1d0cf74f-3e64-4b87-b54a-3f73f7705ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026552215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.4026552215
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.2874747906
Short name T906
Test name
Test status
Simulation time 30067167 ps
CPU time 0.53 seconds
Started Apr 30 03:11:07 PM PDT 24
Finished Apr 30 03:11:08 PM PDT 24
Peak memory 195240 kb
Host smart-96bf2513-622c-491f-b643-e92155a2739b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874747906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.2874747906
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.3609743148
Short name T976
Test name
Test status
Simulation time 85633406203 ps
CPU time 601.81 seconds
Started Apr 30 03:11:02 PM PDT 24
Finished Apr 30 03:21:05 PM PDT 24
Peak memory 200360 kb
Host smart-92c86fde-df87-46bc-af29-0a34a99f0104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609743148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.3609743148
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.2589493902
Short name T148
Test name
Test status
Simulation time 92067975840 ps
CPU time 23.1 seconds
Started Apr 30 03:11:00 PM PDT 24
Finished Apr 30 03:11:23 PM PDT 24
Peak memory 200348 kb
Host smart-59f95c43-90b4-4348-ba66-90950787e65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589493902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.2589493902
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_intr.1619534221
Short name T706
Test name
Test status
Simulation time 38187665881 ps
CPU time 64.83 seconds
Started Apr 30 03:11:02 PM PDT 24
Finished Apr 30 03:12:08 PM PDT 24
Peak memory 200248 kb
Host smart-2dcbd36c-5fff-4230-811a-dc868cdf713a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619534221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.1619534221
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.3746859018
Short name T474
Test name
Test status
Simulation time 76076443569 ps
CPU time 693.08 seconds
Started Apr 30 03:11:00 PM PDT 24
Finished Apr 30 03:22:34 PM PDT 24
Peak memory 200364 kb
Host smart-1b00da8e-b3cb-4331-9656-1d245520cef0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3746859018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.3746859018
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.3958772832
Short name T1082
Test name
Test status
Simulation time 1597506768 ps
CPU time 1.82 seconds
Started Apr 30 03:11:01 PM PDT 24
Finished Apr 30 03:11:04 PM PDT 24
Peak memory 199380 kb
Host smart-ae92b2ab-d4a1-448b-988b-c83b0ec3707f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958772832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.3958772832
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.2298472212
Short name T1120
Test name
Test status
Simulation time 68248412575 ps
CPU time 22.62 seconds
Started Apr 30 03:11:01 PM PDT 24
Finished Apr 30 03:11:24 PM PDT 24
Peak memory 200612 kb
Host smart-01553c4d-c505-4711-ac3f-aba5b77a30fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298472212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.2298472212
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.637813329
Short name T263
Test name
Test status
Simulation time 25154685400 ps
CPU time 160.91 seconds
Started Apr 30 03:11:02 PM PDT 24
Finished Apr 30 03:13:44 PM PDT 24
Peak memory 200364 kb
Host smart-bb554a33-d074-447a-94d1-479b979cebb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=637813329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.637813329
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.4027322938
Short name T362
Test name
Test status
Simulation time 3693461546 ps
CPU time 29.42 seconds
Started Apr 30 03:11:02 PM PDT 24
Finished Apr 30 03:11:32 PM PDT 24
Peak memory 199548 kb
Host smart-035832b9-1c74-4736-8e67-67f0e3b9d34c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4027322938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.4027322938
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.3965571952
Short name T504
Test name
Test status
Simulation time 4889641534 ps
CPU time 8.45 seconds
Started Apr 30 03:11:01 PM PDT 24
Finished Apr 30 03:11:10 PM PDT 24
Peak memory 196428 kb
Host smart-4d246e9e-8501-40e6-925e-4dfea61f2f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965571952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.3965571952
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.937139836
Short name T26
Test name
Test status
Simulation time 134784902 ps
CPU time 0.76 seconds
Started Apr 30 03:11:10 PM PDT 24
Finished Apr 30 03:11:11 PM PDT 24
Peak memory 218404 kb
Host smart-60322d3f-06a5-447d-9235-fdbfed75923b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937139836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.937139836
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.4055003310
Short name T1056
Test name
Test status
Simulation time 11097715562 ps
CPU time 39.01 seconds
Started Apr 30 03:10:56 PM PDT 24
Finished Apr 30 03:11:36 PM PDT 24
Peak memory 200316 kb
Host smart-b7eae3a7-39fd-488b-a1fa-8e8b2e4b9f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055003310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.4055003310
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.3965877933
Short name T169
Test name
Test status
Simulation time 230305726490 ps
CPU time 182.51 seconds
Started Apr 30 03:11:08 PM PDT 24
Finished Apr 30 03:14:12 PM PDT 24
Peak memory 208808 kb
Host smart-a565910a-d903-4b7d-b539-10e23dce2e2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965877933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.3965877933
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.3221251097
Short name T985
Test name
Test status
Simulation time 62906580240 ps
CPU time 346.97 seconds
Started Apr 30 03:11:01 PM PDT 24
Finished Apr 30 03:16:49 PM PDT 24
Peak memory 216908 kb
Host smart-5cb6ff3a-253b-42eb-bd14-9d8153fa046f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221251097 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.3221251097
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.1478978017
Short name T1040
Test name
Test status
Simulation time 1181281359 ps
CPU time 2.01 seconds
Started Apr 30 03:11:03 PM PDT 24
Finished Apr 30 03:11:05 PM PDT 24
Peak memory 199092 kb
Host smart-bceec72f-7d67-4173-82cd-618f59466d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478978017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.1478978017
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.208938106
Short name T705
Test name
Test status
Simulation time 92070115401 ps
CPU time 57.62 seconds
Started Apr 30 03:11:02 PM PDT 24
Finished Apr 30 03:12:00 PM PDT 24
Peak memory 200296 kb
Host smart-ceb9740e-fcd2-41b4-a50f-2af198f184f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208938106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.208938106
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.1340563910
Short name T386
Test name
Test status
Simulation time 149080339 ps
CPU time 0.52 seconds
Started Apr 30 03:12:11 PM PDT 24
Finished Apr 30 03:12:12 PM PDT 24
Peak memory 195816 kb
Host smart-2182850d-2253-401c-9472-2fac086ba490
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340563910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.1340563910
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.2948300611
Short name T521
Test name
Test status
Simulation time 85534960893 ps
CPU time 49.68 seconds
Started Apr 30 03:12:03 PM PDT 24
Finished Apr 30 03:12:54 PM PDT 24
Peak memory 200428 kb
Host smart-83d29b0b-1e74-4db9-aa05-649be0117c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948300611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.2948300611
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.1061476041
Short name T919
Test name
Test status
Simulation time 18765479766 ps
CPU time 13.04 seconds
Started Apr 30 03:12:05 PM PDT 24
Finished Apr 30 03:12:18 PM PDT 24
Peak memory 200060 kb
Host smart-5d891d3f-c226-445f-ac5a-18d336c0a4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061476041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.1061476041
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_intr.476884970
Short name T524
Test name
Test status
Simulation time 22937387185 ps
CPU time 19.83 seconds
Started Apr 30 03:12:06 PM PDT 24
Finished Apr 30 03:12:26 PM PDT 24
Peak memory 198324 kb
Host smart-0531f43c-2efe-45c7-be4e-25ba0c2bdf1c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476884970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.476884970
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.3847267777
Short name T37
Test name
Test status
Simulation time 220135494689 ps
CPU time 589.08 seconds
Started Apr 30 03:12:04 PM PDT 24
Finished Apr 30 03:21:53 PM PDT 24
Peak memory 200408 kb
Host smart-8a80711c-6e24-4826-a774-cebd257d658a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3847267777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.3847267777
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.2859877580
Short name T402
Test name
Test status
Simulation time 7750881931 ps
CPU time 17.15 seconds
Started Apr 30 03:12:03 PM PDT 24
Finished Apr 30 03:12:21 PM PDT 24
Peak memory 200528 kb
Host smart-cec86236-97e2-4a26-9f95-cd35f26d329d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859877580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.2859877580
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.224410163
Short name T731
Test name
Test status
Simulation time 128042746253 ps
CPU time 13.29 seconds
Started Apr 30 03:12:04 PM PDT 24
Finished Apr 30 03:12:18 PM PDT 24
Peak memory 196840 kb
Host smart-887b1ff7-96fc-45ee-9494-09d9794ad1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224410163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.224410163
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.1777607657
Short name T379
Test name
Test status
Simulation time 26652163375 ps
CPU time 1530.82 seconds
Started Apr 30 03:12:08 PM PDT 24
Finished Apr 30 03:37:39 PM PDT 24
Peak memory 200424 kb
Host smart-f98c021d-eb8a-4ac2-ad1e-c3daa34013c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1777607657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.1777607657
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.4104200375
Short name T585
Test name
Test status
Simulation time 7160830098 ps
CPU time 17.54 seconds
Started Apr 30 03:12:06 PM PDT 24
Finished Apr 30 03:12:24 PM PDT 24
Peak memory 200348 kb
Host smart-cf1ce168-8d20-4159-a59a-7acd224db07c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4104200375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.4104200375
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.4205889803
Short name T718
Test name
Test status
Simulation time 21494480889 ps
CPU time 32.83 seconds
Started Apr 30 03:12:04 PM PDT 24
Finished Apr 30 03:12:37 PM PDT 24
Peak memory 200124 kb
Host smart-14605a1a-8507-47b0-9ed8-dde45ab5ff67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205889803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.4205889803
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.2769810582
Short name T611
Test name
Test status
Simulation time 85021125057 ps
CPU time 38.2 seconds
Started Apr 30 03:12:05 PM PDT 24
Finished Apr 30 03:12:43 PM PDT 24
Peak memory 196460 kb
Host smart-fc956457-8d81-45c9-a1af-78636c5f3ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769810582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.2769810582
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.113562893
Short name T309
Test name
Test status
Simulation time 5714873086 ps
CPU time 10.29 seconds
Started Apr 30 03:12:03 PM PDT 24
Finished Apr 30 03:12:14 PM PDT 24
Peak memory 200216 kb
Host smart-72ccc60c-c47d-40da-b154-c45019f62878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113562893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.113562893
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.1551497092
Short name T829
Test name
Test status
Simulation time 585556452314 ps
CPU time 98.89 seconds
Started Apr 30 03:12:09 PM PDT 24
Finished Apr 30 03:13:48 PM PDT 24
Peak memory 200416 kb
Host smart-df3be7a3-f133-41ee-85d9-58580f1f1ada
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551497092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.1551497092
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.3407441002
Short name T781
Test name
Test status
Simulation time 6272926778 ps
CPU time 17.28 seconds
Started Apr 30 03:12:03 PM PDT 24
Finished Apr 30 03:12:20 PM PDT 24
Peak memory 200388 kb
Host smart-ab1a5980-760c-4dbd-8c78-bcef2e0dc115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407441002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.3407441002
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.3655798364
Short name T322
Test name
Test status
Simulation time 117162642620 ps
CPU time 278.34 seconds
Started Apr 30 03:12:05 PM PDT 24
Finished Apr 30 03:16:44 PM PDT 24
Peak memory 200292 kb
Host smart-65641bfa-4bf0-4518-83a3-4b3f3f9cb386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655798364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.3655798364
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.3153227119
Short name T482
Test name
Test status
Simulation time 63120811895 ps
CPU time 129.08 seconds
Started Apr 30 03:16:24 PM PDT 24
Finished Apr 30 03:18:34 PM PDT 24
Peak memory 200372 kb
Host smart-8b06767f-5fa1-4954-b588-0129dcf82395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153227119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.3153227119
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3310417548
Short name T529
Test name
Test status
Simulation time 23871845813 ps
CPU time 22.73 seconds
Started Apr 30 03:16:24 PM PDT 24
Finished Apr 30 03:16:47 PM PDT 24
Peak memory 200408 kb
Host smart-3ca9328d-f11f-4f1a-90fd-5bb0da2641bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310417548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3310417548
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.399116097
Short name T577
Test name
Test status
Simulation time 20199812643 ps
CPU time 56.96 seconds
Started Apr 30 03:16:26 PM PDT 24
Finished Apr 30 03:17:23 PM PDT 24
Peak memory 200444 kb
Host smart-33bd4bc4-ab31-4e19-a05e-f2183ef73171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399116097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.399116097
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.3840706152
Short name T536
Test name
Test status
Simulation time 10983988819 ps
CPU time 31.37 seconds
Started Apr 30 03:16:26 PM PDT 24
Finished Apr 30 03:16:58 PM PDT 24
Peak memory 200364 kb
Host smart-51969f65-81ec-4d2c-8ddd-60ffc79acb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840706152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3840706152
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.1516057168
Short name T289
Test name
Test status
Simulation time 17027848871 ps
CPU time 7.88 seconds
Started Apr 30 03:16:26 PM PDT 24
Finished Apr 30 03:16:34 PM PDT 24
Peak memory 200392 kb
Host smart-6cfe5c9e-7ffe-4581-9a34-524377d3fc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516057168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.1516057168
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.1901628001
Short name T1151
Test name
Test status
Simulation time 38315569725 ps
CPU time 69.64 seconds
Started Apr 30 03:16:26 PM PDT 24
Finished Apr 30 03:17:36 PM PDT 24
Peak memory 200288 kb
Host smart-79e8a8b2-d27e-457d-926e-0578ffe4d2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901628001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1901628001
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.4151159848
Short name T856
Test name
Test status
Simulation time 63325395653 ps
CPU time 101.22 seconds
Started Apr 30 03:16:25 PM PDT 24
Finished Apr 30 03:18:07 PM PDT 24
Peak memory 200396 kb
Host smart-cc6d2c48-250f-4d90-b5b6-3d340b9214de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151159848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.4151159848
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.2512708430
Short name T1022
Test name
Test status
Simulation time 33405765 ps
CPU time 0.56 seconds
Started Apr 30 03:12:19 PM PDT 24
Finished Apr 30 03:12:20 PM PDT 24
Peak memory 195784 kb
Host smart-afb4cf2e-afdb-42b0-8013-f0135bb462c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512708430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.2512708430
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.83681697
Short name T1061
Test name
Test status
Simulation time 23107282121 ps
CPU time 19.74 seconds
Started Apr 30 03:12:11 PM PDT 24
Finished Apr 30 03:12:31 PM PDT 24
Peak memory 200372 kb
Host smart-f61d9db9-8bf2-4fa1-a6a9-90236145c40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83681697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.83681697
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.1430904254
Short name T826
Test name
Test status
Simulation time 121853065068 ps
CPU time 204.61 seconds
Started Apr 30 03:12:11 PM PDT 24
Finished Apr 30 03:15:36 PM PDT 24
Peak memory 200340 kb
Host smart-39d39bbb-7ef7-4259-8f72-1e99793d148f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430904254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.1430904254
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.2090665639
Short name T286
Test name
Test status
Simulation time 138434935422 ps
CPU time 17.73 seconds
Started Apr 30 03:12:11 PM PDT 24
Finished Apr 30 03:12:29 PM PDT 24
Peak memory 200360 kb
Host smart-7d075f05-6541-4f4f-910b-53705853ea06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090665639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2090665639
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.121757441
Short name T325
Test name
Test status
Simulation time 175248035592 ps
CPU time 61.56 seconds
Started Apr 30 03:12:11 PM PDT 24
Finished Apr 30 03:13:13 PM PDT 24
Peak memory 198652 kb
Host smart-f18231b6-164e-4c34-8ad3-5957a8503828
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121757441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.121757441
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.460420037
Short name T376
Test name
Test status
Simulation time 246012784942 ps
CPU time 766.1 seconds
Started Apr 30 03:12:27 PM PDT 24
Finished Apr 30 03:25:14 PM PDT 24
Peak memory 200348 kb
Host smart-8a4727f6-b17a-4049-ae7c-ea348789f096
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=460420037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.460420037
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.3605568817
Short name T509
Test name
Test status
Simulation time 2840537864 ps
CPU time 3.12 seconds
Started Apr 30 03:12:12 PM PDT 24
Finished Apr 30 03:12:16 PM PDT 24
Peak memory 199176 kb
Host smart-7e0c9e87-2cfb-44c3-8d9f-49a34022fb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605568817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.3605568817
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.1945494747
Short name T798
Test name
Test status
Simulation time 37951377205 ps
CPU time 30.24 seconds
Started Apr 30 03:12:10 PM PDT 24
Finished Apr 30 03:12:41 PM PDT 24
Peak memory 199888 kb
Host smart-438b59b4-c3a7-48b7-bc3a-240add06fcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945494747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.1945494747
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.216873552
Short name T833
Test name
Test status
Simulation time 9089722741 ps
CPU time 97.16 seconds
Started Apr 30 03:12:10 PM PDT 24
Finished Apr 30 03:13:48 PM PDT 24
Peak memory 200316 kb
Host smart-d9a1b7e8-e457-4d82-9e3d-67683b664ae0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=216873552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.216873552
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.1456933580
Short name T1125
Test name
Test status
Simulation time 3807746481 ps
CPU time 13.39 seconds
Started Apr 30 03:12:10 PM PDT 24
Finished Apr 30 03:12:24 PM PDT 24
Peak memory 198748 kb
Host smart-c7e5ea0e-cb1d-4b0b-9ef9-b61a9249d860
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1456933580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.1456933580
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.1913798470
Short name T642
Test name
Test status
Simulation time 20888444573 ps
CPU time 32.17 seconds
Started Apr 30 03:12:12 PM PDT 24
Finished Apr 30 03:12:44 PM PDT 24
Peak memory 200264 kb
Host smart-3b5eeec0-960a-470a-93ab-a0b3a1205ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913798470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.1913798470
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.28013450
Short name T296
Test name
Test status
Simulation time 3256300270 ps
CPU time 1.99 seconds
Started Apr 30 03:12:10 PM PDT 24
Finished Apr 30 03:12:13 PM PDT 24
Peak memory 196212 kb
Host smart-fdc29188-5a87-4588-942b-b96761cf7667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28013450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.28013450
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.3327206007
Short name T662
Test name
Test status
Simulation time 652220705 ps
CPU time 1.22 seconds
Started Apr 30 03:12:12 PM PDT 24
Finished Apr 30 03:12:13 PM PDT 24
Peak memory 198896 kb
Host smart-62a9fe99-0add-44a9-ac68-8716ba464f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327206007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.3327206007
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.1393284064
Short name T1033
Test name
Test status
Simulation time 97275002006 ps
CPU time 525.9 seconds
Started Apr 30 03:12:19 PM PDT 24
Finished Apr 30 03:21:05 PM PDT 24
Peak memory 200392 kb
Host smart-8a0375a1-3be4-4cb1-8897-7423a5ca74a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393284064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.1393284064
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.3735591821
Short name T832
Test name
Test status
Simulation time 13628326383 ps
CPU time 59.49 seconds
Started Apr 30 03:12:17 PM PDT 24
Finished Apr 30 03:13:17 PM PDT 24
Peak memory 216864 kb
Host smart-1d8bb036-141c-42c5-90fc-215085fa00d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735591821 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.3735591821
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.2080548439
Short name T578
Test name
Test status
Simulation time 7955669251 ps
CPU time 4.92 seconds
Started Apr 30 03:12:12 PM PDT 24
Finished Apr 30 03:12:17 PM PDT 24
Peak memory 200328 kb
Host smart-6e3b1a47-320a-4890-8216-28227e4fd07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080548439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.2080548439
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.1482514915
Short name T773
Test name
Test status
Simulation time 83334012375 ps
CPU time 159.64 seconds
Started Apr 30 03:12:12 PM PDT 24
Finished Apr 30 03:14:52 PM PDT 24
Peak memory 200420 kb
Host smart-f1bde625-cefb-478e-93cf-22d23ab01034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482514915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.1482514915
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.4167977455
Short name T823
Test name
Test status
Simulation time 121436746729 ps
CPU time 64.41 seconds
Started Apr 30 03:16:34 PM PDT 24
Finished Apr 30 03:17:39 PM PDT 24
Peak memory 200368 kb
Host smart-112237fa-4987-4644-8788-7cd098e53eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167977455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.4167977455
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.3341468951
Short name T924
Test name
Test status
Simulation time 80376057646 ps
CPU time 76.87 seconds
Started Apr 30 03:16:34 PM PDT 24
Finished Apr 30 03:17:51 PM PDT 24
Peak memory 200416 kb
Host smart-004af743-111a-49f3-8189-f33cc5bc5ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341468951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3341468951
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.2995582959
Short name T1168
Test name
Test status
Simulation time 7985525490 ps
CPU time 17.05 seconds
Started Apr 30 03:16:33 PM PDT 24
Finished Apr 30 03:16:51 PM PDT 24
Peak memory 200308 kb
Host smart-ec447a0a-4b72-442c-a460-9b3a430f2a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995582959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.2995582959
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.2302691604
Short name T998
Test name
Test status
Simulation time 64769976841 ps
CPU time 89.87 seconds
Started Apr 30 03:16:32 PM PDT 24
Finished Apr 30 03:18:02 PM PDT 24
Peak memory 200332 kb
Host smart-b888bd10-c6ea-46ad-bcc2-a7a0cb12c474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302691604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.2302691604
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.1586232812
Short name T872
Test name
Test status
Simulation time 15814908430 ps
CPU time 32.63 seconds
Started Apr 30 03:16:35 PM PDT 24
Finished Apr 30 03:17:08 PM PDT 24
Peak memory 200396 kb
Host smart-b4801838-c45d-435c-bbe2-3435a8e62dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586232812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.1586232812
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.3605938061
Short name T543
Test name
Test status
Simulation time 79818459068 ps
CPU time 124.63 seconds
Started Apr 30 03:16:33 PM PDT 24
Finished Apr 30 03:18:38 PM PDT 24
Peak memory 200400 kb
Host smart-95e970e2-08fd-4065-84e5-9412a4b5f65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605938061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.3605938061
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.2730178379
Short name T210
Test name
Test status
Simulation time 295691696956 ps
CPU time 40.84 seconds
Started Apr 30 03:16:40 PM PDT 24
Finished Apr 30 03:17:21 PM PDT 24
Peak memory 200376 kb
Host smart-cb387506-3602-41e1-b8b6-1b3c96d5a5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730178379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.2730178379
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.2530238765
Short name T1043
Test name
Test status
Simulation time 13273920 ps
CPU time 0.56 seconds
Started Apr 30 03:12:26 PM PDT 24
Finished Apr 30 03:12:27 PM PDT 24
Peak memory 195808 kb
Host smart-b1ca825b-c520-466b-90d9-065294505b58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530238765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.2530238765
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.2383633922
Short name T9
Test name
Test status
Simulation time 139883946465 ps
CPU time 190.09 seconds
Started Apr 30 03:12:20 PM PDT 24
Finished Apr 30 03:15:30 PM PDT 24
Peak memory 200456 kb
Host smart-11e6acbb-a9fc-4070-b85b-6ba8b757df05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383633922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2383633922
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.1947454120
Short name T777
Test name
Test status
Simulation time 83110040392 ps
CPU time 28.32 seconds
Started Apr 30 03:12:21 PM PDT 24
Finished Apr 30 03:12:50 PM PDT 24
Peak memory 200300 kb
Host smart-e7a66028-2013-4d5f-ba3f-b88822a527e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947454120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.1947454120
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.2594015167
Short name T807
Test name
Test status
Simulation time 6981963123 ps
CPU time 12.39 seconds
Started Apr 30 03:12:28 PM PDT 24
Finished Apr 30 03:12:41 PM PDT 24
Peak memory 200376 kb
Host smart-4ad85de0-7a6d-4909-8e11-a7686a260375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594015167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.2594015167
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.2370534857
Short name T337
Test name
Test status
Simulation time 25485733211 ps
CPU time 44.7 seconds
Started Apr 30 03:12:19 PM PDT 24
Finished Apr 30 03:13:04 PM PDT 24
Peak memory 198652 kb
Host smart-019b71d7-2c31-4626-bb5d-38a2eb4836c3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370534857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.2370534857
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.4094172460
Short name T767
Test name
Test status
Simulation time 69299442728 ps
CPU time 575.63 seconds
Started Apr 30 03:12:25 PM PDT 24
Finished Apr 30 03:22:02 PM PDT 24
Peak memory 200360 kb
Host smart-beba63cb-d142-402e-ba98-d35f9faf8906
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4094172460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.4094172460
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.1054291093
Short name T834
Test name
Test status
Simulation time 4345805589 ps
CPU time 7.5 seconds
Started Apr 30 03:12:20 PM PDT 24
Finished Apr 30 03:12:28 PM PDT 24
Peak memory 200368 kb
Host smart-8fdf39d9-f87c-47da-b24c-e6f7d529fd6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054291093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.1054291093
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.1004371501
Short name T452
Test name
Test status
Simulation time 178890784163 ps
CPU time 87.12 seconds
Started Apr 30 03:12:26 PM PDT 24
Finished Apr 30 03:13:54 PM PDT 24
Peak memory 208596 kb
Host smart-fcc8e0ac-e9ca-4fcb-b0c5-6be1efc68c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004371501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.1004371501
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.3630414088
Short name T369
Test name
Test status
Simulation time 12968688642 ps
CPU time 665.06 seconds
Started Apr 30 03:12:25 PM PDT 24
Finished Apr 30 03:23:31 PM PDT 24
Peak memory 200428 kb
Host smart-8ea0d0ba-be0c-46dd-93fe-fec311358890
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3630414088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.3630414088
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.2870381871
Short name T547
Test name
Test status
Simulation time 1481004614 ps
CPU time 5.62 seconds
Started Apr 30 03:12:27 PM PDT 24
Finished Apr 30 03:12:33 PM PDT 24
Peak memory 198296 kb
Host smart-98ffd9ea-8a64-4530-b252-6fa83bcc0f79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2870381871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.2870381871
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.2245220404
Short name T259
Test name
Test status
Simulation time 228500926912 ps
CPU time 349.98 seconds
Started Apr 30 03:12:27 PM PDT 24
Finished Apr 30 03:18:17 PM PDT 24
Peak memory 200408 kb
Host smart-672c06eb-9b30-4e69-a117-4c88b2f0e975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245220404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.2245220404
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.2969814414
Short name T298
Test name
Test status
Simulation time 66930293927 ps
CPU time 24.55 seconds
Started Apr 30 03:12:20 PM PDT 24
Finished Apr 30 03:12:45 PM PDT 24
Peak memory 196412 kb
Host smart-823b5db3-2dfe-4921-a8f8-e3b16306e18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969814414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.2969814414
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.3123290199
Short name T40
Test name
Test status
Simulation time 745483002 ps
CPU time 1.4 seconds
Started Apr 30 03:12:26 PM PDT 24
Finished Apr 30 03:12:28 PM PDT 24
Peak memory 198728 kb
Host smart-df42edf8-f9ec-4fc1-b725-736a601aa2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123290199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.3123290199
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.3658623390
Short name T522
Test name
Test status
Simulation time 111801051206 ps
CPU time 736.74 seconds
Started Apr 30 03:12:23 PM PDT 24
Finished Apr 30 03:24:40 PM PDT 24
Peak memory 200356 kb
Host smart-8b8d6b31-f3a0-453a-a492-ce913619e3eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658623390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.3658623390
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.1430328510
Short name T171
Test name
Test status
Simulation time 85179435610 ps
CPU time 640.88 seconds
Started Apr 30 03:12:27 PM PDT 24
Finished Apr 30 03:23:09 PM PDT 24
Peak memory 211912 kb
Host smart-bccc6a8a-20e8-4085-845b-dc6a30c9c474
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430328510 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.1430328510
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.1155137469
Short name T1068
Test name
Test status
Simulation time 3396475157 ps
CPU time 2.36 seconds
Started Apr 30 03:12:18 PM PDT 24
Finished Apr 30 03:12:21 PM PDT 24
Peak memory 199040 kb
Host smart-11553caa-f98f-474d-9495-eff5b9ec9c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155137469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.1155137469
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.2611184804
Short name T704
Test name
Test status
Simulation time 91565720116 ps
CPU time 30.59 seconds
Started Apr 30 03:12:18 PM PDT 24
Finished Apr 30 03:12:49 PM PDT 24
Peak memory 200320 kb
Host smart-f0cc0853-2b42-4ffa-8307-d4b8056e6518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611184804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.2611184804
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.537834121
Short name T1127
Test name
Test status
Simulation time 83806701571 ps
CPU time 47.32 seconds
Started Apr 30 03:16:32 PM PDT 24
Finished Apr 30 03:17:20 PM PDT 24
Peak memory 200364 kb
Host smart-3b3d84f1-3f86-45e9-9ec8-4a29cd6bedbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537834121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.537834121
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.572419300
Short name T756
Test name
Test status
Simulation time 35502602888 ps
CPU time 62.47 seconds
Started Apr 30 03:16:35 PM PDT 24
Finished Apr 30 03:17:38 PM PDT 24
Peak memory 200400 kb
Host smart-0f00d056-81ba-44b1-a1a6-534ec1964781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572419300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.572419300
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.2608324588
Short name T553
Test name
Test status
Simulation time 256121274655 ps
CPU time 34.89 seconds
Started Apr 30 03:16:34 PM PDT 24
Finished Apr 30 03:17:09 PM PDT 24
Peak memory 200440 kb
Host smart-a61e122d-3753-488c-8d2b-b74423f7bb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608324588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.2608324588
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.2397406059
Short name T881
Test name
Test status
Simulation time 50103988036 ps
CPU time 37.16 seconds
Started Apr 30 03:16:40 PM PDT 24
Finished Apr 30 03:17:18 PM PDT 24
Peak memory 200432 kb
Host smart-c4a3e370-00e1-436c-9186-7d679adbfa19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397406059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.2397406059
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.3746938104
Short name T1185
Test name
Test status
Simulation time 56681438170 ps
CPU time 143.28 seconds
Started Apr 30 03:16:39 PM PDT 24
Finished Apr 30 03:19:03 PM PDT 24
Peak memory 200300 kb
Host smart-a37b7e8f-5bb9-49d9-8d97-24c26b20a1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746938104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.3746938104
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.3403708051
Short name T686
Test name
Test status
Simulation time 99649271127 ps
CPU time 158.23 seconds
Started Apr 30 03:16:41 PM PDT 24
Finished Apr 30 03:19:20 PM PDT 24
Peak memory 200444 kb
Host smart-fac2d1cf-6564-42c1-ba00-8f63635aa25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403708051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.3403708051
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.1418117820
Short name T740
Test name
Test status
Simulation time 56449477449 ps
CPU time 100.4 seconds
Started Apr 30 03:16:45 PM PDT 24
Finished Apr 30 03:18:26 PM PDT 24
Peak memory 200452 kb
Host smart-c1a68f42-a54a-49ce-bf23-a36e3123ace0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418117820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.1418117820
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.4079316469
Short name T898
Test name
Test status
Simulation time 20138924056 ps
CPU time 33.51 seconds
Started Apr 30 03:16:43 PM PDT 24
Finished Apr 30 03:17:17 PM PDT 24
Peak memory 200388 kb
Host smart-6eaedcf3-9268-4376-a9b4-d8d3547cf673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079316469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.4079316469
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.580194494
Short name T703
Test name
Test status
Simulation time 17580829305 ps
CPU time 30.75 seconds
Started Apr 30 03:16:41 PM PDT 24
Finished Apr 30 03:17:12 PM PDT 24
Peak memory 200364 kb
Host smart-49289410-e0a5-4063-8564-f810b927b6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580194494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.580194494
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.2700974867
Short name T506
Test name
Test status
Simulation time 19338750448 ps
CPU time 41.64 seconds
Started Apr 30 03:16:42 PM PDT 24
Finished Apr 30 03:17:24 PM PDT 24
Peak memory 200380 kb
Host smart-49aa7bed-2914-4cd1-9fec-74f01e4729b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700974867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2700974867
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.1139012480
Short name T512
Test name
Test status
Simulation time 20285530 ps
CPU time 0.53 seconds
Started Apr 30 03:12:30 PM PDT 24
Finished Apr 30 03:12:31 PM PDT 24
Peak memory 195744 kb
Host smart-aa2fa4bb-69f6-4523-92a3-6cca22032719
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139012480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.1139012480
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.937463707
Short name T471
Test name
Test status
Simulation time 231592262043 ps
CPU time 523.72 seconds
Started Apr 30 03:12:25 PM PDT 24
Finished Apr 30 03:21:09 PM PDT 24
Peak memory 200404 kb
Host smart-f2bee72f-6b0f-4c47-9c66-ddad24f339b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937463707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.937463707
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.2173269228
Short name T571
Test name
Test status
Simulation time 38226503479 ps
CPU time 64.32 seconds
Started Apr 30 03:12:26 PM PDT 24
Finished Apr 30 03:13:31 PM PDT 24
Peak memory 200380 kb
Host smart-87f8d338-e0d5-4adf-b211-6f130f4ed87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173269228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2173269228
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.1835458787
Short name T722
Test name
Test status
Simulation time 42370592812 ps
CPU time 33.65 seconds
Started Apr 30 03:12:25 PM PDT 24
Finished Apr 30 03:13:00 PM PDT 24
Peak memory 200396 kb
Host smart-f8368157-b2b6-477f-8a76-6be83868bd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835458787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.1835458787
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.1659831159
Short name T1123
Test name
Test status
Simulation time 388155825502 ps
CPU time 585.22 seconds
Started Apr 30 03:12:25 PM PDT 24
Finished Apr 30 03:22:11 PM PDT 24
Peak memory 199848 kb
Host smart-0112f273-7112-472b-8345-b6363a97c529
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659831159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.1659831159
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.942679885
Short name T882
Test name
Test status
Simulation time 137772171133 ps
CPU time 426.07 seconds
Started Apr 30 03:12:32 PM PDT 24
Finished Apr 30 03:19:39 PM PDT 24
Peak memory 200372 kb
Host smart-0dde3a62-dce6-40dc-ab9a-e2d8d0a6308c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=942679885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.942679885
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.391769975
Short name T688
Test name
Test status
Simulation time 2279798332 ps
CPU time 4.77 seconds
Started Apr 30 03:12:34 PM PDT 24
Finished Apr 30 03:12:39 PM PDT 24
Peak memory 199004 kb
Host smart-c09cca75-298e-4f30-9ed7-e0d8d0b864e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391769975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.391769975
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.432342492
Short name T410
Test name
Test status
Simulation time 81144376421 ps
CPU time 284.82 seconds
Started Apr 30 03:12:26 PM PDT 24
Finished Apr 30 03:17:11 PM PDT 24
Peak memory 208760 kb
Host smart-b1445406-7e2e-4ba9-8874-085604db4f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432342492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.432342492
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.936893339
Short name T572
Test name
Test status
Simulation time 36404658847 ps
CPU time 2030.28 seconds
Started Apr 30 03:12:32 PM PDT 24
Finished Apr 30 03:46:24 PM PDT 24
Peak memory 200332 kb
Host smart-828edd1e-0cd6-419e-a064-262bf0eba3cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=936893339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.936893339
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.1129782180
Short name T489
Test name
Test status
Simulation time 2037634999 ps
CPU time 1.9 seconds
Started Apr 30 03:12:25 PM PDT 24
Finished Apr 30 03:12:28 PM PDT 24
Peak memory 198536 kb
Host smart-438563a6-7fab-460c-b17d-a965e8a446f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1129782180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.1129782180
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.4194812054
Short name T152
Test name
Test status
Simulation time 206061039217 ps
CPU time 318.53 seconds
Started Apr 30 03:12:34 PM PDT 24
Finished Apr 30 03:17:54 PM PDT 24
Peak memory 200328 kb
Host smart-ac1a8d22-b18f-4632-bf96-f11670f7e5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194812054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.4194812054
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.2085959849
Short name T22
Test name
Test status
Simulation time 3398040551 ps
CPU time 1.92 seconds
Started Apr 30 03:12:25 PM PDT 24
Finished Apr 30 03:12:28 PM PDT 24
Peak memory 196456 kb
Host smart-d97b6059-2dec-4d92-92b7-3a79a2b4cfb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085959849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.2085959849
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.1368828325
Short name T1118
Test name
Test status
Simulation time 646040063 ps
CPU time 2.05 seconds
Started Apr 30 03:12:27 PM PDT 24
Finished Apr 30 03:12:29 PM PDT 24
Peak memory 200288 kb
Host smart-8152390d-ce2a-4817-963e-55010c49410c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368828325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.1368828325
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.2867214690
Short name T921
Test name
Test status
Simulation time 326971239886 ps
CPU time 150.33 seconds
Started Apr 30 03:12:31 PM PDT 24
Finished Apr 30 03:15:02 PM PDT 24
Peak memory 200588 kb
Host smart-c8419e8d-aff0-4772-8560-f9082a6d822c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867214690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.2867214690
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.321594730
Short name T774
Test name
Test status
Simulation time 93363908847 ps
CPU time 557.47 seconds
Started Apr 30 03:12:31 PM PDT 24
Finished Apr 30 03:21:49 PM PDT 24
Peak memory 216180 kb
Host smart-e6a9a08b-3d52-4a27-bb00-ae04a40f5cb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321594730 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.321594730
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.1371609546
Short name T1150
Test name
Test status
Simulation time 452497550 ps
CPU time 2.94 seconds
Started Apr 30 03:12:33 PM PDT 24
Finished Apr 30 03:12:37 PM PDT 24
Peak memory 199276 kb
Host smart-d3b289b7-3a8d-4fff-b5c7-67d8f05bdaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371609546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.1371609546
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.931774902
Short name T1121
Test name
Test status
Simulation time 205971504033 ps
CPU time 83.95 seconds
Started Apr 30 03:12:31 PM PDT 24
Finished Apr 30 03:13:56 PM PDT 24
Peak memory 200404 kb
Host smart-e670a840-724a-4322-aa3d-6a76e4b02db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931774902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.931774902
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.3922581666
Short name T628
Test name
Test status
Simulation time 262259368439 ps
CPU time 484.84 seconds
Started Apr 30 03:16:45 PM PDT 24
Finished Apr 30 03:24:50 PM PDT 24
Peak memory 200332 kb
Host smart-e77a44b7-5982-43d9-a012-68efd259e258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922581666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.3922581666
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.2072623030
Short name T1099
Test name
Test status
Simulation time 159563030158 ps
CPU time 61.99 seconds
Started Apr 30 03:16:39 PM PDT 24
Finished Apr 30 03:17:42 PM PDT 24
Peak memory 200312 kb
Host smart-902a2379-edaf-4fb1-8147-8ec8ec73db55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072623030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.2072623030
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.746437205
Short name T631
Test name
Test status
Simulation time 196732076811 ps
CPU time 84.67 seconds
Started Apr 30 03:16:40 PM PDT 24
Finished Apr 30 03:18:05 PM PDT 24
Peak memory 200468 kb
Host smart-9ef3900a-b51b-4c1e-a1a3-933531b18be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746437205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.746437205
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.1617752152
Short name T476
Test name
Test status
Simulation time 23868386476 ps
CPU time 37.66 seconds
Started Apr 30 03:16:41 PM PDT 24
Finished Apr 30 03:17:19 PM PDT 24
Peak memory 200372 kb
Host smart-8069e129-9908-4018-97ab-ffdb344f766d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617752152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.1617752152
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.1672502986
Short name T236
Test name
Test status
Simulation time 46749214949 ps
CPU time 77.33 seconds
Started Apr 30 03:16:41 PM PDT 24
Finished Apr 30 03:18:00 PM PDT 24
Peak memory 200344 kb
Host smart-6700b9db-cd1e-4570-bc09-18c442fc6640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672502986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1672502986
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.619441111
Short name T1106
Test name
Test status
Simulation time 49702628027 ps
CPU time 90.32 seconds
Started Apr 30 03:16:41 PM PDT 24
Finished Apr 30 03:18:12 PM PDT 24
Peak memory 200372 kb
Host smart-da99b87a-281d-4a41-bdeb-00cea02d6e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619441111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.619441111
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.2036126715
Short name T893
Test name
Test status
Simulation time 29973141959 ps
CPU time 10.53 seconds
Started Apr 30 03:16:42 PM PDT 24
Finished Apr 30 03:16:53 PM PDT 24
Peak memory 200440 kb
Host smart-8583cac8-f932-48a1-8778-2055a16976f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036126715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.2036126715
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.2787784960
Short name T1124
Test name
Test status
Simulation time 63477694033 ps
CPU time 105.9 seconds
Started Apr 30 03:16:42 PM PDT 24
Finished Apr 30 03:18:29 PM PDT 24
Peak memory 200352 kb
Host smart-2215144f-37b7-4583-9ef4-f6eeb4d2c5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787784960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.2787784960
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.940116500
Short name T793
Test name
Test status
Simulation time 115339319493 ps
CPU time 93.57 seconds
Started Apr 30 03:16:43 PM PDT 24
Finished Apr 30 03:18:17 PM PDT 24
Peak memory 200328 kb
Host smart-49641dbe-3726-473e-add0-ef69ea13ac07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940116500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.940116500
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_fifo_full.738288507
Short name T1187
Test name
Test status
Simulation time 71994105531 ps
CPU time 20.89 seconds
Started Apr 30 03:12:32 PM PDT 24
Finished Apr 30 03:12:54 PM PDT 24
Peak memory 200304 kb
Host smart-27b85a20-92f1-4a0d-af82-ee81eae1f51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738288507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.738288507
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.3236203574
Short name T266
Test name
Test status
Simulation time 36152038651 ps
CPU time 30.34 seconds
Started Apr 30 03:12:33 PM PDT 24
Finished Apr 30 03:13:04 PM PDT 24
Peak memory 200404 kb
Host smart-97013c7c-1f89-4eb5-a8c6-13b73f5dca9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236203574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.3236203574
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.1760694456
Short name T202
Test name
Test status
Simulation time 68654022362 ps
CPU time 108.1 seconds
Started Apr 30 03:12:33 PM PDT 24
Finished Apr 30 03:14:22 PM PDT 24
Peak memory 200416 kb
Host smart-57c159ea-fb38-4b18-b028-74b570560abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760694456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.1760694456
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.983821542
Short name T465
Test name
Test status
Simulation time 18107324376 ps
CPU time 26.12 seconds
Started Apr 30 03:12:33 PM PDT 24
Finished Apr 30 03:13:00 PM PDT 24
Peak memory 198768 kb
Host smart-b34fa977-6c4b-430f-b615-7b163bca81d5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983821542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.983821542
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.488291770
Short name T971
Test name
Test status
Simulation time 95011335024 ps
CPU time 600.27 seconds
Started Apr 30 03:12:38 PM PDT 24
Finished Apr 30 03:22:40 PM PDT 24
Peak memory 200396 kb
Host smart-63c7dc73-4582-42de-bf7c-ad212809284e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=488291770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.488291770
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.2267871934
Short name T401
Test name
Test status
Simulation time 6614430571 ps
CPU time 4.71 seconds
Started Apr 30 03:12:37 PM PDT 24
Finished Apr 30 03:12:42 PM PDT 24
Peak memory 199492 kb
Host smart-0ebe4032-d30d-4b1e-8ff5-e54d7e50dc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267871934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.2267871934
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.1028858387
Short name T712
Test name
Test status
Simulation time 56212865622 ps
CPU time 98.97 seconds
Started Apr 30 03:12:33 PM PDT 24
Finished Apr 30 03:14:13 PM PDT 24
Peak memory 200748 kb
Host smart-b37ab32b-123d-46f8-ac7f-6dbb7c22c572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028858387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.1028858387
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.4029915077
Short name T763
Test name
Test status
Simulation time 13277572238 ps
CPU time 144.83 seconds
Started Apr 30 03:12:38 PM PDT 24
Finished Apr 30 03:15:04 PM PDT 24
Peak memory 200356 kb
Host smart-d00f9811-7777-47a6-b31f-a819785c422b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4029915077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.4029915077
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.2979672469
Short name T850
Test name
Test status
Simulation time 3593210296 ps
CPU time 26.28 seconds
Started Apr 30 03:12:35 PM PDT 24
Finished Apr 30 03:13:02 PM PDT 24
Peak memory 198880 kb
Host smart-b5ecd0d2-b81b-4a6f-9c8f-89354f4febbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2979672469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.2979672469
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.3330947800
Short name T1079
Test name
Test status
Simulation time 60077429064 ps
CPU time 47.81 seconds
Started Apr 30 03:12:32 PM PDT 24
Finished Apr 30 03:13:21 PM PDT 24
Peak memory 200388 kb
Host smart-4c25dc82-b52c-4833-9448-78076e0cd456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330947800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.3330947800
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.1401156901
Short name T748
Test name
Test status
Simulation time 1361212976 ps
CPU time 2.77 seconds
Started Apr 30 03:12:32 PM PDT 24
Finished Apr 30 03:12:36 PM PDT 24
Peak memory 195816 kb
Host smart-a7870508-79bf-41d4-bb1f-0b2b73f15c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401156901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.1401156901
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.1374174577
Short name T274
Test name
Test status
Simulation time 607339242 ps
CPU time 2.22 seconds
Started Apr 30 03:12:31 PM PDT 24
Finished Apr 30 03:12:34 PM PDT 24
Peak memory 200180 kb
Host smart-ce35c50c-89c9-4cde-be46-6d85401eef2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374174577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.1374174577
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.1252496136
Short name T726
Test name
Test status
Simulation time 343940131914 ps
CPU time 456.55 seconds
Started Apr 30 03:12:38 PM PDT 24
Finished Apr 30 03:20:16 PM PDT 24
Peak memory 200400 kb
Host smart-63e7e576-f8f5-442f-a0f4-9931fc378a58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252496136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.1252496136
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.3187848190
Short name T808
Test name
Test status
Simulation time 51399353946 ps
CPU time 542.87 seconds
Started Apr 30 03:12:39 PM PDT 24
Finished Apr 30 03:21:43 PM PDT 24
Peak memory 217076 kb
Host smart-6f5bea2c-570b-4f10-8cf6-3535d23d2f2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187848190 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.3187848190
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.2492142403
Short name T940
Test name
Test status
Simulation time 2475880545 ps
CPU time 1.76 seconds
Started Apr 30 03:12:44 PM PDT 24
Finished Apr 30 03:12:47 PM PDT 24
Peak memory 199068 kb
Host smart-4aac8278-4001-4796-9b8a-13bf89e4bcc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492142403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.2492142403
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.2356746599
Short name T1089
Test name
Test status
Simulation time 27882244049 ps
CPU time 45.09 seconds
Started Apr 30 03:12:32 PM PDT 24
Finished Apr 30 03:13:18 PM PDT 24
Peak memory 200440 kb
Host smart-b9a441c7-810a-4f21-bb37-fc3f30763729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356746599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.2356746599
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.1752973788
Short name T746
Test name
Test status
Simulation time 128847425620 ps
CPU time 93.5 seconds
Started Apr 30 03:16:42 PM PDT 24
Finished Apr 30 03:18:16 PM PDT 24
Peak memory 200388 kb
Host smart-b451692c-1b5e-4334-bdbd-9c3192beb8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752973788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.1752973788
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.2743088766
Short name T468
Test name
Test status
Simulation time 207971101997 ps
CPU time 369.57 seconds
Started Apr 30 03:16:42 PM PDT 24
Finished Apr 30 03:22:53 PM PDT 24
Peak memory 200272 kb
Host smart-62f23bc7-fb97-4faf-851d-cf9f27db2fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743088766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.2743088766
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.2114803251
Short name T197
Test name
Test status
Simulation time 24923915181 ps
CPU time 19.66 seconds
Started Apr 30 03:16:41 PM PDT 24
Finished Apr 30 03:17:01 PM PDT 24
Peak memory 200380 kb
Host smart-0e5f1008-b59d-4290-91bf-2ccb91ea054d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114803251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.2114803251
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.2683535009
Short name T654
Test name
Test status
Simulation time 28510833656 ps
CPU time 52.39 seconds
Started Apr 30 03:16:44 PM PDT 24
Finished Apr 30 03:17:37 PM PDT 24
Peak memory 200400 kb
Host smart-386f6d0f-e58e-4361-b04d-579f7bf8fde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683535009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2683535009
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.235842297
Short name T393
Test name
Test status
Simulation time 17386853810 ps
CPU time 26.97 seconds
Started Apr 30 03:16:43 PM PDT 24
Finished Apr 30 03:17:11 PM PDT 24
Peak memory 200200 kb
Host smart-fc5660b6-c05c-4ad0-8213-d8208daa94d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235842297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.235842297
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.93589553
Short name T592
Test name
Test status
Simulation time 69686227359 ps
CPU time 35.03 seconds
Started Apr 30 03:16:43 PM PDT 24
Finished Apr 30 03:17:18 PM PDT 24
Peak memory 200364 kb
Host smart-4cf9c40b-5434-4b34-acd0-256926312d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93589553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.93589553
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.392317644
Short name T338
Test name
Test status
Simulation time 14981915596 ps
CPU time 23.11 seconds
Started Apr 30 03:16:40 PM PDT 24
Finished Apr 30 03:17:04 PM PDT 24
Peak memory 199824 kb
Host smart-038d807c-1aeb-46a8-ba0c-44e12bb109c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392317644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.392317644
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.3514581762
Short name T352
Test name
Test status
Simulation time 30545404 ps
CPU time 0.6 seconds
Started Apr 30 03:12:47 PM PDT 24
Finished Apr 30 03:12:48 PM PDT 24
Peak memory 195780 kb
Host smart-b1cce2da-836b-4d15-8721-ead9d4a99054
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514581762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.3514581762
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.4117477163
Short name T1045
Test name
Test status
Simulation time 125219627786 ps
CPU time 161.27 seconds
Started Apr 30 03:12:46 PM PDT 24
Finished Apr 30 03:15:28 PM PDT 24
Peak memory 200356 kb
Host smart-cab8303d-b114-43d7-9d04-772757df517a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117477163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.4117477163
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.2450598245
Short name T138
Test name
Test status
Simulation time 182685272464 ps
CPU time 25.52 seconds
Started Apr 30 03:12:46 PM PDT 24
Finished Apr 30 03:13:12 PM PDT 24
Peak memory 199700 kb
Host smart-68480891-2f69-430d-8270-dd05510c3615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450598245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.2450598245
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.1075166236
Short name T933
Test name
Test status
Simulation time 197162128173 ps
CPU time 358 seconds
Started Apr 30 03:12:38 PM PDT 24
Finished Apr 30 03:18:37 PM PDT 24
Peak memory 200388 kb
Host smart-05c7eba3-bc9c-4e66-9a04-5930e5558d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075166236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.1075166236
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.1178464285
Short name T865
Test name
Test status
Simulation time 51755857477 ps
CPU time 23.59 seconds
Started Apr 30 03:12:38 PM PDT 24
Finished Apr 30 03:13:03 PM PDT 24
Peak memory 199948 kb
Host smart-76049974-1df7-4e29-b959-60ef7a087a6b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178464285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.1178464285
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.2644294646
Short name T502
Test name
Test status
Simulation time 133538789884 ps
CPU time 327.42 seconds
Started Apr 30 03:12:38 PM PDT 24
Finished Apr 30 03:18:07 PM PDT 24
Peak memory 200396 kb
Host smart-b6059065-613f-4cfa-a3f1-d94a3ddbbcbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2644294646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.2644294646
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.2259937189
Short name T841
Test name
Test status
Simulation time 4529130449 ps
CPU time 9.64 seconds
Started Apr 30 03:12:46 PM PDT 24
Finished Apr 30 03:12:56 PM PDT 24
Peak memory 200332 kb
Host smart-09a61e14-5205-405a-a12d-3678fde02392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259937189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.2259937189
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.3618142379
Short name T423
Test name
Test status
Simulation time 19958502503 ps
CPU time 29.98 seconds
Started Apr 30 03:12:39 PM PDT 24
Finished Apr 30 03:13:10 PM PDT 24
Peak memory 200380 kb
Host smart-7f791212-814c-4a89-8296-dd330c267578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618142379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.3618142379
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.3342229997
Short name T1094
Test name
Test status
Simulation time 10580218547 ps
CPU time 347.38 seconds
Started Apr 30 03:12:37 PM PDT 24
Finished Apr 30 03:18:25 PM PDT 24
Peak memory 200392 kb
Host smart-54eba074-08a8-4ded-a175-9bb2c5cafbd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3342229997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.3342229997
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.1679969076
Short name T930
Test name
Test status
Simulation time 1824768855 ps
CPU time 3.52 seconds
Started Apr 30 03:12:46 PM PDT 24
Finished Apr 30 03:12:50 PM PDT 24
Peak memory 198384 kb
Host smart-5a57aef6-c07e-47a9-b3ef-7fd16adedbd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1679969076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.1679969076
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.1049838005
Short name T928
Test name
Test status
Simulation time 89106063650 ps
CPU time 36.16 seconds
Started Apr 30 03:12:38 PM PDT 24
Finished Apr 30 03:13:16 PM PDT 24
Peak memory 200364 kb
Host smart-0df4c05c-a355-40b0-ad81-d323f9acf4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049838005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.1049838005
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.384589281
Short name T381
Test name
Test status
Simulation time 48005908892 ps
CPU time 9.5 seconds
Started Apr 30 03:12:38 PM PDT 24
Finished Apr 30 03:12:49 PM PDT 24
Peak memory 196164 kb
Host smart-d6484fba-174a-4e2d-9d58-34001f5abc3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384589281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.384589281
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.217101957
Short name T550
Test name
Test status
Simulation time 6086638160 ps
CPU time 11.85 seconds
Started Apr 30 03:12:38 PM PDT 24
Finished Apr 30 03:12:51 PM PDT 24
Peak memory 200140 kb
Host smart-5d0caf8e-bf11-407a-8994-681da93c3dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217101957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.217101957
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.1769928639
Short name T220
Test name
Test status
Simulation time 72806037669 ps
CPU time 118.81 seconds
Started Apr 30 03:12:39 PM PDT 24
Finished Apr 30 03:14:39 PM PDT 24
Peak memory 200404 kb
Host smart-31eeabed-12bb-4f04-a475-ec1587e497cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769928639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1769928639
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.2628216773
Short name T775
Test name
Test status
Simulation time 62287193113 ps
CPU time 795.4 seconds
Started Apr 30 03:12:38 PM PDT 24
Finished Apr 30 03:25:55 PM PDT 24
Peak memory 216828 kb
Host smart-7c1b2648-24c5-43b1-a446-826a5974a577
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628216773 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.2628216773
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.2661568614
Short name T38
Test name
Test status
Simulation time 6361497692 ps
CPU time 29.52 seconds
Started Apr 30 03:12:40 PM PDT 24
Finished Apr 30 03:13:10 PM PDT 24
Peak memory 200352 kb
Host smart-af9809a1-8501-4555-8b8b-9d1148c996e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661568614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.2661568614
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.3848471299
Short name T616
Test name
Test status
Simulation time 36456539488 ps
CPU time 18.72 seconds
Started Apr 30 03:12:38 PM PDT 24
Finished Apr 30 03:12:58 PM PDT 24
Peak memory 200376 kb
Host smart-b59e95c6-e8b5-4ede-97c8-2895bfa30c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848471299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.3848471299
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.23299035
Short name T487
Test name
Test status
Simulation time 62758866837 ps
CPU time 36.83 seconds
Started Apr 30 03:16:41 PM PDT 24
Finished Apr 30 03:17:18 PM PDT 24
Peak memory 200428 kb
Host smart-16600bb5-0a91-4dfe-9baa-fecc25a4a2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23299035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.23299035
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.2607649246
Short name T948
Test name
Test status
Simulation time 30912370576 ps
CPU time 55.61 seconds
Started Apr 30 03:16:48 PM PDT 24
Finished Apr 30 03:17:45 PM PDT 24
Peak memory 200436 kb
Host smart-f8ab04d6-9002-41cb-81cb-220a6994c190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607649246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.2607649246
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.1267494442
Short name T400
Test name
Test status
Simulation time 39642294883 ps
CPU time 67.46 seconds
Started Apr 30 03:16:48 PM PDT 24
Finished Apr 30 03:17:56 PM PDT 24
Peak memory 200204 kb
Host smart-13078b8b-a100-447f-a91b-0c53e57e20ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267494442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.1267494442
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.3531898816
Short name T191
Test name
Test status
Simulation time 175354361485 ps
CPU time 157.65 seconds
Started Apr 30 03:16:52 PM PDT 24
Finished Apr 30 03:19:30 PM PDT 24
Peak memory 200468 kb
Host smart-28e31cae-c8f2-4a7b-a49c-6bd5ddb2e2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531898816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.3531898816
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.2253184320
Short name T863
Test name
Test status
Simulation time 92001795734 ps
CPU time 125.71 seconds
Started Apr 30 03:16:50 PM PDT 24
Finished Apr 30 03:18:57 PM PDT 24
Peak memory 200180 kb
Host smart-a86de5b3-0c2b-458e-8cd6-32d88404730a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253184320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.2253184320
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.3612897038
Short name T966
Test name
Test status
Simulation time 23678936341 ps
CPU time 9.6 seconds
Started Apr 30 03:16:49 PM PDT 24
Finished Apr 30 03:16:59 PM PDT 24
Peak memory 200452 kb
Host smart-efb37e5c-3b6a-4444-8669-54d6385e19d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612897038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.3612897038
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.1643449919
Short name T1012
Test name
Test status
Simulation time 73191750764 ps
CPU time 130.91 seconds
Started Apr 30 03:16:48 PM PDT 24
Finished Apr 30 03:19:00 PM PDT 24
Peak memory 200356 kb
Host smart-c464400b-0f3f-40d2-9341-31b7951fedf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643449919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.1643449919
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.1129284306
Short name T693
Test name
Test status
Simulation time 115726926103 ps
CPU time 208.77 seconds
Started Apr 30 03:16:48 PM PDT 24
Finished Apr 30 03:20:18 PM PDT 24
Peak memory 200456 kb
Host smart-0f9ff217-d436-4615-80ed-9f769a431f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129284306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.1129284306
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.3743009325
Short name T1016
Test name
Test status
Simulation time 116998257637 ps
CPU time 181.62 seconds
Started Apr 30 03:16:51 PM PDT 24
Finished Apr 30 03:19:53 PM PDT 24
Peak memory 200380 kb
Host smart-20cf4646-3e4f-4e5c-aaa4-222c7c7c1bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743009325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.3743009325
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.3698001633
Short name T1139
Test name
Test status
Simulation time 61001618787 ps
CPU time 30.49 seconds
Started Apr 30 03:16:49 PM PDT 24
Finished Apr 30 03:17:20 PM PDT 24
Peak memory 200416 kb
Host smart-1ce931e7-d1f0-462c-9a9c-881844846427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698001633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.3698001633
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.1094920719
Short name T485
Test name
Test status
Simulation time 35540332 ps
CPU time 0.57 seconds
Started Apr 30 03:12:54 PM PDT 24
Finished Apr 30 03:12:55 PM PDT 24
Peak memory 195808 kb
Host smart-d0011ccf-f9d5-4859-8f12-4a1e8ee2d7c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094920719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.1094920719
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.1549453488
Short name T1158
Test name
Test status
Simulation time 35643209867 ps
CPU time 15.3 seconds
Started Apr 30 03:12:46 PM PDT 24
Finished Apr 30 03:13:02 PM PDT 24
Peak memory 200376 kb
Host smart-ffe3781f-90dd-43d4-87e3-966f768c98b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549453488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.1549453488
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.3620624344
Short name T467
Test name
Test status
Simulation time 13132468421 ps
CPU time 20.72 seconds
Started Apr 30 03:12:51 PM PDT 24
Finished Apr 30 03:13:12 PM PDT 24
Peak memory 200176 kb
Host smart-53237b90-b4cd-46ce-b01f-0af1aaf4675d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620624344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.3620624344
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.4063718105
Short name T239
Test name
Test status
Simulation time 24556613222 ps
CPU time 41.57 seconds
Started Apr 30 03:12:48 PM PDT 24
Finished Apr 30 03:13:30 PM PDT 24
Peak memory 200368 kb
Host smart-fa8f4b6f-d6af-4184-9588-d18b4e25f4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063718105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.4063718105
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.4072677255
Short name T1160
Test name
Test status
Simulation time 171884593126 ps
CPU time 52.51 seconds
Started Apr 30 03:12:44 PM PDT 24
Finished Apr 30 03:13:37 PM PDT 24
Peak memory 199600 kb
Host smart-af7ef13a-366b-4f4d-81c5-615dc4725f0c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072677255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.4072677255
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.332196446
Short name T1021
Test name
Test status
Simulation time 134834478990 ps
CPU time 297.99 seconds
Started Apr 30 03:12:45 PM PDT 24
Finished Apr 30 03:17:44 PM PDT 24
Peak memory 200428 kb
Host smart-8c97fb3c-7cc1-4a11-828f-fbc4ea776577
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=332196446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.332196446
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.2352657313
Short name T334
Test name
Test status
Simulation time 2381715043 ps
CPU time 2.97 seconds
Started Apr 30 03:12:46 PM PDT 24
Finished Apr 30 03:12:49 PM PDT 24
Peak memory 197812 kb
Host smart-65566b0a-3a8d-45b4-9263-f97f4ca7edcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352657313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.2352657313
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.455927932
Short name T779
Test name
Test status
Simulation time 58489117301 ps
CPU time 91.68 seconds
Started Apr 30 03:12:45 PM PDT 24
Finished Apr 30 03:14:17 PM PDT 24
Peak memory 199776 kb
Host smart-b9b99103-67b5-4f2c-9298-f2250e67d739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455927932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.455927932
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.4205426901
Short name T896
Test name
Test status
Simulation time 14812487222 ps
CPU time 296.19 seconds
Started Apr 30 03:12:45 PM PDT 24
Finished Apr 30 03:17:41 PM PDT 24
Peak memory 200376 kb
Host smart-db1c6837-4829-4394-9e44-96cd852132f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4205426901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.4205426901
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.2627665644
Short name T377
Test name
Test status
Simulation time 3547582400 ps
CPU time 25.94 seconds
Started Apr 30 03:12:46 PM PDT 24
Finished Apr 30 03:13:13 PM PDT 24
Peak memory 199572 kb
Host smart-f0e14bbf-a16b-4eb4-8b9d-ff197abe768f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2627665644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.2627665644
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.4261607713
Short name T15
Test name
Test status
Simulation time 158620651183 ps
CPU time 76.61 seconds
Started Apr 30 03:12:47 PM PDT 24
Finished Apr 30 03:14:04 PM PDT 24
Peak memory 200352 kb
Host smart-3489d674-b47e-4edd-b918-0a4cc2d4ea62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261607713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.4261607713
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.773297438
Short name T809
Test name
Test status
Simulation time 3380429266 ps
CPU time 3.5 seconds
Started Apr 30 03:12:45 PM PDT 24
Finished Apr 30 03:12:49 PM PDT 24
Peak memory 196416 kb
Host smart-e6b6bb91-3445-4d97-8ccb-aaab34725d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773297438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.773297438
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.2520776742
Short name T735
Test name
Test status
Simulation time 496413252 ps
CPU time 1.16 seconds
Started Apr 30 03:12:48 PM PDT 24
Finished Apr 30 03:12:49 PM PDT 24
Peak memory 199764 kb
Host smart-15dab467-50e3-4c82-a911-ab57307c915e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520776742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.2520776742
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.3980468155
Short name T343
Test name
Test status
Simulation time 132078368073 ps
CPU time 440.19 seconds
Started Apr 30 03:12:53 PM PDT 24
Finished Apr 30 03:20:14 PM PDT 24
Peak memory 200452 kb
Host smart-0b259650-c81d-4f9b-85d8-ae4fc0dfb87d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980468155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.3980468155
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.3675248864
Short name T958
Test name
Test status
Simulation time 178259089679 ps
CPU time 373.04 seconds
Started Apr 30 03:12:45 PM PDT 24
Finished Apr 30 03:18:59 PM PDT 24
Peak memory 216992 kb
Host smart-4dcdd93a-757f-45cd-b12a-d705fc58413a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675248864 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.3675248864
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.3429171261
Short name T391
Test name
Test status
Simulation time 459631313 ps
CPU time 2.03 seconds
Started Apr 30 03:12:45 PM PDT 24
Finished Apr 30 03:12:48 PM PDT 24
Peak memory 200096 kb
Host smart-2d9d3b77-ced1-4185-b6f0-6ad466a71b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429171261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.3429171261
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.2570396900
Short name T390
Test name
Test status
Simulation time 214992993626 ps
CPU time 39.87 seconds
Started Apr 30 03:12:45 PM PDT 24
Finished Apr 30 03:13:26 PM PDT 24
Peak memory 200428 kb
Host smart-ee952b87-7e82-4dcc-8da2-1a106ac5b4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570396900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.2570396900
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.2773212808
Short name T164
Test name
Test status
Simulation time 46669865189 ps
CPU time 38.57 seconds
Started Apr 30 03:16:48 PM PDT 24
Finished Apr 30 03:17:28 PM PDT 24
Peak memory 200256 kb
Host smart-4365f3a0-6087-4ec9-a121-09aeb90a8144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773212808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.2773212808
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.3253760355
Short name T997
Test name
Test status
Simulation time 32161303982 ps
CPU time 26.56 seconds
Started Apr 30 03:16:48 PM PDT 24
Finished Apr 30 03:17:15 PM PDT 24
Peak memory 200428 kb
Host smart-6461a53e-acea-4f63-9b76-f33ab9cb8f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253760355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.3253760355
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.481665997
Short name T597
Test name
Test status
Simulation time 110044611605 ps
CPU time 49.05 seconds
Started Apr 30 03:16:49 PM PDT 24
Finished Apr 30 03:17:38 PM PDT 24
Peak memory 200436 kb
Host smart-be2d74e2-8030-4b2b-8895-e349c7f32fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481665997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.481665997
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.3730328661
Short name T691
Test name
Test status
Simulation time 98185995121 ps
CPU time 23.67 seconds
Started Apr 30 03:16:50 PM PDT 24
Finished Apr 30 03:17:14 PM PDT 24
Peak memory 200068 kb
Host smart-9e1d6aa7-9b83-4e55-a979-f194673c73f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730328661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.3730328661
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.3720422675
Short name T1064
Test name
Test status
Simulation time 95877494986 ps
CPU time 175.02 seconds
Started Apr 30 03:16:48 PM PDT 24
Finished Apr 30 03:19:44 PM PDT 24
Peak memory 200380 kb
Host smart-335c209e-f0fd-43d0-af38-299fabbe179a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720422675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.3720422675
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.608880407
Short name T1186
Test name
Test status
Simulation time 47468794770 ps
CPU time 22.98 seconds
Started Apr 30 03:16:47 PM PDT 24
Finished Apr 30 03:17:11 PM PDT 24
Peak memory 200420 kb
Host smart-e6e502c7-be5b-44a0-850b-f6ed6050b080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608880407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.608880407
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.1379975412
Short name T149
Test name
Test status
Simulation time 104557929229 ps
CPU time 112.14 seconds
Started Apr 30 03:16:48 PM PDT 24
Finished Apr 30 03:18:41 PM PDT 24
Peak memory 200360 kb
Host smart-8ff39bc3-8994-41d9-8764-f750592d0aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379975412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1379975412
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.1035908174
Short name T454
Test name
Test status
Simulation time 90476995000 ps
CPU time 159.16 seconds
Started Apr 30 03:16:56 PM PDT 24
Finished Apr 30 03:19:36 PM PDT 24
Peak memory 200384 kb
Host smart-7810b7cf-dd6e-4634-96c8-229202b3f1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035908174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.1035908174
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.4246546123
Short name T753
Test name
Test status
Simulation time 179541213 ps
CPU time 0.55 seconds
Started Apr 30 03:12:55 PM PDT 24
Finished Apr 30 03:12:56 PM PDT 24
Peak memory 195788 kb
Host smart-0c4f4579-0870-44b3-9299-e97cff74aea9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246546123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.4246546123
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.1197485044
Short name T392
Test name
Test status
Simulation time 31557268615 ps
CPU time 14.62 seconds
Started Apr 30 03:12:55 PM PDT 24
Finished Apr 30 03:13:10 PM PDT 24
Peak memory 200404 kb
Host smart-82dbf46d-e92a-436f-86f7-837476099e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197485044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1197485044
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.2677304595
Short name T1019
Test name
Test status
Simulation time 15168300254 ps
CPU time 23.41 seconds
Started Apr 30 03:12:55 PM PDT 24
Finished Apr 30 03:13:19 PM PDT 24
Peak memory 200384 kb
Host smart-0825ca22-955d-4c52-9787-ab873bde6361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677304595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.2677304595
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.3823869594
Short name T233
Test name
Test status
Simulation time 146696953992 ps
CPU time 69.83 seconds
Started Apr 30 03:12:53 PM PDT 24
Finished Apr 30 03:14:04 PM PDT 24
Peak memory 200420 kb
Host smart-d79fb86f-c300-4b1e-9ed2-4c3842564521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823869594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.3823869594
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.213308242
Short name T724
Test name
Test status
Simulation time 24418148908 ps
CPU time 9.11 seconds
Started Apr 30 03:12:55 PM PDT 24
Finished Apr 30 03:13:05 PM PDT 24
Peak memory 200380 kb
Host smart-4ab5b520-d8b3-45e2-85fa-3e0f9c26f3f5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213308242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.213308242
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.780364780
Short name T955
Test name
Test status
Simulation time 141118928766 ps
CPU time 1395.68 seconds
Started Apr 30 03:12:55 PM PDT 24
Finished Apr 30 03:36:12 PM PDT 24
Peak memory 200324 kb
Host smart-2840cd70-e66f-4223-99ae-5aed5b7636b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=780364780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.780364780
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.575740399
Short name T448
Test name
Test status
Simulation time 9758415894 ps
CPU time 25.06 seconds
Started Apr 30 03:12:53 PM PDT 24
Finished Apr 30 03:13:19 PM PDT 24
Peak memory 200360 kb
Host smart-dc01d8dc-faaf-458e-b43d-9749a187ad24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575740399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.575740399
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.1962557987
Short name T918
Test name
Test status
Simulation time 83421361915 ps
CPU time 26.3 seconds
Started Apr 30 03:12:54 PM PDT 24
Finished Apr 30 03:13:21 PM PDT 24
Peak memory 199800 kb
Host smart-32523cf9-4bb7-4b9c-8a4c-7af87b0a9f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962557987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.1962557987
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.1625535546
Short name T800
Test name
Test status
Simulation time 11911460197 ps
CPU time 490.32 seconds
Started Apr 30 03:12:54 PM PDT 24
Finished Apr 30 03:21:05 PM PDT 24
Peak memory 200420 kb
Host smart-bc7c9add-3889-4e4f-b591-dddacb69080a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1625535546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.1625535546
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.2468640331
Short name T566
Test name
Test status
Simulation time 4879201086 ps
CPU time 10.65 seconds
Started Apr 30 03:12:56 PM PDT 24
Finished Apr 30 03:13:07 PM PDT 24
Peak memory 199644 kb
Host smart-8baba6db-d1e7-441f-b8b0-4d61bfad58cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2468640331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.2468640331
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.800653022
Short name T621
Test name
Test status
Simulation time 9596361478 ps
CPU time 18.85 seconds
Started Apr 30 03:12:54 PM PDT 24
Finished Apr 30 03:13:13 PM PDT 24
Peak memory 200492 kb
Host smart-fddcd6dd-989d-48b3-afe3-c0f37a8a50a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800653022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.800653022
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.3393801708
Short name T1126
Test name
Test status
Simulation time 2586126455 ps
CPU time 2.85 seconds
Started Apr 30 03:12:55 PM PDT 24
Finished Apr 30 03:12:58 PM PDT 24
Peak memory 196124 kb
Host smart-366811fb-03d6-462c-ad70-6800afcc6ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393801708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.3393801708
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.339699697
Short name T666
Test name
Test status
Simulation time 832374999 ps
CPU time 1.2 seconds
Started Apr 30 03:12:53 PM PDT 24
Finished Apr 30 03:12:54 PM PDT 24
Peak memory 198812 kb
Host smart-c571e73d-839f-433f-935d-ab1490171c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339699697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.339699697
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.3692033060
Short name T1188
Test name
Test status
Simulation time 493123050390 ps
CPU time 583.32 seconds
Started Apr 30 03:12:52 PM PDT 24
Finished Apr 30 03:22:36 PM PDT 24
Peak memory 200388 kb
Host smart-3d5c131a-ec5b-48a1-8ed9-a1f0deace37c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692033060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.3692033060
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.2576373294
Short name T30
Test name
Test status
Simulation time 59046404341 ps
CPU time 843.04 seconds
Started Apr 30 03:12:54 PM PDT 24
Finished Apr 30 03:26:58 PM PDT 24
Peak memory 216864 kb
Host smart-86bb3652-34d7-4b6b-9775-1cd4494d9b57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576373294 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.2576373294
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.56057700
Short name T565
Test name
Test status
Simulation time 6571946524 ps
CPU time 14.62 seconds
Started Apr 30 03:12:56 PM PDT 24
Finished Apr 30 03:13:11 PM PDT 24
Peak memory 200396 kb
Host smart-b223caa9-8603-4f85-a19a-59a3f6890276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56057700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.56057700
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.3886660592
Short name T39
Test name
Test status
Simulation time 80482999466 ps
CPU time 41.91 seconds
Started Apr 30 03:12:55 PM PDT 24
Finished Apr 30 03:13:37 PM PDT 24
Peak memory 200360 kb
Host smart-bd4112df-b7f3-4362-989a-2278fd364ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886660592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.3886660592
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.369075077
Short name T245
Test name
Test status
Simulation time 39824788317 ps
CPU time 73.79 seconds
Started Apr 30 03:16:56 PM PDT 24
Finished Apr 30 03:18:10 PM PDT 24
Peak memory 200384 kb
Host smart-7edb7429-b1c5-4de6-9ead-6c541b646cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369075077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.369075077
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.4185350574
Short name T434
Test name
Test status
Simulation time 91126625602 ps
CPU time 96.01 seconds
Started Apr 30 03:17:00 PM PDT 24
Finished Apr 30 03:18:36 PM PDT 24
Peak memory 200444 kb
Host smart-0994efd0-faf0-4a5b-b802-598ba3d862bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185350574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.4185350574
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.202777311
Short name T980
Test name
Test status
Simulation time 34037553461 ps
CPU time 17.34 seconds
Started Apr 30 03:16:55 PM PDT 24
Finished Apr 30 03:17:13 PM PDT 24
Peak memory 200384 kb
Host smart-58971c18-a7cf-41ab-890a-360f0a653e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202777311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.202777311
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.2971611104
Short name T1179
Test name
Test status
Simulation time 92879384388 ps
CPU time 79.75 seconds
Started Apr 30 03:16:56 PM PDT 24
Finished Apr 30 03:18:16 PM PDT 24
Peak memory 200428 kb
Host smart-8edb1d1f-fa3e-457b-ac65-368e05d22b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971611104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.2971611104
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.2902623326
Short name T143
Test name
Test status
Simulation time 72343481556 ps
CPU time 29.37 seconds
Started Apr 30 03:16:55 PM PDT 24
Finished Apr 30 03:17:24 PM PDT 24
Peak memory 200316 kb
Host smart-dfd0f292-63fb-49e8-b404-91b39f3a4598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902623326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.2902623326
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.1920926532
Short name T126
Test name
Test status
Simulation time 122011186311 ps
CPU time 148.81 seconds
Started Apr 30 03:16:57 PM PDT 24
Finished Apr 30 03:19:27 PM PDT 24
Peak memory 200420 kb
Host smart-af9e244a-f20e-45e4-94c2-1c6050cccbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920926532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.1920926532
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.968928393
Short name T211
Test name
Test status
Simulation time 8293439280 ps
CPU time 7.72 seconds
Started Apr 30 03:17:00 PM PDT 24
Finished Apr 30 03:17:08 PM PDT 24
Peak memory 200456 kb
Host smart-399929bb-ad5e-4ccb-b078-241401cbc006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968928393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.968928393
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.3371970505
Short name T1167
Test name
Test status
Simulation time 47289928763 ps
CPU time 24.47 seconds
Started Apr 30 03:16:56 PM PDT 24
Finished Apr 30 03:17:21 PM PDT 24
Peak memory 200468 kb
Host smart-ea84bd60-6960-4a45-987b-fcce9b376432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371970505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.3371970505
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.1894134470
Short name T761
Test name
Test status
Simulation time 67546197396 ps
CPU time 208.44 seconds
Started Apr 30 03:16:57 PM PDT 24
Finished Apr 30 03:20:27 PM PDT 24
Peak memory 200312 kb
Host smart-de2e298b-784c-4554-bd24-22bc0f64065d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894134470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.1894134470
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.1027566176
Short name T137
Test name
Test status
Simulation time 148047322151 ps
CPU time 66.91 seconds
Started Apr 30 03:17:04 PM PDT 24
Finished Apr 30 03:18:12 PM PDT 24
Peak memory 200408 kb
Host smart-0160d048-a039-4e1a-856f-34b04607b657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027566176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.1027566176
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.938974359
Short name T435
Test name
Test status
Simulation time 50089910 ps
CPU time 0.55 seconds
Started Apr 30 03:13:04 PM PDT 24
Finished Apr 30 03:13:05 PM PDT 24
Peak memory 195784 kb
Host smart-298b7d75-a7bd-42ec-99ad-80bc66954a3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938974359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.938974359
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.3894564736
Short name T754
Test name
Test status
Simulation time 426584815780 ps
CPU time 98.1 seconds
Started Apr 30 03:13:03 PM PDT 24
Finished Apr 30 03:14:42 PM PDT 24
Peak memory 200308 kb
Host smart-68a62337-388f-42a5-ac9d-c7155029e5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894564736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3894564736
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.1105002787
Short name T599
Test name
Test status
Simulation time 29482743198 ps
CPU time 51.96 seconds
Started Apr 30 03:13:04 PM PDT 24
Finished Apr 30 03:13:57 PM PDT 24
Peak memory 200544 kb
Host smart-613748fd-dfc3-4829-bd31-6d1cfc57f91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105002787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.1105002787
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_intr.3278253297
Short name T437
Test name
Test status
Simulation time 20977288706 ps
CPU time 18.65 seconds
Started Apr 30 03:13:05 PM PDT 24
Finished Apr 30 03:13:24 PM PDT 24
Peak memory 200152 kb
Host smart-b0d4c538-38a5-48e3-a7e2-7d91c68ecb4c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278253297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.3278253297
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.1722231645
Short name T1002
Test name
Test status
Simulation time 111569502989 ps
CPU time 207.94 seconds
Started Apr 30 03:13:04 PM PDT 24
Finished Apr 30 03:16:33 PM PDT 24
Peak memory 200336 kb
Host smart-7a56470f-a252-47c0-b60a-e49328dbe430
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1722231645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.1722231645
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.1920079208
Short name T852
Test name
Test status
Simulation time 4265353348 ps
CPU time 6.91 seconds
Started Apr 30 03:13:04 PM PDT 24
Finished Apr 30 03:13:11 PM PDT 24
Peak memory 200352 kb
Host smart-a2847089-3f0f-4cfa-8907-3309c6e7426a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920079208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.1920079208
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.4069831835
Short name T1044
Test name
Test status
Simulation time 86894081606 ps
CPU time 112.49 seconds
Started Apr 30 03:13:01 PM PDT 24
Finished Apr 30 03:14:54 PM PDT 24
Peak memory 200568 kb
Host smart-1d8e0110-6dd9-487c-a402-8aa544f44be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069831835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.4069831835
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.3308293103
Short name T612
Test name
Test status
Simulation time 21857392938 ps
CPU time 269.31 seconds
Started Apr 30 03:13:07 PM PDT 24
Finished Apr 30 03:17:38 PM PDT 24
Peak memory 200364 kb
Host smart-4ca5f850-daca-4ae0-bcb7-aa0997bd70ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3308293103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.3308293103
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.884271156
Short name T558
Test name
Test status
Simulation time 1908270368 ps
CPU time 3.59 seconds
Started Apr 30 03:13:05 PM PDT 24
Finished Apr 30 03:13:09 PM PDT 24
Peak memory 198688 kb
Host smart-d675252f-30ac-44ee-8879-af108b1575bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=884271156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.884271156
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.2109579647
Short name T695
Test name
Test status
Simulation time 29624981103 ps
CPU time 48.7 seconds
Started Apr 30 03:13:03 PM PDT 24
Finished Apr 30 03:13:52 PM PDT 24
Peak memory 200428 kb
Host smart-2959cdf4-2c56-47a6-948f-6fe9b603174e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109579647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.2109579647
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.1322497216
Short name T999
Test name
Test status
Simulation time 32816652802 ps
CPU time 52.07 seconds
Started Apr 30 03:13:03 PM PDT 24
Finished Apr 30 03:13:56 PM PDT 24
Peak memory 196164 kb
Host smart-e8a5fa79-af23-4ab6-9dae-9ed56c12d793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322497216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.1322497216
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.1706482198
Short name T1049
Test name
Test status
Simulation time 5463460845 ps
CPU time 14.56 seconds
Started Apr 30 03:13:02 PM PDT 24
Finished Apr 30 03:13:17 PM PDT 24
Peak memory 199500 kb
Host smart-fbef510f-c128-4f1b-bae2-9406caf33eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706482198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.1706482198
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.4131106418
Short name T332
Test name
Test status
Simulation time 153558921633 ps
CPU time 641.81 seconds
Started Apr 30 03:13:05 PM PDT 24
Finished Apr 30 03:23:47 PM PDT 24
Peak memory 217080 kb
Host smart-cc8b84d5-65de-4a1f-99b8-959ce05c8cf4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131106418 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.4131106418
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.4161191598
Short name T294
Test name
Test status
Simulation time 2185733167 ps
CPU time 2.63 seconds
Started Apr 30 03:13:05 PM PDT 24
Finished Apr 30 03:13:08 PM PDT 24
Peak memory 199412 kb
Host smart-a71af9ec-79ba-4628-bddf-fa91fc6c35fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161191598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.4161191598
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.3034153321
Short name T1153
Test name
Test status
Simulation time 36948649382 ps
CPU time 72.1 seconds
Started Apr 30 03:13:03 PM PDT 24
Finished Apr 30 03:14:16 PM PDT 24
Peak memory 200400 kb
Host smart-30890418-ccc3-4ce4-91c1-d70e15d6f6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034153321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.3034153321
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.2522195504
Short name T189
Test name
Test status
Simulation time 24086415393 ps
CPU time 87.08 seconds
Started Apr 30 03:17:04 PM PDT 24
Finished Apr 30 03:18:31 PM PDT 24
Peak memory 200364 kb
Host smart-03bd5868-3125-490e-98c2-8c7bb8951f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522195504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2522195504
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.1978105262
Short name T128
Test name
Test status
Simulation time 101436465691 ps
CPU time 92.12 seconds
Started Apr 30 03:17:04 PM PDT 24
Finished Apr 30 03:18:37 PM PDT 24
Peak memory 200236 kb
Host smart-792fffac-a530-4769-bfdd-2079c94e0bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978105262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1978105262
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.346051699
Short name T846
Test name
Test status
Simulation time 35622974199 ps
CPU time 14.82 seconds
Started Apr 30 03:17:03 PM PDT 24
Finished Apr 30 03:17:19 PM PDT 24
Peak memory 200396 kb
Host smart-0a6378e2-e5f6-4f1c-82c9-72ea9fc73ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346051699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.346051699
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.1606880854
Short name T747
Test name
Test status
Simulation time 95751805116 ps
CPU time 25.8 seconds
Started Apr 30 03:17:03 PM PDT 24
Finished Apr 30 03:17:29 PM PDT 24
Peak memory 200444 kb
Host smart-565e4bb5-c4e0-46c5-b742-6dd91917d889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606880854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.1606880854
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.2119503181
Short name T890
Test name
Test status
Simulation time 172067910756 ps
CPU time 273.35 seconds
Started Apr 30 03:17:05 PM PDT 24
Finished Apr 30 03:21:39 PM PDT 24
Peak memory 200400 kb
Host smart-407fcd46-b0fa-44aa-96c3-903ae1c705fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119503181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.2119503181
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.4273720585
Short name T992
Test name
Test status
Simulation time 14831718034 ps
CPU time 7.51 seconds
Started Apr 30 03:17:05 PM PDT 24
Finished Apr 30 03:17:13 PM PDT 24
Peak memory 200204 kb
Host smart-83de8c67-eb5b-4d75-b38d-0b4636178a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273720585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.4273720585
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.4112086225
Short name T840
Test name
Test status
Simulation time 58770910868 ps
CPU time 21.7 seconds
Started Apr 30 03:17:08 PM PDT 24
Finished Apr 30 03:17:30 PM PDT 24
Peak memory 200396 kb
Host smart-5b43405f-8869-4bf0-b681-a01fef794174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112086225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.4112086225
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.670237985
Short name T778
Test name
Test status
Simulation time 59559064529 ps
CPU time 97.62 seconds
Started Apr 30 03:17:04 PM PDT 24
Finished Apr 30 03:18:42 PM PDT 24
Peak memory 200364 kb
Host smart-8b7ad61f-8532-4fc7-8a75-04405000821e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670237985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.670237985
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.3069125616
Short name T446
Test name
Test status
Simulation time 10277268 ps
CPU time 0.58 seconds
Started Apr 30 03:13:09 PM PDT 24
Finished Apr 30 03:13:10 PM PDT 24
Peak memory 194776 kb
Host smart-4b4fbfe4-f1a0-40d8-a4e6-638d91e35eef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069125616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.3069125616
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.686153612
Short name T895
Test name
Test status
Simulation time 73605535627 ps
CPU time 118.52 seconds
Started Apr 30 03:13:09 PM PDT 24
Finished Apr 30 03:15:08 PM PDT 24
Peak memory 200376 kb
Host smart-7d406ff8-d90b-4710-bfd5-6aa429b36d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686153612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.686153612
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.3806800418
Short name T1020
Test name
Test status
Simulation time 228336554165 ps
CPU time 351.52 seconds
Started Apr 30 03:13:12 PM PDT 24
Finished Apr 30 03:19:04 PM PDT 24
Peak memory 200372 kb
Host smart-a9c27a1b-df71-4cab-b9b5-2ffa6a9112b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806800418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.3806800418
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.338283119
Short name T590
Test name
Test status
Simulation time 61239663925 ps
CPU time 100.56 seconds
Started Apr 30 03:13:09 PM PDT 24
Finished Apr 30 03:14:51 PM PDT 24
Peak memory 200332 kb
Host smart-b129c29f-a999-4768-85b6-503bb7a7c4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338283119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.338283119
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.4219308074
Short name T432
Test name
Test status
Simulation time 60788215633 ps
CPU time 27.48 seconds
Started Apr 30 03:13:10 PM PDT 24
Finished Apr 30 03:13:39 PM PDT 24
Peak memory 200464 kb
Host smart-68a172c8-3cc0-4153-b515-617dddc21399
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219308074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.4219308074
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.571436391
Short name T117
Test name
Test status
Simulation time 135577040557 ps
CPU time 946.72 seconds
Started Apr 30 03:13:09 PM PDT 24
Finished Apr 30 03:28:57 PM PDT 24
Peak memory 200364 kb
Host smart-25940b37-8fc6-49f8-b03f-b98161c2582e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=571436391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.571436391
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.3812470059
Short name T652
Test name
Test status
Simulation time 6757891518 ps
CPU time 10.94 seconds
Started Apr 30 03:13:12 PM PDT 24
Finished Apr 30 03:13:23 PM PDT 24
Peak memory 200024 kb
Host smart-51c6ee3e-c0d3-4866-890e-5d723ea01896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812470059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.3812470059
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.2770764822
Short name T671
Test name
Test status
Simulation time 91250199543 ps
CPU time 173.79 seconds
Started Apr 30 03:13:10 PM PDT 24
Finished Apr 30 03:16:05 PM PDT 24
Peak memory 199640 kb
Host smart-6b1d5340-33df-474c-bdc9-9ad7045ba4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770764822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.2770764822
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.2183629064
Short name T1135
Test name
Test status
Simulation time 21306590400 ps
CPU time 299.27 seconds
Started Apr 30 03:13:08 PM PDT 24
Finished Apr 30 03:18:08 PM PDT 24
Peak memory 200376 kb
Host smart-b41e6c35-ba56-4f90-beaa-36d44fd97282
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2183629064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.2183629064
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.141920892
Short name T1084
Test name
Test status
Simulation time 3631862986 ps
CPU time 1.85 seconds
Started Apr 30 03:13:13 PM PDT 24
Finished Apr 30 03:13:15 PM PDT 24
Peak memory 198332 kb
Host smart-05eda38c-87c1-4ddd-bfb0-f9b1c8bdb689
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=141920892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.141920892
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.566160224
Short name T784
Test name
Test status
Simulation time 65254916784 ps
CPU time 151.73 seconds
Started Apr 30 03:13:12 PM PDT 24
Finished Apr 30 03:15:44 PM PDT 24
Peak memory 200460 kb
Host smart-98f1a6a7-2694-4a24-a6a1-df3c78af3c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566160224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.566160224
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.3100362532
Short name T640
Test name
Test status
Simulation time 2740897949 ps
CPU time 1.78 seconds
Started Apr 30 03:13:10 PM PDT 24
Finished Apr 30 03:13:13 PM PDT 24
Peak memory 196120 kb
Host smart-4a18603e-bfe4-4fb0-b636-92efc5dea6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100362532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.3100362532
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.721499802
Short name T306
Test name
Test status
Simulation time 452260208 ps
CPU time 2.02 seconds
Started Apr 30 03:13:05 PM PDT 24
Finished Apr 30 03:13:08 PM PDT 24
Peak memory 198768 kb
Host smart-f62e3237-a144-4eef-a626-094718a4b385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721499802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.721499802
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.2889782982
Short name T810
Test name
Test status
Simulation time 276538092758 ps
CPU time 238.1 seconds
Started Apr 30 03:13:08 PM PDT 24
Finished Apr 30 03:17:07 PM PDT 24
Peak memory 200464 kb
Host smart-a262b7a2-523d-46c0-9b5c-32516ece5640
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889782982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.2889782982
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.2832220003
Short name T56
Test name
Test status
Simulation time 421769077495 ps
CPU time 1315.72 seconds
Started Apr 30 03:13:09 PM PDT 24
Finished Apr 30 03:35:06 PM PDT 24
Peak memory 226316 kb
Host smart-65f2eb17-1346-409b-9127-bdd730c3093b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832220003 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.2832220003
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.2167948629
Short name T282
Test name
Test status
Simulation time 2586261079 ps
CPU time 1.64 seconds
Started Apr 30 03:13:08 PM PDT 24
Finished Apr 30 03:13:11 PM PDT 24
Peak memory 198928 kb
Host smart-bf45d0e0-57eb-4499-9a93-7fad1bfbfb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167948629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.2167948629
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.2973920678
Short name T711
Test name
Test status
Simulation time 99874954684 ps
CPU time 37.39 seconds
Started Apr 30 03:13:08 PM PDT 24
Finished Apr 30 03:13:47 PM PDT 24
Peak memory 200320 kb
Host smart-f1db1790-ae54-4dcc-9d56-a9bb59dccbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973920678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.2973920678
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.3360873168
Short name T201
Test name
Test status
Simulation time 23195311493 ps
CPU time 37.86 seconds
Started Apr 30 03:17:06 PM PDT 24
Finished Apr 30 03:17:44 PM PDT 24
Peak memory 200440 kb
Host smart-7a8ac878-1a80-4c5c-9811-2cb57cf30dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360873168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.3360873168
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.900834362
Short name T920
Test name
Test status
Simulation time 48023803336 ps
CPU time 41.36 seconds
Started Apr 30 03:17:04 PM PDT 24
Finished Apr 30 03:17:46 PM PDT 24
Peak memory 200404 kb
Host smart-b873f422-71d2-4474-92a5-d16d2769290a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900834362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.900834362
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.228689078
Short name T699
Test name
Test status
Simulation time 123051913561 ps
CPU time 200.39 seconds
Started Apr 30 03:17:06 PM PDT 24
Finished Apr 30 03:20:27 PM PDT 24
Peak memory 200444 kb
Host smart-f7521a31-9635-4406-8c24-76ecbbc5290b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228689078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.228689078
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.139854605
Short name T195
Test name
Test status
Simulation time 83884894857 ps
CPU time 33.77 seconds
Started Apr 30 03:17:04 PM PDT 24
Finished Apr 30 03:17:39 PM PDT 24
Peak memory 200308 kb
Host smart-d41bf8f0-a932-4dea-90dd-f4c2c6abfb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139854605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.139854605
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.2170796387
Short name T429
Test name
Test status
Simulation time 94307159318 ps
CPU time 30.59 seconds
Started Apr 30 03:17:05 PM PDT 24
Finished Apr 30 03:17:36 PM PDT 24
Peak memory 200440 kb
Host smart-929c7ff9-7894-4b1a-a21f-a60886a9d33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170796387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.2170796387
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.754833416
Short name T730
Test name
Test status
Simulation time 179829066099 ps
CPU time 16.79 seconds
Started Apr 30 03:17:05 PM PDT 24
Finished Apr 30 03:17:22 PM PDT 24
Peak memory 200440 kb
Host smart-b4bb1b0f-75d3-4d84-abee-0fbc7b1f65c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754833416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.754833416
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.3897418648
Short name T917
Test name
Test status
Simulation time 128094464837 ps
CPU time 36.84 seconds
Started Apr 30 03:17:04 PM PDT 24
Finished Apr 30 03:17:42 PM PDT 24
Peak memory 199084 kb
Host smart-e2efc3b7-0d0f-4a58-8f45-543633b82ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897418648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.3897418648
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.2720239250
Short name T715
Test name
Test status
Simulation time 16023508242 ps
CPU time 18.83 seconds
Started Apr 30 03:17:11 PM PDT 24
Finished Apr 30 03:17:30 PM PDT 24
Peak memory 200312 kb
Host smart-c3574f4e-f4f4-478a-b60a-30df7221d25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720239250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.2720239250
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.3936221313
Short name T25
Test name
Test status
Simulation time 35037561 ps
CPU time 0.56 seconds
Started Apr 30 03:11:13 PM PDT 24
Finished Apr 30 03:11:14 PM PDT 24
Peak memory 195820 kb
Host smart-8f0fed64-8191-46cf-8c7c-3c278ba15089
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936221313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.3936221313
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.664320809
Short name T755
Test name
Test status
Simulation time 22202995712 ps
CPU time 14.42 seconds
Started Apr 30 03:11:06 PM PDT 24
Finished Apr 30 03:11:22 PM PDT 24
Peak memory 200416 kb
Host smart-bd99f21a-399d-4253-a7b3-553d7a56879d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664320809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.664320809
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.2801379191
Short name T153
Test name
Test status
Simulation time 38472771728 ps
CPU time 68.53 seconds
Started Apr 30 03:11:06 PM PDT 24
Finished Apr 30 03:12:15 PM PDT 24
Peak memory 200360 kb
Host smart-f4c0bab7-caf8-4b8e-9462-b6548d59f13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801379191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.2801379191
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.3900710110
Short name T145
Test name
Test status
Simulation time 98593863782 ps
CPU time 147.73 seconds
Started Apr 30 03:11:10 PM PDT 24
Finished Apr 30 03:13:38 PM PDT 24
Peak memory 200356 kb
Host smart-bef6284e-23db-4311-b158-8e5678a0d8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900710110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.3900710110
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.1982879064
Short name T1128
Test name
Test status
Simulation time 21414551095 ps
CPU time 23.25 seconds
Started Apr 30 03:11:08 PM PDT 24
Finished Apr 30 03:11:32 PM PDT 24
Peak memory 200380 kb
Host smart-9b30d8df-4491-408a-97da-94a751cdcd65
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982879064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.1982879064
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.3343686227
Short name T658
Test name
Test status
Simulation time 106623793301 ps
CPU time 289.37 seconds
Started Apr 30 03:11:07 PM PDT 24
Finished Apr 30 03:15:57 PM PDT 24
Peak memory 200380 kb
Host smart-37de42dc-e959-47a8-abb7-ce507c3a7356
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3343686227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.3343686227
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.2863501568
Short name T354
Test name
Test status
Simulation time 5840412504 ps
CPU time 19.14 seconds
Started Apr 30 03:11:10 PM PDT 24
Finished Apr 30 03:11:29 PM PDT 24
Peak memory 200392 kb
Host smart-3c9c74a6-f2cd-4d59-beb4-7f5b141072d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863501568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.2863501568
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.4020458909
Short name T665
Test name
Test status
Simulation time 67540746589 ps
CPU time 56.84 seconds
Started Apr 30 03:11:06 PM PDT 24
Finished Apr 30 03:12:04 PM PDT 24
Peak memory 200472 kb
Host smart-ded03c8b-a927-48ff-b1ff-ee591c289d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020458909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.4020458909
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.1624791111
Short name T847
Test name
Test status
Simulation time 11130161263 ps
CPU time 272.14 seconds
Started Apr 30 03:11:06 PM PDT 24
Finished Apr 30 03:15:39 PM PDT 24
Peak memory 200408 kb
Host smart-36aeb95b-12a1-4483-87f0-7f620b60d71c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1624791111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.1624791111
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.565861879
Short name T388
Test name
Test status
Simulation time 3285229021 ps
CPU time 25.64 seconds
Started Apr 30 03:11:12 PM PDT 24
Finished Apr 30 03:11:38 PM PDT 24
Peak memory 198852 kb
Host smart-5f277114-124e-45e6-b5fc-d8bcc5bd0775
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=565861879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.565861879
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.3511679769
Short name T367
Test name
Test status
Simulation time 11953168360 ps
CPU time 18.78 seconds
Started Apr 30 03:11:07 PM PDT 24
Finished Apr 30 03:11:26 PM PDT 24
Peak memory 200444 kb
Host smart-2079bbfd-941e-40cc-9e7f-09ba61422874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511679769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.3511679769
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.3042526133
Short name T981
Test name
Test status
Simulation time 4461782341 ps
CPU time 2.55 seconds
Started Apr 30 03:11:10 PM PDT 24
Finished Apr 30 03:11:13 PM PDT 24
Peak memory 196380 kb
Host smart-372b2b00-cb74-495a-81d9-b568f3473044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042526133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.3042526133
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.1730654855
Short name T97
Test name
Test status
Simulation time 61653673 ps
CPU time 0.74 seconds
Started Apr 30 03:11:19 PM PDT 24
Finished Apr 30 03:11:20 PM PDT 24
Peak memory 218388 kb
Host smart-f11e40ec-acfd-49fb-957b-22f27dd89fca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730654855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.1730654855
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.1510358347
Short name T1173
Test name
Test status
Simulation time 496054774 ps
CPU time 1.29 seconds
Started Apr 30 03:11:10 PM PDT 24
Finished Apr 30 03:11:12 PM PDT 24
Peak memory 200008 kb
Host smart-ee64d3b8-6eb0-4b40-bff9-51ef04e4698c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510358347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.1510358347
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.3483640135
Short name T795
Test name
Test status
Simulation time 45789464064 ps
CPU time 49.13 seconds
Started Apr 30 03:11:19 PM PDT 24
Finished Apr 30 03:12:08 PM PDT 24
Peak memory 200404 kb
Host smart-20a663ac-8684-4273-a041-1c30c3f75981
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483640135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.3483640135
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.1780976344
Short name T952
Test name
Test status
Simulation time 95093955804 ps
CPU time 349.62 seconds
Started Apr 30 03:11:15 PM PDT 24
Finished Apr 30 03:17:05 PM PDT 24
Peak memory 217036 kb
Host smart-83a31ca4-9d25-426b-8ebb-e946513f59c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780976344 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.1780976344
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.3395408361
Short name T442
Test name
Test status
Simulation time 688967545 ps
CPU time 2.84 seconds
Started Apr 30 03:11:10 PM PDT 24
Finished Apr 30 03:11:13 PM PDT 24
Peak memory 198572 kb
Host smart-1b38c2da-edfa-45af-b7f7-0c68724527ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395408361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.3395408361
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.3116809602
Short name T115
Test name
Test status
Simulation time 454848296969 ps
CPU time 35.4 seconds
Started Apr 30 03:11:08 PM PDT 24
Finished Apr 30 03:11:44 PM PDT 24
Peak memory 200392 kb
Host smart-247b147f-7751-4a49-b556-97df93c53cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116809602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3116809602
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.4200128022
Short name T1140
Test name
Test status
Simulation time 32282533 ps
CPU time 0.57 seconds
Started Apr 30 03:13:19 PM PDT 24
Finished Apr 30 03:13:20 PM PDT 24
Peak memory 194824 kb
Host smart-abbfd68c-bcf6-41f7-a502-b31b80f4d5bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200128022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.4200128022
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.2118582983
Short name T728
Test name
Test status
Simulation time 177717514566 ps
CPU time 88.09 seconds
Started Apr 30 03:13:11 PM PDT 24
Finished Apr 30 03:14:40 PM PDT 24
Peak memory 200468 kb
Host smart-ccd0be06-3505-4790-9ea1-6ab7bacc5f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118582983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.2118582983
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.1657426627
Short name T1169
Test name
Test status
Simulation time 38073818179 ps
CPU time 37.08 seconds
Started Apr 30 03:13:09 PM PDT 24
Finished Apr 30 03:13:47 PM PDT 24
Peak memory 200432 kb
Host smart-a24342c6-604d-48f9-a51b-600b08d44fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657426627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.1657426627
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.782912290
Short name T204
Test name
Test status
Simulation time 45232062215 ps
CPU time 74.98 seconds
Started Apr 30 03:13:11 PM PDT 24
Finished Apr 30 03:14:27 PM PDT 24
Peak memory 200360 kb
Host smart-2cabea9e-a507-4bd7-80e9-c9e534b5c3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782912290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.782912290
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.3161460357
Short name T105
Test name
Test status
Simulation time 63423278196 ps
CPU time 27.89 seconds
Started Apr 30 03:13:12 PM PDT 24
Finished Apr 30 03:13:41 PM PDT 24
Peak memory 200216 kb
Host smart-5f8d9aff-8a1a-4e63-99b2-caeb0d65f836
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161460357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.3161460357
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.2586668352
Short name T1115
Test name
Test status
Simulation time 118337314951 ps
CPU time 588.05 seconds
Started Apr 30 03:13:15 PM PDT 24
Finished Apr 30 03:23:04 PM PDT 24
Peak memory 200432 kb
Host smart-63685a7f-74cc-44a0-87ba-bf808cd1e3b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2586668352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.2586668352
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.3127226134
Short name T942
Test name
Test status
Simulation time 4787438871 ps
CPU time 12.03 seconds
Started Apr 30 03:13:17 PM PDT 24
Finished Apr 30 03:13:30 PM PDT 24
Peak memory 199408 kb
Host smart-97f1681b-4943-46d4-8cf4-72c6ecec4eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127226134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.3127226134
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.2591932448
Short name T420
Test name
Test status
Simulation time 225339009009 ps
CPU time 53.29 seconds
Started Apr 30 03:13:18 PM PDT 24
Finished Apr 30 03:14:12 PM PDT 24
Peak memory 208760 kb
Host smart-6d519d97-2245-4a6e-b6f7-1437e7620453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591932448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.2591932448
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.2517471418
Short name T1166
Test name
Test status
Simulation time 17577660044 ps
CPU time 42.1 seconds
Started Apr 30 03:13:18 PM PDT 24
Finished Apr 30 03:14:00 PM PDT 24
Peak memory 200396 kb
Host smart-b996c700-f754-4bd4-9880-294b16a962cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2517471418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.2517471418
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.3646583458
Short name T426
Test name
Test status
Simulation time 5780103196 ps
CPU time 54.7 seconds
Started Apr 30 03:13:12 PM PDT 24
Finished Apr 30 03:14:07 PM PDT 24
Peak memory 198540 kb
Host smart-696c7124-ca87-426b-843c-ee77024caa91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3646583458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.3646583458
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.2595045817
Short name T772
Test name
Test status
Simulation time 3210368063 ps
CPU time 5.41 seconds
Started Apr 30 03:13:17 PM PDT 24
Finished Apr 30 03:13:23 PM PDT 24
Peak memory 196412 kb
Host smart-7e62eac9-8b21-4e7a-8e3d-813193854d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595045817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.2595045817
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.842046405
Short name T1005
Test name
Test status
Simulation time 635579231 ps
CPU time 2.17 seconds
Started Apr 30 03:13:10 PM PDT 24
Finished Apr 30 03:13:13 PM PDT 24
Peak memory 199344 kb
Host smart-c5a4d1bf-aef2-4af1-89c3-a5dde6679787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842046405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.842046405
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.795130471
Short name T17
Test name
Test status
Simulation time 2129808517 ps
CPU time 1.81 seconds
Started Apr 30 03:13:16 PM PDT 24
Finished Apr 30 03:13:19 PM PDT 24
Peak memory 199028 kb
Host smart-637505ce-5320-4fc2-9a36-374c03ec5918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795130471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.795130471
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.1784552076
Short name T582
Test name
Test status
Simulation time 108826227425 ps
CPU time 114.83 seconds
Started Apr 30 03:13:10 PM PDT 24
Finished Apr 30 03:15:06 PM PDT 24
Peak memory 200468 kb
Host smart-dba5655c-057a-4827-b135-66de7f1513a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784552076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.1784552076
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.3475315166
Short name T503
Test name
Test status
Simulation time 31985751382 ps
CPU time 30 seconds
Started Apr 30 03:17:11 PM PDT 24
Finished Apr 30 03:17:42 PM PDT 24
Peak memory 200348 kb
Host smart-8d3292c7-e829-4f8c-b09d-cd4ef07fc326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475315166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.3475315166
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.3716358480
Short name T853
Test name
Test status
Simulation time 216558610572 ps
CPU time 87.68 seconds
Started Apr 30 03:17:12 PM PDT 24
Finished Apr 30 03:18:40 PM PDT 24
Peak memory 200388 kb
Host smart-36e10379-75d2-49aa-a520-638997a7801f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716358480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3716358480
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.3534181446
Short name T255
Test name
Test status
Simulation time 64791526127 ps
CPU time 23.31 seconds
Started Apr 30 03:17:12 PM PDT 24
Finished Apr 30 03:17:36 PM PDT 24
Peak memory 200400 kb
Host smart-95e2ad2b-0f47-40f4-929d-09d90e66b270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534181446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.3534181446
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.3183984929
Short name T1172
Test name
Test status
Simulation time 284578567556 ps
CPU time 144.4 seconds
Started Apr 30 03:17:11 PM PDT 24
Finished Apr 30 03:19:36 PM PDT 24
Peak memory 200392 kb
Host smart-ee51a583-adc6-4b7d-8b0b-5bd42c0c16b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183984929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.3183984929
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.351176620
Short name T610
Test name
Test status
Simulation time 25367952558 ps
CPU time 24.13 seconds
Started Apr 30 03:17:12 PM PDT 24
Finished Apr 30 03:17:37 PM PDT 24
Peak memory 200352 kb
Host smart-5a834b0b-1c65-4ba3-80ab-bf1637014835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351176620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.351176620
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.3103504829
Short name T174
Test name
Test status
Simulation time 198214577946 ps
CPU time 77.89 seconds
Started Apr 30 03:17:11 PM PDT 24
Finished Apr 30 03:18:29 PM PDT 24
Peak memory 200400 kb
Host smart-1bd08844-5a50-417c-8023-ef92777bd383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103504829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.3103504829
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.1176068682
Short name T157
Test name
Test status
Simulation time 68170627240 ps
CPU time 52.09 seconds
Started Apr 30 03:17:14 PM PDT 24
Finished Apr 30 03:18:06 PM PDT 24
Peak memory 200420 kb
Host smart-b860299b-0825-4449-9eba-fc8785879cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176068682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1176068682
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.4154681094
Short name T371
Test name
Test status
Simulation time 15406245 ps
CPU time 0.56 seconds
Started Apr 30 03:13:33 PM PDT 24
Finished Apr 30 03:13:34 PM PDT 24
Peak memory 195792 kb
Host smart-4ff7e611-67f4-46c6-8801-ad2dffc25eac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154681094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.4154681094
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.2634298704
Short name T488
Test name
Test status
Simulation time 131158479276 ps
CPU time 51.35 seconds
Started Apr 30 03:13:20 PM PDT 24
Finished Apr 30 03:14:12 PM PDT 24
Peak memory 200356 kb
Host smart-8b8c8b27-7a64-4ce9-9923-e84f37f35dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634298704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2634298704
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.3597887999
Short name T696
Test name
Test status
Simulation time 41051823737 ps
CPU time 75.83 seconds
Started Apr 30 03:13:19 PM PDT 24
Finished Apr 30 03:14:36 PM PDT 24
Peak memory 200408 kb
Host smart-3728d1fd-becb-4357-a9d3-3ed9200937b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597887999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.3597887999
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.1554294094
Short name T733
Test name
Test status
Simulation time 81463314215 ps
CPU time 67.09 seconds
Started Apr 30 03:13:17 PM PDT 24
Finished Apr 30 03:14:25 PM PDT 24
Peak memory 200600 kb
Host smart-9f7aa199-820b-4179-8161-5494140348a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554294094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.1554294094
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.3618403912
Short name T21
Test name
Test status
Simulation time 8792580446 ps
CPU time 10.44 seconds
Started Apr 30 03:13:18 PM PDT 24
Finished Apr 30 03:13:29 PM PDT 24
Peak memory 200296 kb
Host smart-188dfe04-5632-474e-acce-18b98a923e7b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618403912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.3618403912
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.1295755052
Short name T1037
Test name
Test status
Simulation time 117430036469 ps
CPU time 368.63 seconds
Started Apr 30 03:13:15 PM PDT 24
Finished Apr 30 03:19:24 PM PDT 24
Peak memory 200456 kb
Host smart-d6386daa-f520-4a7e-a545-be279789c256
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1295755052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.1295755052
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.2427383542
Short name T576
Test name
Test status
Simulation time 4275385216 ps
CPU time 3.48 seconds
Started Apr 30 03:13:22 PM PDT 24
Finished Apr 30 03:13:26 PM PDT 24
Peak memory 199604 kb
Host smart-a544da1a-51a7-43d2-bd11-63229eb2c937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427383542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2427383542
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.3984553825
Short name T271
Test name
Test status
Simulation time 57000762474 ps
CPU time 122.3 seconds
Started Apr 30 03:13:22 PM PDT 24
Finished Apr 30 03:15:25 PM PDT 24
Peak memory 200400 kb
Host smart-a7524268-d4b4-4cc3-a253-5fe3e634976a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984553825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.3984553825
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.1108996063
Short name T394
Test name
Test status
Simulation time 16420644942 ps
CPU time 60.59 seconds
Started Apr 30 03:13:20 PM PDT 24
Finished Apr 30 03:14:21 PM PDT 24
Peak memory 200392 kb
Host smart-27061494-6621-423b-9894-349604ea5bf8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1108996063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.1108996063
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.3456464155
Short name T1047
Test name
Test status
Simulation time 1899861016 ps
CPU time 9.89 seconds
Started Apr 30 03:13:17 PM PDT 24
Finished Apr 30 03:13:28 PM PDT 24
Peak memory 198528 kb
Host smart-d8e590f8-a9a2-4f3e-9bea-bd4b0b5a1260
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3456464155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.3456464155
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.4178630144
Short name T601
Test name
Test status
Simulation time 115110394545 ps
CPU time 33.3 seconds
Started Apr 30 03:13:18 PM PDT 24
Finished Apr 30 03:13:52 PM PDT 24
Peak memory 200412 kb
Host smart-b12d754b-e4ac-404d-ba55-0f6d158b8fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178630144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.4178630144
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.3933954636
Short name T805
Test name
Test status
Simulation time 47175050335 ps
CPU time 80.83 seconds
Started Apr 30 03:13:16 PM PDT 24
Finished Apr 30 03:14:37 PM PDT 24
Peak memory 196252 kb
Host smart-eced609a-d7cd-49e3-8291-728888275237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933954636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.3933954636
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.1103809324
Short name T588
Test name
Test status
Simulation time 568114932 ps
CPU time 1.27 seconds
Started Apr 30 03:13:17 PM PDT 24
Finished Apr 30 03:13:19 PM PDT 24
Peak memory 198728 kb
Host smart-5c7d5c64-813e-4972-a355-5d2df9ca5457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103809324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.1103809324
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.1686778577
Short name T190
Test name
Test status
Simulation time 1056361087414 ps
CPU time 169.28 seconds
Started Apr 30 03:13:26 PM PDT 24
Finished Apr 30 03:16:16 PM PDT 24
Peak memory 200324 kb
Host smart-cff82026-5f25-4c3e-b51d-5ffac0252274
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686778577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.1686778577
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.3089876663
Short name T58
Test name
Test status
Simulation time 66633133631 ps
CPU time 1223.62 seconds
Started Apr 30 03:13:26 PM PDT 24
Finished Apr 30 03:33:50 PM PDT 24
Peak memory 217044 kb
Host smart-b39dc709-b8c4-4790-88be-990dfbc48ce6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089876663 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.3089876663
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.2891292980
Short name T440
Test name
Test status
Simulation time 12444978563 ps
CPU time 9.15 seconds
Started Apr 30 03:13:17 PM PDT 24
Finished Apr 30 03:13:27 PM PDT 24
Peak memory 200232 kb
Host smart-a1521340-5a7f-4f2e-9f4c-c8d7913aa17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891292980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.2891292980
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.2071255029
Short name T304
Test name
Test status
Simulation time 91638111384 ps
CPU time 189.5 seconds
Started Apr 30 03:13:21 PM PDT 24
Finished Apr 30 03:16:31 PM PDT 24
Peak memory 200340 kb
Host smart-953a0f74-afce-4534-821c-cdfef8783a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071255029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.2071255029
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.3305030618
Short name T935
Test name
Test status
Simulation time 27750034688 ps
CPU time 42.4 seconds
Started Apr 30 03:17:14 PM PDT 24
Finished Apr 30 03:17:57 PM PDT 24
Peak memory 200456 kb
Host smart-03496bd4-d94f-4445-a8d4-1f5ad86a5b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305030618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.3305030618
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.822640628
Short name T986
Test name
Test status
Simulation time 13012815463 ps
CPU time 27 seconds
Started Apr 30 03:17:12 PM PDT 24
Finished Apr 30 03:17:40 PM PDT 24
Peak memory 200448 kb
Host smart-f702bf9e-131a-4447-a046-a395ea723e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822640628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.822640628
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.1733437648
Short name T974
Test name
Test status
Simulation time 69101502128 ps
CPU time 100.64 seconds
Started Apr 30 03:17:12 PM PDT 24
Finished Apr 30 03:18:53 PM PDT 24
Peak memory 200348 kb
Host smart-43660e07-2dcd-47fa-95bd-a2d87050a95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733437648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.1733437648
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.2637055070
Short name T721
Test name
Test status
Simulation time 37572122525 ps
CPU time 66.61 seconds
Started Apr 30 03:17:12 PM PDT 24
Finished Apr 30 03:18:19 PM PDT 24
Peak memory 200328 kb
Host smart-4db540ed-2755-4545-9df8-1438473c2d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637055070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2637055070
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.2481298740
Short name T1081
Test name
Test status
Simulation time 27038373801 ps
CPU time 13.29 seconds
Started Apr 30 03:17:14 PM PDT 24
Finished Apr 30 03:17:28 PM PDT 24
Peak memory 200412 kb
Host smart-81295167-3613-48f3-8cc4-f674b6591ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481298740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.2481298740
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.2375658927
Short name T341
Test name
Test status
Simulation time 16406887790 ps
CPU time 12.83 seconds
Started Apr 30 03:17:21 PM PDT 24
Finished Apr 30 03:17:35 PM PDT 24
Peak memory 200396 kb
Host smart-34468fbe-40f2-4470-ab9f-feea9873a046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375658927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.2375658927
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.2400533007
Short name T1157
Test name
Test status
Simulation time 55688520302 ps
CPU time 21.89 seconds
Started Apr 30 03:17:24 PM PDT 24
Finished Apr 30 03:17:47 PM PDT 24
Peak memory 200372 kb
Host smart-c476f6b4-4c21-458c-ac88-544513f441a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400533007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.2400533007
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.2296505239
Short name T929
Test name
Test status
Simulation time 10641661885 ps
CPU time 7.42 seconds
Started Apr 30 03:17:25 PM PDT 24
Finished Apr 30 03:17:33 PM PDT 24
Peak memory 200408 kb
Host smart-6052037b-f67d-4229-a992-8b8cb8d25a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296505239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.2296505239
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.260029675
Short name T645
Test name
Test status
Simulation time 223548422433 ps
CPU time 101.92 seconds
Started Apr 30 03:17:21 PM PDT 24
Finished Apr 30 03:19:03 PM PDT 24
Peak memory 200108 kb
Host smart-c7a65113-897e-448c-8653-86f09e750fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260029675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.260029675
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.3173760764
Short name T1013
Test name
Test status
Simulation time 13060672 ps
CPU time 0.55 seconds
Started Apr 30 03:13:43 PM PDT 24
Finished Apr 30 03:13:44 PM PDT 24
Peak memory 195804 kb
Host smart-a5ae427d-f156-43d9-a467-a7e610e4a7c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173760764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.3173760764
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.336887361
Short name T707
Test name
Test status
Simulation time 62213055224 ps
CPU time 28.55 seconds
Started Apr 30 03:13:25 PM PDT 24
Finished Apr 30 03:13:54 PM PDT 24
Peak memory 200404 kb
Host smart-d4115bc3-1ae7-4bb0-b980-39313165cce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336887361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.336887361
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.2946658850
Short name T500
Test name
Test status
Simulation time 135186260986 ps
CPU time 35.22 seconds
Started Apr 30 03:13:27 PM PDT 24
Finished Apr 30 03:14:03 PM PDT 24
Peak memory 200240 kb
Host smart-932c58c0-4b1a-4486-a7aa-244b12ed6843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946658850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2946658850
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.349002049
Short name T421
Test name
Test status
Simulation time 190448824499 ps
CPU time 120.27 seconds
Started Apr 30 03:13:25 PM PDT 24
Finished Apr 30 03:15:26 PM PDT 24
Peak memory 200420 kb
Host smart-04b288a9-1013-4969-9ba9-ed9d5705a55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349002049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.349002049
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.1573578289
Short name T927
Test name
Test status
Simulation time 54755085869 ps
CPU time 40.01 seconds
Started Apr 30 03:13:27 PM PDT 24
Finished Apr 30 03:14:07 PM PDT 24
Peak memory 200396 kb
Host smart-1b02e988-3fb3-4933-b907-015f63a8a1b8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573578289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.1573578289
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.4070710874
Short name T370
Test name
Test status
Simulation time 104572716255 ps
CPU time 163.49 seconds
Started Apr 30 03:13:26 PM PDT 24
Finished Apr 30 03:16:10 PM PDT 24
Peak memory 200424 kb
Host smart-17e49bec-e991-4a2e-8308-1c434de30bcb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4070710874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.4070710874
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.4041501662
Short name T1057
Test name
Test status
Simulation time 2202252770 ps
CPU time 7.81 seconds
Started Apr 30 03:13:32 PM PDT 24
Finished Apr 30 03:13:41 PM PDT 24
Peak memory 198672 kb
Host smart-dd2aa0f2-c819-4162-bbf0-de4d81dbff56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041501662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.4041501662
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.779518475
Short name T8
Test name
Test status
Simulation time 16710645820 ps
CPU time 15.53 seconds
Started Apr 30 03:13:26 PM PDT 24
Finished Apr 30 03:13:42 PM PDT 24
Peak memory 199280 kb
Host smart-8c1519ae-f85c-48eb-b0d4-94ab77d169eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779518475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.779518475
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.2791286537
Short name T326
Test name
Test status
Simulation time 4249579352 ps
CPU time 57.33 seconds
Started Apr 30 03:13:26 PM PDT 24
Finished Apr 30 03:14:24 PM PDT 24
Peak memory 200432 kb
Host smart-6908a79d-e54a-4f1f-b694-060631ed6207
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2791286537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.2791286537
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.1300253383
Short name T727
Test name
Test status
Simulation time 4135237791 ps
CPU time 9.34 seconds
Started Apr 30 03:13:25 PM PDT 24
Finished Apr 30 03:13:35 PM PDT 24
Peak memory 199228 kb
Host smart-cb78354f-3629-44ee-82c7-d953cf913936
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1300253383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.1300253383
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.1557284602
Short name T907
Test name
Test status
Simulation time 30577061612 ps
CPU time 6.1 seconds
Started Apr 30 03:13:24 PM PDT 24
Finished Apr 30 03:13:31 PM PDT 24
Peak memory 200128 kb
Host smart-d77e7584-442f-4fb8-ba16-6740de018ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557284602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.1557284602
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.471142084
Short name T953
Test name
Test status
Simulation time 1669790621 ps
CPU time 2.57 seconds
Started Apr 30 03:13:24 PM PDT 24
Finished Apr 30 03:13:27 PM PDT 24
Peak memory 196100 kb
Host smart-4bd803dc-595e-4ebd-ada5-03014aee4997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471142084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.471142084
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.415911322
Short name T520
Test name
Test status
Simulation time 885596389 ps
CPU time 4.51 seconds
Started Apr 30 03:13:33 PM PDT 24
Finished Apr 30 03:13:38 PM PDT 24
Peak memory 200104 kb
Host smart-92bff274-e7b8-4900-a9fb-7668b419b90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415911322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.415911322
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.2888812710
Short name T883
Test name
Test status
Simulation time 22285987619 ps
CPU time 526.15 seconds
Started Apr 30 03:13:24 PM PDT 24
Finished Apr 30 03:22:11 PM PDT 24
Peak memory 200400 kb
Host smart-5c2b8cfa-0158-45ec-8ae1-a9be3b22586e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888812710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.2888812710
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.4149553422
Short name T825
Test name
Test status
Simulation time 76242775131 ps
CPU time 114.88 seconds
Started Apr 30 03:13:32 PM PDT 24
Finished Apr 30 03:15:28 PM PDT 24
Peak memory 216628 kb
Host smart-a8ec215f-8cb7-4537-8cb7-62c17ad8a111
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149553422 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.4149553422
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.960429253
Short name T934
Test name
Test status
Simulation time 8095657428 ps
CPU time 6.45 seconds
Started Apr 30 03:13:25 PM PDT 24
Finished Apr 30 03:13:32 PM PDT 24
Peak memory 200180 kb
Host smart-673b7aa1-ec69-434a-8b81-d3c86d061b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960429253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.960429253
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.2948406326
Short name T719
Test name
Test status
Simulation time 209605627003 ps
CPU time 74.35 seconds
Started Apr 30 03:13:27 PM PDT 24
Finished Apr 30 03:14:42 PM PDT 24
Peak memory 200380 kb
Host smart-9740b758-11b3-4484-81f5-0eb3d4ce1347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948406326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.2948406326
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.2429045721
Short name T839
Test name
Test status
Simulation time 107673123342 ps
CPU time 46.54 seconds
Started Apr 30 03:17:21 PM PDT 24
Finished Apr 30 03:18:08 PM PDT 24
Peak memory 200388 kb
Host smart-1a0c86fc-d215-4ae8-a669-91884fa5d7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429045721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.2429045721
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.2971819610
Short name T159
Test name
Test status
Simulation time 39095334570 ps
CPU time 65.18 seconds
Started Apr 30 03:17:21 PM PDT 24
Finished Apr 30 03:18:28 PM PDT 24
Peak memory 200400 kb
Host smart-c9b117f1-0c48-4d9e-bd70-dc318352d836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971819610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.2971819610
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.2689732697
Short name T1103
Test name
Test status
Simulation time 24163024608 ps
CPU time 41.28 seconds
Started Apr 30 03:17:22 PM PDT 24
Finished Apr 30 03:18:04 PM PDT 24
Peak memory 200400 kb
Host smart-589f8f6e-8d3a-4ea5-b472-80bd561abfdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689732697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.2689732697
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.3545626955
Short name T1097
Test name
Test status
Simulation time 40349598949 ps
CPU time 65.94 seconds
Started Apr 30 03:17:22 PM PDT 24
Finished Apr 30 03:18:29 PM PDT 24
Peak memory 200396 kb
Host smart-666c9ef5-b3a7-4c43-8b90-b61b96c1593b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545626955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.3545626955
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.2493307127
Short name T344
Test name
Test status
Simulation time 89879615056 ps
CPU time 38.26 seconds
Started Apr 30 03:17:23 PM PDT 24
Finished Apr 30 03:18:02 PM PDT 24
Peak memory 200376 kb
Host smart-2f893308-cb85-42cf-8e7a-f6d539d17dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493307127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.2493307127
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.2282694548
Short name T216
Test name
Test status
Simulation time 106879399043 ps
CPU time 176 seconds
Started Apr 30 03:17:22 PM PDT 24
Finished Apr 30 03:20:19 PM PDT 24
Peak memory 200356 kb
Host smart-2ccb7569-72a8-4ca5-83fb-11e163a54666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282694548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.2282694548
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.2622913547
Short name T160
Test name
Test status
Simulation time 125294535246 ps
CPU time 112.87 seconds
Started Apr 30 03:17:21 PM PDT 24
Finished Apr 30 03:19:14 PM PDT 24
Peak memory 200452 kb
Host smart-b84bc242-3d41-4223-ade8-111b3d509a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622913547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.2622913547
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.161391835
Short name T936
Test name
Test status
Simulation time 48488643130 ps
CPU time 47.64 seconds
Started Apr 30 03:17:21 PM PDT 24
Finished Apr 30 03:18:10 PM PDT 24
Peak memory 200316 kb
Host smart-136262fe-d5df-4b55-b87b-1539f18a41f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161391835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.161391835
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.1257759468
Short name T203
Test name
Test status
Simulation time 31602610142 ps
CPU time 27.66 seconds
Started Apr 30 03:17:23 PM PDT 24
Finished Apr 30 03:17:51 PM PDT 24
Peak memory 200360 kb
Host smart-74036539-a42f-42e9-b91f-07ebb631773a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257759468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.1257759468
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.2291040599
Short name T1051
Test name
Test status
Simulation time 63010879981 ps
CPU time 217.27 seconds
Started Apr 30 03:17:22 PM PDT 24
Finished Apr 30 03:21:00 PM PDT 24
Peak memory 200364 kb
Host smart-2b5a62b5-d9e4-4208-8b08-645c48e723bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291040599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.2291040599
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.1353925154
Short name T678
Test name
Test status
Simulation time 11780794 ps
CPU time 0.53 seconds
Started Apr 30 03:13:33 PM PDT 24
Finished Apr 30 03:13:34 PM PDT 24
Peak memory 194780 kb
Host smart-76115659-3a61-4dd0-9434-698ca5926639
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353925154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.1353925154
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.3695675539
Short name T180
Test name
Test status
Simulation time 80996188435 ps
CPU time 32.83 seconds
Started Apr 30 03:13:34 PM PDT 24
Finished Apr 30 03:14:07 PM PDT 24
Peak memory 200460 kb
Host smart-0ff7e60a-038c-4252-9e55-e35ff0bc5223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695675539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.3695675539
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.3408305171
Short name T814
Test name
Test status
Simulation time 72044315934 ps
CPU time 57.67 seconds
Started Apr 30 03:13:40 PM PDT 24
Finished Apr 30 03:14:38 PM PDT 24
Peak memory 200408 kb
Host smart-60b2f33a-a5d7-435e-bd04-d3a7f3b1e871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408305171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.3408305171
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.1407088133
Short name T219
Test name
Test status
Simulation time 120561274435 ps
CPU time 85.8 seconds
Started Apr 30 03:13:40 PM PDT 24
Finished Apr 30 03:15:06 PM PDT 24
Peak memory 200324 kb
Host smart-b351529e-6b50-426f-a241-a5a93693c4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407088133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.1407088133
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.1142798274
Short name T470
Test name
Test status
Simulation time 161825839880 ps
CPU time 247.08 seconds
Started Apr 30 03:13:43 PM PDT 24
Finished Apr 30 03:17:51 PM PDT 24
Peak memory 200436 kb
Host smart-b5d21e43-2b71-4e8f-956a-6c0ced1e8021
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142798274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.1142798274
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.1473091231
Short name T653
Test name
Test status
Simulation time 47694337931 ps
CPU time 179.12 seconds
Started Apr 30 03:13:40 PM PDT 24
Finished Apr 30 03:16:40 PM PDT 24
Peak memory 200364 kb
Host smart-b2de0f74-84fd-4e27-b27c-2e59ff6cb65a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1473091231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1473091231
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.2169489844
Short name T458
Test name
Test status
Simulation time 4227674813 ps
CPU time 4.22 seconds
Started Apr 30 03:13:35 PM PDT 24
Finished Apr 30 03:13:39 PM PDT 24
Peak memory 200408 kb
Host smart-c099c6ea-d521-4536-b4e8-f6a09dbadfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169489844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.2169489844
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.2226600646
Short name T278
Test name
Test status
Simulation time 68173582716 ps
CPU time 48.85 seconds
Started Apr 30 03:13:36 PM PDT 24
Finished Apr 30 03:14:25 PM PDT 24
Peak memory 200552 kb
Host smart-93c2b378-14d6-406e-b838-6800344e4398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226600646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.2226600646
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.2588330407
Short name T481
Test name
Test status
Simulation time 7362492711 ps
CPU time 384.65 seconds
Started Apr 30 03:13:35 PM PDT 24
Finished Apr 30 03:20:00 PM PDT 24
Peak memory 200392 kb
Host smart-75423409-de92-4dbc-9c5c-c38732e4b0d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2588330407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.2588330407
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.223360349
Short name T984
Test name
Test status
Simulation time 5435900595 ps
CPU time 22 seconds
Started Apr 30 03:13:32 PM PDT 24
Finished Apr 30 03:13:54 PM PDT 24
Peak memory 199232 kb
Host smart-43fa5e66-c974-40d0-8219-1559c78002e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=223360349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.223360349
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.297448956
Short name T1050
Test name
Test status
Simulation time 129748120591 ps
CPU time 56.9 seconds
Started Apr 30 03:13:30 PM PDT 24
Finished Apr 30 03:14:27 PM PDT 24
Peak memory 200388 kb
Host smart-5b9feba4-d395-4c54-add3-c8e173e43b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297448956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.297448956
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.429204079
Short name T637
Test name
Test status
Simulation time 401844886 ps
CPU time 1.25 seconds
Started Apr 30 03:13:35 PM PDT 24
Finished Apr 30 03:13:37 PM PDT 24
Peak memory 195812 kb
Host smart-acd6a16e-164b-4605-950c-23863db8f6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429204079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.429204079
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.3184739500
Short name T886
Test name
Test status
Simulation time 659924509 ps
CPU time 2.78 seconds
Started Apr 30 03:13:32 PM PDT 24
Finished Apr 30 03:13:35 PM PDT 24
Peak memory 198780 kb
Host smart-e07e3158-611f-4e39-9928-34adf1e2c52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184739500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.3184739500
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.2313239006
Short name T464
Test name
Test status
Simulation time 210848751486 ps
CPU time 397.73 seconds
Started Apr 30 03:13:34 PM PDT 24
Finished Apr 30 03:20:12 PM PDT 24
Peak memory 216468 kb
Host smart-eaec9927-33bf-4d95-87a1-732f12f77c5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313239006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.2313239006
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.1345708340
Short name T378
Test name
Test status
Simulation time 2098791099 ps
CPU time 2.41 seconds
Started Apr 30 03:13:32 PM PDT 24
Finished Apr 30 03:13:35 PM PDT 24
Peak memory 198968 kb
Host smart-913cb256-8957-47e0-b2db-eceeb3f98def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345708340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.1345708340
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.1326034063
Short name T1058
Test name
Test status
Simulation time 68541157674 ps
CPU time 38.29 seconds
Started Apr 30 03:13:33 PM PDT 24
Finished Apr 30 03:14:11 PM PDT 24
Peak memory 200392 kb
Host smart-6c68e4dc-9c05-4f83-b946-7e95b18e58e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326034063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.1326034063
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.876605668
Short name T551
Test name
Test status
Simulation time 117046304981 ps
CPU time 95.56 seconds
Started Apr 30 03:17:24 PM PDT 24
Finished Apr 30 03:19:00 PM PDT 24
Peak memory 200396 kb
Host smart-e497189e-da60-4b40-a393-277c4f6eb556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876605668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.876605668
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3241975423
Short name T937
Test name
Test status
Simulation time 22488344187 ps
CPU time 45.64 seconds
Started Apr 30 03:17:29 PM PDT 24
Finished Apr 30 03:18:16 PM PDT 24
Peak memory 200408 kb
Host smart-eeb64b1d-d63a-4226-b920-33a23b77b423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241975423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3241975423
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.2922290387
Short name T594
Test name
Test status
Simulation time 117613392149 ps
CPU time 57.27 seconds
Started Apr 30 03:17:29 PM PDT 24
Finished Apr 30 03:18:27 PM PDT 24
Peak memory 200356 kb
Host smart-1d26ff48-c868-41a1-8894-ea2376cfdeca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922290387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.2922290387
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.1456396996
Short name T214
Test name
Test status
Simulation time 26917104898 ps
CPU time 24.52 seconds
Started Apr 30 03:17:30 PM PDT 24
Finished Apr 30 03:17:55 PM PDT 24
Peak memory 199252 kb
Host smart-0d291374-1459-4675-a99f-76fab2e22208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456396996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.1456396996
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.647521979
Short name T234
Test name
Test status
Simulation time 40378375554 ps
CPU time 21.52 seconds
Started Apr 30 03:17:32 PM PDT 24
Finished Apr 30 03:17:54 PM PDT 24
Peak memory 200400 kb
Host smart-b53c445c-648d-4e0e-bbec-23ca43fdb7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647521979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.647521979
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.3062851072
Short name T584
Test name
Test status
Simulation time 55540797965 ps
CPU time 82.33 seconds
Started Apr 30 03:17:31 PM PDT 24
Finished Apr 30 03:18:54 PM PDT 24
Peak memory 200336 kb
Host smart-bafa3907-f40c-4cd4-ba86-aaad5c578c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062851072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3062851072
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.324110950
Short name T187
Test name
Test status
Simulation time 105923214796 ps
CPU time 94.99 seconds
Started Apr 30 03:17:32 PM PDT 24
Finished Apr 30 03:19:07 PM PDT 24
Peak memory 200444 kb
Host smart-d6e7246c-a678-420e-9412-598904ff1c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324110950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.324110950
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.2998056122
Short name T46
Test name
Test status
Simulation time 82393811771 ps
CPU time 123.6 seconds
Started Apr 30 03:17:40 PM PDT 24
Finished Apr 30 03:19:44 PM PDT 24
Peak memory 200400 kb
Host smart-89e20ff2-0c64-47f6-89d8-2b84de786fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998056122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.2998056122
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.4233545327
Short name T1137
Test name
Test status
Simulation time 15535685 ps
CPU time 0.56 seconds
Started Apr 30 03:13:44 PM PDT 24
Finished Apr 30 03:13:45 PM PDT 24
Peak memory 195812 kb
Host smart-889119d2-2f12-4d14-b0df-09cfa7daefa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233545327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.4233545327
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.3496371184
Short name T542
Test name
Test status
Simulation time 150300301020 ps
CPU time 216.78 seconds
Started Apr 30 03:13:35 PM PDT 24
Finished Apr 30 03:17:13 PM PDT 24
Peak memory 200308 kb
Host smart-6746f2d4-0b22-4551-a527-aa4016093d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496371184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.3496371184
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.1406491536
Short name T1113
Test name
Test status
Simulation time 143676940538 ps
CPU time 107.13 seconds
Started Apr 30 03:13:33 PM PDT 24
Finished Apr 30 03:15:20 PM PDT 24
Peak memory 200412 kb
Host smart-e449e406-bfeb-4b3c-8a8d-8233d625c142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406491536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.1406491536
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.3672143934
Short name T1093
Test name
Test status
Simulation time 55006770241 ps
CPU time 66.38 seconds
Started Apr 30 03:13:32 PM PDT 24
Finished Apr 30 03:14:39 PM PDT 24
Peak memory 200480 kb
Host smart-963cbe32-06e6-4687-97db-a2917fe8b145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672143934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.3672143934
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.1061549946
Short name T47
Test name
Test status
Simulation time 30907283372 ps
CPU time 33.33 seconds
Started Apr 30 03:13:37 PM PDT 24
Finished Apr 30 03:14:11 PM PDT 24
Peak memory 200280 kb
Host smart-ce344587-8606-4bdd-9a9a-ab81cb624878
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061549946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.1061549946
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.1717215749
Short name T267
Test name
Test status
Simulation time 93452566224 ps
CPU time 401.6 seconds
Started Apr 30 03:13:41 PM PDT 24
Finished Apr 30 03:20:23 PM PDT 24
Peak memory 200368 kb
Host smart-0af92aef-9544-405a-86d0-d2d8db062a29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1717215749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1717215749
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.570512143
Short name T365
Test name
Test status
Simulation time 3341301024 ps
CPU time 7.13 seconds
Started Apr 30 03:13:40 PM PDT 24
Finished Apr 30 03:13:47 PM PDT 24
Peak memory 199676 kb
Host smart-3db2f8f6-8d57-463f-b99b-8a566513d593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570512143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.570512143
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.986886859
Short name T287
Test name
Test status
Simulation time 78183790465 ps
CPU time 14.57 seconds
Started Apr 30 03:13:33 PM PDT 24
Finished Apr 30 03:13:48 PM PDT 24
Peak memory 197980 kb
Host smart-5ab22743-12a5-4d2d-ad91-7d537a1bcb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986886859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.986886859
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.3448561590
Short name T710
Test name
Test status
Simulation time 18521550407 ps
CPU time 389.42 seconds
Started Apr 30 03:13:45 PM PDT 24
Finished Apr 30 03:20:15 PM PDT 24
Peak memory 200420 kb
Host smart-4ad6e53c-4330-470d-8aa8-8ae213a9e50e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3448561590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.3448561590
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.1585555202
Short name T351
Test name
Test status
Simulation time 6312196983 ps
CPU time 25.72 seconds
Started Apr 30 03:13:32 PM PDT 24
Finished Apr 30 03:13:58 PM PDT 24
Peak memory 199576 kb
Host smart-0c128798-4333-4189-a14a-ce01527c6178
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1585555202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1585555202
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.2434127644
Short name T1060
Test name
Test status
Simulation time 161701042179 ps
CPU time 81.24 seconds
Started Apr 30 03:13:40 PM PDT 24
Finished Apr 30 03:15:02 PM PDT 24
Peak memory 200144 kb
Host smart-a4242cd1-ea4f-4a96-b1a2-ff5fcf6a963c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434127644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.2434127644
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.3822960242
Short name T552
Test name
Test status
Simulation time 4527731157 ps
CPU time 2.58 seconds
Started Apr 30 03:13:32 PM PDT 24
Finished Apr 30 03:13:36 PM PDT 24
Peak memory 196704 kb
Host smart-6a4ca6ec-4106-4e21-9e87-0c2e9cb22110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822960242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.3822960242
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.2446899673
Short name T788
Test name
Test status
Simulation time 660065637 ps
CPU time 1.29 seconds
Started Apr 30 03:13:34 PM PDT 24
Finished Apr 30 03:13:36 PM PDT 24
Peak memory 198808 kb
Host smart-d60e4406-2ab3-40e1-b9f5-5884bfbe02dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446899673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.2446899673
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.2487379961
Short name T741
Test name
Test status
Simulation time 22865323060 ps
CPU time 304.57 seconds
Started Apr 30 03:13:45 PM PDT 24
Finished Apr 30 03:18:50 PM PDT 24
Peak memory 209092 kb
Host smart-7c170524-9c4e-4a34-8454-977b203c7a74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487379961 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.2487379961
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.3944056017
Short name T648
Test name
Test status
Simulation time 813950786 ps
CPU time 3.17 seconds
Started Apr 30 03:13:40 PM PDT 24
Finished Apr 30 03:13:43 PM PDT 24
Peak memory 199320 kb
Host smart-e83d24a4-8354-488e-810f-7db1daccf484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944056017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.3944056017
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.964518323
Short name T1155
Test name
Test status
Simulation time 291074061824 ps
CPU time 154.92 seconds
Started Apr 30 03:13:33 PM PDT 24
Finished Apr 30 03:16:09 PM PDT 24
Peak memory 200468 kb
Host smart-3dbd2b14-162a-4484-b474-f91a480ff939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964518323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.964518323
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.3692006892
Short name T213
Test name
Test status
Simulation time 106322104782 ps
CPU time 163.52 seconds
Started Apr 30 03:17:36 PM PDT 24
Finished Apr 30 03:20:20 PM PDT 24
Peak memory 200336 kb
Host smart-04d62825-d87d-42f2-bf09-7b051d951364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692006892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.3692006892
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.1194251841
Short name T398
Test name
Test status
Simulation time 14952553062 ps
CPU time 26.19 seconds
Started Apr 30 03:17:29 PM PDT 24
Finished Apr 30 03:17:56 PM PDT 24
Peak memory 200048 kb
Host smart-83d66c81-7d79-4039-a3a6-16ed7b49cda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194251841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.1194251841
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.3523076424
Short name T527
Test name
Test status
Simulation time 21087797265 ps
CPU time 34.81 seconds
Started Apr 30 03:17:30 PM PDT 24
Finished Apr 30 03:18:05 PM PDT 24
Peak memory 200396 kb
Host smart-e5e676ee-6bfa-42dc-a69a-2f120bfd51b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523076424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.3523076424
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.4212001256
Short name T436
Test name
Test status
Simulation time 53489150506 ps
CPU time 101.99 seconds
Started Apr 30 03:17:31 PM PDT 24
Finished Apr 30 03:19:13 PM PDT 24
Peak memory 200324 kb
Host smart-dfcfe768-c0b9-4b59-8486-17c611a681c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212001256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.4212001256
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.221677810
Short name T627
Test name
Test status
Simulation time 45274978952 ps
CPU time 21.15 seconds
Started Apr 30 03:17:31 PM PDT 24
Finished Apr 30 03:17:53 PM PDT 24
Peak memory 200364 kb
Host smart-fdd9b3ce-da18-4ba8-81b6-f547ef4f43c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221677810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.221677810
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.4289567374
Short name T290
Test name
Test status
Simulation time 174342635990 ps
CPU time 55.1 seconds
Started Apr 30 03:17:31 PM PDT 24
Finished Apr 30 03:18:27 PM PDT 24
Peak memory 200472 kb
Host smart-c985c07b-4496-4f70-b36c-63810e34bc4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289567374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.4289567374
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.3935518131
Short name T752
Test name
Test status
Simulation time 193265057521 ps
CPU time 84.36 seconds
Started Apr 30 03:17:29 PM PDT 24
Finished Apr 30 03:18:54 PM PDT 24
Peak memory 200392 kb
Host smart-5833c56c-e90a-4fc6-bb9b-c797366213ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935518131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.3935518131
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.126560462
Short name T818
Test name
Test status
Simulation time 158534249643 ps
CPU time 67.7 seconds
Started Apr 30 03:17:40 PM PDT 24
Finished Apr 30 03:18:49 PM PDT 24
Peak memory 200384 kb
Host smart-695a5b20-a6a5-4517-a8b5-065ecae887e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126560462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.126560462
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.1224510516
Short name T395
Test name
Test status
Simulation time 13168293 ps
CPU time 0.56 seconds
Started Apr 30 03:13:45 PM PDT 24
Finished Apr 30 03:13:46 PM PDT 24
Peak memory 195788 kb
Host smart-cc57b250-d9d2-4bf9-a50f-cddd242b5c80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224510516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.1224510516
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.1415856551
Short name T593
Test name
Test status
Simulation time 85006914880 ps
CPU time 67.51 seconds
Started Apr 30 03:13:38 PM PDT 24
Finished Apr 30 03:14:46 PM PDT 24
Peak memory 200316 kb
Host smart-7f2630d1-e5a8-4e03-814b-895b0ed10d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415856551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.1415856551
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.3873765626
Short name T993
Test name
Test status
Simulation time 107674027731 ps
CPU time 48.39 seconds
Started Apr 30 03:13:38 PM PDT 24
Finished Apr 30 03:14:27 PM PDT 24
Peak memory 200464 kb
Host smart-480c06ca-91fb-4144-9d33-29be980a4ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873765626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.3873765626
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.2218393633
Short name T685
Test name
Test status
Simulation time 35248876492 ps
CPU time 75.7 seconds
Started Apr 30 03:13:39 PM PDT 24
Finished Apr 30 03:14:55 PM PDT 24
Peak memory 200420 kb
Host smart-63aca714-5a94-4cef-bd78-552647b2f9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218393633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.2218393633
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.2859941255
Short name T897
Test name
Test status
Simulation time 52509739413 ps
CPU time 89.28 seconds
Started Apr 30 03:13:39 PM PDT 24
Finished Apr 30 03:15:09 PM PDT 24
Peak memory 200044 kb
Host smart-ee732456-a52a-403f-9a7d-10fc64256612
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859941255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.2859941255
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.422108039
Short name T639
Test name
Test status
Simulation time 294369981704 ps
CPU time 367.15 seconds
Started Apr 30 03:13:44 PM PDT 24
Finished Apr 30 03:19:51 PM PDT 24
Peak memory 200436 kb
Host smart-a1e09fa7-1020-40bf-ae22-076f9ea8c501
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=422108039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.422108039
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.897767305
Short name T1096
Test name
Test status
Simulation time 10719687974 ps
CPU time 10.29 seconds
Started Apr 30 03:13:45 PM PDT 24
Finished Apr 30 03:13:56 PM PDT 24
Peak memory 199884 kb
Host smart-3919c530-310e-4f78-aaa1-65cd21e2c001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897767305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.897767305
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.2476456930
Short name T413
Test name
Test status
Simulation time 7996296748 ps
CPU time 11.5 seconds
Started Apr 30 03:13:38 PM PDT 24
Finished Apr 30 03:13:51 PM PDT 24
Peak memory 196292 kb
Host smart-b6c6da92-e5eb-4376-8754-d2a7610e458b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476456930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.2476456930
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.1536348055
Short name T1031
Test name
Test status
Simulation time 13811996499 ps
CPU time 336.17 seconds
Started Apr 30 03:13:44 PM PDT 24
Finished Apr 30 03:19:21 PM PDT 24
Peak memory 200400 kb
Host smart-af51639f-0611-4e1b-877e-bad4f8124dc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1536348055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.1536348055
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.1799551663
Short name T867
Test name
Test status
Simulation time 2229075006 ps
CPU time 16.27 seconds
Started Apr 30 03:13:38 PM PDT 24
Finished Apr 30 03:13:55 PM PDT 24
Peak memory 199200 kb
Host smart-4e8bb175-a9ca-48b5-9f91-819c3341b3ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1799551663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.1799551663
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.1594561498
Short name T261
Test name
Test status
Simulation time 46858338361 ps
CPU time 45.02 seconds
Started Apr 30 03:13:46 PM PDT 24
Finished Apr 30 03:14:32 PM PDT 24
Peak memory 200460 kb
Host smart-3acaa691-355c-4f40-b77d-5a4d02c14c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594561498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.1594561498
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.688065917
Short name T433
Test name
Test status
Simulation time 6864241318 ps
CPU time 10.82 seconds
Started Apr 30 03:13:39 PM PDT 24
Finished Apr 30 03:13:51 PM PDT 24
Peak memory 196452 kb
Host smart-d8387210-e9a4-42c9-9f05-71c6366e586b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688065917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.688065917
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.178931575
Short name T743
Test name
Test status
Simulation time 676951578 ps
CPU time 2.22 seconds
Started Apr 30 03:13:45 PM PDT 24
Finished Apr 30 03:13:48 PM PDT 24
Peak memory 200224 kb
Host smart-d153c6e3-ffc1-441d-937b-101e5ed973fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178931575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.178931575
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.886815186
Short name T317
Test name
Test status
Simulation time 263596754329 ps
CPU time 384.39 seconds
Started Apr 30 03:13:44 PM PDT 24
Finished Apr 30 03:20:09 PM PDT 24
Peak memory 200420 kb
Host smart-e06f341c-44d1-4b52-a224-393e8597ffa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886815186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.886815186
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.952542519
Short name T751
Test name
Test status
Simulation time 74007156558 ps
CPU time 409.11 seconds
Started Apr 30 03:13:44 PM PDT 24
Finished Apr 30 03:20:34 PM PDT 24
Peak memory 216836 kb
Host smart-eb325426-e0b1-49b9-b5da-c34876386249
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952542519 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.952542519
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.1105231746
Short name T445
Test name
Test status
Simulation time 628094440 ps
CPU time 2.74 seconds
Started Apr 30 03:13:44 PM PDT 24
Finished Apr 30 03:13:48 PM PDT 24
Peak memory 198820 kb
Host smart-a59585e4-73aa-40a8-af9a-dd910419775d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105231746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.1105231746
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.2674863970
Short name T260
Test name
Test status
Simulation time 92426621105 ps
CPU time 213.19 seconds
Started Apr 30 03:13:38 PM PDT 24
Finished Apr 30 03:17:12 PM PDT 24
Peak memory 200404 kb
Host smart-5e310fb1-5757-4fc3-b56c-d2eb812d1e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674863970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.2674863970
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.2524163382
Short name T941
Test name
Test status
Simulation time 15483433453 ps
CPU time 26.11 seconds
Started Apr 30 03:17:32 PM PDT 24
Finished Apr 30 03:17:59 PM PDT 24
Peak memory 200380 kb
Host smart-c82fcdbc-5b35-4aba-9060-2f232cb933f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524163382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.2524163382
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.2616470713
Short name T975
Test name
Test status
Simulation time 99358573159 ps
CPU time 222.54 seconds
Started Apr 30 03:17:30 PM PDT 24
Finished Apr 30 03:21:13 PM PDT 24
Peak memory 200332 kb
Host smart-95930dd9-ee1a-4039-914a-12e61bfd5061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616470713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.2616470713
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.563271317
Short name T114
Test name
Test status
Simulation time 53247594891 ps
CPU time 23.57 seconds
Started Apr 30 03:17:42 PM PDT 24
Finished Apr 30 03:18:06 PM PDT 24
Peak memory 200428 kb
Host smart-8447286b-cc74-4588-be3a-dae73c3c5ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563271317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.563271317
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.2741259813
Short name T1164
Test name
Test status
Simulation time 26365235470 ps
CPU time 42.18 seconds
Started Apr 30 03:17:42 PM PDT 24
Finished Apr 30 03:18:25 PM PDT 24
Peak memory 200476 kb
Host smart-3aafd61f-c507-46a8-b4cc-cf33f0194028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741259813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.2741259813
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.2693118511
Short name T212
Test name
Test status
Simulation time 136666140347 ps
CPU time 128.43 seconds
Started Apr 30 03:17:41 PM PDT 24
Finished Apr 30 03:19:51 PM PDT 24
Peak memory 200320 kb
Host smart-028655e9-c596-4ae6-a4e5-dd1b90b3b464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693118511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.2693118511
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.1958057138
Short name T692
Test name
Test status
Simulation time 35692933452 ps
CPU time 41.7 seconds
Started Apr 30 03:17:39 PM PDT 24
Finished Apr 30 03:18:22 PM PDT 24
Peak memory 200428 kb
Host smart-eb482e47-4b16-4f09-8717-63f0fc5286df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958057138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.1958057138
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.3978465276
Short name T409
Test name
Test status
Simulation time 39096866722 ps
CPU time 64.58 seconds
Started Apr 30 03:17:38 PM PDT 24
Finished Apr 30 03:18:44 PM PDT 24
Peak memory 200440 kb
Host smart-11bd06c9-6d52-4682-8474-5a2c88fc2655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978465276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.3978465276
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.1630857931
Short name T660
Test name
Test status
Simulation time 37137062 ps
CPU time 0.53 seconds
Started Apr 30 03:13:53 PM PDT 24
Finished Apr 30 03:13:54 PM PDT 24
Peak memory 194772 kb
Host smart-e9fdc6aa-b521-4cb5-a2c9-ad26a33cef81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630857931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.1630857931
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.2539521969
Short name T570
Test name
Test status
Simulation time 53471343894 ps
CPU time 84.34 seconds
Started Apr 30 03:13:46 PM PDT 24
Finished Apr 30 03:15:11 PM PDT 24
Peak memory 200404 kb
Host smart-764493cc-99c3-48bf-9ed7-64b1408d7e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539521969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.2539521969
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.2091411252
Short name T1055
Test name
Test status
Simulation time 36807936918 ps
CPU time 52.69 seconds
Started Apr 30 03:13:44 PM PDT 24
Finished Apr 30 03:14:38 PM PDT 24
Peak memory 200204 kb
Host smart-06d40709-4c74-4ffe-a717-443c341fe91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091411252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.2091411252
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.2442932987
Short name T608
Test name
Test status
Simulation time 16058588494 ps
CPU time 13 seconds
Started Apr 30 03:13:44 PM PDT 24
Finished Apr 30 03:13:57 PM PDT 24
Peak memory 200320 kb
Host smart-01dba70f-9459-4471-b226-9e83c9fa5f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442932987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.2442932987
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.1247960252
Short name T1170
Test name
Test status
Simulation time 29597917072 ps
CPU time 16.42 seconds
Started Apr 30 03:13:44 PM PDT 24
Finished Apr 30 03:14:01 PM PDT 24
Peak memory 200380 kb
Host smart-448a5a82-861a-4c87-9dbf-06301b4f1730
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247960252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.1247960252
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.800117583
Short name T609
Test name
Test status
Simulation time 82147241123 ps
CPU time 312.04 seconds
Started Apr 30 03:13:52 PM PDT 24
Finished Apr 30 03:19:05 PM PDT 24
Peak memory 200408 kb
Host smart-454583b4-d5b7-4040-9c58-33733a43fef3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=800117583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.800117583
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.2215707012
Short name T1052
Test name
Test status
Simulation time 10568549091 ps
CPU time 19.3 seconds
Started Apr 30 03:13:51 PM PDT 24
Finished Apr 30 03:14:11 PM PDT 24
Peak memory 199616 kb
Host smart-a3bbe0fa-5a86-4837-8ad1-a6421b7cf73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215707012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.2215707012
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.2850807864
Short name T283
Test name
Test status
Simulation time 139226590047 ps
CPU time 96.94 seconds
Started Apr 30 03:13:45 PM PDT 24
Finished Apr 30 03:15:23 PM PDT 24
Peak memory 200564 kb
Host smart-9cd9c54b-acfa-467b-b947-7ee84ff09aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850807864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.2850807864
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.329759834
Short name T717
Test name
Test status
Simulation time 10548918370 ps
CPU time 562.04 seconds
Started Apr 30 03:13:54 PM PDT 24
Finished Apr 30 03:23:17 PM PDT 24
Peak memory 200388 kb
Host smart-6dd1816f-de2f-4323-99fd-023b7a6c3ea7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=329759834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.329759834
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.4182266915
Short name T556
Test name
Test status
Simulation time 7197668713 ps
CPU time 26.17 seconds
Started Apr 30 03:13:44 PM PDT 24
Finished Apr 30 03:14:11 PM PDT 24
Peak memory 199616 kb
Host smart-4552b916-e873-4f27-9814-3bcdb8d7fda8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4182266915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.4182266915
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.3478863128
Short name T477
Test name
Test status
Simulation time 123607831426 ps
CPU time 60.09 seconds
Started Apr 30 03:13:46 PM PDT 24
Finished Apr 30 03:14:47 PM PDT 24
Peak memory 200456 kb
Host smart-74578d40-ce71-499d-92e7-f881731943f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478863128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.3478863128
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.1195814199
Short name T416
Test name
Test status
Simulation time 4148037241 ps
CPU time 2.37 seconds
Started Apr 30 03:13:45 PM PDT 24
Finished Apr 30 03:13:48 PM PDT 24
Peak memory 196408 kb
Host smart-3f937063-cb16-463a-b27b-d189628f402c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195814199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.1195814199
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.601553001
Short name T636
Test name
Test status
Simulation time 728045904 ps
CPU time 1.39 seconds
Started Apr 30 03:13:44 PM PDT 24
Finished Apr 30 03:13:46 PM PDT 24
Peak memory 199760 kb
Host smart-f432697e-6e35-4b4d-a2e0-dbfa5f000563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601553001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.601553001
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.2871043008
Short name T123
Test name
Test status
Simulation time 310315653539 ps
CPU time 507.71 seconds
Started Apr 30 03:13:52 PM PDT 24
Finished Apr 30 03:22:20 PM PDT 24
Peak memory 208720 kb
Host smart-a88cfe7f-f235-4241-a8b0-5a2d5a89e73a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871043008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.2871043008
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.1839723619
Short name T820
Test name
Test status
Simulation time 108588131235 ps
CPU time 203.48 seconds
Started Apr 30 03:13:51 PM PDT 24
Finished Apr 30 03:17:16 PM PDT 24
Peak memory 208848 kb
Host smart-d6ca065f-9dd4-4848-a151-f18eda3a61be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839723619 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.1839723619
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.2310983383
Short name T545
Test name
Test status
Simulation time 646659450 ps
CPU time 1.91 seconds
Started Apr 30 03:13:46 PM PDT 24
Finished Apr 30 03:13:49 PM PDT 24
Peak memory 199288 kb
Host smart-8378474b-9556-434e-8046-1d2cb63661a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310983383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2310983383
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.20902093
Short name T649
Test name
Test status
Simulation time 48592956760 ps
CPU time 85.37 seconds
Started Apr 30 03:13:44 PM PDT 24
Finished Apr 30 03:15:10 PM PDT 24
Peak memory 200452 kb
Host smart-a2a699be-97e2-4131-a09c-05383efc1249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20902093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.20902093
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.2178451109
Short name T249
Test name
Test status
Simulation time 114845136401 ps
CPU time 53.54 seconds
Started Apr 30 03:17:40 PM PDT 24
Finished Apr 30 03:18:35 PM PDT 24
Peak memory 200432 kb
Host smart-0c5cf958-8965-4f54-8da3-721b7bbce9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178451109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2178451109
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.484544369
Short name T36
Test name
Test status
Simulation time 30916717860 ps
CPU time 56.52 seconds
Started Apr 30 03:17:39 PM PDT 24
Finished Apr 30 03:18:36 PM PDT 24
Peak memory 200436 kb
Host smart-eaedfc5d-a5ef-400a-9281-ff13e41a7760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484544369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.484544369
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.2646837099
Short name T720
Test name
Test status
Simulation time 31808105338 ps
CPU time 57.68 seconds
Started Apr 30 03:17:43 PM PDT 24
Finished Apr 30 03:18:41 PM PDT 24
Peak memory 200408 kb
Host smart-12f48f23-e9a3-453b-b0ec-dd3cf20b116a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646837099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.2646837099
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.1807479276
Short name T873
Test name
Test status
Simulation time 176644126523 ps
CPU time 81.6 seconds
Started Apr 30 03:17:41 PM PDT 24
Finished Apr 30 03:19:03 PM PDT 24
Peak memory 200608 kb
Host smart-fcb31045-6efe-495a-8aec-f89ede7aefe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807479276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.1807479276
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.2116759165
Short name T844
Test name
Test status
Simulation time 40752044862 ps
CPU time 19.05 seconds
Started Apr 30 03:17:39 PM PDT 24
Finished Apr 30 03:17:59 PM PDT 24
Peak memory 200316 kb
Host smart-d73d749a-08c8-42bf-ada6-5e0c702f497a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116759165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.2116759165
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.4042838366
Short name T230
Test name
Test status
Simulation time 34567906109 ps
CPU time 14.82 seconds
Started Apr 30 03:17:42 PM PDT 24
Finished Apr 30 03:17:58 PM PDT 24
Peak memory 200068 kb
Host smart-ddf33932-64f6-4f90-beab-7b485b67a3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042838366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.4042838366
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.491027100
Short name T1029
Test name
Test status
Simulation time 16658369 ps
CPU time 0.54 seconds
Started Apr 30 03:13:51 PM PDT 24
Finished Apr 30 03:13:53 PM PDT 24
Peak memory 195176 kb
Host smart-43f90d74-b451-43a6-8db6-f13e35cd773c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491027100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.491027100
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.807366378
Short name T618
Test name
Test status
Simulation time 63089959268 ps
CPU time 57.76 seconds
Started Apr 30 03:13:55 PM PDT 24
Finished Apr 30 03:14:54 PM PDT 24
Peak memory 200428 kb
Host smart-8cfa53a8-4d73-45aa-9115-cee246fc5453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807366378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.807366378
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.4018422637
Short name T185
Test name
Test status
Simulation time 152106356832 ps
CPU time 74.77 seconds
Started Apr 30 03:13:51 PM PDT 24
Finished Apr 30 03:15:06 PM PDT 24
Peak memory 200448 kb
Host smart-8b07cc3e-c2c9-4af1-90a1-df4c77ea6b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018422637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.4018422637
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.2062416749
Short name T1142
Test name
Test status
Simulation time 27390018896 ps
CPU time 50.79 seconds
Started Apr 30 03:13:51 PM PDT 24
Finished Apr 30 03:14:42 PM PDT 24
Peak memory 200328 kb
Host smart-cf839aa9-2309-4916-bff1-e6095118d891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062416749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.2062416749
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.1974984014
Short name T836
Test name
Test status
Simulation time 52150584751 ps
CPU time 49.49 seconds
Started Apr 30 03:13:51 PM PDT 24
Finished Apr 30 03:14:41 PM PDT 24
Peak memory 200300 kb
Host smart-90acfc93-c92c-4149-b14a-8d601c9e363d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974984014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.1974984014
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.3928021484
Short name T555
Test name
Test status
Simulation time 68541399777 ps
CPU time 304.65 seconds
Started Apr 30 03:13:58 PM PDT 24
Finished Apr 30 03:19:03 PM PDT 24
Peak memory 200388 kb
Host smart-31dd9383-4092-4154-b908-73ed47f0a12a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3928021484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.3928021484
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.287748994
Short name T780
Test name
Test status
Simulation time 6585397001 ps
CPU time 5.3 seconds
Started Apr 30 03:13:49 PM PDT 24
Finished Apr 30 03:13:55 PM PDT 24
Peak memory 199268 kb
Host smart-301d7165-6fc1-488a-9185-773a013817a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287748994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.287748994
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.473423576
Short name T497
Test name
Test status
Simulation time 57829980702 ps
CPU time 27.06 seconds
Started Apr 30 03:13:53 PM PDT 24
Finished Apr 30 03:14:20 PM PDT 24
Peak memory 199480 kb
Host smart-20d834f4-34fd-47bd-a34f-f9e066cfb7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473423576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.473423576
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.1788940830
Short name T494
Test name
Test status
Simulation time 18890587985 ps
CPU time 1070.25 seconds
Started Apr 30 03:13:53 PM PDT 24
Finished Apr 30 03:31:44 PM PDT 24
Peak memory 200404 kb
Host smart-f3bf5525-8d7c-4f1a-b19d-7960741b5f91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1788940830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.1788940830
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.1739589250
Short name T729
Test name
Test status
Simulation time 7404892430 ps
CPU time 7.53 seconds
Started Apr 30 03:13:52 PM PDT 24
Finished Apr 30 03:14:00 PM PDT 24
Peak memory 200400 kb
Host smart-2e754dd1-f36a-4cde-9268-be5a2abae6a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1739589250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.1739589250
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.3497451909
Short name T857
Test name
Test status
Simulation time 93890049867 ps
CPU time 152.9 seconds
Started Apr 30 03:13:52 PM PDT 24
Finished Apr 30 03:16:25 PM PDT 24
Peak memory 200432 kb
Host smart-8557b60b-20f6-4625-ae05-3cd08985b103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497451909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.3497451909
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.86324810
Short name T885
Test name
Test status
Simulation time 33494007900 ps
CPU time 21.98 seconds
Started Apr 30 03:13:52 PM PDT 24
Finished Apr 30 03:14:14 PM PDT 24
Peak memory 196464 kb
Host smart-1aefd9cf-0960-4688-91bf-ca3d0fc39f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86324810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.86324810
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.4253365584
Short name T838
Test name
Test status
Simulation time 5531052277 ps
CPU time 9.05 seconds
Started Apr 30 03:13:52 PM PDT 24
Finished Apr 30 03:14:02 PM PDT 24
Peak memory 200372 kb
Host smart-c186c0b0-6cb4-45ef-8ff0-0fdd2a6705c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253365584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.4253365584
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.3889244676
Short name T673
Test name
Test status
Simulation time 109964552924 ps
CPU time 186.17 seconds
Started Apr 30 03:13:54 PM PDT 24
Finished Apr 30 03:17:01 PM PDT 24
Peak memory 200440 kb
Host smart-ead17c72-4ef1-465d-a2b9-0b10840d697e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889244676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.3889244676
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.650635889
Short name T900
Test name
Test status
Simulation time 368343175248 ps
CPU time 986.73 seconds
Started Apr 30 03:13:51 PM PDT 24
Finished Apr 30 03:30:19 PM PDT 24
Peak memory 216768 kb
Host smart-c2069ac6-c717-4490-ac71-2696f3a26826
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650635889 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.650635889
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.2548683499
Short name T44
Test name
Test status
Simulation time 746486751 ps
CPU time 1.54 seconds
Started Apr 30 03:13:52 PM PDT 24
Finished Apr 30 03:13:54 PM PDT 24
Peak memory 198904 kb
Host smart-e7788db9-b8b6-4e1d-9283-1ce39a8b823f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548683499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.2548683499
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.3660459400
Short name T1104
Test name
Test status
Simulation time 76881227767 ps
CPU time 61.97 seconds
Started Apr 30 03:13:58 PM PDT 24
Finished Apr 30 03:15:01 PM PDT 24
Peak memory 200384 kb
Host smart-a0123545-ff9b-4c6e-81cd-2f7f9b4853fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660459400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.3660459400
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.1977717297
Short name T396
Test name
Test status
Simulation time 4360786328 ps
CPU time 7.8 seconds
Started Apr 30 03:17:41 PM PDT 24
Finished Apr 30 03:17:50 PM PDT 24
Peak memory 200160 kb
Host smart-671ba32d-b8fb-4f5a-b3eb-06eee3f012a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977717297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.1977717297
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.2606032627
Short name T568
Test name
Test status
Simulation time 116057059139 ps
CPU time 187.87 seconds
Started Apr 30 03:17:41 PM PDT 24
Finished Apr 30 03:20:49 PM PDT 24
Peak memory 200348 kb
Host smart-937e1c88-bc38-487d-94a6-4ca43983ddb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606032627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.2606032627
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.2779061347
Short name T939
Test name
Test status
Simulation time 91660525230 ps
CPU time 66.18 seconds
Started Apr 30 03:17:41 PM PDT 24
Finished Apr 30 03:18:47 PM PDT 24
Peak memory 200328 kb
Host smart-a742c60c-dacc-4d71-b749-774e952dc9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779061347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.2779061347
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.2731420605
Short name T280
Test name
Test status
Simulation time 51568962518 ps
CPU time 20.38 seconds
Started Apr 30 03:17:44 PM PDT 24
Finished Apr 30 03:18:05 PM PDT 24
Peak memory 200408 kb
Host smart-40ef652b-01f5-455e-b20e-0d523bc347eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731420605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.2731420605
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.1092613152
Short name T564
Test name
Test status
Simulation time 153758638512 ps
CPU time 73.03 seconds
Started Apr 30 03:17:39 PM PDT 24
Finished Apr 30 03:18:53 PM PDT 24
Peak memory 200364 kb
Host smart-59272027-e3cf-4624-9cde-e61bc4753062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092613152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.1092613152
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.3363844999
Short name T987
Test name
Test status
Simulation time 41637643007 ps
CPU time 24.9 seconds
Started Apr 30 03:17:40 PM PDT 24
Finished Apr 30 03:18:05 PM PDT 24
Peak memory 200200 kb
Host smart-2d3cdb6e-af85-4759-ab90-76a8ff3bbb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363844999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.3363844999
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.3925882348
Short name T447
Test name
Test status
Simulation time 136220164109 ps
CPU time 21.06 seconds
Started Apr 30 03:17:48 PM PDT 24
Finished Apr 30 03:18:10 PM PDT 24
Peak memory 200384 kb
Host smart-2cd9eecb-4027-4174-ba61-2312b32f6aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925882348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.3925882348
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.335420864
Short name T218
Test name
Test status
Simulation time 19742247192 ps
CPU time 36.49 seconds
Started Apr 30 03:17:47 PM PDT 24
Finished Apr 30 03:18:24 PM PDT 24
Peak memory 200400 kb
Host smart-da3dc778-2b78-44a8-819d-79af0d4d8286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335420864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.335420864
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.2273090036
Short name T510
Test name
Test status
Simulation time 59906501883 ps
CPU time 22.81 seconds
Started Apr 30 03:17:47 PM PDT 24
Finished Apr 30 03:18:10 PM PDT 24
Peak memory 200440 kb
Host smart-835cee19-5102-410e-90c6-d1d604190ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273090036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2273090036
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.186424115
Short name T1101
Test name
Test status
Simulation time 82056215239 ps
CPU time 41.72 seconds
Started Apr 30 03:17:47 PM PDT 24
Finished Apr 30 03:18:29 PM PDT 24
Peak memory 200472 kb
Host smart-8462dc28-cefb-42e1-aa33-08855dac8d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186424115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.186424115
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.1156935899
Short name T1177
Test name
Test status
Simulation time 42380789 ps
CPU time 0.55 seconds
Started Apr 30 03:13:57 PM PDT 24
Finished Apr 30 03:13:58 PM PDT 24
Peak memory 195824 kb
Host smart-1f957290-6c79-48ad-af35-c15959a4d109
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156935899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.1156935899
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.243263522
Short name T295
Test name
Test status
Simulation time 132142446842 ps
CPU time 101.01 seconds
Started Apr 30 03:13:58 PM PDT 24
Finished Apr 30 03:15:39 PM PDT 24
Peak memory 200316 kb
Host smart-5cff12c5-24ce-426f-8a3c-2fe4c0529486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243263522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.243263522
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.1673983246
Short name T1111
Test name
Test status
Simulation time 81608970991 ps
CPU time 31.24 seconds
Started Apr 30 03:14:00 PM PDT 24
Finished Apr 30 03:14:32 PM PDT 24
Peak memory 200244 kb
Host smart-61c65618-bf90-45d2-9acb-6a27d6d38067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673983246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.1673983246
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.1378447425
Short name T276
Test name
Test status
Simulation time 50002296370 ps
CPU time 18.72 seconds
Started Apr 30 03:14:01 PM PDT 24
Finished Apr 30 03:14:21 PM PDT 24
Peak memory 200444 kb
Host smart-5dcc45cf-8826-4c21-98a6-0be1816dea15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378447425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.1378447425
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.1285219320
Short name T655
Test name
Test status
Simulation time 40501184561 ps
CPU time 69.32 seconds
Started Apr 30 03:14:00 PM PDT 24
Finished Apr 30 03:15:10 PM PDT 24
Peak memory 200352 kb
Host smart-874d2b69-3308-44db-a862-f052a25abe06
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285219320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.1285219320
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.4258858445
Short name T915
Test name
Test status
Simulation time 104781095025 ps
CPU time 244.96 seconds
Started Apr 30 03:13:57 PM PDT 24
Finished Apr 30 03:18:03 PM PDT 24
Peak memory 200408 kb
Host smart-5da502c9-0698-4fe7-aa0d-e644b915cc7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4258858445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.4258858445
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.3885746113
Short name T19
Test name
Test status
Simulation time 2948733262 ps
CPU time 4.99 seconds
Started Apr 30 03:13:59 PM PDT 24
Finished Apr 30 03:14:04 PM PDT 24
Peak memory 196560 kb
Host smart-d2f5a89d-56f0-4ac5-a774-7e7628a8d202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885746113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.3885746113
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.3019757507
Short name T796
Test name
Test status
Simulation time 108517872600 ps
CPU time 267.22 seconds
Started Apr 30 03:14:00 PM PDT 24
Finished Apr 30 03:18:28 PM PDT 24
Peak memory 200620 kb
Host smart-538cb9d7-6b37-4b03-8ff0-6859390f0c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019757507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.3019757507
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.368404180
Short name T771
Test name
Test status
Simulation time 11626956611 ps
CPU time 177.99 seconds
Started Apr 30 03:13:58 PM PDT 24
Finished Apr 30 03:16:57 PM PDT 24
Peak memory 200352 kb
Host smart-ab203fb5-486d-4607-a8e6-f62c88a5bb4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=368404180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.368404180
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.48006572
Short name T1119
Test name
Test status
Simulation time 2566731064 ps
CPU time 3.66 seconds
Started Apr 30 03:14:05 PM PDT 24
Finished Apr 30 03:14:09 PM PDT 24
Peak memory 199500 kb
Host smart-81d27eca-398e-43a9-952e-0a06f88d939d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=48006572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.48006572
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.296928250
Short name T785
Test name
Test status
Simulation time 37383760759 ps
CPU time 16.42 seconds
Started Apr 30 03:13:59 PM PDT 24
Finished Apr 30 03:14:17 PM PDT 24
Peak memory 200452 kb
Host smart-cc7a07ca-ee3f-46a0-82ea-326505ba1b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296928250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.296928250
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.829513064
Short name T835
Test name
Test status
Simulation time 4612642387 ps
CPU time 7.74 seconds
Started Apr 30 03:13:58 PM PDT 24
Finished Apr 30 03:14:06 PM PDT 24
Peak memory 196452 kb
Host smart-927d1e49-aa88-4df0-a9dd-08ceb45a8f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829513064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.829513064
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.4029444052
Short name T412
Test name
Test status
Simulation time 973834045 ps
CPU time 1.62 seconds
Started Apr 30 03:13:52 PM PDT 24
Finished Apr 30 03:13:55 PM PDT 24
Peak memory 200236 kb
Host smart-40f4e8fa-a1de-4ebc-be9e-5f0fcb837edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029444052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.4029444052
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.1764085996
Short name T546
Test name
Test status
Simulation time 226162739218 ps
CPU time 727.16 seconds
Started Apr 30 03:13:57 PM PDT 24
Finished Apr 30 03:26:05 PM PDT 24
Peak memory 208844 kb
Host smart-f3bf6c99-c252-495e-b975-991d350f38de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764085996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.1764085996
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.1962759298
Short name T14
Test name
Test status
Simulation time 27992599176 ps
CPU time 330.17 seconds
Started Apr 30 03:13:59 PM PDT 24
Finished Apr 30 03:19:30 PM PDT 24
Peak memory 216876 kb
Host smart-4afff729-e401-43de-bd63-3f36097a2da8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962759298 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.1962759298
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.2285713789
Short name T764
Test name
Test status
Simulation time 752409963 ps
CPU time 3.29 seconds
Started Apr 30 03:13:58 PM PDT 24
Finished Apr 30 03:14:02 PM PDT 24
Peak memory 199260 kb
Host smart-a00f429d-b2f3-4bd0-80e6-b7a6acdd6706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285713789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.2285713789
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.4162936364
Short name T932
Test name
Test status
Simulation time 11269032276 ps
CPU time 14.42 seconds
Started Apr 30 03:13:55 PM PDT 24
Finished Apr 30 03:14:10 PM PDT 24
Peak memory 198024 kb
Host smart-8d0b972b-d891-4fc2-bbb3-1b097efec885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162936364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.4162936364
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.2624202118
Short name T812
Test name
Test status
Simulation time 106798361585 ps
CPU time 165.53 seconds
Started Apr 30 03:17:48 PM PDT 24
Finished Apr 30 03:20:34 PM PDT 24
Peak memory 200392 kb
Host smart-49d8caff-ea7e-4d0c-9b21-e5fa05bbf4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624202118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.2624202118
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.3188383426
Short name T1110
Test name
Test status
Simulation time 24706392805 ps
CPU time 22.61 seconds
Started Apr 30 03:17:48 PM PDT 24
Finished Apr 30 03:18:11 PM PDT 24
Peak memory 200440 kb
Host smart-9257acff-f053-4fef-b7d8-53bc7e87ddb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188383426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.3188383426
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.2758835358
Short name T1070
Test name
Test status
Simulation time 55002950479 ps
CPU time 25.93 seconds
Started Apr 30 03:17:48 PM PDT 24
Finished Apr 30 03:18:14 PM PDT 24
Peak memory 200432 kb
Host smart-ccdb5ae7-1e11-4216-b5b7-f8e0936ea67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758835358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2758835358
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.1532619908
Short name T963
Test name
Test status
Simulation time 214367046678 ps
CPU time 61.94 seconds
Started Apr 30 03:17:48 PM PDT 24
Finished Apr 30 03:18:50 PM PDT 24
Peak memory 199136 kb
Host smart-0df7fc5d-20f5-4d9f-a568-329ca7a7359a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532619908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.1532619908
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.256682598
Short name T554
Test name
Test status
Simulation time 166252636846 ps
CPU time 28.94 seconds
Started Apr 30 03:17:47 PM PDT 24
Finished Apr 30 03:18:17 PM PDT 24
Peak memory 200368 kb
Host smart-f24c993b-7c8e-4554-b4ad-921b840a8b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256682598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.256682598
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.3594370344
Short name T619
Test name
Test status
Simulation time 68223516789 ps
CPU time 29.7 seconds
Started Apr 30 03:17:48 PM PDT 24
Finished Apr 30 03:18:19 PM PDT 24
Peak memory 200336 kb
Host smart-c76c5a33-e596-4efe-b795-b9cb1310ebf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594370344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.3594370344
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.3986621025
Short name T916
Test name
Test status
Simulation time 263120738168 ps
CPU time 112.95 seconds
Started Apr 30 03:17:48 PM PDT 24
Finished Apr 30 03:19:41 PM PDT 24
Peak memory 200424 kb
Host smart-157b7488-3fc6-4e6e-bbc4-ba7a8f74daf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986621025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.3986621025
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.592035498
Short name T86
Test name
Test status
Simulation time 114932175046 ps
CPU time 49.36 seconds
Started Apr 30 03:17:47 PM PDT 24
Finished Apr 30 03:18:37 PM PDT 24
Peak memory 200308 kb
Host smart-4bbb12ea-d253-4d53-8f77-475682016636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592035498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.592035498
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.374253539
Short name T1152
Test name
Test status
Simulation time 118506151447 ps
CPU time 52.88 seconds
Started Apr 30 03:17:48 PM PDT 24
Finished Apr 30 03:18:42 PM PDT 24
Peak memory 200396 kb
Host smart-e3d4c1ab-d54f-434b-8024-3349b7e914ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374253539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.374253539
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.4137236180
Short name T983
Test name
Test status
Simulation time 11423307951 ps
CPU time 18.27 seconds
Started Apr 30 03:17:47 PM PDT 24
Finished Apr 30 03:18:06 PM PDT 24
Peak memory 200204 kb
Host smart-29b08a5d-6a77-43ca-b7de-94abacbe7192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137236180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.4137236180
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.4266202130
Short name T24
Test name
Test status
Simulation time 114520418 ps
CPU time 0.54 seconds
Started Apr 30 03:14:06 PM PDT 24
Finished Apr 30 03:14:07 PM PDT 24
Peak memory 195848 kb
Host smart-efa1699f-4745-488e-8757-6be661bc8ecc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266202130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.4266202130
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.2284192105
Short name T1136
Test name
Test status
Simulation time 28920768347 ps
CPU time 11.58 seconds
Started Apr 30 03:13:59 PM PDT 24
Finished Apr 30 03:14:11 PM PDT 24
Peak memory 200452 kb
Host smart-8819e7b5-8050-4fb4-bdad-feeeaf045cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284192105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.2284192105
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.1747030524
Short name T931
Test name
Test status
Simulation time 74444735664 ps
CPU time 242 seconds
Started Apr 30 03:14:02 PM PDT 24
Finished Apr 30 03:18:04 PM PDT 24
Peak memory 200032 kb
Host smart-47573068-32b9-4054-82e3-3d414dce111c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747030524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.1747030524
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.1817655117
Short name T256
Test name
Test status
Simulation time 206455303028 ps
CPU time 123.91 seconds
Started Apr 30 03:14:06 PM PDT 24
Finished Apr 30 03:16:10 PM PDT 24
Peak memory 200444 kb
Host smart-1e0f90a7-a562-49f4-9270-805d2406d641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817655117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.1817655117
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.1532676680
Short name T1116
Test name
Test status
Simulation time 13491358291 ps
CPU time 11.41 seconds
Started Apr 30 03:14:09 PM PDT 24
Finished Apr 30 03:14:21 PM PDT 24
Peak memory 197312 kb
Host smart-8e7badbb-6bc0-4f8c-b7fa-0d6b54c4055a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532676680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1532676680
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.1139356477
Short name T1071
Test name
Test status
Simulation time 115281149396 ps
CPU time 146.67 seconds
Started Apr 30 03:14:08 PM PDT 24
Finished Apr 30 03:16:35 PM PDT 24
Peak memory 200432 kb
Host smart-b03d9fd7-9294-4170-94e0-339072e5e559
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1139356477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.1139356477
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.2951808266
Short name T397
Test name
Test status
Simulation time 11936806523 ps
CPU time 34.61 seconds
Started Apr 30 03:14:05 PM PDT 24
Finished Apr 30 03:14:40 PM PDT 24
Peak memory 200156 kb
Host smart-79b4a118-4895-444f-99b3-26e02c01a308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951808266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.2951808266
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.271513197
Short name T382
Test name
Test status
Simulation time 10612848556 ps
CPU time 17.54 seconds
Started Apr 30 03:14:07 PM PDT 24
Finished Apr 30 03:14:25 PM PDT 24
Peak memory 200496 kb
Host smart-658ce86d-8136-47f8-9777-e0f2dd6b9218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271513197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.271513197
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.3956147734
Short name T318
Test name
Test status
Simulation time 11491171773 ps
CPU time 162.96 seconds
Started Apr 30 03:14:05 PM PDT 24
Finished Apr 30 03:16:48 PM PDT 24
Peak memory 200400 kb
Host smart-d57cc3e4-f79c-4761-8b6d-83dbd61ec831
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3956147734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.3956147734
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.2451519367
Short name T768
Test name
Test status
Simulation time 4537036411 ps
CPU time 36.27 seconds
Started Apr 30 03:14:05 PM PDT 24
Finished Apr 30 03:14:42 PM PDT 24
Peak memory 198588 kb
Host smart-3ff62c71-c903-4df3-82bb-fdcc69917a05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2451519367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.2451519367
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.1855226980
Short name T472
Test name
Test status
Simulation time 42388174955 ps
CPU time 42.37 seconds
Started Apr 30 03:14:08 PM PDT 24
Finished Apr 30 03:14:51 PM PDT 24
Peak memory 200452 kb
Host smart-e8b9fd77-11b3-470b-b235-9d285fbc2369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855226980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1855226980
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.1487552076
Short name T606
Test name
Test status
Simulation time 5012540530 ps
CPU time 1.77 seconds
Started Apr 30 03:14:10 PM PDT 24
Finished Apr 30 03:14:12 PM PDT 24
Peak memory 196452 kb
Host smart-43fcc375-bd2c-4f2a-a889-346caef8432c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487552076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.1487552076
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.1664361485
Short name T708
Test name
Test status
Simulation time 450222132 ps
CPU time 2.41 seconds
Started Apr 30 03:14:01 PM PDT 24
Finished Apr 30 03:14:04 PM PDT 24
Peak memory 199184 kb
Host smart-f982f161-4a37-427f-8586-6fc5138ed491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664361485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1664361485
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.1970155885
Short name T989
Test name
Test status
Simulation time 292055258066 ps
CPU time 116.58 seconds
Started Apr 30 03:14:06 PM PDT 24
Finished Apr 30 03:16:03 PM PDT 24
Peak memory 200392 kb
Host smart-4651d6d9-2482-458e-9d03-53504fe4127d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970155885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.1970155885
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.2235775567
Short name T1108
Test name
Test status
Simulation time 13399798114 ps
CPU time 114.3 seconds
Started Apr 30 03:14:07 PM PDT 24
Finished Apr 30 03:16:02 PM PDT 24
Peak memory 208676 kb
Host smart-56393a2e-7ad9-4243-abee-16718e4153e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235775567 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.2235775567
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.2635922515
Short name T297
Test name
Test status
Simulation time 6431043524 ps
CPU time 18.65 seconds
Started Apr 30 03:14:04 PM PDT 24
Finished Apr 30 03:14:24 PM PDT 24
Peak memory 200160 kb
Host smart-e00f62f8-2f04-45ff-bcbb-3f312a27e362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635922515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.2635922515
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.675513566
Short name T670
Test name
Test status
Simulation time 6838785813 ps
CPU time 3.24 seconds
Started Apr 30 03:14:00 PM PDT 24
Finished Apr 30 03:14:04 PM PDT 24
Peak memory 199100 kb
Host smart-486e088e-0071-4fcc-a16a-71b5b6d4fa30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675513566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.675513566
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.2911254309
Short name T336
Test name
Test status
Simulation time 37375312258 ps
CPU time 33.6 seconds
Started Apr 30 03:17:48 PM PDT 24
Finished Apr 30 03:18:22 PM PDT 24
Peak memory 200428 kb
Host smart-5073a5f4-b53f-43ce-acc8-01868cc8dace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911254309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.2911254309
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1347476953
Short name T238
Test name
Test status
Simulation time 187051616052 ps
CPU time 28.64 seconds
Started Apr 30 03:17:49 PM PDT 24
Finished Apr 30 03:18:18 PM PDT 24
Peak memory 200440 kb
Host smart-93375a8c-2234-4c05-866c-e7d292363eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347476953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1347476953
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.3815261050
Short name T697
Test name
Test status
Simulation time 63137066154 ps
CPU time 73.15 seconds
Started Apr 30 03:17:49 PM PDT 24
Finished Apr 30 03:19:02 PM PDT 24
Peak memory 200440 kb
Host smart-c75666c2-2a51-4bd8-b883-7cae1bbb2625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815261050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.3815261050
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.732073633
Short name T822
Test name
Test status
Simulation time 50789594146 ps
CPU time 46.34 seconds
Started Apr 30 03:17:47 PM PDT 24
Finished Apr 30 03:18:34 PM PDT 24
Peak memory 200320 kb
Host smart-5d78b028-645b-45c1-ab05-58f50f924f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732073633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.732073633
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.2642552594
Short name T194
Test name
Test status
Simulation time 103225076467 ps
CPU time 63.88 seconds
Started Apr 30 03:17:48 PM PDT 24
Finished Apr 30 03:18:53 PM PDT 24
Peak memory 200440 kb
Host smart-bf3fddca-b1ec-4aca-ab8f-5f20a572f9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642552594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2642552594
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.3852836448
Short name T803
Test name
Test status
Simulation time 196542065400 ps
CPU time 31.4 seconds
Started Apr 30 03:17:51 PM PDT 24
Finished Apr 30 03:18:23 PM PDT 24
Peak memory 200312 kb
Host smart-21090a95-f9d9-4f8a-b1b1-cc200702958b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852836448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.3852836448
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.1050070625
Short name T783
Test name
Test status
Simulation time 75876582675 ps
CPU time 81.99 seconds
Started Apr 30 03:17:48 PM PDT 24
Finished Apr 30 03:19:11 PM PDT 24
Peak memory 200428 kb
Host smart-5971e0b6-e637-4caf-8bbb-5593549b2174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050070625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.1050070625
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.1149798172
Short name T723
Test name
Test status
Simulation time 41075295891 ps
CPU time 60.94 seconds
Started Apr 30 03:17:49 PM PDT 24
Finished Apr 30 03:18:51 PM PDT 24
Peak memory 200420 kb
Host smart-9b469f13-c4c5-48eb-8cc8-86a8122a70a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149798172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1149798172
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.1256258115
Short name T837
Test name
Test status
Simulation time 75179469454 ps
CPU time 88.61 seconds
Started Apr 30 03:17:48 PM PDT 24
Finished Apr 30 03:19:17 PM PDT 24
Peak memory 200416 kb
Host smart-cf750b1f-c8b0-42a8-8f03-b7fb75e19c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256258115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.1256258115
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.3314805798
Short name T804
Test name
Test status
Simulation time 15606455 ps
CPU time 0.55 seconds
Started Apr 30 03:11:20 PM PDT 24
Finished Apr 30 03:11:21 PM PDT 24
Peak memory 195780 kb
Host smart-d2bd6426-3b07-4697-b157-d48f4a100ced
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314805798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.3314805798
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.910429568
Short name T851
Test name
Test status
Simulation time 147851293183 ps
CPU time 242.29 seconds
Started Apr 30 03:11:14 PM PDT 24
Finished Apr 30 03:15:17 PM PDT 24
Peak memory 200428 kb
Host smart-0b6f527f-e272-430f-9227-4d513caf0d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910429568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.910429568
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.1349917343
Short name T228
Test name
Test status
Simulation time 24509535657 ps
CPU time 13.99 seconds
Started Apr 30 03:11:14 PM PDT 24
Finished Apr 30 03:11:29 PM PDT 24
Peak memory 200356 kb
Host smart-6087994e-88a5-4112-8028-3467aeedaf91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349917343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.1349917343
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.3111022885
Short name T1090
Test name
Test status
Simulation time 61701482662 ps
CPU time 44.93 seconds
Started Apr 30 03:11:18 PM PDT 24
Finished Apr 30 03:12:03 PM PDT 24
Peak memory 200352 kb
Host smart-88c6c18a-2076-442e-8f24-5f9ab2866947
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111022885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.3111022885
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.1356762249
Short name T742
Test name
Test status
Simulation time 106102572456 ps
CPU time 501 seconds
Started Apr 30 03:11:22 PM PDT 24
Finished Apr 30 03:19:44 PM PDT 24
Peak memory 200396 kb
Host smart-d28d8f75-1795-4b31-b428-ec19b520a5f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1356762249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.1356762249
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.3958194275
Short name T357
Test name
Test status
Simulation time 3468106593 ps
CPU time 7.2 seconds
Started Apr 30 03:11:13 PM PDT 24
Finished Apr 30 03:11:21 PM PDT 24
Peak memory 198128 kb
Host smart-53521091-f551-46bf-8228-707738a7235f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958194275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.3958194275
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.261704408
Short name T449
Test name
Test status
Simulation time 60698221960 ps
CPU time 54.52 seconds
Started Apr 30 03:11:13 PM PDT 24
Finished Apr 30 03:12:08 PM PDT 24
Peak memory 200540 kb
Host smart-21d681f6-ac0e-4c9e-b0aa-0593d988349f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261704408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.261704408
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.3673454084
Short name T1175
Test name
Test status
Simulation time 32875480640 ps
CPU time 1046.85 seconds
Started Apr 30 03:11:14 PM PDT 24
Finished Apr 30 03:28:41 PM PDT 24
Peak memory 200424 kb
Host smart-2b4757f8-92df-4bee-b415-726e92241f7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3673454084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.3673454084
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.1004582967
Short name T453
Test name
Test status
Simulation time 4285882266 ps
CPU time 7.82 seconds
Started Apr 30 03:11:19 PM PDT 24
Finished Apr 30 03:11:27 PM PDT 24
Peak memory 199324 kb
Host smart-199290ad-4d7d-4c5e-a460-bea8b04ca0a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1004582967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.1004582967
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.3008546191
Short name T163
Test name
Test status
Simulation time 115822546227 ps
CPU time 176.22 seconds
Started Apr 30 03:11:13 PM PDT 24
Finished Apr 30 03:14:10 PM PDT 24
Peak memory 200400 kb
Host smart-02df4327-9f05-40ca-ae43-2f5c6b9c872d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008546191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.3008546191
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.275921221
Short name T1007
Test name
Test status
Simulation time 1385678714 ps
CPU time 2.77 seconds
Started Apr 30 03:11:14 PM PDT 24
Finished Apr 30 03:11:18 PM PDT 24
Peak memory 196060 kb
Host smart-bda117e0-8cd9-4553-bca3-0006ca6ffa7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275921221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.275921221
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.1449824413
Short name T27
Test name
Test status
Simulation time 160132784 ps
CPU time 0.77 seconds
Started Apr 30 03:11:20 PM PDT 24
Finished Apr 30 03:11:21 PM PDT 24
Peak memory 218728 kb
Host smart-1f7d9741-4713-4e1e-b26b-cd6ce0ac69f4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449824413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.1449824413
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.1989298148
Short name T848
Test name
Test status
Simulation time 530077292 ps
CPU time 2.72 seconds
Started Apr 30 03:11:12 PM PDT 24
Finished Apr 30 03:11:15 PM PDT 24
Peak memory 199204 kb
Host smart-9af25a69-a894-435d-aa0f-2d5e99057447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989298148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.1989298148
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.969254745
Short name T222
Test name
Test status
Simulation time 375008091289 ps
CPU time 604.36 seconds
Started Apr 30 03:11:19 PM PDT 24
Finished Apr 30 03:21:24 PM PDT 24
Peak memory 200408 kb
Host smart-c90f5e7e-0edf-4e4d-b3e4-05852684fb90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969254745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.969254745
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.157247566
Short name T874
Test name
Test status
Simulation time 63942434733 ps
CPU time 560.88 seconds
Started Apr 30 03:11:22 PM PDT 24
Finished Apr 30 03:20:43 PM PDT 24
Peak memory 216768 kb
Host smart-efd91d1a-6d13-405c-b86b-57e00165d9cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157247566 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.157247566
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.337102422
Short name T990
Test name
Test status
Simulation time 8363886150 ps
CPU time 12.75 seconds
Started Apr 30 03:11:14 PM PDT 24
Finished Apr 30 03:11:27 PM PDT 24
Peak memory 199376 kb
Host smart-10748a5f-4ed3-410a-8be5-15415aaf83e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337102422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.337102422
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.1276415891
Short name T659
Test name
Test status
Simulation time 140634900847 ps
CPU time 54.76 seconds
Started Apr 30 03:11:13 PM PDT 24
Finished Apr 30 03:12:08 PM PDT 24
Peak memory 200400 kb
Host smart-aebf1bb6-2466-43ec-b2a4-59bc0eafce37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276415891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.1276415891
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.424267377
Short name T23
Test name
Test status
Simulation time 14801848 ps
CPU time 0.57 seconds
Started Apr 30 03:14:12 PM PDT 24
Finished Apr 30 03:14:13 PM PDT 24
Peak memory 195804 kb
Host smart-6d378fc4-1ded-43fa-85e2-3f9c90c5cf5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424267377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.424267377
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.2230992258
Short name T1143
Test name
Test status
Simulation time 229137036996 ps
CPU time 489.09 seconds
Started Apr 30 03:14:12 PM PDT 24
Finished Apr 30 03:22:21 PM PDT 24
Peak memory 200388 kb
Host smart-cae1bd10-1483-442f-8c94-385dcc738aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230992258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.2230992258
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.4203649913
Short name T151
Test name
Test status
Simulation time 73903469033 ps
CPU time 42.01 seconds
Started Apr 30 03:14:10 PM PDT 24
Finished Apr 30 03:14:53 PM PDT 24
Peak memory 200308 kb
Host smart-ea23e8dc-eb4d-4843-9aa3-443cd34473de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203649913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.4203649913
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.3421608714
Short name T235
Test name
Test status
Simulation time 96109684096 ps
CPU time 85.54 seconds
Started Apr 30 03:14:13 PM PDT 24
Finished Apr 30 03:15:39 PM PDT 24
Peak memory 200416 kb
Host smart-077b7f94-2652-4254-bc65-47f7921ad237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421608714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3421608714
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.3931582463
Short name T18
Test name
Test status
Simulation time 75955900198 ps
CPU time 22.23 seconds
Started Apr 30 03:14:11 PM PDT 24
Finished Apr 30 03:14:34 PM PDT 24
Peak memory 200188 kb
Host smart-e74cebd5-c594-4238-b168-3db74c241127
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931582463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.3931582463
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_loopback.1888068724
Short name T1182
Test name
Test status
Simulation time 10114600487 ps
CPU time 22.74 seconds
Started Apr 30 03:14:13 PM PDT 24
Finished Apr 30 03:14:36 PM PDT 24
Peak memory 199512 kb
Host smart-29181ecb-cf4f-4980-af0d-9791d792f816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888068724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1888068724
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.1820332656
Short name T831
Test name
Test status
Simulation time 91488022655 ps
CPU time 76.74 seconds
Started Apr 30 03:14:11 PM PDT 24
Finished Apr 30 03:15:29 PM PDT 24
Peak memory 200520 kb
Host smart-d73ca778-b305-4fe2-9084-e5e380ca68df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820332656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.1820332656
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.3740498382
Short name T1174
Test name
Test status
Simulation time 28412513583 ps
CPU time 673.01 seconds
Started Apr 30 03:14:12 PM PDT 24
Finished Apr 30 03:25:25 PM PDT 24
Peak memory 200632 kb
Host smart-b631cd74-605d-4b3a-987e-3b93eda80d4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3740498382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.3740498382
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.387303122
Short name T507
Test name
Test status
Simulation time 2137430723 ps
CPU time 3.41 seconds
Started Apr 30 03:14:13 PM PDT 24
Finished Apr 30 03:14:17 PM PDT 24
Peak memory 198484 kb
Host smart-6489dd77-a39a-457b-905a-3fc20371108b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=387303122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.387303122
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.2880328512
Short name T389
Test name
Test status
Simulation time 9962248277 ps
CPU time 18.38 seconds
Started Apr 30 03:14:14 PM PDT 24
Finished Apr 30 03:14:32 PM PDT 24
Peak memory 200404 kb
Host smart-ca34a3a5-db58-4191-8c37-fbcaf35890e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880328512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.2880328512
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.1430662427
Short name T359
Test name
Test status
Simulation time 4227396983 ps
CPU time 7.92 seconds
Started Apr 30 03:14:12 PM PDT 24
Finished Apr 30 03:14:21 PM PDT 24
Peak memory 196452 kb
Host smart-c6b8daf7-cd5a-4361-bbf5-61e6e985c37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430662427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.1430662427
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.1834205114
Short name T776
Test name
Test status
Simulation time 457290263 ps
CPU time 1.84 seconds
Started Apr 30 03:14:05 PM PDT 24
Finished Apr 30 03:14:07 PM PDT 24
Peak memory 200328 kb
Host smart-c1399bcb-feee-4840-afe0-d54272abb0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834205114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.1834205114
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.2086365736
Short name T1023
Test name
Test status
Simulation time 130153739155 ps
CPU time 62.89 seconds
Started Apr 30 03:14:12 PM PDT 24
Finished Apr 30 03:15:15 PM PDT 24
Peak memory 200568 kb
Host smart-e837915c-7947-4a13-a74b-00babe5fd006
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086365736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.2086365736
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.493524866
Short name T217
Test name
Test status
Simulation time 197775740170 ps
CPU time 609.45 seconds
Started Apr 30 03:14:13 PM PDT 24
Finished Apr 30 03:24:23 PM PDT 24
Peak memory 216924 kb
Host smart-82099e5a-fd53-4a97-9c86-21a939aceab7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493524866 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.493524866
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.1782317830
Short name T739
Test name
Test status
Simulation time 7621003979 ps
CPU time 7.95 seconds
Started Apr 30 03:14:12 PM PDT 24
Finished Apr 30 03:14:21 PM PDT 24
Peak memory 200112 kb
Host smart-85143b01-e605-4ca1-a93b-a659e1aab61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782317830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.1782317830
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.325658899
Short name T1112
Test name
Test status
Simulation time 60338455754 ps
CPU time 32.72 seconds
Started Apr 30 03:14:14 PM PDT 24
Finished Apr 30 03:14:48 PM PDT 24
Peak memory 200428 kb
Host smart-3dfd91d0-5430-4f15-beb1-c9f37344f286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325658899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.325658899
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.1382041650
Short name T399
Test name
Test status
Simulation time 15333261 ps
CPU time 0.58 seconds
Started Apr 30 03:14:20 PM PDT 24
Finished Apr 30 03:14:21 PM PDT 24
Peak memory 195804 kb
Host smart-85b0872b-86fd-44df-8f48-d269e127663b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382041650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.1382041650
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.1145285788
Short name T914
Test name
Test status
Simulation time 18418853429 ps
CPU time 34.1 seconds
Started Apr 30 03:14:13 PM PDT 24
Finished Apr 30 03:14:47 PM PDT 24
Peak memory 200396 kb
Host smart-eb34cd93-6a7b-4156-8925-c0c04d2792e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145285788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.1145285788
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.326827227
Short name T147
Test name
Test status
Simulation time 38295518514 ps
CPU time 25.41 seconds
Started Apr 30 03:14:15 PM PDT 24
Finished Apr 30 03:14:41 PM PDT 24
Peak memory 200464 kb
Host smart-e7a5c316-ea21-4023-80fc-2c0d0a1303a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326827227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.326827227
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.373372465
Short name T178
Test name
Test status
Simulation time 252085808637 ps
CPU time 26.18 seconds
Started Apr 30 03:14:14 PM PDT 24
Finished Apr 30 03:14:41 PM PDT 24
Peak memory 200416 kb
Host smart-f4d86dcf-199c-46fe-824b-a32b994bd004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373372465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.373372465
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.3968839784
Short name T372
Test name
Test status
Simulation time 43883742801 ps
CPU time 22.95 seconds
Started Apr 30 03:14:20 PM PDT 24
Finished Apr 30 03:14:43 PM PDT 24
Peak memory 200352 kb
Host smart-6e86f25a-0238-4dc9-841c-b6da47e88e09
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968839784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.3968839784
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.2844286639
Short name T1046
Test name
Test status
Simulation time 182385306386 ps
CPU time 232.08 seconds
Started Apr 30 03:14:20 PM PDT 24
Finished Apr 30 03:18:13 PM PDT 24
Peak memory 200396 kb
Host smart-552e0059-4a8f-40b2-9d63-78835fe91aa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2844286639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.2844286639
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.1360460504
Short name T604
Test name
Test status
Simulation time 5391862654 ps
CPU time 17.51 seconds
Started Apr 30 03:14:25 PM PDT 24
Finished Apr 30 03:14:43 PM PDT 24
Peak memory 200336 kb
Host smart-3d1a7622-8c3e-494b-b882-34cb72322b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360460504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.1360460504
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.1151510650
Short name T643
Test name
Test status
Simulation time 85495858322 ps
CPU time 176.62 seconds
Started Apr 30 03:14:25 PM PDT 24
Finished Apr 30 03:17:22 PM PDT 24
Peak memory 200652 kb
Host smart-00860b4e-1986-4dc2-9598-787e8930f8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151510650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.1151510650
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.1529358126
Short name T1134
Test name
Test status
Simulation time 11133111464 ps
CPU time 279.87 seconds
Started Apr 30 03:14:25 PM PDT 24
Finished Apr 30 03:19:05 PM PDT 24
Peak memory 200416 kb
Host smart-d66bf183-3798-4831-947e-8c3170eef839
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1529358126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.1529358126
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.3239796765
Short name T373
Test name
Test status
Simulation time 2044518955 ps
CPU time 2.78 seconds
Started Apr 30 03:14:13 PM PDT 24
Finished Apr 30 03:14:16 PM PDT 24
Peak memory 198480 kb
Host smart-7b040310-10ca-468d-845b-237b5a4f0f72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3239796765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.3239796765
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.4148556376
Short name T965
Test name
Test status
Simulation time 76838634262 ps
CPU time 28.78 seconds
Started Apr 30 03:14:23 PM PDT 24
Finished Apr 30 03:14:52 PM PDT 24
Peak memory 200300 kb
Host smart-144888e5-dd50-466d-8ad1-0a4341a948f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148556376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.4148556376
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.1453003217
Short name T581
Test name
Test status
Simulation time 4613339176 ps
CPU time 2.27 seconds
Started Apr 30 03:14:21 PM PDT 24
Finished Apr 30 03:14:24 PM PDT 24
Peak memory 196376 kb
Host smart-26d31c1b-6c9a-44ea-a6fc-589a4dd6a469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453003217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.1453003217
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.1025325254
Short name T884
Test name
Test status
Simulation time 872061136 ps
CPU time 1.24 seconds
Started Apr 30 03:14:11 PM PDT 24
Finished Apr 30 03:14:12 PM PDT 24
Peak memory 198860 kb
Host smart-4eb6c7ed-16e6-471d-b74d-0ff578fc9096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025325254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.1025325254
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.3515876276
Short name T842
Test name
Test status
Simulation time 201150695200 ps
CPU time 98.45 seconds
Started Apr 30 03:14:22 PM PDT 24
Finished Apr 30 03:16:01 PM PDT 24
Peak memory 217036 kb
Host smart-c18a81cd-7605-4898-9be3-e061b3b1ba04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515876276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.3515876276
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.3956552378
Short name T1181
Test name
Test status
Simulation time 34956960029 ps
CPU time 220.34 seconds
Started Apr 30 03:14:21 PM PDT 24
Finished Apr 30 03:18:02 PM PDT 24
Peak memory 216264 kb
Host smart-da3f12e8-84d4-48ca-9265-cb5a40caaf49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956552378 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.3956552378
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1143810981
Short name T441
Test name
Test status
Simulation time 12714749603 ps
CPU time 17.33 seconds
Started Apr 30 03:14:21 PM PDT 24
Finished Apr 30 03:14:38 PM PDT 24
Peak memory 200316 kb
Host smart-ee961bc5-b8af-4825-89f4-727a7a4210c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143810981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1143810981
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.3580965723
Short name T827
Test name
Test status
Simulation time 16167520763 ps
CPU time 7.44 seconds
Started Apr 30 03:14:12 PM PDT 24
Finished Apr 30 03:14:20 PM PDT 24
Peak memory 198028 kb
Host smart-010930db-a3a2-414e-880d-89470d78c7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580965723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.3580965723
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.3035107663
Short name T406
Test name
Test status
Simulation time 23383328 ps
CPU time 0.55 seconds
Started Apr 30 03:14:28 PM PDT 24
Finished Apr 30 03:14:30 PM PDT 24
Peak memory 195796 kb
Host smart-5258d0f3-8576-4d87-8b71-43b119c88e34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035107663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.3035107663
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.1645995990
Short name T633
Test name
Test status
Simulation time 83385162238 ps
CPU time 68.77 seconds
Started Apr 30 03:14:26 PM PDT 24
Finished Apr 30 03:15:35 PM PDT 24
Peak memory 200424 kb
Host smart-06fc7d9c-60dd-4f3d-aa54-d1dc834364be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645995990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.1645995990
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.2491425910
Short name T1102
Test name
Test status
Simulation time 28222224057 ps
CPU time 24.8 seconds
Started Apr 30 03:14:23 PM PDT 24
Finished Apr 30 03:14:49 PM PDT 24
Peak memory 200276 kb
Host smart-b7a20580-509f-46f2-b0df-edd7a05c0d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491425910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2491425910
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.2944371303
Short name T947
Test name
Test status
Simulation time 17061937830 ps
CPU time 23.68 seconds
Started Apr 30 03:14:21 PM PDT 24
Finished Apr 30 03:14:45 PM PDT 24
Peak memory 200360 kb
Host smart-409fad03-8151-40a7-a303-fe6254bbbad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944371303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.2944371303
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.764292627
Short name T962
Test name
Test status
Simulation time 8841667598 ps
CPU time 5.62 seconds
Started Apr 30 03:14:25 PM PDT 24
Finished Apr 30 03:14:31 PM PDT 24
Peak memory 200360 kb
Host smart-180192e2-4c3a-4ab8-9ade-c1c7ebea3374
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764292627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.764292627
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.2499759733
Short name T1154
Test name
Test status
Simulation time 78433670159 ps
CPU time 321.65 seconds
Started Apr 30 03:14:25 PM PDT 24
Finished Apr 30 03:19:47 PM PDT 24
Peak memory 200360 kb
Host smart-8ab6f972-430c-4c94-8306-93b9884c96a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2499759733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.2499759733
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.673786442
Short name T1072
Test name
Test status
Simulation time 1905739259 ps
CPU time 1.56 seconds
Started Apr 30 03:14:19 PM PDT 24
Finished Apr 30 03:14:21 PM PDT 24
Peak memory 198176 kb
Host smart-eca08d1f-51ae-4846-b19a-a6a8a269e6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673786442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.673786442
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.1565434958
Short name T375
Test name
Test status
Simulation time 30952765442 ps
CPU time 29.56 seconds
Started Apr 30 03:14:24 PM PDT 24
Finished Apr 30 03:14:54 PM PDT 24
Peak memory 200612 kb
Host smart-55934899-fc0b-4c4f-be18-56651077a426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565434958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.1565434958
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.249959488
Short name T498
Test name
Test status
Simulation time 3028036397 ps
CPU time 78.59 seconds
Started Apr 30 03:14:26 PM PDT 24
Finished Apr 30 03:15:45 PM PDT 24
Peak memory 200416 kb
Host smart-dc91b95c-2581-4b27-9975-710c514c40c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=249959488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.249959488
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.471733084
Short name T908
Test name
Test status
Simulation time 4407963461 ps
CPU time 18.48 seconds
Started Apr 30 03:14:23 PM PDT 24
Finished Apr 30 03:14:42 PM PDT 24
Peak memory 199500 kb
Host smart-38da19be-914c-4e0e-ada6-89f7ec3e673f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=471733084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.471733084
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.721092693
Short name T1109
Test name
Test status
Simulation time 22881719123 ps
CPU time 24 seconds
Started Apr 30 03:14:25 PM PDT 24
Finished Apr 30 03:14:50 PM PDT 24
Peak memory 200432 kb
Host smart-c036da67-1972-4aa6-a3c5-03574ad5c148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721092693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.721092693
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.3745918181
Short name T531
Test name
Test status
Simulation time 1956120406 ps
CPU time 3.55 seconds
Started Apr 30 03:14:21 PM PDT 24
Finished Apr 30 03:14:25 PM PDT 24
Peak memory 195816 kb
Host smart-588b4945-84da-4515-835c-61fbf2d15801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745918181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.3745918181
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.4127265
Short name T979
Test name
Test status
Simulation time 704122491 ps
CPU time 1.5 seconds
Started Apr 30 03:14:25 PM PDT 24
Finished Apr 30 03:14:27 PM PDT 24
Peak memory 198592 kb
Host smart-0514cdd2-e5fe-4a26-983c-2910bf47a889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.4127265
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.650594304
Short name T181
Test name
Test status
Simulation time 636075974563 ps
CPU time 585.86 seconds
Started Apr 30 03:14:28 PM PDT 24
Finished Apr 30 03:24:15 PM PDT 24
Peak memory 200432 kb
Host smart-4a2c5e89-ec5c-4dec-9119-56c560fe0203
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650594304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.650594304
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.1789536194
Short name T62
Test name
Test status
Simulation time 459356423911 ps
CPU time 605.61 seconds
Started Apr 30 03:14:20 PM PDT 24
Finished Apr 30 03:24:26 PM PDT 24
Peak memory 225164 kb
Host smart-8f706d29-65e3-470c-8a42-dc327e574322
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789536194 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.1789536194
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.3315595153
Short name T16
Test name
Test status
Simulation time 461504563 ps
CPU time 1.56 seconds
Started Apr 30 03:14:19 PM PDT 24
Finished Apr 30 03:14:20 PM PDT 24
Peak memory 198512 kb
Host smart-1dbbb93a-4002-495c-a701-ed0b41dd82bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315595153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.3315595153
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.2640947328
Short name T1018
Test name
Test status
Simulation time 89220813939 ps
CPU time 179.2 seconds
Started Apr 30 03:14:22 PM PDT 24
Finished Apr 30 03:17:22 PM PDT 24
Peak memory 200408 kb
Host smart-ae66ddfb-662d-4463-aa0c-107e1990386a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640947328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.2640947328
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.1789813936
Short name T1010
Test name
Test status
Simulation time 38264388 ps
CPU time 0.56 seconds
Started Apr 30 03:14:30 PM PDT 24
Finished Apr 30 03:14:31 PM PDT 24
Peak memory 195792 kb
Host smart-eccfd23a-2c9f-4fef-a77f-170564243ea6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789813936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.1789813936
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.1048269060
Short name T923
Test name
Test status
Simulation time 9522962176 ps
CPU time 17.97 seconds
Started Apr 30 03:14:29 PM PDT 24
Finished Apr 30 03:14:48 PM PDT 24
Peak memory 200376 kb
Host smart-ea1f98bb-3e72-4771-a03e-4151437750e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048269060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.1048269060
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.2541304662
Short name T246
Test name
Test status
Simulation time 134842883130 ps
CPU time 66.95 seconds
Started Apr 30 03:14:30 PM PDT 24
Finished Apr 30 03:15:37 PM PDT 24
Peak memory 200356 kb
Host smart-18dd1c76-7b3e-44c5-ab15-c8f1ee28c0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541304662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.2541304662
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.498827405
Short name T129
Test name
Test status
Simulation time 68731889280 ps
CPU time 26.2 seconds
Started Apr 30 03:14:28 PM PDT 24
Finished Apr 30 03:14:55 PM PDT 24
Peak memory 200296 kb
Host smart-8442a918-0733-44fd-9d86-b3aff2077a7f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498827405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.498827405
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.2430395635
Short name T661
Test name
Test status
Simulation time 122962064171 ps
CPU time 537.34 seconds
Started Apr 30 03:14:28 PM PDT 24
Finished Apr 30 03:23:27 PM PDT 24
Peak memory 200400 kb
Host smart-95bc0c5b-b06d-459b-aa09-420f5db2b8bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2430395635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2430395635
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.743826041
Short name T349
Test name
Test status
Simulation time 1495922638 ps
CPU time 3.03 seconds
Started Apr 30 03:14:29 PM PDT 24
Finished Apr 30 03:14:33 PM PDT 24
Peak memory 196500 kb
Host smart-25fc4995-d6d3-4255-9bb7-47e4b5bc6442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743826041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.743826041
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.4000016728
Short name T479
Test name
Test status
Simulation time 565118227691 ps
CPU time 65.46 seconds
Started Apr 30 03:14:29 PM PDT 24
Finished Apr 30 03:15:35 PM PDT 24
Peak memory 200636 kb
Host smart-1b5f233f-b370-4fad-a20c-2a0c1ad8a96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000016728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.4000016728
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.3522021010
Short name T647
Test name
Test status
Simulation time 11499191960 ps
CPU time 512.9 seconds
Started Apr 30 03:14:27 PM PDT 24
Finished Apr 30 03:23:01 PM PDT 24
Peak memory 200432 kb
Host smart-0cbde4ad-36fc-4131-87a7-aeb3d4b76e06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3522021010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.3522021010
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.3952562193
Short name T596
Test name
Test status
Simulation time 3936789014 ps
CPU time 16.44 seconds
Started Apr 30 03:14:29 PM PDT 24
Finished Apr 30 03:14:46 PM PDT 24
Peak memory 198724 kb
Host smart-9505edae-b945-4b02-9499-d47018b15d58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3952562193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.3952562193
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.473938290
Short name T515
Test name
Test status
Simulation time 189963026198 ps
CPU time 229.28 seconds
Started Apr 30 03:14:29 PM PDT 24
Finished Apr 30 03:18:19 PM PDT 24
Peak memory 200460 kb
Host smart-97f50232-e601-426b-8c70-90690ccd09ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473938290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.473938290
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.796817955
Short name T591
Test name
Test status
Simulation time 3731862143 ps
CPU time 6.8 seconds
Started Apr 30 03:14:27 PM PDT 24
Finished Apr 30 03:14:34 PM PDT 24
Peak memory 196436 kb
Host smart-1b98e052-2527-4e51-8efd-f2f9aded2427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796817955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.796817955
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.3738966110
Short name T862
Test name
Test status
Simulation time 306108863 ps
CPU time 1.71 seconds
Started Apr 30 03:14:29 PM PDT 24
Finished Apr 30 03:14:31 PM PDT 24
Peak memory 198940 kb
Host smart-9d6a5dfd-9047-49a3-a7ea-eb16f244d2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738966110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3738966110
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.4126963792
Short name T456
Test name
Test status
Simulation time 461114794220 ps
CPU time 726.13 seconds
Started Apr 30 03:14:28 PM PDT 24
Finished Apr 30 03:26:34 PM PDT 24
Peak memory 200356 kb
Host smart-42cb776b-f77f-499f-8f08-8f7e99cf5c86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126963792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.4126963792
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.3036759274
Short name T43
Test name
Test status
Simulation time 19260562853 ps
CPU time 117.01 seconds
Started Apr 30 03:14:29 PM PDT 24
Finished Apr 30 03:16:26 PM PDT 24
Peak memory 215972 kb
Host smart-15104818-7501-4bdf-9d9a-98b10f9b0ecf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036759274 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.3036759274
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.1079623200
Short name T469
Test name
Test status
Simulation time 6461382993 ps
CPU time 7.16 seconds
Started Apr 30 03:14:29 PM PDT 24
Finished Apr 30 03:14:37 PM PDT 24
Peak memory 200192 kb
Host smart-bd902f9c-f197-4126-a951-271573910c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079623200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.1079623200
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.2216959277
Short name T316
Test name
Test status
Simulation time 71410647378 ps
CPU time 31.34 seconds
Started Apr 30 03:14:29 PM PDT 24
Finished Apr 30 03:15:01 PM PDT 24
Peak memory 200396 kb
Host smart-459ead40-b362-4b7f-8704-17f8d88f1510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216959277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.2216959277
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.3232404667
Short name T361
Test name
Test status
Simulation time 11656616 ps
CPU time 0.54 seconds
Started Apr 30 03:14:41 PM PDT 24
Finished Apr 30 03:14:42 PM PDT 24
Peak memory 195792 kb
Host smart-3b0409b7-0641-4c1b-a740-60ffce864e26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232404667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.3232404667
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.631112265
Short name T1098
Test name
Test status
Simulation time 42387011310 ps
CPU time 18.09 seconds
Started Apr 30 03:14:29 PM PDT 24
Finished Apr 30 03:14:48 PM PDT 24
Peak memory 200368 kb
Host smart-8cabdeaf-b204-463e-9e1b-bb60a48d1947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631112265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.631112265
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.1686551230
Short name T161
Test name
Test status
Simulation time 144825784903 ps
CPU time 287.18 seconds
Started Apr 30 03:14:27 PM PDT 24
Finished Apr 30 03:19:15 PM PDT 24
Peak memory 200332 kb
Host smart-9831ade5-97cd-4507-a6f8-d20844b7f9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686551230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.1686551230
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_intr.129412212
Short name T496
Test name
Test status
Simulation time 9751359311 ps
CPU time 15.86 seconds
Started Apr 30 03:14:39 PM PDT 24
Finished Apr 30 03:14:56 PM PDT 24
Peak memory 198140 kb
Host smart-a80e7105-d38a-47c1-87a7-53f264e64d2f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129412212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.129412212
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.689888459
Short name T702
Test name
Test status
Simulation time 75372913452 ps
CPU time 249.21 seconds
Started Apr 30 03:14:40 PM PDT 24
Finished Apr 30 03:18:51 PM PDT 24
Peak memory 200436 kb
Host smart-ea0d9f89-5d0b-489c-bb9d-6eeda3babfbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=689888459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.689888459
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.1550564693
Short name T899
Test name
Test status
Simulation time 9321518603 ps
CPU time 4.86 seconds
Started Apr 30 03:14:39 PM PDT 24
Finished Apr 30 03:14:45 PM PDT 24
Peak memory 200464 kb
Host smart-06bbd585-a0e0-43be-b7d5-11ebe79db12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550564693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.1550564693
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.2167484631
Short name T125
Test name
Test status
Simulation time 64677178558 ps
CPU time 62.7 seconds
Started Apr 30 03:14:38 PM PDT 24
Finished Apr 30 03:15:41 PM PDT 24
Peak memory 208804 kb
Host smart-9d44edb4-81ac-457e-944d-30cce506cd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167484631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.2167484631
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.3829567031
Short name T650
Test name
Test status
Simulation time 13047745641 ps
CPU time 689.72 seconds
Started Apr 30 03:14:35 PM PDT 24
Finished Apr 30 03:26:05 PM PDT 24
Peak memory 200368 kb
Host smart-9e47f074-8748-40fa-9aa4-bd4329076efc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3829567031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.3829567031
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.4187485193
Short name T51
Test name
Test status
Simulation time 3953681339 ps
CPU time 7.5 seconds
Started Apr 30 03:14:39 PM PDT 24
Finished Apr 30 03:14:48 PM PDT 24
Peak memory 199308 kb
Host smart-68cb3b4d-ebe6-495c-9aca-4aebae321bcd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4187485193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.4187485193
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.3658888696
Short name T663
Test name
Test status
Simulation time 19868215826 ps
CPU time 32.63 seconds
Started Apr 30 03:14:41 PM PDT 24
Finished Apr 30 03:15:15 PM PDT 24
Peak memory 200452 kb
Host smart-05b0e57d-33e5-45a7-b825-af9f45ee1747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658888696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.3658888696
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.959141031
Short name T303
Test name
Test status
Simulation time 4909142523 ps
CPU time 2.78 seconds
Started Apr 30 03:14:40 PM PDT 24
Finished Apr 30 03:14:44 PM PDT 24
Peak memory 196412 kb
Host smart-c7ee5b3a-f8e7-4631-9e69-99988e542df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959141031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.959141031
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.58590787
Short name T912
Test name
Test status
Simulation time 724126380 ps
CPU time 2.44 seconds
Started Apr 30 03:14:28 PM PDT 24
Finished Apr 30 03:14:31 PM PDT 24
Peak memory 200276 kb
Host smart-decbc566-eb4b-4d1c-bc27-8b686260c4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58590787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.58590787
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.3279347268
Short name T110
Test name
Test status
Simulation time 502785524511 ps
CPU time 807.02 seconds
Started Apr 30 03:14:39 PM PDT 24
Finished Apr 30 03:28:06 PM PDT 24
Peak memory 217168 kb
Host smart-b0ea28aa-35ce-4feb-aae7-ffd47b2b9817
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279347268 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.3279347268
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.1855568493
Short name T1073
Test name
Test status
Simulation time 1347127320 ps
CPU time 1.91 seconds
Started Apr 30 03:14:40 PM PDT 24
Finished Apr 30 03:14:43 PM PDT 24
Peak memory 199152 kb
Host smart-ae352b9f-1715-4d24-8062-67e2677bf920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855568493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1855568493
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.1088187140
Short name T861
Test name
Test status
Simulation time 42851634077 ps
CPU time 6.5 seconds
Started Apr 30 03:14:29 PM PDT 24
Finished Apr 30 03:14:36 PM PDT 24
Peak memory 200452 kb
Host smart-8410b9cf-4177-4517-a117-a5d8e7ec6521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088187140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.1088187140
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.1975601102
Short name T749
Test name
Test status
Simulation time 38930209 ps
CPU time 0.54 seconds
Started Apr 30 03:14:46 PM PDT 24
Finished Apr 30 03:14:47 PM PDT 24
Peak memory 195780 kb
Host smart-e2038152-5ff8-4fc5-8c67-69568aceb5d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975601102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.1975601102
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.3997757372
Short name T821
Test name
Test status
Simulation time 21782640522 ps
CPU time 36.08 seconds
Started Apr 30 03:14:37 PM PDT 24
Finished Apr 30 03:15:14 PM PDT 24
Peak memory 200580 kb
Host smart-92fb5490-74b3-432c-83f2-8112113368ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997757372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.3997757372
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.2469275069
Short name T1086
Test name
Test status
Simulation time 37961212489 ps
CPU time 18.6 seconds
Started Apr 30 03:14:40 PM PDT 24
Finished Apr 30 03:15:00 PM PDT 24
Peak memory 200300 kb
Host smart-5727bb76-41c5-493e-9584-13c3e6886c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469275069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.2469275069
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.2692853872
Short name T909
Test name
Test status
Simulation time 62689820751 ps
CPU time 98.27 seconds
Started Apr 30 03:14:38 PM PDT 24
Finished Apr 30 03:16:18 PM PDT 24
Peak memory 200464 kb
Host smart-bbe9fc67-0ade-4753-886a-1125e3c5765f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692853872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.2692853872
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.2026730469
Short name T1138
Test name
Test status
Simulation time 50469172638 ps
CPU time 81.25 seconds
Started Apr 30 03:14:38 PM PDT 24
Finished Apr 30 03:15:59 PM PDT 24
Peak memory 200376 kb
Host smart-07a6b9a9-7652-4b1a-80f4-9ae581c4bd7e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026730469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.2026730469
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_loopback.567578946
Short name T1156
Test name
Test status
Simulation time 4116286872 ps
CPU time 3.29 seconds
Started Apr 30 03:14:40 PM PDT 24
Finished Apr 30 03:14:44 PM PDT 24
Peak memory 199172 kb
Host smart-6051e917-72bf-46a1-a2bd-9f9b976747e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567578946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.567578946
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.1426043269
Short name T335
Test name
Test status
Simulation time 97266985164 ps
CPU time 92.63 seconds
Started Apr 30 03:14:38 PM PDT 24
Finished Apr 30 03:16:12 PM PDT 24
Peak memory 208872 kb
Host smart-e3e3d1e3-0e89-423d-bf3f-e8f11d065068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426043269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.1426043269
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.1937263915
Short name T519
Test name
Test status
Simulation time 5123111866 ps
CPU time 321.27 seconds
Started Apr 30 03:14:40 PM PDT 24
Finished Apr 30 03:20:03 PM PDT 24
Peak memory 200432 kb
Host smart-70dfff81-ab0c-406d-8252-0b98a1256761
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1937263915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.1937263915
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.2358126841
Short name T13
Test name
Test status
Simulation time 4765885207 ps
CPU time 32.81 seconds
Started Apr 30 03:14:42 PM PDT 24
Finished Apr 30 03:15:15 PM PDT 24
Peak memory 199104 kb
Host smart-5d44ee7c-04f6-429b-981e-7f3897d554f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2358126841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.2358126841
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.4220103142
Short name T887
Test name
Test status
Simulation time 94077392209 ps
CPU time 60.55 seconds
Started Apr 30 03:14:39 PM PDT 24
Finished Apr 30 03:15:41 PM PDT 24
Peak memory 200384 kb
Host smart-647a0a25-c3c4-488c-933a-b8afb475a58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220103142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.4220103142
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.3243148021
Short name T457
Test name
Test status
Simulation time 2033008307 ps
CPU time 3.99 seconds
Started Apr 30 03:14:38 PM PDT 24
Finished Apr 30 03:14:42 PM PDT 24
Peak memory 196076 kb
Host smart-b293e52f-d504-476e-866e-99e6ce3c47f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243148021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.3243148021
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.916604358
Short name T951
Test name
Test status
Simulation time 287149812 ps
CPU time 2.17 seconds
Started Apr 30 03:14:39 PM PDT 24
Finished Apr 30 03:14:43 PM PDT 24
Peak memory 199176 kb
Host smart-1c016ec4-5614-4c33-99d2-b17232d385ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916604358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.916604358
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.3179994261
Short name T166
Test name
Test status
Simulation time 80994803182 ps
CPU time 85.4 seconds
Started Apr 30 03:14:47 PM PDT 24
Finished Apr 30 03:16:13 PM PDT 24
Peak memory 200420 kb
Host smart-913c7713-8e26-4e6f-a48d-d4d23812383b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179994261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.3179994261
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.2986575445
Short name T769
Test name
Test status
Simulation time 149713301267 ps
CPU time 1033.63 seconds
Started Apr 30 03:14:47 PM PDT 24
Finished Apr 30 03:32:01 PM PDT 24
Peak memory 227052 kb
Host smart-9de637c0-adcb-4648-af64-adf45f2a02ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986575445 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.2986575445
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.868755563
Short name T1017
Test name
Test status
Simulation time 1171590802 ps
CPU time 4.28 seconds
Started Apr 30 03:14:38 PM PDT 24
Finished Apr 30 03:14:43 PM PDT 24
Peak memory 199412 kb
Host smart-dfb12601-c168-42ea-b608-b946f42d61ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868755563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.868755563
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.1773293212
Short name T490
Test name
Test status
Simulation time 66561370406 ps
CPU time 130.33 seconds
Started Apr 30 03:14:40 PM PDT 24
Finished Apr 30 03:16:51 PM PDT 24
Peak memory 200380 kb
Host smart-80e906bf-138e-4939-a574-548e642872c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773293212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.1773293212
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.2959397295
Short name T358
Test name
Test status
Simulation time 14437403 ps
CPU time 0.55 seconds
Started Apr 30 03:14:51 PM PDT 24
Finished Apr 30 03:14:52 PM PDT 24
Peak memory 195772 kb
Host smart-952f0528-f794-443f-8780-c29d90b868e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959397295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.2959397295
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.395234659
Short name T1176
Test name
Test status
Simulation time 58102198799 ps
CPU time 64.42 seconds
Started Apr 30 03:14:45 PM PDT 24
Finished Apr 30 03:15:50 PM PDT 24
Peak memory 200344 kb
Host smart-156483f3-af80-4140-b22a-f40cb0ba651a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395234659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.395234659
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.2062194217
Short name T945
Test name
Test status
Simulation time 8949340668 ps
CPU time 24.97 seconds
Started Apr 30 03:14:46 PM PDT 24
Finished Apr 30 03:15:12 PM PDT 24
Peak memory 200384 kb
Host smart-0ee4e057-49f9-4c54-b0fa-cf1b2e285a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062194217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.2062194217
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.2519587673
Short name T1039
Test name
Test status
Simulation time 44774732164 ps
CPU time 18.18 seconds
Started Apr 30 03:14:47 PM PDT 24
Finished Apr 30 03:15:06 PM PDT 24
Peak memory 200400 kb
Host smart-56214cdc-6dc9-4e7a-92dd-ca5631dc68ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519587673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.2519587673
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.3464047771
Short name T656
Test name
Test status
Simulation time 47631609162 ps
CPU time 29.88 seconds
Started Apr 30 03:14:45 PM PDT 24
Finished Apr 30 03:15:15 PM PDT 24
Peak memory 200400 kb
Host smart-7f874912-a2c5-4a94-8e63-ae97d03c79ed
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464047771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.3464047771
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.2341859261
Short name T439
Test name
Test status
Simulation time 79645880572 ps
CPU time 153.23 seconds
Started Apr 30 03:14:50 PM PDT 24
Finished Apr 30 03:17:24 PM PDT 24
Peak memory 200416 kb
Host smart-5b403d03-6fb4-4b5b-9918-c14145ee31e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2341859261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.2341859261
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.980356370
Short name T364
Test name
Test status
Simulation time 2713779086 ps
CPU time 2.68 seconds
Started Apr 30 03:14:45 PM PDT 24
Finished Apr 30 03:14:49 PM PDT 24
Peak memory 197728 kb
Host smart-0abe3275-2893-4218-a448-70f881a21312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980356370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.980356370
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.2214172190
Short name T625
Test name
Test status
Simulation time 73185170506 ps
CPU time 35.21 seconds
Started Apr 30 03:14:46 PM PDT 24
Finished Apr 30 03:15:22 PM PDT 24
Peak memory 200672 kb
Host smart-63dff289-23bb-483c-89b8-546dbac74789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214172190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.2214172190
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.2976150558
Short name T385
Test name
Test status
Simulation time 5659180497 ps
CPU time 130.02 seconds
Started Apr 30 03:14:47 PM PDT 24
Finished Apr 30 03:16:58 PM PDT 24
Peak memory 200380 kb
Host smart-94b8a572-b25c-49ee-8690-47bf03fee38e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2976150558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.2976150558
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.527398354
Short name T501
Test name
Test status
Simulation time 5900919025 ps
CPU time 12.87 seconds
Started Apr 30 03:14:47 PM PDT 24
Finished Apr 30 03:15:01 PM PDT 24
Peak memory 198576 kb
Host smart-397534ff-1de8-472a-92a1-1ec0e2c826b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=527398354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.527398354
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.2027476924
Short name T766
Test name
Test status
Simulation time 108126629257 ps
CPU time 212.09 seconds
Started Apr 30 03:14:44 PM PDT 24
Finished Apr 30 03:18:17 PM PDT 24
Peak memory 200332 kb
Host smart-4c4191aa-ae6a-444c-8d98-8368dc23dbb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027476924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.2027476924
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.1291422183
Short name T641
Test name
Test status
Simulation time 5963584516 ps
CPU time 10.02 seconds
Started Apr 30 03:14:45 PM PDT 24
Finished Apr 30 03:14:56 PM PDT 24
Peak memory 196436 kb
Host smart-7c7fbd58-b384-48df-860c-1a982aa05302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291422183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.1291422183
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.4188760690
Short name T698
Test name
Test status
Simulation time 284703680 ps
CPU time 1.67 seconds
Started Apr 30 03:14:46 PM PDT 24
Finished Apr 30 03:14:49 PM PDT 24
Peak memory 199168 kb
Host smart-0dbe9bf6-ce9a-4950-be0d-2690b2881e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188760690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.4188760690
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.737264551
Short name T1165
Test name
Test status
Simulation time 66029787212 ps
CPU time 421.99 seconds
Started Apr 30 03:14:50 PM PDT 24
Finished Apr 30 03:21:52 PM PDT 24
Peak memory 216224 kb
Host smart-ab5b7f4c-4f22-44e2-8574-9b851621ca16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737264551 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.737264551
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.896326001
Short name T770
Test name
Test status
Simulation time 612695322 ps
CPU time 2.44 seconds
Started Apr 30 03:14:46 PM PDT 24
Finished Apr 30 03:14:49 PM PDT 24
Peak memory 199152 kb
Host smart-aa583872-2747-4552-9743-f4b198cc078f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896326001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.896326001
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.1970178635
Short name T664
Test name
Test status
Simulation time 15838001919 ps
CPU time 34.64 seconds
Started Apr 30 03:14:51 PM PDT 24
Finished Apr 30 03:15:26 PM PDT 24
Peak memory 200328 kb
Host smart-ed10741d-75e7-4db3-8e18-4a199748cd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970178635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.1970178635
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.3179175594
Short name T478
Test name
Test status
Simulation time 13194388 ps
CPU time 0.57 seconds
Started Apr 30 03:14:56 PM PDT 24
Finished Apr 30 03:14:57 PM PDT 24
Peak memory 195792 kb
Host smart-6fc1140e-76e1-4d05-ad1b-6f33bd3101b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179175594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.3179175594
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.2881280302
Short name T158
Test name
Test status
Simulation time 38558036292 ps
CPU time 16.9 seconds
Started Apr 30 03:14:48 PM PDT 24
Finished Apr 30 03:15:05 PM PDT 24
Peak memory 200408 kb
Host smart-2d8095ba-d880-40c0-95f5-6557715ab225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881280302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.2881280302
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.331995685
Short name T638
Test name
Test status
Simulation time 129542100916 ps
CPU time 222.4 seconds
Started Apr 30 03:14:47 PM PDT 24
Finished Apr 30 03:18:30 PM PDT 24
Peak memory 200452 kb
Host smart-7c6b26dc-a756-4b13-81d5-ef170c0df97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331995685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.331995685
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.312594515
Short name T140
Test name
Test status
Simulation time 53573107342 ps
CPU time 42.46 seconds
Started Apr 30 03:14:46 PM PDT 24
Finished Apr 30 03:15:29 PM PDT 24
Peak memory 200444 kb
Host smart-5b87fa6f-7f99-480f-a9e2-2a5639173dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312594515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.312594515
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.945873238
Short name T363
Test name
Test status
Simulation time 43679956849 ps
CPU time 69.41 seconds
Started Apr 30 03:14:54 PM PDT 24
Finished Apr 30 03:16:04 PM PDT 24
Peak memory 200464 kb
Host smart-dbb64a51-5380-4449-ad4e-ce8b7956bdcc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945873238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.945873238
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.973921297
Short name T575
Test name
Test status
Simulation time 166849466137 ps
CPU time 684.19 seconds
Started Apr 30 03:14:58 PM PDT 24
Finished Apr 30 03:26:23 PM PDT 24
Peak memory 200392 kb
Host smart-928175d0-e647-4bd5-b529-b6b1d2ba2d0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=973921297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.973921297
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.2487607445
Short name T690
Test name
Test status
Simulation time 11784155948 ps
CPU time 10.47 seconds
Started Apr 30 03:14:59 PM PDT 24
Finished Apr 30 03:15:10 PM PDT 24
Peak memory 200068 kb
Host smart-6a342160-c27c-42ed-ae5c-79a18aa8aeee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487607445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2487607445
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.2399893422
Short name T1074
Test name
Test status
Simulation time 63337210455 ps
CPU time 47.85 seconds
Started Apr 30 03:14:55 PM PDT 24
Finished Apr 30 03:15:43 PM PDT 24
Peak memory 200656 kb
Host smart-990744be-c74b-4527-847b-5f9e51503fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399893422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.2399893422
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.1938971108
Short name T845
Test name
Test status
Simulation time 4631863006 ps
CPU time 67.9 seconds
Started Apr 30 03:14:55 PM PDT 24
Finished Apr 30 03:16:03 PM PDT 24
Peak memory 200416 kb
Host smart-a13c02ce-b6f4-49a2-96dc-63e9deb85434
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1938971108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.1938971108
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.1852259121
Short name T7
Test name
Test status
Simulation time 2135414906 ps
CPU time 3 seconds
Started Apr 30 03:14:46 PM PDT 24
Finished Apr 30 03:14:50 PM PDT 24
Peak memory 198376 kb
Host smart-10ec8b0f-6cdd-4343-94e9-ba99d8d7e01b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1852259121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.1852259121
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.1721934670
Short name T1141
Test name
Test status
Simulation time 59295522817 ps
CPU time 28.61 seconds
Started Apr 30 03:14:53 PM PDT 24
Finished Apr 30 03:15:22 PM PDT 24
Peak memory 200060 kb
Host smart-6dfef305-db2d-453f-8010-e950c0839451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721934670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1721934670
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.321763460
Short name T10
Test name
Test status
Simulation time 3417450152 ps
CPU time 6.25 seconds
Started Apr 30 03:14:54 PM PDT 24
Finished Apr 30 03:15:01 PM PDT 24
Peak memory 196444 kb
Host smart-8ed6e700-1ff1-43bc-b9d5-6cab54ee5944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321763460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.321763460
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.2985517521
Short name T843
Test name
Test status
Simulation time 532299264 ps
CPU time 1.28 seconds
Started Apr 30 03:14:47 PM PDT 24
Finished Apr 30 03:14:49 PM PDT 24
Peak memory 199128 kb
Host smart-34af7246-9677-4a08-9470-84550ee13daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985517521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.2985517521
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.3309494509
Short name T1105
Test name
Test status
Simulation time 26986667563 ps
CPU time 781.1 seconds
Started Apr 30 03:14:54 PM PDT 24
Finished Apr 30 03:27:56 PM PDT 24
Peak memory 200616 kb
Host smart-baf6c169-1233-4f4b-8c0e-af79b63bdcb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309494509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.3309494509
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.2086638459
Short name T108
Test name
Test status
Simulation time 63772571214 ps
CPU time 667.99 seconds
Started Apr 30 03:14:55 PM PDT 24
Finished Apr 30 03:26:04 PM PDT 24
Peak memory 212784 kb
Host smart-1b2bd89c-e5bd-4000-b953-de2adb5a5482
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086638459 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.2086638459
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.1133916073
Short name T562
Test name
Test status
Simulation time 695944086 ps
CPU time 3.05 seconds
Started Apr 30 03:14:57 PM PDT 24
Finished Apr 30 03:15:01 PM PDT 24
Peak memory 199288 kb
Host smart-b17e9332-6be2-41b5-9103-8f753e9dc66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133916073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1133916073
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.2118683237
Short name T1015
Test name
Test status
Simulation time 86601031203 ps
CPU time 145.87 seconds
Started Apr 30 03:14:46 PM PDT 24
Finished Apr 30 03:17:13 PM PDT 24
Peak memory 200392 kb
Host smart-1cb90168-6afa-48f2-8863-a3d55aa62f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118683237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.2118683237
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.2875749080
Short name T864
Test name
Test status
Simulation time 15675141 ps
CPU time 0.56 seconds
Started Apr 30 03:14:59 PM PDT 24
Finished Apr 30 03:15:00 PM PDT 24
Peak memory 195812 kb
Host smart-00343302-67c9-4900-b778-a877d3976fb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875749080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.2875749080
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.3109423712
Short name T817
Test name
Test status
Simulation time 97571710819 ps
CPU time 136.71 seconds
Started Apr 30 03:14:53 PM PDT 24
Finished Apr 30 03:17:10 PM PDT 24
Peak memory 200316 kb
Host smart-3b0069dd-61c3-4a2c-8ec0-7f1b8d1c4264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109423712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.3109423712
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.4006885704
Short name T1117
Test name
Test status
Simulation time 82844737261 ps
CPU time 39.76 seconds
Started Apr 30 03:14:56 PM PDT 24
Finished Apr 30 03:15:37 PM PDT 24
Peak memory 199608 kb
Host smart-b615271b-6e0e-4c53-b561-a5dfadb61a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006885704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.4006885704
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_intr.277842173
Short name T131
Test name
Test status
Simulation time 36432220185 ps
CPU time 15.87 seconds
Started Apr 30 03:14:54 PM PDT 24
Finished Apr 30 03:15:11 PM PDT 24
Peak memory 199904 kb
Host smart-c97a6731-8d40-4667-870e-d51ea7cfde8c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277842173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.277842173
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.3478007359
Short name T537
Test name
Test status
Simulation time 70021923089 ps
CPU time 350.32 seconds
Started Apr 30 03:14:54 PM PDT 24
Finished Apr 30 03:20:45 PM PDT 24
Peak memory 200340 kb
Host smart-bcb13369-d35e-467e-9e6f-8e0e2d7a5fc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3478007359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.3478007359
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.523525970
Short name T573
Test name
Test status
Simulation time 3524755093 ps
CPU time 2.82 seconds
Started Apr 30 03:14:54 PM PDT 24
Finished Apr 30 03:14:57 PM PDT 24
Peak memory 198956 kb
Host smart-7bd0dbe7-fc8c-4861-a6de-0b7f8c51b031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523525970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.523525970
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.3432622220
Short name T1122
Test name
Test status
Simulation time 44167637825 ps
CPU time 16.51 seconds
Started Apr 30 03:14:53 PM PDT 24
Finished Apr 30 03:15:10 PM PDT 24
Peak memory 200500 kb
Host smart-6eaac8c9-48c3-4809-b7a3-41ce9dba360f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432622220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.3432622220
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.227204604
Short name T580
Test name
Test status
Simulation time 12305300099 ps
CPU time 149.51 seconds
Started Apr 30 03:14:53 PM PDT 24
Finished Apr 30 03:17:23 PM PDT 24
Peak memory 200456 kb
Host smart-fc93e754-2cb7-4581-8c28-9c436c5019be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=227204604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.227204604
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.3719710094
Short name T106
Test name
Test status
Simulation time 7706238809 ps
CPU time 57.1 seconds
Started Apr 30 03:14:53 PM PDT 24
Finished Apr 30 03:15:51 PM PDT 24
Peak memory 199576 kb
Host smart-03e2415e-a03b-4311-8e86-abc955eab369
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3719710094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.3719710094
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.1856811867
Short name T188
Test name
Test status
Simulation time 31265344160 ps
CPU time 52.35 seconds
Started Apr 30 03:14:56 PM PDT 24
Finished Apr 30 03:15:49 PM PDT 24
Peak memory 200328 kb
Host smart-f8747664-3d3a-41f2-bbc3-19d39b8b7532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856811867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.1856811867
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.1805516368
Short name T419
Test name
Test status
Simulation time 5074100346 ps
CPU time 8.9 seconds
Started Apr 30 03:14:53 PM PDT 24
Finished Apr 30 03:15:03 PM PDT 24
Peak memory 196460 kb
Host smart-0391c645-bd71-4b34-9e85-5ba6a06e3f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805516368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.1805516368
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.753707241
Short name T459
Test name
Test status
Simulation time 696207334 ps
CPU time 2.44 seconds
Started Apr 30 03:14:54 PM PDT 24
Finished Apr 30 03:14:57 PM PDT 24
Peak memory 198792 kb
Host smart-741b3ac1-6fe0-4a7b-a180-e23e515ec5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753707241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.753707241
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.3299662948
Short name T491
Test name
Test status
Simulation time 157536764267 ps
CPU time 539.8 seconds
Started Apr 30 03:14:53 PM PDT 24
Finished Apr 30 03:23:54 PM PDT 24
Peak memory 200404 kb
Host smart-ed6a9626-b569-4dd0-8a04-3e2d7a9813b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299662948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.3299662948
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.1771844980
Short name T277
Test name
Test status
Simulation time 7383146144 ps
CPU time 17.26 seconds
Started Apr 30 03:14:54 PM PDT 24
Finished Apr 30 03:15:12 PM PDT 24
Peak memory 200280 kb
Host smart-241fd642-c93a-4807-8a88-c131593526b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771844980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.1771844980
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.235201624
Short name T794
Test name
Test status
Simulation time 90161939687 ps
CPU time 133.33 seconds
Started Apr 30 03:14:56 PM PDT 24
Finished Apr 30 03:17:10 PM PDT 24
Peak memory 200408 kb
Host smart-0efc624e-f13e-4f3b-8097-50882f72beea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235201624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.235201624
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.2011943706
Short name T345
Test name
Test status
Simulation time 27532537 ps
CPU time 0.57 seconds
Started Apr 30 03:15:03 PM PDT 24
Finished Apr 30 03:15:05 PM PDT 24
Peak memory 195216 kb
Host smart-758b00d1-2df5-4e0a-a214-f307a435b50f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011943706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.2011943706
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.4015030173
Short name T405
Test name
Test status
Simulation time 49719310432 ps
CPU time 72.96 seconds
Started Apr 30 03:15:00 PM PDT 24
Finished Apr 30 03:16:13 PM PDT 24
Peak memory 200336 kb
Host smart-a88d9318-8c44-4e19-9038-9f54b1e3d644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015030173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.4015030173
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.352249095
Short name T438
Test name
Test status
Simulation time 90459992597 ps
CPU time 230.66 seconds
Started Apr 30 03:14:59 PM PDT 24
Finished Apr 30 03:18:51 PM PDT 24
Peak memory 200372 kb
Host smart-8fa27efc-757f-4310-b963-57f319e13296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352249095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.352249095
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.1573169192
Short name T1076
Test name
Test status
Simulation time 23581168081 ps
CPU time 14.59 seconds
Started Apr 30 03:15:02 PM PDT 24
Finished Apr 30 03:15:17 PM PDT 24
Peak memory 200432 kb
Host smart-d726adc5-3773-496c-ac52-b1434bebdeef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573169192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.1573169192
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.3824294526
Short name T366
Test name
Test status
Simulation time 34343567706 ps
CPU time 8.33 seconds
Started Apr 30 03:15:00 PM PDT 24
Finished Apr 30 03:15:08 PM PDT 24
Peak memory 200312 kb
Host smart-8795493f-59c8-43c1-be42-dac7e6611f78
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824294526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.3824294526
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.863778656
Short name T967
Test name
Test status
Simulation time 152641737668 ps
CPU time 476.26 seconds
Started Apr 30 03:15:08 PM PDT 24
Finished Apr 30 03:23:05 PM PDT 24
Peak memory 199776 kb
Host smart-7889933b-6237-4f91-97ea-4044bf5bbaa1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=863778656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.863778656
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.3764045538
Short name T672
Test name
Test status
Simulation time 1327938516 ps
CPU time 3.27 seconds
Started Apr 30 03:15:03 PM PDT 24
Finished Apr 30 03:15:08 PM PDT 24
Peak memory 198980 kb
Host smart-c2524cc3-5fe9-47c8-8ff5-bbd99ca6a91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764045538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.3764045538
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.2804238772
Short name T1088
Test name
Test status
Simulation time 24341633756 ps
CPU time 10.09 seconds
Started Apr 30 03:15:00 PM PDT 24
Finished Apr 30 03:15:10 PM PDT 24
Peak memory 196592 kb
Host smart-6d36553b-7717-4b2f-a483-1c6097c6957e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804238772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.2804238772
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.4019962945
Short name T269
Test name
Test status
Simulation time 27901632601 ps
CPU time 512.1 seconds
Started Apr 30 03:15:03 PM PDT 24
Finished Apr 30 03:23:36 PM PDT 24
Peak memory 200408 kb
Host smart-264fb994-df05-44c4-a3e4-0c68aec92b59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4019962945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.4019962945
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.35093976
Short name T635
Test name
Test status
Simulation time 1707657053 ps
CPU time 4.93 seconds
Started Apr 30 03:15:02 PM PDT 24
Finished Apr 30 03:15:08 PM PDT 24
Peak memory 199476 kb
Host smart-e27e86c0-f98f-406f-9128-afc593333541
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=35093976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.35093976
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.4247720045
Short name T268
Test name
Test status
Simulation time 122337312041 ps
CPU time 232.65 seconds
Started Apr 30 03:15:01 PM PDT 24
Finished Apr 30 03:18:54 PM PDT 24
Peak memory 200348 kb
Host smart-812253ef-2c3e-486d-a6a1-7881640d837e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247720045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.4247720045
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.77857354
Short name T824
Test name
Test status
Simulation time 3278625949 ps
CPU time 1.96 seconds
Started Apr 30 03:15:01 PM PDT 24
Finished Apr 30 03:15:04 PM PDT 24
Peak memory 196424 kb
Host smart-0e6fd398-0681-4b72-bf8d-60565987bb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77857354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.77857354
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.1075050209
Short name T561
Test name
Test status
Simulation time 324578976 ps
CPU time 1.12 seconds
Started Apr 30 03:14:55 PM PDT 24
Finished Apr 30 03:14:57 PM PDT 24
Peak memory 198672 kb
Host smart-79dc1d40-42d0-4bd5-8fc4-d694f7a54c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075050209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1075050209
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.4224245828
Short name T170
Test name
Test status
Simulation time 260081996035 ps
CPU time 1271.58 seconds
Started Apr 30 03:15:02 PM PDT 24
Finished Apr 30 03:36:15 PM PDT 24
Peak memory 200424 kb
Host smart-ce6e366e-845e-4133-b04c-3a39ab940d89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224245828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.4224245828
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.3299483866
Short name T308
Test name
Test status
Simulation time 1107880402 ps
CPU time 1.84 seconds
Started Apr 30 03:15:02 PM PDT 24
Finished Apr 30 03:15:04 PM PDT 24
Peak memory 199136 kb
Host smart-8af8ab27-c3f3-4424-a132-27673553910c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299483866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.3299483866
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.1301274182
Short name T288
Test name
Test status
Simulation time 58236271402 ps
CPU time 92.4 seconds
Started Apr 30 03:14:56 PM PDT 24
Finished Apr 30 03:16:29 PM PDT 24
Peak memory 200364 kb
Host smart-bf9f7824-e379-409b-9b1e-de916beb0268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301274182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1301274182
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.4076255391
Short name T758
Test name
Test status
Simulation time 12045561 ps
CPU time 0.55 seconds
Started Apr 30 03:11:27 PM PDT 24
Finished Apr 30 03:11:28 PM PDT 24
Peak memory 195800 kb
Host smart-db002024-f177-4cf7-a160-e2017d6bc65d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076255391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.4076255391
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.2484980209
Short name T624
Test name
Test status
Simulation time 220901750219 ps
CPU time 516.78 seconds
Started Apr 30 03:11:20 PM PDT 24
Finished Apr 30 03:19:57 PM PDT 24
Peak memory 200384 kb
Host smart-42301bdd-dfd4-4a71-a632-6fe4c68d65dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484980209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.2484980209
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.1588214320
Short name T139
Test name
Test status
Simulation time 27718225100 ps
CPU time 42.75 seconds
Started Apr 30 03:11:20 PM PDT 24
Finished Apr 30 03:12:03 PM PDT 24
Peak memory 200336 kb
Host smart-ad370277-267c-4b7f-a085-274e86c90c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588214320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1588214320
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.74811785
Short name T583
Test name
Test status
Simulation time 121594805639 ps
CPU time 85.13 seconds
Started Apr 30 03:11:22 PM PDT 24
Finished Apr 30 03:12:48 PM PDT 24
Peak memory 200412 kb
Host smart-e390c8a1-e86d-4fd4-af15-2ffd9c40b4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74811785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.74811785
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.587535672
Short name T473
Test name
Test status
Simulation time 17416497812 ps
CPU time 17.78 seconds
Started Apr 30 03:11:22 PM PDT 24
Finished Apr 30 03:11:40 PM PDT 24
Peak memory 200044 kb
Host smart-5e71bcfb-397c-413b-b766-fe53dec9349e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587535672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.587535672
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.1403332920
Short name T407
Test name
Test status
Simulation time 99182240911 ps
CPU time 325.6 seconds
Started Apr 30 03:11:28 PM PDT 24
Finished Apr 30 03:16:54 PM PDT 24
Peak memory 200404 kb
Host smart-8c9a0ded-cad8-40fd-b61e-7a4225df5a0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1403332920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.1403332920
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.1765818679
Short name T816
Test name
Test status
Simulation time 10093048057 ps
CPU time 17.46 seconds
Started Apr 30 03:11:28 PM PDT 24
Finished Apr 30 03:11:46 PM PDT 24
Peak memory 200300 kb
Host smart-27116af1-6053-4ded-baef-3011530b1c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765818679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.1765818679
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.3359862935
Short name T516
Test name
Test status
Simulation time 135961406448 ps
CPU time 56.41 seconds
Started Apr 30 03:11:20 PM PDT 24
Finished Apr 30 03:12:17 PM PDT 24
Peak memory 200588 kb
Host smart-e80e07f3-8bc8-4421-b206-7819407971a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359862935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.3359862935
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.987934235
Short name T792
Test name
Test status
Simulation time 13225857246 ps
CPU time 732.07 seconds
Started Apr 30 03:11:28 PM PDT 24
Finished Apr 30 03:23:41 PM PDT 24
Peak memory 200416 kb
Host smart-480a7698-143f-49df-9208-47693f86c975
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=987934235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.987934235
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.4219013278
Short name T1092
Test name
Test status
Simulation time 4228917674 ps
CPU time 9.28 seconds
Started Apr 30 03:11:20 PM PDT 24
Finished Apr 30 03:11:30 PM PDT 24
Peak memory 199596 kb
Host smart-0e78e961-4b15-44f2-a28b-9e7f2d6a6f66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4219013278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.4219013278
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.3331304794
Short name T526
Test name
Test status
Simulation time 97295288679 ps
CPU time 87.02 seconds
Started Apr 30 03:11:28 PM PDT 24
Finished Apr 30 03:12:56 PM PDT 24
Peak memory 200364 kb
Host smart-a4dded01-5d9f-4f7c-b5ed-99d6de1021bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331304794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.3331304794
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.745950023
Short name T799
Test name
Test status
Simulation time 52369589777 ps
CPU time 81.45 seconds
Started Apr 30 03:11:29 PM PDT 24
Finished Apr 30 03:12:51 PM PDT 24
Peak memory 196728 kb
Host smart-a5b1c159-3e9c-4b65-9903-4ebd9b5f9e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745950023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.745950023
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.3488049470
Short name T28
Test name
Test status
Simulation time 378297730 ps
CPU time 0.84 seconds
Started Apr 30 03:11:27 PM PDT 24
Finished Apr 30 03:11:28 PM PDT 24
Peak memory 218656 kb
Host smart-01903368-9751-41b9-8ab8-23c87785aa39
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488049470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.3488049470
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.1255848660
Short name T669
Test name
Test status
Simulation time 722517683 ps
CPU time 1.76 seconds
Started Apr 30 03:11:19 PM PDT 24
Finished Apr 30 03:11:22 PM PDT 24
Peak memory 200172 kb
Host smart-f6979a64-2a04-42fb-bb8c-11d8efc886d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255848660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.1255848660
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.2395689238
Short name T1163
Test name
Test status
Simulation time 141300981149 ps
CPU time 122.48 seconds
Started Apr 30 03:11:27 PM PDT 24
Finished Apr 30 03:13:30 PM PDT 24
Peak memory 200400 kb
Host smart-0557421d-4f40-4a4f-b9de-ba7cf0cc7189
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395689238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2395689238
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.3128125351
Short name T926
Test name
Test status
Simulation time 407314644343 ps
CPU time 820.87 seconds
Started Apr 30 03:11:28 PM PDT 24
Finished Apr 30 03:25:10 PM PDT 24
Peak memory 230752 kb
Host smart-64204dfb-74d8-476c-9d3e-2da4343127ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128125351 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.3128125351
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.3147828796
Short name T1038
Test name
Test status
Simulation time 1689103932 ps
CPU time 1.54 seconds
Started Apr 30 03:11:27 PM PDT 24
Finished Apr 30 03:11:29 PM PDT 24
Peak memory 199252 kb
Host smart-f7005b24-aca6-465b-8b46-b8916152593e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147828796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.3147828796
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.2094152072
Short name T813
Test name
Test status
Simulation time 57743137610 ps
CPU time 115.14 seconds
Started Apr 30 03:11:23 PM PDT 24
Finished Apr 30 03:13:19 PM PDT 24
Peak memory 200380 kb
Host smart-a335fc00-f8ef-4bcc-8d62-97ed4c846b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094152072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.2094152072
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.4210207395
Short name T789
Test name
Test status
Simulation time 24312521 ps
CPU time 0.56 seconds
Started Apr 30 03:15:08 PM PDT 24
Finished Apr 30 03:15:10 PM PDT 24
Peak memory 194716 kb
Host smart-7873ade8-bbca-47ca-8d6c-d5cf8e11e72d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210207395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.4210207395
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.1674379945
Short name T869
Test name
Test status
Simulation time 22019322817 ps
CPU time 31.7 seconds
Started Apr 30 03:15:02 PM PDT 24
Finished Apr 30 03:15:34 PM PDT 24
Peak memory 200372 kb
Host smart-4a0c5879-6b70-404f-94a6-337996581df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674379945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.1674379945
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.634350956
Short name T880
Test name
Test status
Simulation time 28015221164 ps
CPU time 49.7 seconds
Started Apr 30 03:15:02 PM PDT 24
Finished Apr 30 03:15:52 PM PDT 24
Peak memory 200432 kb
Host smart-e57af12e-73b1-42a6-a42b-6e5c07e4215e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634350956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.634350956
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_intr.2680589780
Short name T292
Test name
Test status
Simulation time 12665304500 ps
CPU time 17.1 seconds
Started Apr 30 03:14:59 PM PDT 24
Finished Apr 30 03:15:17 PM PDT 24
Peak memory 200168 kb
Host smart-052128e0-9a4f-4f68-892d-6c80273ec229
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680589780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.2680589780
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.2371044860
Short name T687
Test name
Test status
Simulation time 57287798623 ps
CPU time 159.54 seconds
Started Apr 30 03:15:09 PM PDT 24
Finished Apr 30 03:17:49 PM PDT 24
Peak memory 200388 kb
Host smart-921ec771-b77f-4364-96fc-cc4bf69b4b22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2371044860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2371044860
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.2328287493
Short name T938
Test name
Test status
Simulation time 8711690679 ps
CPU time 9.47 seconds
Started Apr 30 03:15:11 PM PDT 24
Finished Apr 30 03:15:21 PM PDT 24
Peak memory 199292 kb
Host smart-ed6c931f-1075-4038-9f29-9c3b9871629b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328287493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.2328287493
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.1845872428
Short name T1034
Test name
Test status
Simulation time 478423677440 ps
CPU time 94.34 seconds
Started Apr 30 03:15:02 PM PDT 24
Finished Apr 30 03:16:37 PM PDT 24
Peak memory 200660 kb
Host smart-32c99883-938e-4281-a4d2-370fa55b1685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845872428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.1845872428
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.3619402539
Short name T1078
Test name
Test status
Simulation time 10233707412 ps
CPU time 266.33 seconds
Started Apr 30 03:15:09 PM PDT 24
Finished Apr 30 03:19:36 PM PDT 24
Peak memory 200308 kb
Host smart-cc418f6b-9f45-4537-8287-835b6acc46c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3619402539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.3619402539
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.1773540732
Short name T889
Test name
Test status
Simulation time 3569604502 ps
CPU time 27.12 seconds
Started Apr 30 03:15:00 PM PDT 24
Finished Apr 30 03:15:27 PM PDT 24
Peak memory 198512 kb
Host smart-828ef784-8965-4d9d-951d-a97641356e97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1773540732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.1773540732
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.1318582634
Short name T1
Test name
Test status
Simulation time 60462660047 ps
CPU time 112.27 seconds
Started Apr 30 03:15:08 PM PDT 24
Finished Apr 30 03:17:01 PM PDT 24
Peak memory 200156 kb
Host smart-c48949cd-0c1e-4e36-b2e0-c2a83e5adaee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318582634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.1318582634
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.756178683
Short name T716
Test name
Test status
Simulation time 30662251351 ps
CPU time 13.69 seconds
Started Apr 30 03:15:03 PM PDT 24
Finished Apr 30 03:15:17 PM PDT 24
Peak memory 196404 kb
Host smart-1c0c8bd2-b9f1-4983-bee2-342d24308cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756178683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.756178683
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.1751075663
Short name T387
Test name
Test status
Simulation time 445339940 ps
CPU time 1.25 seconds
Started Apr 30 03:14:59 PM PDT 24
Finished Apr 30 03:15:01 PM PDT 24
Peak memory 200284 kb
Host smart-67861c36-80d1-4ffa-b522-f535e86012d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751075663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.1751075663
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.240835527
Short name T888
Test name
Test status
Simulation time 166394981377 ps
CPU time 468.46 seconds
Started Apr 30 03:15:09 PM PDT 24
Finished Apr 30 03:22:58 PM PDT 24
Peak memory 200396 kb
Host smart-9254fe3f-13e4-4750-8aa7-a641ffc4a795
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240835527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.240835527
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.3559602713
Short name T1024
Test name
Test status
Simulation time 53712050063 ps
CPU time 165.67 seconds
Started Apr 30 03:15:07 PM PDT 24
Finished Apr 30 03:17:53 PM PDT 24
Peak memory 213252 kb
Host smart-ee68a3a1-28ea-407b-84d2-4d6db93835bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559602713 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.3559602713
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.2152685145
Short name T602
Test name
Test status
Simulation time 6428206636 ps
CPU time 15.63 seconds
Started Apr 30 03:15:08 PM PDT 24
Finished Apr 30 03:15:24 PM PDT 24
Peak memory 200260 kb
Host smart-6fcccc3a-bebc-406e-81b5-59387995b987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152685145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.2152685145
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.2013644126
Short name T732
Test name
Test status
Simulation time 25966903608 ps
CPU time 22.68 seconds
Started Apr 30 03:15:03 PM PDT 24
Finished Apr 30 03:15:27 PM PDT 24
Peak memory 200372 kb
Host smart-5c7ef640-089e-43ab-a211-47b13a5d9277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013644126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.2013644126
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.1495469476
Short name T744
Test name
Test status
Simulation time 14990909 ps
CPU time 0.56 seconds
Started Apr 30 03:15:13 PM PDT 24
Finished Apr 30 03:15:14 PM PDT 24
Peak memory 195844 kb
Host smart-2cc19aef-45b7-438f-bf8f-32799e5e5b86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495469476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.1495469476
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.1925693361
Short name T535
Test name
Test status
Simulation time 35908843444 ps
CPU time 43.23 seconds
Started Apr 30 03:15:10 PM PDT 24
Finished Apr 30 03:15:54 PM PDT 24
Peak memory 200348 kb
Host smart-d4373385-eef4-427d-a39a-430c619b901d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925693361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.1925693361
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.1400323109
Short name T603
Test name
Test status
Simulation time 137693676738 ps
CPU time 206.23 seconds
Started Apr 30 03:15:09 PM PDT 24
Finished Apr 30 03:18:36 PM PDT 24
Peak memory 200604 kb
Host smart-d3f31b7a-81fc-4f0c-839b-fe80726aca48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400323109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.1400323109
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.3955197718
Short name T786
Test name
Test status
Simulation time 44707104889 ps
CPU time 34.07 seconds
Started Apr 30 03:15:08 PM PDT 24
Finished Apr 30 03:15:43 PM PDT 24
Peak memory 200452 kb
Host smart-f3180e7b-f3ff-4f89-9447-2a39eeca83e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955197718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3955197718
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.2334782837
Short name T651
Test name
Test status
Simulation time 337996779424 ps
CPU time 125.48 seconds
Started Apr 30 03:15:10 PM PDT 24
Finished Apr 30 03:17:16 PM PDT 24
Peak memory 200424 kb
Host smart-607143f3-5e89-41c3-a101-febefb00640a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334782837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.2334782837
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.3241138641
Short name T910
Test name
Test status
Simulation time 165459242952 ps
CPU time 432.36 seconds
Started Apr 30 03:15:15 PM PDT 24
Finished Apr 30 03:22:28 PM PDT 24
Peak memory 200444 kb
Host smart-c2adf9d7-6e73-4c96-b510-8ca0dfcc7ecd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3241138641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.3241138641
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.3418622528
Short name T949
Test name
Test status
Simulation time 2355284818 ps
CPU time 5.56 seconds
Started Apr 30 03:15:13 PM PDT 24
Finished Apr 30 03:15:19 PM PDT 24
Peak memory 199548 kb
Host smart-8a9133fa-215c-486f-809e-8a6cd3fbb644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418622528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.3418622528
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.3419214970
Short name T549
Test name
Test status
Simulation time 20264579227 ps
CPU time 33.63 seconds
Started Apr 30 03:15:09 PM PDT 24
Finished Apr 30 03:15:43 PM PDT 24
Peak memory 198404 kb
Host smart-782f22b6-51bf-419a-95aa-619104371d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419214970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.3419214970
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.3164360091
Short name T574
Test name
Test status
Simulation time 14400346430 ps
CPU time 837.22 seconds
Started Apr 30 03:15:14 PM PDT 24
Finished Apr 30 03:29:13 PM PDT 24
Peak memory 200420 kb
Host smart-ecf1f303-d835-42a7-a3c5-93d3aeb6c47e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3164360091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.3164360091
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.1024095460
Short name T50
Test name
Test status
Simulation time 2857796636 ps
CPU time 23.05 seconds
Started Apr 30 03:15:10 PM PDT 24
Finished Apr 30 03:15:34 PM PDT 24
Peak memory 198564 kb
Host smart-7911db58-ef48-497e-b3b5-8e00d5aaa539
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1024095460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.1024095460
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.170161095
Short name T511
Test name
Test status
Simulation time 170060762444 ps
CPU time 69.48 seconds
Started Apr 30 03:15:16 PM PDT 24
Finished Apr 30 03:16:26 PM PDT 24
Peak memory 200320 kb
Host smart-3c986c7a-1b63-4779-a897-647729beccc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170161095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.170161095
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.2631198292
Short name T450
Test name
Test status
Simulation time 2375725178 ps
CPU time 2.52 seconds
Started Apr 30 03:15:12 PM PDT 24
Finished Apr 30 03:15:16 PM PDT 24
Peak memory 196160 kb
Host smart-635e477f-dc7f-43eb-9a1a-030fc3822bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631198292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.2631198292
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.1545180599
Short name T626
Test name
Test status
Simulation time 649970963 ps
CPU time 2.68 seconds
Started Apr 30 03:15:14 PM PDT 24
Finished Apr 30 03:15:18 PM PDT 24
Peak memory 198680 kb
Host smart-176c0272-01a7-455b-96d9-415924f5bdf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545180599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.1545180599
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.2950261967
Short name T668
Test name
Test status
Simulation time 257761408707 ps
CPU time 103.58 seconds
Started Apr 30 03:15:15 PM PDT 24
Finished Apr 30 03:17:00 PM PDT 24
Peak memory 200452 kb
Host smart-678e897c-ac53-49b8-9eb0-84f0287b16dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950261967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.2950261967
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.465100782
Short name T586
Test name
Test status
Simulation time 40387732610 ps
CPU time 390.09 seconds
Started Apr 30 03:15:15 PM PDT 24
Finished Apr 30 03:21:46 PM PDT 24
Peak memory 217124 kb
Host smart-7a548ccc-e3a5-4ded-988e-63ba09a511d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465100782 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.465100782
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.2449977178
Short name T539
Test name
Test status
Simulation time 560064298 ps
CPU time 2.45 seconds
Started Apr 30 03:15:17 PM PDT 24
Finished Apr 30 03:15:20 PM PDT 24
Peak memory 198776 kb
Host smart-7c24ee99-1db6-404f-96e2-09b1af65ed3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449977178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.2449977178
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.1965544204
Short name T427
Test name
Test status
Simulation time 50840965366 ps
CPU time 161.9 seconds
Started Apr 30 03:15:08 PM PDT 24
Finished Apr 30 03:17:51 PM PDT 24
Peak memory 200428 kb
Host smart-13c89345-acbc-4558-a154-abe41e4285eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965544204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.1965544204
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.3242648170
Short name T725
Test name
Test status
Simulation time 22302186 ps
CPU time 0.54 seconds
Started Apr 30 03:15:24 PM PDT 24
Finished Apr 30 03:15:25 PM PDT 24
Peak memory 195824 kb
Host smart-e3930de6-74d1-46e3-9b6f-6ec0cb9e3fd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242648170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.3242648170
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.3176656037
Short name T156
Test name
Test status
Simulation time 177441932251 ps
CPU time 94.35 seconds
Started Apr 30 03:15:13 PM PDT 24
Finished Apr 30 03:16:48 PM PDT 24
Peak memory 200368 kb
Host smart-c2f3dc09-6fa2-497e-b427-dc34c129097a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176656037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.3176656037
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.886463264
Short name T595
Test name
Test status
Simulation time 16687820699 ps
CPU time 15.55 seconds
Started Apr 30 03:15:13 PM PDT 24
Finished Apr 30 03:15:30 PM PDT 24
Peak memory 200372 kb
Host smart-dd91667e-6b0b-4ac0-93f1-0af754114d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886463264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.886463264
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.136595502
Short name T598
Test name
Test status
Simulation time 222069770650 ps
CPU time 44.73 seconds
Started Apr 30 03:15:14 PM PDT 24
Finished Apr 30 03:15:59 PM PDT 24
Peak memory 200212 kb
Host smart-6f0e70f0-61ee-4884-89e3-31a3615ec3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136595502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.136595502
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.3740642096
Short name T871
Test name
Test status
Simulation time 262407017222 ps
CPU time 231.75 seconds
Started Apr 30 03:15:15 PM PDT 24
Finished Apr 30 03:19:08 PM PDT 24
Peak memory 199872 kb
Host smart-00e6d7b9-4b1b-49a0-8410-05086e9be5e3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740642096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.3740642096
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.1155487019
Short name T533
Test name
Test status
Simulation time 115309042106 ps
CPU time 444.98 seconds
Started Apr 30 03:15:21 PM PDT 24
Finished Apr 30 03:22:47 PM PDT 24
Peak memory 200484 kb
Host smart-8391ca32-3205-4182-96fd-472c97ef0be7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1155487019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.1155487019
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.488022188
Short name T1004
Test name
Test status
Simulation time 4528435970 ps
CPU time 7.85 seconds
Started Apr 30 03:15:17 PM PDT 24
Finished Apr 30 03:15:26 PM PDT 24
Peak memory 200188 kb
Host smart-90091ec0-a86c-43bb-b008-6eefa028ebac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488022188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.488022188
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.3196700661
Short name T1067
Test name
Test status
Simulation time 36393200856 ps
CPU time 31.48 seconds
Started Apr 30 03:15:14 PM PDT 24
Finished Apr 30 03:15:47 PM PDT 24
Peak memory 200604 kb
Host smart-4c68e5b3-23fa-4647-932d-800cdf4a4a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196700661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.3196700661
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.1889691971
Short name T418
Test name
Test status
Simulation time 18759695869 ps
CPU time 974.96 seconds
Started Apr 30 03:15:15 PM PDT 24
Finished Apr 30 03:31:31 PM PDT 24
Peak memory 200384 kb
Host smart-d84e6a6a-4982-47f9-8a48-c34961fa84be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1889691971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.1889691971
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.3849968859
Short name T444
Test name
Test status
Simulation time 4746662452 ps
CPU time 22.25 seconds
Started Apr 30 03:15:15 PM PDT 24
Finished Apr 30 03:15:39 PM PDT 24
Peak memory 199556 kb
Host smart-37085ca7-5194-404a-8f3a-6b8ec998fc83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3849968859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3849968859
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.1270529777
Short name T891
Test name
Test status
Simulation time 339535889400 ps
CPU time 61.82 seconds
Started Apr 30 03:15:13 PM PDT 24
Finished Apr 30 03:16:16 PM PDT 24
Peak memory 200360 kb
Host smart-c4a43942-f579-4798-8b04-571bcf10f852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270529777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.1270529777
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.3134966727
Short name T461
Test name
Test status
Simulation time 5936832609 ps
CPU time 4.14 seconds
Started Apr 30 03:15:15 PM PDT 24
Finished Apr 30 03:15:21 PM PDT 24
Peak memory 196716 kb
Host smart-dea227c7-fac9-47a9-b216-168c3a63dd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134966727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.3134966727
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.3184109798
Short name T629
Test name
Test status
Simulation time 689066355 ps
CPU time 2.61 seconds
Started Apr 30 03:15:14 PM PDT 24
Finished Apr 30 03:15:18 PM PDT 24
Peak memory 199924 kb
Host smart-4a72fe47-fc14-429d-a032-ac7690a69a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184109798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.3184109798
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.1510718995
Short name T339
Test name
Test status
Simulation time 102700183064 ps
CPU time 189.61 seconds
Started Apr 30 03:15:20 PM PDT 24
Finished Apr 30 03:18:31 PM PDT 24
Peak memory 200492 kb
Host smart-a5c5af40-e9a1-43b9-870f-0a33156564d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510718995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.1510718995
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.235791234
Short name T782
Test name
Test status
Simulation time 147570875689 ps
CPU time 686.72 seconds
Started Apr 30 03:15:25 PM PDT 24
Finished Apr 30 03:26:53 PM PDT 24
Peak memory 227272 kb
Host smart-9eb54a2c-55d6-4fa5-ab26-5c46822a6382
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235791234 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.235791234
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.3447094288
Short name T819
Test name
Test status
Simulation time 1200538723 ps
CPU time 3.92 seconds
Started Apr 30 03:15:15 PM PDT 24
Finished Apr 30 03:15:20 PM PDT 24
Peak memory 199276 kb
Host smart-2a045616-3a33-4c45-a049-22ec0879fb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447094288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.3447094288
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.4100052392
Short name T675
Test name
Test status
Simulation time 85116311190 ps
CPU time 72.67 seconds
Started Apr 30 03:15:14 PM PDT 24
Finished Apr 30 03:16:28 PM PDT 24
Peak memory 200448 kb
Host smart-6379650c-0391-4ee6-90bf-d0a74ca85c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100052392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.4100052392
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.1459113949
Short name T1075
Test name
Test status
Simulation time 20918370 ps
CPU time 0.58 seconds
Started Apr 30 03:15:20 PM PDT 24
Finished Apr 30 03:15:21 PM PDT 24
Peak memory 194796 kb
Host smart-6bd4c696-ac89-488f-9bf5-d9656f943c0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459113949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1459113949
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.2172950964
Short name T969
Test name
Test status
Simulation time 95932167895 ps
CPU time 52.32 seconds
Started Apr 30 03:15:21 PM PDT 24
Finished Apr 30 03:16:14 PM PDT 24
Peak memory 200384 kb
Host smart-c3dcfbef-7288-4830-836f-cd95d90b9f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172950964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.2172950964
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.3055724315
Short name T734
Test name
Test status
Simulation time 61969806260 ps
CPU time 26.18 seconds
Started Apr 30 03:15:28 PM PDT 24
Finished Apr 30 03:15:54 PM PDT 24
Peak memory 200372 kb
Host smart-e9c42392-7899-4d2c-b7ab-81cfc7aab798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055724315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.3055724315
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.3688330488
Short name T1146
Test name
Test status
Simulation time 5828707153 ps
CPU time 8.81 seconds
Started Apr 30 03:15:22 PM PDT 24
Finished Apr 30 03:15:31 PM PDT 24
Peak memory 196940 kb
Host smart-1a73b187-0de5-417b-82d2-e91ccec3f474
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688330488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3688330488
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.456326878
Short name T103
Test name
Test status
Simulation time 76718600755 ps
CPU time 563.25 seconds
Started Apr 30 03:15:22 PM PDT 24
Finished Apr 30 03:24:46 PM PDT 24
Peak memory 200440 kb
Host smart-a2f38c9b-61b9-4869-b9d8-722d51ee5b0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=456326878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.456326878
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.3062699668
Short name T858
Test name
Test status
Simulation time 7292248318 ps
CPU time 8.35 seconds
Started Apr 30 03:15:23 PM PDT 24
Finished Apr 30 03:15:32 PM PDT 24
Peak memory 200328 kb
Host smart-dc478013-e6e0-4c50-b473-91f8bbcaa7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062699668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.3062699668
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.1794652543
Short name T104
Test name
Test status
Simulation time 7044985279 ps
CPU time 12.13 seconds
Started Apr 30 03:15:21 PM PDT 24
Finished Apr 30 03:15:34 PM PDT 24
Peak memory 195032 kb
Host smart-23a3d240-d080-4dc7-8760-c01245b53fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794652543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.1794652543
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.1672852780
Short name T901
Test name
Test status
Simulation time 9651285690 ps
CPU time 265.32 seconds
Started Apr 30 03:15:25 PM PDT 24
Finished Apr 30 03:19:50 PM PDT 24
Peak memory 200336 kb
Host smart-fad7b4ad-eb50-44a2-a8ba-1c2dbdcc6246
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1672852780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1672852780
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.1870581412
Short name T1003
Test name
Test status
Simulation time 2552295779 ps
CPU time 18.04 seconds
Started Apr 30 03:15:20 PM PDT 24
Finished Apr 30 03:15:39 PM PDT 24
Peak memory 199372 kb
Host smart-a05fccc2-c4a4-4a39-8988-b6e104b9c745
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1870581412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.1870581412
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.881923645
Short name T281
Test name
Test status
Simulation time 95209547040 ps
CPU time 149.46 seconds
Started Apr 30 03:15:22 PM PDT 24
Finished Apr 30 03:17:52 PM PDT 24
Peak memory 200364 kb
Host smart-b25d550e-ef61-4e45-9c65-8ea83ca32b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881923645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.881923645
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.2658426254
Short name T311
Test name
Test status
Simulation time 1717260237 ps
CPU time 2.98 seconds
Started Apr 30 03:15:23 PM PDT 24
Finished Apr 30 03:15:26 PM PDT 24
Peak memory 196108 kb
Host smart-7dd5f400-68a3-49ae-b215-409637c22280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658426254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.2658426254
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.3461280341
Short name T757
Test name
Test status
Simulation time 129497559 ps
CPU time 1.02 seconds
Started Apr 30 03:15:21 PM PDT 24
Finished Apr 30 03:15:22 PM PDT 24
Peak memory 199036 kb
Host smart-2e23a304-eb8b-440e-9e86-34a318245179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461280341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.3461280341
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.1355938046
Short name T61
Test name
Test status
Simulation time 44370770396 ps
CPU time 833.81 seconds
Started Apr 30 03:15:21 PM PDT 24
Finished Apr 30 03:29:15 PM PDT 24
Peak memory 225244 kb
Host smart-d0449351-baa0-43da-849e-00759465214f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355938046 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.1355938046
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.124495428
Short name T1028
Test name
Test status
Simulation time 2590628468 ps
CPU time 2.16 seconds
Started Apr 30 03:15:21 PM PDT 24
Finished Apr 30 03:15:23 PM PDT 24
Peak memory 198808 kb
Host smart-c3b86222-8be3-46b0-8b30-a4f11a874a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124495428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.124495428
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.3638759552
Short name T313
Test name
Test status
Simulation time 207917893038 ps
CPU time 106.56 seconds
Started Apr 30 03:15:23 PM PDT 24
Finished Apr 30 03:17:10 PM PDT 24
Peak memory 200240 kb
Host smart-6a3f5825-dfb1-4e8c-9b39-233211f64dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638759552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.3638759552
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.3849636640
Short name T961
Test name
Test status
Simulation time 42421084 ps
CPU time 0.55 seconds
Started Apr 30 03:15:30 PM PDT 24
Finished Apr 30 03:15:31 PM PDT 24
Peak memory 195796 kb
Host smart-354e1d76-6c4c-4784-ba1c-a02ae5332c05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849636640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.3849636640
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.499260673
Short name T681
Test name
Test status
Simulation time 266180271344 ps
CPU time 159.84 seconds
Started Apr 30 03:15:28 PM PDT 24
Finished Apr 30 03:18:08 PM PDT 24
Peak memory 200372 kb
Host smart-f683828c-34a2-4fdd-93d1-a02c94959041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499260673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.499260673
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.1730515486
Short name T623
Test name
Test status
Simulation time 138235806464 ps
CPU time 96.44 seconds
Started Apr 30 03:15:20 PM PDT 24
Finished Apr 30 03:16:57 PM PDT 24
Peak memory 200380 kb
Host smart-40e2b025-0e0e-47f7-9d92-d32bc357d4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730515486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1730515486
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.1251020267
Short name T237
Test name
Test status
Simulation time 118168848337 ps
CPU time 636.43 seconds
Started Apr 30 03:15:21 PM PDT 24
Finished Apr 30 03:25:58 PM PDT 24
Peak memory 200444 kb
Host smart-420825da-494b-4f6b-a443-4f7b10389290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251020267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.1251020267
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.2735288831
Short name T324
Test name
Test status
Simulation time 132105941630 ps
CPU time 97.19 seconds
Started Apr 30 03:15:28 PM PDT 24
Finished Apr 30 03:17:06 PM PDT 24
Peak memory 196476 kb
Host smart-8725c84c-615e-4751-89e7-7439a89213fc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735288831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.2735288831
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.286147783
Short name T293
Test name
Test status
Simulation time 70123643813 ps
CPU time 122.22 seconds
Started Apr 30 03:15:29 PM PDT 24
Finished Apr 30 03:17:32 PM PDT 24
Peak memory 200308 kb
Host smart-74994fe1-aa81-4aa5-965b-35c462e117a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=286147783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.286147783
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.220013476
Short name T6
Test name
Test status
Simulation time 1475066011 ps
CPU time 1.1 seconds
Started Apr 30 03:15:32 PM PDT 24
Finished Apr 30 03:15:34 PM PDT 24
Peak memory 197464 kb
Host smart-5b7740f5-3a6f-44cd-b984-6de74461dd6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220013476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.220013476
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.1932484570
Short name T1027
Test name
Test status
Simulation time 22544588213 ps
CPU time 17.34 seconds
Started Apr 30 03:15:29 PM PDT 24
Finished Apr 30 03:15:47 PM PDT 24
Peak memory 198080 kb
Host smart-51cb12d4-7ea5-483a-9ddf-f2c3f03cc275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932484570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.1932484570
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.936150473
Short name T430
Test name
Test status
Simulation time 12777011610 ps
CPU time 726.5 seconds
Started Apr 30 03:15:28 PM PDT 24
Finished Apr 30 03:27:35 PM PDT 24
Peak memory 200412 kb
Host smart-68e30c8c-f999-4e73-acdf-7f1748fc80ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=936150473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.936150473
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.2654052219
Short name T1184
Test name
Test status
Simulation time 1920901795 ps
CPU time 3.51 seconds
Started Apr 30 03:15:28 PM PDT 24
Finished Apr 30 03:15:32 PM PDT 24
Peak memory 199004 kb
Host smart-64c04831-ff86-4ee8-9cd2-c450ae87a2e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2654052219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.2654052219
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.1861475458
Short name T709
Test name
Test status
Simulation time 58673039152 ps
CPU time 97.96 seconds
Started Apr 30 03:15:28 PM PDT 24
Finished Apr 30 03:17:07 PM PDT 24
Peak memory 200372 kb
Host smart-0a7f3bad-18b4-4528-a3c4-f76bad935bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861475458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.1861475458
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.904983934
Short name T622
Test name
Test status
Simulation time 1971534971 ps
CPU time 1.53 seconds
Started Apr 30 03:15:29 PM PDT 24
Finished Apr 30 03:15:31 PM PDT 24
Peak memory 195784 kb
Host smart-db3ad7ef-b849-47cc-b034-45222ddddf5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904983934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.904983934
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.2176964609
Short name T797
Test name
Test status
Simulation time 460084818 ps
CPU time 2.19 seconds
Started Apr 30 03:15:28 PM PDT 24
Finished Apr 30 03:15:31 PM PDT 24
Peak memory 199952 kb
Host smart-bcfd4e91-2600-4dbf-bfcc-08cfc1b194a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176964609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.2176964609
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.163509654
Short name T484
Test name
Test status
Simulation time 223549797117 ps
CPU time 902.55 seconds
Started Apr 30 03:15:32 PM PDT 24
Finished Apr 30 03:30:35 PM PDT 24
Peak memory 200388 kb
Host smart-e400d1dd-0b25-4711-a09e-48bc13f53473
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163509654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.163509654
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.442062270
Short name T913
Test name
Test status
Simulation time 754245219 ps
CPU time 2.45 seconds
Started Apr 30 03:15:32 PM PDT 24
Finished Apr 30 03:15:35 PM PDT 24
Peak memory 198884 kb
Host smart-4baf3f2e-d16a-4897-93a7-0b438872248c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442062270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.442062270
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.1665101061
Short name T102
Test name
Test status
Simulation time 154466897763 ps
CPU time 99.52 seconds
Started Apr 30 03:15:23 PM PDT 24
Finished Apr 30 03:17:03 PM PDT 24
Peak memory 200436 kb
Host smart-4b489022-85d9-4178-b95e-ac88c8d1ad8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665101061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.1665101061
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.1925288655
Short name T950
Test name
Test status
Simulation time 69307271 ps
CPU time 0.54 seconds
Started Apr 30 03:15:35 PM PDT 24
Finished Apr 30 03:15:36 PM PDT 24
Peak memory 195780 kb
Host smart-c18ab987-3f9f-43a9-8ae2-299e7e19922f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925288655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.1925288655
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.2914983504
Short name T815
Test name
Test status
Simulation time 127377161893 ps
CPU time 49.62 seconds
Started Apr 30 03:15:31 PM PDT 24
Finished Apr 30 03:16:21 PM PDT 24
Peak memory 200400 kb
Host smart-94c420f1-c491-465a-9cd4-fcfa68ea41b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914983504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.2914983504
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.3881792990
Short name T534
Test name
Test status
Simulation time 129799566235 ps
CPU time 53.58 seconds
Started Apr 30 03:15:28 PM PDT 24
Finished Apr 30 03:16:22 PM PDT 24
Peak memory 200364 kb
Host smart-5af75c86-a2cb-40b2-9804-43aff2041ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881792990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.3881792990
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.486074549
Short name T589
Test name
Test status
Simulation time 17253727363 ps
CPU time 31.77 seconds
Started Apr 30 03:15:28 PM PDT 24
Finished Apr 30 03:16:00 PM PDT 24
Peak memory 200404 kb
Host smart-264489f4-d6c3-46f9-aff9-de33c31e2c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486074549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.486074549
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.1504245804
Short name T680
Test name
Test status
Simulation time 7433891822 ps
CPU time 4.79 seconds
Started Apr 30 03:15:28 PM PDT 24
Finished Apr 30 03:15:33 PM PDT 24
Peak memory 196996 kb
Host smart-a9133e1a-2718-481b-84e2-3c4ef5a610ad
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504245804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.1504245804
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.2923515886
Short name T569
Test name
Test status
Simulation time 127746302065 ps
CPU time 243.65 seconds
Started Apr 30 03:15:35 PM PDT 24
Finished Apr 30 03:19:40 PM PDT 24
Peak memory 200404 kb
Host smart-2f631818-ce1c-4484-9858-51336e02840e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2923515886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.2923515886
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.2163708733
Short name T1077
Test name
Test status
Simulation time 7143225417 ps
CPU time 5.25 seconds
Started Apr 30 03:15:37 PM PDT 24
Finished Apr 30 03:15:43 PM PDT 24
Peak memory 199676 kb
Host smart-2f9d4073-512f-4bf0-93a2-f94ff61683a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163708733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.2163708733
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.952824556
Short name T713
Test name
Test status
Simulation time 98082138226 ps
CPU time 57.14 seconds
Started Apr 30 03:15:30 PM PDT 24
Finished Apr 30 03:16:28 PM PDT 24
Peak memory 199760 kb
Host smart-5c765412-5a1d-4b4e-bc79-ea02a8bde520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952824556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.952824556
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.49925043
Short name T270
Test name
Test status
Simulation time 32200714908 ps
CPU time 454.74 seconds
Started Apr 30 03:15:37 PM PDT 24
Finished Apr 30 03:23:13 PM PDT 24
Peak memory 200380 kb
Host smart-05d458fc-caab-4445-a4a8-a42679d730f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=49925043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.49925043
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.3041168949
Short name T530
Test name
Test status
Simulation time 3502886985 ps
CPU time 8.64 seconds
Started Apr 30 03:15:32 PM PDT 24
Finished Apr 30 03:15:41 PM PDT 24
Peak memory 199244 kb
Host smart-4a42921d-b9b8-4707-9bca-4b4b8fdc600a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3041168949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.3041168949
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.2407790503
Short name T154
Test name
Test status
Simulation time 127897556122 ps
CPU time 20.66 seconds
Started Apr 30 03:15:28 PM PDT 24
Finished Apr 30 03:15:49 PM PDT 24
Peak memory 200400 kb
Host smart-f0572c1e-f64e-4919-a375-88ccf8e58f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407790503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.2407790503
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.3520662784
Short name T868
Test name
Test status
Simulation time 4803465414 ps
CPU time 1.33 seconds
Started Apr 30 03:15:27 PM PDT 24
Finished Apr 30 03:15:29 PM PDT 24
Peak memory 196376 kb
Host smart-8b066317-70ef-45df-a4df-80590d665c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520662784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3520662784
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.2908015941
Short name T1147
Test name
Test status
Simulation time 672977998 ps
CPU time 2.02 seconds
Started Apr 30 03:15:29 PM PDT 24
Finished Apr 30 03:15:32 PM PDT 24
Peak memory 199104 kb
Host smart-9c3e8bf0-90d5-4d81-b7e8-dafbd04e7e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908015941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.2908015941
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.497393311
Short name T828
Test name
Test status
Simulation time 458111861070 ps
CPU time 622.76 seconds
Started Apr 30 03:15:37 PM PDT 24
Finished Apr 30 03:26:00 PM PDT 24
Peak memory 200624 kb
Host smart-1148a05c-760d-4f4d-8ba2-76234b84ab12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497393311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.497393311
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.1353305860
Short name T231
Test name
Test status
Simulation time 128016315861 ps
CPU time 329.46 seconds
Started Apr 30 03:15:37 PM PDT 24
Finished Apr 30 03:21:08 PM PDT 24
Peak memory 225296 kb
Host smart-89083731-1087-4bb5-9b98-793a10d67ed5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353305860 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.1353305860
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.3262425095
Short name T404
Test name
Test status
Simulation time 229424193 ps
CPU time 1.13 seconds
Started Apr 30 03:15:37 PM PDT 24
Finished Apr 30 03:15:38 PM PDT 24
Peak memory 198560 kb
Host smart-4b22cf12-3f8c-4efa-a1b6-8646f64c43cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262425095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.3262425095
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.1672246210
Short name T870
Test name
Test status
Simulation time 82136532230 ps
CPU time 40.02 seconds
Started Apr 30 03:15:29 PM PDT 24
Finished Apr 30 03:16:10 PM PDT 24
Peak memory 200400 kb
Host smart-d993f4d8-07aa-44b9-b96a-a5ee9f5d0ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672246210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.1672246210
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.2785418616
Short name T806
Test name
Test status
Simulation time 75532577 ps
CPU time 0.54 seconds
Started Apr 30 03:15:43 PM PDT 24
Finished Apr 30 03:15:44 PM PDT 24
Peak memory 195196 kb
Host smart-09550440-90c3-426d-bbbb-5970d4557802
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785418616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.2785418616
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.2665592987
Short name T414
Test name
Test status
Simulation time 125958583227 ps
CPU time 60.92 seconds
Started Apr 30 03:15:37 PM PDT 24
Finished Apr 30 03:16:39 PM PDT 24
Peak memory 200400 kb
Host smart-479ed779-759b-4e9f-a3cb-c0a12b59beda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665592987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.2665592987
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.3807511208
Short name T617
Test name
Test status
Simulation time 109346128302 ps
CPU time 141.39 seconds
Started Apr 30 03:15:37 PM PDT 24
Finished Apr 30 03:17:59 PM PDT 24
Peak memory 200376 kb
Host smart-96683354-968c-4b92-bf39-0e0ee5aa7da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807511208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.3807511208
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.3635139643
Short name T1014
Test name
Test status
Simulation time 64476333971 ps
CPU time 15.85 seconds
Started Apr 30 03:15:37 PM PDT 24
Finished Apr 30 03:15:53 PM PDT 24
Peak memory 200416 kb
Host smart-a6d66720-8f28-4ad0-9dba-4f9fb4830f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635139643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.3635139643
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.3567533583
Short name T925
Test name
Test status
Simulation time 44268552236 ps
CPU time 71.57 seconds
Started Apr 30 03:15:36 PM PDT 24
Finished Apr 30 03:16:48 PM PDT 24
Peak memory 199440 kb
Host smart-b5e6ef58-eebe-4bac-98d7-90df4b89ce1c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567533583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.3567533583
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.3218129391
Short name T380
Test name
Test status
Simulation time 150787335637 ps
CPU time 236.15 seconds
Started Apr 30 03:15:41 PM PDT 24
Finished Apr 30 03:19:38 PM PDT 24
Peak memory 200364 kb
Host smart-7a0bbde8-fdf6-4b47-8323-9e80ac5b126d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3218129391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3218129391
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.1543110425
Short name T353
Test name
Test status
Simulation time 12604699129 ps
CPU time 4.86 seconds
Started Apr 30 03:15:36 PM PDT 24
Finished Apr 30 03:15:41 PM PDT 24
Peak memory 200388 kb
Host smart-e4377467-5dda-42fc-8d34-e7b3bb8013a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543110425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.1543110425
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.1669700838
Short name T101
Test name
Test status
Simulation time 34597889276 ps
CPU time 58.78 seconds
Started Apr 30 03:15:40 PM PDT 24
Finished Apr 30 03:16:39 PM PDT 24
Peak memory 199288 kb
Host smart-98ef50da-7b08-4c65-a9a7-92c33f2ee7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669700838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.1669700838
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.3678539603
Short name T978
Test name
Test status
Simulation time 25390705340 ps
CPU time 301.51 seconds
Started Apr 30 03:15:44 PM PDT 24
Finished Apr 30 03:20:46 PM PDT 24
Peak memory 200376 kb
Host smart-e000f87f-3f9e-4217-b86e-5492605d206f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3678539603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.3678539603
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.3886618242
Short name T736
Test name
Test status
Simulation time 2757503278 ps
CPU time 16.64 seconds
Started Apr 30 03:15:35 PM PDT 24
Finished Apr 30 03:15:52 PM PDT 24
Peak memory 198568 kb
Host smart-daa73810-ce3b-44a4-bae8-64661cfdec8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3886618242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.3886618242
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.1269216407
Short name T605
Test name
Test status
Simulation time 114569483671 ps
CPU time 71.3 seconds
Started Apr 30 03:15:36 PM PDT 24
Finished Apr 30 03:16:48 PM PDT 24
Peak memory 200408 kb
Host smart-557fa013-d9d9-4531-9395-73352e6ce3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269216407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.1269216407
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.220329790
Short name T991
Test name
Test status
Simulation time 35950127720 ps
CPU time 55.91 seconds
Started Apr 30 03:15:37 PM PDT 24
Finished Apr 30 03:16:33 PM PDT 24
Peak memory 196452 kb
Host smart-a1831a0c-1ad3-47d8-9df4-adfe7da03f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220329790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.220329790
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.74325062
Short name T557
Test name
Test status
Simulation time 444230696 ps
CPU time 1.34 seconds
Started Apr 30 03:15:35 PM PDT 24
Finished Apr 30 03:15:37 PM PDT 24
Peak memory 199248 kb
Host smart-1e658cdc-d203-4b85-959e-bd279b19287a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74325062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.74325062
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.3889508339
Short name T305
Test name
Test status
Simulation time 218027590083 ps
CPU time 374.7 seconds
Started Apr 30 03:15:44 PM PDT 24
Finished Apr 30 03:22:00 PM PDT 24
Peak memory 208800 kb
Host smart-479843a7-eb53-404e-a0ef-0d52783e4dc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889508339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.3889508339
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.1158437377
Short name T745
Test name
Test status
Simulation time 714417033 ps
CPU time 2.13 seconds
Started Apr 30 03:15:36 PM PDT 24
Finished Apr 30 03:15:39 PM PDT 24
Peak memory 198684 kb
Host smart-c2c5e434-c5b1-43d2-9890-0deaa6c32556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158437377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.1158437377
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.3185490115
Short name T548
Test name
Test status
Simulation time 134358869427 ps
CPU time 325.74 seconds
Started Apr 30 03:15:37 PM PDT 24
Finished Apr 30 03:21:03 PM PDT 24
Peak memory 200412 kb
Host smart-6168bc20-7c94-436c-b01b-cd8fc81c3800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185490115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.3185490115
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.96999030
Short name T614
Test name
Test status
Simulation time 27150132 ps
CPU time 0.55 seconds
Started Apr 30 03:15:47 PM PDT 24
Finished Apr 30 03:15:48 PM PDT 24
Peak memory 195820 kb
Host smart-b3e07821-f623-4e5e-97a7-eb1c1567a9a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96999030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.96999030
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.260799627
Short name T146
Test name
Test status
Simulation time 104009444444 ps
CPU time 24.7 seconds
Started Apr 30 03:15:45 PM PDT 24
Finished Apr 30 03:16:10 PM PDT 24
Peak memory 200380 kb
Host smart-576a2853-0b4b-48dc-be76-938831f75837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260799627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.260799627
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.3335221355
Short name T1008
Test name
Test status
Simulation time 75748584496 ps
CPU time 163.57 seconds
Started Apr 30 03:15:43 PM PDT 24
Finished Apr 30 03:18:27 PM PDT 24
Peak memory 200304 kb
Host smart-e55628c4-2b50-4691-963d-fb15876c137f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335221355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.3335221355
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.2239884208
Short name T644
Test name
Test status
Simulation time 189287405090 ps
CPU time 311.9 seconds
Started Apr 30 03:15:42 PM PDT 24
Finished Apr 30 03:20:55 PM PDT 24
Peak memory 200348 kb
Host smart-a7b1236e-6e5e-41ad-8889-80e1b51b09ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239884208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.2239884208
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.2375345428
Short name T995
Test name
Test status
Simulation time 32432518883 ps
CPU time 15.51 seconds
Started Apr 30 03:15:43 PM PDT 24
Finished Apr 30 03:15:59 PM PDT 24
Peak memory 200444 kb
Host smart-d5ed9e56-18fb-43e7-bcc2-83803a6ecbb1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375345428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.2375345428
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.4145617739
Short name T428
Test name
Test status
Simulation time 115373528520 ps
CPU time 617.6 seconds
Started Apr 30 03:15:43 PM PDT 24
Finished Apr 30 03:26:01 PM PDT 24
Peak memory 200444 kb
Host smart-ac0dd3ff-6abe-4686-83a5-d29f4d7171af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4145617739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.4145617739
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.587156647
Short name T1059
Test name
Test status
Simulation time 4311749529 ps
CPU time 7.92 seconds
Started Apr 30 03:15:46 PM PDT 24
Finished Apr 30 03:15:54 PM PDT 24
Peak memory 199924 kb
Host smart-84e42e1f-14c8-45c6-b9e8-34474e889dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587156647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.587156647
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.784232576
Short name T307
Test name
Test status
Simulation time 17958461915 ps
CPU time 17.77 seconds
Started Apr 30 03:15:42 PM PDT 24
Finished Apr 30 03:16:01 PM PDT 24
Peak memory 200592 kb
Host smart-1b65e342-9fd8-46e6-8e71-32eac0158072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784232576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.784232576
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.2656937028
Short name T922
Test name
Test status
Simulation time 7238915984 ps
CPU time 104.05 seconds
Started Apr 30 03:15:43 PM PDT 24
Finished Apr 30 03:17:28 PM PDT 24
Peak memory 200400 kb
Host smart-9054e37d-7ead-4518-b0ef-3ebd6d2d7296
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2656937028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.2656937028
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.605186082
Short name T1032
Test name
Test status
Simulation time 1792980293 ps
CPU time 9.35 seconds
Started Apr 30 03:15:42 PM PDT 24
Finished Apr 30 03:15:52 PM PDT 24
Peak memory 199544 kb
Host smart-a1f35870-80e3-47b4-be79-bc632a319c35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=605186082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.605186082
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.1123186506
Short name T1114
Test name
Test status
Simulation time 117152964154 ps
CPU time 138.5 seconds
Started Apr 30 03:15:44 PM PDT 24
Finished Apr 30 03:18:03 PM PDT 24
Peak memory 200412 kb
Host smart-27b977b5-f3e6-4367-ad60-aa4683c54ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123186506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.1123186506
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.229558594
Short name T1080
Test name
Test status
Simulation time 2075437902 ps
CPU time 3.8 seconds
Started Apr 30 03:15:43 PM PDT 24
Finished Apr 30 03:15:48 PM PDT 24
Peak memory 195764 kb
Host smart-51f4cec3-6469-4322-b0b6-b5d62ed017e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229558594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.229558594
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.2542861662
Short name T954
Test name
Test status
Simulation time 942830833 ps
CPU time 1.58 seconds
Started Apr 30 03:15:45 PM PDT 24
Finished Apr 30 03:15:47 PM PDT 24
Peak memory 199024 kb
Host smart-6a2c797c-e079-4973-b6d6-51fed36d54d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542861662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.2542861662
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.3317010130
Short name T273
Test name
Test status
Simulation time 924239241 ps
CPU time 2.21 seconds
Started Apr 30 03:15:46 PM PDT 24
Finished Apr 30 03:15:48 PM PDT 24
Peak memory 200316 kb
Host smart-4078a66d-6e3e-448e-bc63-a372780467c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317010130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.3317010130
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.1132003656
Short name T431
Test name
Test status
Simulation time 60483912150 ps
CPU time 115.9 seconds
Started Apr 30 03:15:44 PM PDT 24
Finished Apr 30 03:17:41 PM PDT 24
Peak memory 200372 kb
Host smart-e09a234c-23d0-4866-8d3d-8fbc5861227d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132003656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.1132003656
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.3219421796
Short name T486
Test name
Test status
Simulation time 13526671 ps
CPU time 0.56 seconds
Started Apr 30 03:15:51 PM PDT 24
Finished Apr 30 03:15:52 PM PDT 24
Peak memory 195820 kb
Host smart-75123507-14e5-4fb5-8a3e-84e6f8784256
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219421796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.3219421796
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.1755753336
Short name T701
Test name
Test status
Simulation time 140376912664 ps
CPU time 65.78 seconds
Started Apr 30 03:15:53 PM PDT 24
Finished Apr 30 03:16:59 PM PDT 24
Peak memory 200420 kb
Host smart-d9a1655c-09ea-4c84-95cc-56fd827036e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755753336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.1755753336
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.2452927309
Short name T84
Test name
Test status
Simulation time 43673524048 ps
CPU time 70.33 seconds
Started Apr 30 03:15:47 PM PDT 24
Finished Apr 30 03:16:58 PM PDT 24
Peak memory 200292 kb
Host smart-2aa9aee4-a53f-4dbf-8525-821cb784dcce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452927309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.2452927309
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.1194103543
Short name T120
Test name
Test status
Simulation time 8112618208 ps
CPU time 14.16 seconds
Started Apr 30 03:15:44 PM PDT 24
Finished Apr 30 03:15:59 PM PDT 24
Peak memory 200392 kb
Host smart-14cff1f8-0c78-41c5-9107-28155db70622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194103543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.1194103543
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.4150818946
Short name T130
Test name
Test status
Simulation time 39235579810 ps
CPU time 13.27 seconds
Started Apr 30 03:15:44 PM PDT 24
Finished Apr 30 03:15:58 PM PDT 24
Peak memory 199552 kb
Host smart-38e532d9-29c7-4bc4-84ae-5bd6798f0988
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150818946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.4150818946
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.1439609773
Short name T1183
Test name
Test status
Simulation time 122191775470 ps
CPU time 532.92 seconds
Started Apr 30 03:15:50 PM PDT 24
Finished Apr 30 03:24:43 PM PDT 24
Peak memory 200408 kb
Host smart-947a1262-5c12-4745-93e3-212b26c41d0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1439609773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.1439609773
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.2367019463
Short name T1063
Test name
Test status
Simulation time 9007974944 ps
CPU time 32.65 seconds
Started Apr 30 03:15:58 PM PDT 24
Finished Apr 30 03:16:31 PM PDT 24
Peak memory 199884 kb
Host smart-07abda63-cb5e-4c2f-8c68-d98d7b6f832b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367019463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.2367019463
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.3447748888
Short name T340
Test name
Test status
Simulation time 249193300 ps
CPU time 0.99 seconds
Started Apr 30 03:15:51 PM PDT 24
Finished Apr 30 03:15:52 PM PDT 24
Peak memory 194928 kb
Host smart-fc60e877-9296-4f1a-b924-d7ec781fdce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447748888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.3447748888
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.2668692145
Short name T944
Test name
Test status
Simulation time 12478682724 ps
CPU time 205.78 seconds
Started Apr 30 03:15:50 PM PDT 24
Finished Apr 30 03:19:16 PM PDT 24
Peak memory 200284 kb
Host smart-212cfac4-9f9d-491d-a814-f0ce3d368418
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2668692145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2668692145
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.2543205867
Short name T350
Test name
Test status
Simulation time 2201013636 ps
CPU time 12.55 seconds
Started Apr 30 03:15:44 PM PDT 24
Finished Apr 30 03:15:57 PM PDT 24
Peak memory 198492 kb
Host smart-1826a901-1190-4e66-9c91-df9ff9e84d3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2543205867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.2543205867
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.782238621
Short name T1130
Test name
Test status
Simulation time 81987047808 ps
CPU time 191.8 seconds
Started Apr 30 03:15:57 PM PDT 24
Finished Apr 30 03:19:10 PM PDT 24
Peak memory 200396 kb
Host smart-397d7fa2-4bcb-448a-b0b2-2c8b33e19786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782238621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.782238621
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.10978474
Short name T802
Test name
Test status
Simulation time 77041468757 ps
CPU time 138.56 seconds
Started Apr 30 03:15:48 PM PDT 24
Finished Apr 30 03:18:07 PM PDT 24
Peak memory 196172 kb
Host smart-6bf97ea3-201d-4117-ba1b-95ab64fc85c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10978474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.10978474
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.1865774883
Short name T1161
Test name
Test status
Simulation time 833042380 ps
CPU time 1.95 seconds
Started Apr 30 03:15:44 PM PDT 24
Finished Apr 30 03:15:46 PM PDT 24
Peak memory 199208 kb
Host smart-38eb9373-eb50-4eae-b090-5b1177a2b267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865774883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.1865774883
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.3745791869
Short name T679
Test name
Test status
Simulation time 324638693855 ps
CPU time 837.02 seconds
Started Apr 30 03:15:51 PM PDT 24
Finished Apr 30 03:29:49 PM PDT 24
Peak memory 200624 kb
Host smart-417abc45-2b92-4881-84de-fcfdaaa8bece
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745791869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.3745791869
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.2201288004
Short name T587
Test name
Test status
Simulation time 154972340454 ps
CPU time 674.93 seconds
Started Apr 30 03:15:51 PM PDT 24
Finished Apr 30 03:27:06 PM PDT 24
Peak memory 225164 kb
Host smart-27939e95-5e7f-4406-94de-b3be76f5d6de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201288004 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.2201288004
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.3790747003
Short name T646
Test name
Test status
Simulation time 731311488 ps
CPU time 1.95 seconds
Started Apr 30 03:15:52 PM PDT 24
Finished Apr 30 03:15:55 PM PDT 24
Peak memory 198776 kb
Host smart-10050435-7ca2-4ca0-a0a8-59818d830104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790747003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.3790747003
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.1731383856
Short name T830
Test name
Test status
Simulation time 63325494318 ps
CPU time 165.15 seconds
Started Apr 30 03:15:53 PM PDT 24
Finished Apr 30 03:18:39 PM PDT 24
Peak memory 200436 kb
Host smart-b761e2a1-3f14-4e7a-9b6d-16ccec280492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731383856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.1731383856
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.2119990484
Short name T684
Test name
Test status
Simulation time 12885414 ps
CPU time 0.54 seconds
Started Apr 30 03:15:56 PM PDT 24
Finished Apr 30 03:15:58 PM PDT 24
Peak memory 194752 kb
Host smart-fa1c5a02-da24-4290-8b36-3480cf838cd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119990484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.2119990484
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.4221949466
Short name T460
Test name
Test status
Simulation time 107207064518 ps
CPU time 46.21 seconds
Started Apr 30 03:15:51 PM PDT 24
Finished Apr 30 03:16:38 PM PDT 24
Peak memory 200364 kb
Host smart-d96e0b59-20f6-4898-836b-ee079c879bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221949466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.4221949466
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.1639527449
Short name T173
Test name
Test status
Simulation time 123364372127 ps
CPU time 16.92 seconds
Started Apr 30 03:15:56 PM PDT 24
Finished Apr 30 03:16:13 PM PDT 24
Peak memory 200400 kb
Host smart-5c1f24c2-d980-4a10-ae78-7a24df31cf92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639527449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.1639527449
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.3023178374
Short name T223
Test name
Test status
Simulation time 112851219963 ps
CPU time 176.04 seconds
Started Apr 30 03:15:58 PM PDT 24
Finished Apr 30 03:18:55 PM PDT 24
Peak memory 200396 kb
Host smart-21fc45e0-4a19-4d3a-a27c-9da5847b2d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023178374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.3023178374
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.1316330695
Short name T903
Test name
Test status
Simulation time 18169303492 ps
CPU time 8.15 seconds
Started Apr 30 03:15:56 PM PDT 24
Finished Apr 30 03:16:04 PM PDT 24
Peak memory 197572 kb
Host smart-6a420e01-9d3a-4282-871a-9d870578d883
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316330695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.1316330695
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.142797509
Short name T310
Test name
Test status
Simulation time 59245765972 ps
CPU time 429.7 seconds
Started Apr 30 03:15:56 PM PDT 24
Finished Apr 30 03:23:06 PM PDT 24
Peak memory 200464 kb
Host smart-e8732e9f-3b0e-4308-854f-d59a38ee34fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=142797509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.142797509
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.2230950642
Short name T368
Test name
Test status
Simulation time 9571690249 ps
CPU time 19.14 seconds
Started Apr 30 03:15:58 PM PDT 24
Finished Apr 30 03:16:18 PM PDT 24
Peak memory 199320 kb
Host smart-11b17c77-5c57-4497-b72e-f6e0d0e54c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230950642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.2230950642
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.2271861554
Short name T320
Test name
Test status
Simulation time 35848460293 ps
CPU time 13.22 seconds
Started Apr 30 03:15:50 PM PDT 24
Finished Apr 30 03:16:04 PM PDT 24
Peak memory 200400 kb
Host smart-01a7d64b-9bcd-4a09-8bf4-70be2432f76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271861554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.2271861554
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.3374519250
Short name T384
Test name
Test status
Simulation time 7489535983 ps
CPU time 110.73 seconds
Started Apr 30 03:15:56 PM PDT 24
Finished Apr 30 03:17:47 PM PDT 24
Peak memory 200364 kb
Host smart-cf7e18da-2f87-4886-a713-4ed10d265743
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3374519250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.3374519250
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.2167397882
Short name T346
Test name
Test status
Simulation time 3283832234 ps
CPU time 11.94 seconds
Started Apr 30 03:15:52 PM PDT 24
Finished Apr 30 03:16:04 PM PDT 24
Peak memory 199416 kb
Host smart-dcad5cd6-05a6-4552-ac4f-26b66c0d0ba8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2167397882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.2167397882
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.609012515
Short name T959
Test name
Test status
Simulation time 63257904312 ps
CPU time 66.13 seconds
Started Apr 30 03:15:58 PM PDT 24
Finished Apr 30 03:17:05 PM PDT 24
Peak memory 200436 kb
Host smart-821ce528-bfd9-468d-9620-ad34db5679b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609012515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.609012515
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.2628421376
Short name T424
Test name
Test status
Simulation time 25309313335 ps
CPU time 44.27 seconds
Started Apr 30 03:15:50 PM PDT 24
Finished Apr 30 03:16:35 PM PDT 24
Peak memory 196448 kb
Host smart-f1b0933b-02bc-4b04-b1be-9d46c028e996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628421376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.2628421376
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.1658213054
Short name T1054
Test name
Test status
Simulation time 506817641 ps
CPU time 1.82 seconds
Started Apr 30 03:15:49 PM PDT 24
Finished Apr 30 03:15:51 PM PDT 24
Peak memory 200052 kb
Host smart-5ca5c53b-5557-4a3e-866e-1d55f700025e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658213054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.1658213054
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.1983165812
Short name T877
Test name
Test status
Simulation time 99865081410 ps
CPU time 26.39 seconds
Started Apr 30 03:15:57 PM PDT 24
Finished Apr 30 03:16:24 PM PDT 24
Peak memory 200388 kb
Host smart-dfea2aa3-f84b-476f-a53a-d3adc74617d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983165812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.1983165812
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.2362847349
Short name T328
Test name
Test status
Simulation time 62431448744 ps
CPU time 967.9 seconds
Started Apr 30 03:16:00 PM PDT 24
Finished Apr 30 03:32:09 PM PDT 24
Peak memory 231660 kb
Host smart-db2b1842-3de9-4e5a-a011-b225f41a9765
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362847349 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.2362847349
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.3836123597
Short name T315
Test name
Test status
Simulation time 593616721 ps
CPU time 1.45 seconds
Started Apr 30 03:16:00 PM PDT 24
Finished Apr 30 03:16:02 PM PDT 24
Peak memory 198792 kb
Host smart-594d6923-2d26-462a-a165-64939082f446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836123597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.3836123597
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.3431251702
Short name T977
Test name
Test status
Simulation time 87752613144 ps
CPU time 40.44 seconds
Started Apr 30 03:15:57 PM PDT 24
Finished Apr 30 03:16:38 PM PDT 24
Peak memory 200436 kb
Host smart-3ee218a5-21c1-4cbf-8166-5312f2b7eda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431251702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.3431251702
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.1902419851
Short name T790
Test name
Test status
Simulation time 16961181 ps
CPU time 0.57 seconds
Started Apr 30 03:11:36 PM PDT 24
Finished Apr 30 03:11:37 PM PDT 24
Peak memory 195792 kb
Host smart-7fa86953-6878-4d02-95fb-02df10232388
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902419851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.1902419851
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1351599142
Short name T630
Test name
Test status
Simulation time 93189270460 ps
CPU time 79.29 seconds
Started Apr 30 03:11:28 PM PDT 24
Finished Apr 30 03:12:48 PM PDT 24
Peak memory 200388 kb
Host smart-940c02a9-907b-404f-ac47-73451b20151e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351599142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1351599142
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.2312462271
Short name T956
Test name
Test status
Simulation time 152239161597 ps
CPU time 181.76 seconds
Started Apr 30 03:11:27 PM PDT 24
Finished Apr 30 03:14:29 PM PDT 24
Peak memory 200440 kb
Host smart-662dac51-704b-482a-a153-5edc45e2afbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312462271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.2312462271
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.3733475057
Short name T866
Test name
Test status
Simulation time 88691786618 ps
CPU time 131.5 seconds
Started Apr 30 03:11:27 PM PDT 24
Finished Apr 30 03:13:40 PM PDT 24
Peak memory 200432 kb
Host smart-c04c627b-2a86-45c5-bf58-d7114fecc752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733475057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.3733475057
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.2563694765
Short name T1180
Test name
Test status
Simulation time 11056263313 ps
CPU time 11.47 seconds
Started Apr 30 03:11:26 PM PDT 24
Finished Apr 30 03:11:38 PM PDT 24
Peak memory 200408 kb
Host smart-46cfff8a-c3c7-41b1-9df2-dcaf800a8d35
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563694765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.2563694765
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.363963834
Short name T1042
Test name
Test status
Simulation time 65443167871 ps
CPU time 211.47 seconds
Started Apr 30 03:11:34 PM PDT 24
Finished Apr 30 03:15:06 PM PDT 24
Peak memory 200348 kb
Host smart-9d80ffde-449b-456d-9591-13e81402464b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=363963834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.363963834
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.814068433
Short name T463
Test name
Test status
Simulation time 4847516688 ps
CPU time 4.99 seconds
Started Apr 30 03:11:34 PM PDT 24
Finished Apr 30 03:11:39 PM PDT 24
Peak memory 199332 kb
Host smart-54f5cc1f-3656-493a-b2ce-fd92520901d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814068433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.814068433
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.2716793362
Short name T657
Test name
Test status
Simulation time 137836617529 ps
CPU time 57.66 seconds
Started Apr 30 03:11:35 PM PDT 24
Finished Apr 30 03:12:34 PM PDT 24
Peak memory 199140 kb
Host smart-b00372b4-a3d9-464d-abb3-3d9092173c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716793362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.2716793362
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.2300971345
Short name T265
Test name
Test status
Simulation time 12852900336 ps
CPU time 129.22 seconds
Started Apr 30 03:11:36 PM PDT 24
Finished Apr 30 03:13:46 PM PDT 24
Peak memory 200448 kb
Host smart-78ada0c6-0468-4a72-9a6f-1d2cdbf1a879
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2300971345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2300971345
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.449637166
Short name T1048
Test name
Test status
Simulation time 2481588575 ps
CPU time 9.01 seconds
Started Apr 30 03:11:26 PM PDT 24
Finished Apr 30 03:11:35 PM PDT 24
Peak memory 198768 kb
Host smart-9eb66f06-7be8-4c51-84d9-674cdfb65e74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=449637166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.449637166
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.710488145
Short name T184
Test name
Test status
Simulation time 135364003288 ps
CPU time 247.8 seconds
Started Apr 30 03:11:35 PM PDT 24
Finished Apr 30 03:15:43 PM PDT 24
Peak memory 200404 kb
Host smart-e544c9ac-f235-4846-a376-a127005587f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710488145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.710488145
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.4290870786
Short name T299
Test name
Test status
Simulation time 1637694759 ps
CPU time 2.72 seconds
Started Apr 30 03:11:36 PM PDT 24
Finished Apr 30 03:11:39 PM PDT 24
Peak memory 195736 kb
Host smart-4a428035-82b9-4a65-b599-a0b44891fdbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290870786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.4290870786
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.1580400265
Short name T528
Test name
Test status
Simulation time 646974497 ps
CPU time 1.44 seconds
Started Apr 30 03:11:29 PM PDT 24
Finished Apr 30 03:11:31 PM PDT 24
Peak memory 199880 kb
Host smart-99e9ca3d-9b5f-40bc-9610-23922b3171b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580400265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1580400265
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.1835762518
Short name T179
Test name
Test status
Simulation time 177447812610 ps
CPU time 158.92 seconds
Started Apr 30 03:11:34 PM PDT 24
Finished Apr 30 03:14:14 PM PDT 24
Peak memory 200396 kb
Host smart-bef241a5-23c3-4b92-b144-49d370db6687
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835762518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.1835762518
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.523643024
Short name T119
Test name
Test status
Simulation time 78680763052 ps
CPU time 535.5 seconds
Started Apr 30 03:11:36 PM PDT 24
Finished Apr 30 03:20:32 PM PDT 24
Peak memory 210948 kb
Host smart-c1ac442c-fe41-430b-94fa-b96ee80173cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523643024 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.523643024
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.2633766997
Short name T314
Test name
Test status
Simulation time 6560169399 ps
CPU time 7.44 seconds
Started Apr 30 03:11:35 PM PDT 24
Finished Apr 30 03:11:43 PM PDT 24
Peak memory 200376 kb
Host smart-ea2f44a1-cd22-41bb-8992-7ab226a35d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633766997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.2633766997
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.1823413828
Short name T750
Test name
Test status
Simulation time 23475032347 ps
CPU time 20.82 seconds
Started Apr 30 03:11:26 PM PDT 24
Finished Apr 30 03:11:48 PM PDT 24
Peak memory 200432 kb
Host smart-3e4f1a72-0f20-4b34-b35e-b992ef7e8cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823413828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.1823413828
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.2827984286
Short name T417
Test name
Test status
Simulation time 10109653029 ps
CPU time 24.93 seconds
Started Apr 30 03:15:56 PM PDT 24
Finished Apr 30 03:16:21 PM PDT 24
Peak memory 200428 kb
Host smart-2979b7a7-4809-4c02-9f3f-819c6c680302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827984286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.2827984286
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.973120116
Short name T508
Test name
Test status
Simulation time 81470962842 ps
CPU time 485.95 seconds
Started Apr 30 03:15:56 PM PDT 24
Finished Apr 30 03:24:02 PM PDT 24
Peak memory 225284 kb
Host smart-42da96df-621e-4ec9-ba8f-480226d0c6e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973120116 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.973120116
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.391951866
Short name T1062
Test name
Test status
Simulation time 33523134001 ps
CPU time 13.81 seconds
Started Apr 30 03:15:56 PM PDT 24
Finished Apr 30 03:16:10 PM PDT 24
Peak memory 199840 kb
Host smart-6e225029-4a5c-4f47-b2fc-5ea88f257749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391951866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.391951866
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.1688799844
Short name T493
Test name
Test status
Simulation time 88933115572 ps
CPU time 1009.64 seconds
Started Apr 30 03:15:56 PM PDT 24
Finished Apr 30 03:32:47 PM PDT 24
Peak memory 225268 kb
Host smart-b9e25bfd-cc39-42eb-8063-3315465b5130
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688799844 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.1688799844
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.1621974842
Short name T1009
Test name
Test status
Simulation time 198459636961 ps
CPU time 327.6 seconds
Started Apr 30 03:15:57 PM PDT 24
Finished Apr 30 03:21:25 PM PDT 24
Peak memory 200456 kb
Host smart-089d93f3-d205-4622-b1d3-58d4cd8c54df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621974842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.1621974842
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.3624462555
Short name T329
Test name
Test status
Simulation time 90465636333 ps
CPU time 286.77 seconds
Started Apr 30 03:15:57 PM PDT 24
Finished Apr 30 03:20:44 PM PDT 24
Peak memory 217040 kb
Host smart-eadc26f1-c0c8-4576-828b-4c5a7af43eda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624462555 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.3624462555
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.3067403163
Short name T300
Test name
Test status
Simulation time 85356064650 ps
CPU time 154.11 seconds
Started Apr 30 03:15:56 PM PDT 24
Finished Apr 30 03:18:31 PM PDT 24
Peak memory 200576 kb
Host smart-bdf84248-3faa-4e28-a56b-eec761f366ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067403163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.3067403163
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.3617653474
Short name T113
Test name
Test status
Simulation time 79503543263 ps
CPU time 739.15 seconds
Started Apr 30 03:15:59 PM PDT 24
Finished Apr 30 03:28:19 PM PDT 24
Peak memory 216680 kb
Host smart-41361604-ddb6-409f-a0b2-e5eb44ff531c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617653474 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.3617653474
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.2458238735
Short name T150
Test name
Test status
Simulation time 39694468605 ps
CPU time 56.38 seconds
Started Apr 30 03:15:59 PM PDT 24
Finished Apr 30 03:16:56 PM PDT 24
Peak memory 199972 kb
Host smart-d2274669-9a3c-442e-bb48-a893497a610e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458238735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.2458238735
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.2469538435
Short name T600
Test name
Test status
Simulation time 20094155799 ps
CPU time 34.56 seconds
Started Apr 30 03:15:55 PM PDT 24
Finished Apr 30 03:16:30 PM PDT 24
Peak memory 200388 kb
Host smart-1ff9b3e8-1f10-4804-8987-6f9e0c258272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469538435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.2469538435
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.671073212
Short name T737
Test name
Test status
Simulation time 15698493330 ps
CPU time 181.03 seconds
Started Apr 30 03:15:57 PM PDT 24
Finished Apr 30 03:18:58 PM PDT 24
Peak memory 209928 kb
Host smart-4bc286ea-ab7c-480a-98ce-e16b2d538ef6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671073212 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.671073212
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.4046492326
Short name T408
Test name
Test status
Simulation time 12729350895 ps
CPU time 5.28 seconds
Started Apr 30 03:15:58 PM PDT 24
Finished Apr 30 03:16:03 PM PDT 24
Peak memory 200224 kb
Host smart-c27f60dc-1560-4fde-bec7-c3ec94f5812e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046492326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.4046492326
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.3422493154
Short name T1030
Test name
Test status
Simulation time 109191888628 ps
CPU time 679.35 seconds
Started Apr 30 03:16:01 PM PDT 24
Finished Apr 30 03:27:22 PM PDT 24
Peak memory 215128 kb
Host smart-0d57cde7-d15c-4650-ad19-7a1bd29dabe2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422493154 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.3422493154
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.4269605565
Short name T1162
Test name
Test status
Simulation time 22831206689 ps
CPU time 11.2 seconds
Started Apr 30 03:15:56 PM PDT 24
Finished Apr 30 03:16:08 PM PDT 24
Peak memory 200360 kb
Host smart-51ecb4a8-5394-4493-b519-b8c61c62e1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269605565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.4269605565
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.3655063722
Short name T700
Test name
Test status
Simulation time 228835480076 ps
CPU time 109.37 seconds
Started Apr 30 03:16:03 PM PDT 24
Finished Apr 30 03:17:53 PM PDT 24
Peak memory 200432 kb
Host smart-ec469069-1486-457c-bca2-d327e18f9c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655063722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.3655063722
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.1287848089
Short name T1131
Test name
Test status
Simulation time 31737946560 ps
CPU time 84.72 seconds
Started Apr 30 03:16:01 PM PDT 24
Finished Apr 30 03:17:26 PM PDT 24
Peak memory 216040 kb
Host smart-4d4eb7c4-4607-4610-a415-5fd0467cb4e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287848089 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.1287848089
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.2669801974
Short name T225
Test name
Test status
Simulation time 58330128933 ps
CPU time 21.58 seconds
Started Apr 30 03:16:08 PM PDT 24
Finished Apr 30 03:16:30 PM PDT 24
Peak memory 200424 kb
Host smart-5484f3f8-70f6-4b0e-ad68-439b1bd1012e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669801974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.2669801974
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.3909820227
Short name T253
Test name
Test status
Simulation time 420370824917 ps
CPU time 1480.89 seconds
Started Apr 30 03:16:05 PM PDT 24
Finished Apr 30 03:40:47 PM PDT 24
Peak memory 228428 kb
Host smart-8a8a742e-936b-4b0b-b0fe-10074d56f25e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909820227 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.3909820227
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.3994481222
Short name T1095
Test name
Test status
Simulation time 15312640 ps
CPU time 0.59 seconds
Started Apr 30 03:11:41 PM PDT 24
Finished Apr 30 03:11:42 PM PDT 24
Peak memory 195800 kb
Host smart-b797974d-bb1b-42b0-83d9-04c942f0231f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994481222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3994481222
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.2154757260
Short name T342
Test name
Test status
Simulation time 20704399727 ps
CPU time 8.85 seconds
Started Apr 30 03:11:38 PM PDT 24
Finished Apr 30 03:11:47 PM PDT 24
Peak memory 200452 kb
Host smart-ed412ce5-be56-4808-b045-60b2a9ead078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154757260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.2154757260
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.3266496056
Short name T415
Test name
Test status
Simulation time 73215168331 ps
CPU time 109.7 seconds
Started Apr 30 03:11:42 PM PDT 24
Finished Apr 30 03:13:33 PM PDT 24
Peak memory 200376 kb
Host smart-11c1e6d5-7bb8-460c-9cfa-1aa5fe109751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266496056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.3266496056
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.4036174369
Short name T1107
Test name
Test status
Simulation time 66756271653 ps
CPU time 94.67 seconds
Started Apr 30 03:11:41 PM PDT 24
Finished Apr 30 03:13:16 PM PDT 24
Peak memory 200364 kb
Host smart-8407edb9-9186-41ee-98ab-f9c2d5604765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036174369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.4036174369
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.1063649287
Short name T360
Test name
Test status
Simulation time 3756043313 ps
CPU time 5.94 seconds
Started Apr 30 03:11:41 PM PDT 24
Finished Apr 30 03:11:47 PM PDT 24
Peak memory 197076 kb
Host smart-b2e9dfa3-8e77-472c-b676-a894af9568f6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063649287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1063649287
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.101500591
Short name T1178
Test name
Test status
Simulation time 49781798546 ps
CPU time 221.47 seconds
Started Apr 30 03:11:42 PM PDT 24
Finished Apr 30 03:15:24 PM PDT 24
Peak memory 200384 kb
Host smart-281e9217-1688-4e49-9357-74643640114c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=101500591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.101500591
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.1221941691
Short name T1041
Test name
Test status
Simulation time 5289532764 ps
CPU time 5.36 seconds
Started Apr 30 03:11:45 PM PDT 24
Finished Apr 30 03:11:51 PM PDT 24
Peak memory 198828 kb
Host smart-6dc6d53d-54e4-48c4-ba7c-3723ea65dd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221941691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.1221941691
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.1102827835
Short name T475
Test name
Test status
Simulation time 167769708679 ps
CPU time 81.88 seconds
Started Apr 30 03:11:45 PM PDT 24
Finished Apr 30 03:13:07 PM PDT 24
Peak memory 208600 kb
Host smart-eef562d8-0e2f-43d3-9939-0a798f1b54d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102827835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.1102827835
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.401884211
Short name T1171
Test name
Test status
Simulation time 27495506074 ps
CPU time 1489.3 seconds
Started Apr 30 03:11:41 PM PDT 24
Finished Apr 30 03:36:31 PM PDT 24
Peak memory 200444 kb
Host smart-b71409f6-b91f-4eb7-ae58-3872204b8833
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=401884211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.401884211
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.2149301222
Short name T374
Test name
Test status
Simulation time 4312650350 ps
CPU time 30.36 seconds
Started Apr 30 03:11:41 PM PDT 24
Finished Apr 30 03:12:11 PM PDT 24
Peak memory 199328 kb
Host smart-86228383-d956-4b45-b9c1-93d1348e4152
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2149301222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.2149301222
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.1490679387
Short name T615
Test name
Test status
Simulation time 55488708995 ps
CPU time 50.98 seconds
Started Apr 30 03:11:42 PM PDT 24
Finished Apr 30 03:12:33 PM PDT 24
Peak memory 200416 kb
Host smart-3500586a-1b22-4f91-b6e9-7f821e2de468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490679387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.1490679387
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.854060556
Short name T994
Test name
Test status
Simulation time 40953470691 ps
CPU time 58.31 seconds
Started Apr 30 03:11:45 PM PDT 24
Finished Apr 30 03:12:44 PM PDT 24
Peak memory 196132 kb
Host smart-44c79139-76da-4f5b-ab99-c911c27df7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854060556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.854060556
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.1213904446
Short name T312
Test name
Test status
Simulation time 250314459 ps
CPU time 1.91 seconds
Started Apr 30 03:11:35 PM PDT 24
Finished Apr 30 03:11:38 PM PDT 24
Peak memory 199052 kb
Host smart-cfbb371d-1e48-43cf-8327-4733d4c70107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213904446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.1213904446
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.3420693014
Short name T1083
Test name
Test status
Simulation time 23171699547 ps
CPU time 66.87 seconds
Started Apr 30 03:11:40 PM PDT 24
Finished Apr 30 03:12:48 PM PDT 24
Peak memory 200452 kb
Host smart-6f1f4f51-1f7a-4612-a9ac-af5d04ae6a98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420693014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.3420693014
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.3561887466
Short name T674
Test name
Test status
Simulation time 81068957491 ps
CPU time 224.61 seconds
Started Apr 30 03:11:41 PM PDT 24
Finished Apr 30 03:15:26 PM PDT 24
Peak memory 216908 kb
Host smart-0ebeb31d-e90d-4b2f-a2e6-ead47ce3cdbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561887466 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.3561887466
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.2456841166
Short name T540
Test name
Test status
Simulation time 457357133 ps
CPU time 2.22 seconds
Started Apr 30 03:11:41 PM PDT 24
Finished Apr 30 03:11:44 PM PDT 24
Peak memory 198596 kb
Host smart-bd6fa565-2e97-4011-8124-e276d35df4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456841166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.2456841166
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.821573941
Short name T1159
Test name
Test status
Simulation time 41596750009 ps
CPU time 19.92 seconds
Started Apr 30 03:11:40 PM PDT 24
Finished Apr 30 03:12:01 PM PDT 24
Peak memory 200416 kb
Host smart-5fbb897a-ca1a-4f6f-9695-a4403957b69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821573941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.821573941
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.2168675092
Short name T894
Test name
Test status
Simulation time 38781280587 ps
CPU time 60.24 seconds
Started Apr 30 03:16:03 PM PDT 24
Finished Apr 30 03:17:04 PM PDT 24
Peak memory 200356 kb
Host smart-752719cd-147f-42af-9335-794c694e469f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168675092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.2168675092
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.3388215131
Short name T801
Test name
Test status
Simulation time 87303435246 ps
CPU time 140.81 seconds
Started Apr 30 03:16:02 PM PDT 24
Finished Apr 30 03:18:24 PM PDT 24
Peak memory 200444 kb
Host smart-55492155-4aee-44bb-93b3-b04c20c7d4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388215131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.3388215131
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.2964320632
Short name T970
Test name
Test status
Simulation time 13564013553 ps
CPU time 119.5 seconds
Started Apr 30 03:16:03 PM PDT 24
Finished Apr 30 03:18:03 PM PDT 24
Peak memory 209848 kb
Host smart-efc55000-bac5-404f-a553-63486b320878
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964320632 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.2964320632
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.203329236
Short name T4
Test name
Test status
Simulation time 66905953837 ps
CPU time 22.98 seconds
Started Apr 30 03:16:03 PM PDT 24
Finished Apr 30 03:16:26 PM PDT 24
Peak memory 200344 kb
Host smart-17947e31-f84f-45ca-b777-c7bb52cc39df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203329236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.203329236
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.371726654
Short name T331
Test name
Test status
Simulation time 52213785300 ps
CPU time 572.02 seconds
Started Apr 30 03:16:02 PM PDT 24
Finished Apr 30 03:25:35 PM PDT 24
Peak memory 213944 kb
Host smart-ceba2bed-c62c-4e81-816b-20025d7bfe40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371726654 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.371726654
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.1954622408
Short name T240
Test name
Test status
Simulation time 21203548719 ps
CPU time 37.84 seconds
Started Apr 30 03:16:05 PM PDT 24
Finished Apr 30 03:16:44 PM PDT 24
Peak memory 200412 kb
Host smart-b06eac0c-09b1-449c-be06-3658c52d5e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954622408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.1954622408
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.4025832473
Short name T1091
Test name
Test status
Simulation time 378288445833 ps
CPU time 370.64 seconds
Started Apr 30 03:16:10 PM PDT 24
Finished Apr 30 03:22:21 PM PDT 24
Peak memory 225220 kb
Host smart-39153a54-6d6a-4ff8-add4-2b879e6b78da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025832473 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.4025832473
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.2559020399
Short name T683
Test name
Test status
Simulation time 11641386822 ps
CPU time 20.96 seconds
Started Apr 30 03:16:01 PM PDT 24
Finished Apr 30 03:16:23 PM PDT 24
Peak memory 200296 kb
Host smart-2ec9c8c9-570b-4740-bea9-15d63643dd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559020399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.2559020399
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.3513928379
Short name T1085
Test name
Test status
Simulation time 254597677820 ps
CPU time 826.94 seconds
Started Apr 30 03:16:05 PM PDT 24
Finished Apr 30 03:29:52 PM PDT 24
Peak memory 217080 kb
Host smart-81ccd1f4-b025-4055-9eba-0de0cd1166eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513928379 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.3513928379
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.3175442977
Short name T525
Test name
Test status
Simulation time 9661133338 ps
CPU time 16.62 seconds
Started Apr 30 03:16:04 PM PDT 24
Finished Apr 30 03:16:21 PM PDT 24
Peak memory 200384 kb
Host smart-3cab4b7a-c247-49ab-a507-1866dc5a209d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175442977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.3175442977
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.655828828
Short name T667
Test name
Test status
Simulation time 57765368606 ps
CPU time 31.11 seconds
Started Apr 30 03:16:02 PM PDT 24
Finished Apr 30 03:16:34 PM PDT 24
Peak memory 200444 kb
Host smart-84b0a023-61cc-4c56-ac26-4802e44a9857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655828828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.655828828
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.391227248
Short name T902
Test name
Test status
Simulation time 100309000799 ps
CPU time 306.03 seconds
Started Apr 30 03:16:09 PM PDT 24
Finished Apr 30 03:21:16 PM PDT 24
Peak memory 217044 kb
Host smart-09a04025-fdd8-4e92-b238-498998f169c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391227248 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.391227248
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.1336170644
Short name T243
Test name
Test status
Simulation time 32905455482 ps
CPU time 14.92 seconds
Started Apr 30 03:16:03 PM PDT 24
Finished Apr 30 03:16:19 PM PDT 24
Peak memory 200484 kb
Host smart-dd19a457-7d9d-4972-910a-9749d6567fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336170644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.1336170644
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.2171731042
Short name T996
Test name
Test status
Simulation time 117722651730 ps
CPU time 490.57 seconds
Started Apr 30 03:16:03 PM PDT 24
Finished Apr 30 03:24:14 PM PDT 24
Peak memory 216828 kb
Host smart-1290547d-1e1c-4674-9579-adcad066c205
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171731042 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.2171731042
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.828816443
Short name T1132
Test name
Test status
Simulation time 77834150497 ps
CPU time 32.31 seconds
Started Apr 30 03:16:05 PM PDT 24
Finished Apr 30 03:16:38 PM PDT 24
Peak memory 200532 kb
Host smart-52ba3037-ea18-4466-89f9-f92910f732e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828816443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.828816443
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.1919574894
Short name T765
Test name
Test status
Simulation time 19797878697 ps
CPU time 179.96 seconds
Started Apr 30 03:16:04 PM PDT 24
Finished Apr 30 03:19:05 PM PDT 24
Peak memory 216660 kb
Host smart-84aff0f0-fc4e-47e9-a436-b1ca5e8c388c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919574894 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.1919574894
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.1761656425
Short name T689
Test name
Test status
Simulation time 46739753853 ps
CPU time 36.04 seconds
Started Apr 30 03:16:04 PM PDT 24
Finished Apr 30 03:16:41 PM PDT 24
Peak memory 200628 kb
Host smart-3f45ff7c-b5ed-4103-a492-0bafc4e430eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761656425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.1761656425
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.547897442
Short name T422
Test name
Test status
Simulation time 67119832383 ps
CPU time 805.4 seconds
Started Apr 30 03:16:04 PM PDT 24
Finished Apr 30 03:29:30 PM PDT 24
Peak memory 225272 kb
Host smart-ebfd0ed3-a25b-4b15-aead-7bec978f68fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547897442 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.547897442
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.2888752962
Short name T1036
Test name
Test status
Simulation time 20319961 ps
CPU time 0.56 seconds
Started Apr 30 03:11:56 PM PDT 24
Finished Apr 30 03:11:57 PM PDT 24
Peak memory 195820 kb
Host smart-770677f6-e696-40ce-85bd-e456e9330f69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888752962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2888752962
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.3752252212
Short name T122
Test name
Test status
Simulation time 22280874723 ps
CPU time 46.03 seconds
Started Apr 30 03:11:48 PM PDT 24
Finished Apr 30 03:12:34 PM PDT 24
Peak memory 200452 kb
Host smart-26eef078-f6cd-474c-a5d3-01e7b2111d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752252212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.3752252212
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.2226593334
Short name T988
Test name
Test status
Simulation time 42539125572 ps
CPU time 36.61 seconds
Started Apr 30 03:11:50 PM PDT 24
Finished Apr 30 03:12:27 PM PDT 24
Peak memory 200456 kb
Host smart-97de5d6b-9865-43c2-80cb-107326a820ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226593334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2226593334
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.1281135576
Short name T403
Test name
Test status
Simulation time 20271735377 ps
CPU time 36.64 seconds
Started Apr 30 03:11:49 PM PDT 24
Finished Apr 30 03:12:26 PM PDT 24
Peak memory 200332 kb
Host smart-f870211c-285f-4d97-ac71-519410cf60ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281135576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.1281135576
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.49456952
Short name T1129
Test name
Test status
Simulation time 21515322400 ps
CPU time 8.71 seconds
Started Apr 30 03:11:45 PM PDT 24
Finished Apr 30 03:11:55 PM PDT 24
Peak memory 197784 kb
Host smart-a2b9610e-356b-4fea-9fec-0b141b76c1e9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49456952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.49456952
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.234365285
Short name T42
Test name
Test status
Simulation time 124103789146 ps
CPU time 291.13 seconds
Started Apr 30 03:11:50 PM PDT 24
Finished Apr 30 03:16:42 PM PDT 24
Peak memory 200428 kb
Host smart-efc1d818-60e7-4eed-b5fd-af051ab42e35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=234365285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.234365285
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.2604083511
Short name T607
Test name
Test status
Simulation time 7271579680 ps
CPU time 8.04 seconds
Started Apr 30 03:11:45 PM PDT 24
Finished Apr 30 03:11:54 PM PDT 24
Peak memory 200352 kb
Host smart-7baef15d-76f5-4ebf-92b7-4373f87d5ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604083511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.2604083511
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.2190251408
Short name T579
Test name
Test status
Simulation time 102715563110 ps
CPU time 52.09 seconds
Started Apr 30 03:11:46 PM PDT 24
Finished Apr 30 03:12:39 PM PDT 24
Peak memory 200628 kb
Host smart-e3fd90c7-51d6-475f-b80a-67b5b1f5f236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190251408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.2190251408
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.2649659039
Short name T968
Test name
Test status
Simulation time 9093662702 ps
CPU time 61.2 seconds
Started Apr 30 03:11:50 PM PDT 24
Finished Apr 30 03:12:52 PM PDT 24
Peak memory 200404 kb
Host smart-d487cf8f-83ed-43ce-8529-eacc47809e39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2649659039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.2649659039
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.3521613059
Short name T517
Test name
Test status
Simulation time 5512440551 ps
CPU time 49.98 seconds
Started Apr 30 03:11:47 PM PDT 24
Finished Apr 30 03:12:37 PM PDT 24
Peak memory 199540 kb
Host smart-58a83063-e1ed-4126-a5c6-ac876d47bf0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3521613059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.3521613059
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.549894363
Short name T694
Test name
Test status
Simulation time 17397562116 ps
CPU time 14.3 seconds
Started Apr 30 03:11:47 PM PDT 24
Finished Apr 30 03:12:02 PM PDT 24
Peak memory 200404 kb
Host smart-ecf3570b-283a-407a-b252-35dff149d67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549894363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.549894363
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.1947891424
Short name T682
Test name
Test status
Simulation time 36435848371 ps
CPU time 14.25 seconds
Started Apr 30 03:11:51 PM PDT 24
Finished Apr 30 03:12:06 PM PDT 24
Peak memory 196140 kb
Host smart-76070d80-ce85-4de2-86ab-0f471aa63447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947891424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1947891424
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.1633381745
Short name T859
Test name
Test status
Simulation time 129803860 ps
CPU time 0.72 seconds
Started Apr 30 03:11:47 PM PDT 24
Finished Apr 30 03:11:48 PM PDT 24
Peak memory 197480 kb
Host smart-101555c4-9ed7-4d86-a508-ea404c547e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633381745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.1633381745
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.3553156946
Short name T957
Test name
Test status
Simulation time 540813311369 ps
CPU time 795.74 seconds
Started Apr 30 03:11:51 PM PDT 24
Finished Apr 30 03:25:07 PM PDT 24
Peak memory 208768 kb
Host smart-98bcd2d7-05d7-4e03-a492-51c6a12431d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553156946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.3553156946
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.1426585980
Short name T284
Test name
Test status
Simulation time 2291123693 ps
CPU time 2.18 seconds
Started Apr 30 03:11:48 PM PDT 24
Finished Apr 30 03:11:51 PM PDT 24
Peak memory 200340 kb
Host smart-ff3b2765-6847-4a90-b402-ab8adccac168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426585980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.1426585980
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.3812964902
Short name T878
Test name
Test status
Simulation time 277485263842 ps
CPU time 105.88 seconds
Started Apr 30 03:11:47 PM PDT 24
Finished Apr 30 03:13:33 PM PDT 24
Peak memory 200344 kb
Host smart-a511ae2b-215b-41e4-bd94-fc2a68308b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812964902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.3812964902
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.991407556
Short name T495
Test name
Test status
Simulation time 142321775588 ps
CPU time 133.41 seconds
Started Apr 30 03:16:02 PM PDT 24
Finished Apr 30 03:18:16 PM PDT 24
Peak memory 200412 kb
Host smart-b5779925-0308-4736-9acd-b29b5ef9f01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991407556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.991407556
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.1076728762
Short name T302
Test name
Test status
Simulation time 52158897188 ps
CPU time 583.5 seconds
Started Apr 30 03:16:15 PM PDT 24
Finished Apr 30 03:25:59 PM PDT 24
Peak memory 216784 kb
Host smart-f54b3e1f-9038-4420-be9d-0afc418861a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076728762 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.1076728762
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.90566296
Short name T208
Test name
Test status
Simulation time 442751080554 ps
CPU time 41.59 seconds
Started Apr 30 03:16:12 PM PDT 24
Finished Apr 30 03:16:55 PM PDT 24
Peak memory 200408 kb
Host smart-f849adc9-7ce2-4a47-ae67-45a58940d962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90566296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.90566296
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.3136338104
Short name T499
Test name
Test status
Simulation time 339379036609 ps
CPU time 1123.26 seconds
Started Apr 30 03:16:12 PM PDT 24
Finished Apr 30 03:34:56 PM PDT 24
Peak memory 216872 kb
Host smart-adbf0cdf-32de-4bb5-b85e-fdaed864b092
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136338104 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.3136338104
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.3426386997
Short name T1066
Test name
Test status
Simulation time 49633208522 ps
CPU time 102.5 seconds
Started Apr 30 03:16:12 PM PDT 24
Finished Apr 30 03:17:55 PM PDT 24
Peak memory 200440 kb
Host smart-b03e94a3-758b-4ac0-933b-92d923b116b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426386997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3426386997
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.1907565301
Short name T1100
Test name
Test status
Simulation time 34542285891 ps
CPU time 398.44 seconds
Started Apr 30 03:16:12 PM PDT 24
Finished Apr 30 03:22:51 PM PDT 24
Peak memory 225204 kb
Host smart-9fe4ae02-5f94-4361-b062-73161ec4aafa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907565301 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.1907565301
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.3484501872
Short name T455
Test name
Test status
Simulation time 85589584020 ps
CPU time 36.77 seconds
Started Apr 30 03:16:11 PM PDT 24
Finished Apr 30 03:16:49 PM PDT 24
Peak memory 200396 kb
Host smart-ecd62b32-7d04-48d7-85a8-08947b553cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484501872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.3484501872
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.369227543
Short name T1006
Test name
Test status
Simulation time 89574479064 ps
CPU time 376.89 seconds
Started Apr 30 03:16:11 PM PDT 24
Finished Apr 30 03:22:29 PM PDT 24
Peak memory 226384 kb
Host smart-0bca8d38-7402-44df-9386-5e01629c573d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369227543 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.369227543
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.2052781049
Short name T207
Test name
Test status
Simulation time 40891170133 ps
CPU time 71.14 seconds
Started Apr 30 03:16:14 PM PDT 24
Finished Apr 30 03:17:26 PM PDT 24
Peak memory 200380 kb
Host smart-fd7d9ce9-af84-444c-a973-fa15d7294031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052781049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.2052781049
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.465360737
Short name T632
Test name
Test status
Simulation time 198340149224 ps
CPU time 230.12 seconds
Started Apr 30 03:16:12 PM PDT 24
Finished Apr 30 03:20:02 PM PDT 24
Peak memory 217156 kb
Host smart-439248ab-61bd-40d5-a49e-1a09f3bcb39d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465360737 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.465360737
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.3590395198
Short name T849
Test name
Test status
Simulation time 62083083234 ps
CPU time 26.93 seconds
Started Apr 30 03:16:13 PM PDT 24
Finished Apr 30 03:16:41 PM PDT 24
Peak memory 200440 kb
Host smart-914da32c-d2f3-4af5-ab78-4ddb8632fc59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590395198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.3590395198
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.3598307016
Short name T860
Test name
Test status
Simulation time 71394225411 ps
CPU time 451.06 seconds
Started Apr 30 03:16:12 PM PDT 24
Finished Apr 30 03:23:44 PM PDT 24
Peak memory 217080 kb
Host smart-7e8b01c6-70b6-4b37-8ae2-c9b6209a137e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598307016 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.3598307016
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.3233976060
Short name T327
Test name
Test status
Simulation time 93634027218 ps
CPU time 40.05 seconds
Started Apr 30 03:16:14 PM PDT 24
Finished Apr 30 03:16:54 PM PDT 24
Peak memory 200304 kb
Host smart-16478c47-bc06-420c-a0ed-bbeb7a86b7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233976060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.3233976060
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.1303782100
Short name T964
Test name
Test status
Simulation time 50211383374 ps
CPU time 604.44 seconds
Started Apr 30 03:16:13 PM PDT 24
Finished Apr 30 03:26:18 PM PDT 24
Peak memory 217104 kb
Host smart-de4e388a-0ddb-40e7-ba6b-2118c428d856
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303782100 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.1303782100
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.731483025
Short name T972
Test name
Test status
Simulation time 19276399111 ps
CPU time 6.34 seconds
Started Apr 30 03:16:12 PM PDT 24
Finished Apr 30 03:16:18 PM PDT 24
Peak memory 200292 kb
Host smart-7ef6dc9a-6fa9-4182-911d-97e8610f599a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731483025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.731483025
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.2106804759
Short name T911
Test name
Test status
Simulation time 397420049875 ps
CPU time 1188 seconds
Started Apr 30 03:16:12 PM PDT 24
Finished Apr 30 03:36:00 PM PDT 24
Peak memory 228512 kb
Host smart-872fa63c-f82a-49e2-9cf8-3daf36b29ff5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106804759 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.2106804759
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.2944552187
Short name T480
Test name
Test status
Simulation time 88333215593 ps
CPU time 37.83 seconds
Started Apr 30 03:16:09 PM PDT 24
Finished Apr 30 03:16:48 PM PDT 24
Peak memory 200376 kb
Host smart-62ded885-b0ad-4926-aa22-1b9e105db287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944552187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2944552187
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.3706199436
Short name T1011
Test name
Test status
Simulation time 29215857476 ps
CPU time 231.15 seconds
Started Apr 30 03:16:14 PM PDT 24
Finished Apr 30 03:20:06 PM PDT 24
Peak memory 208596 kb
Host smart-1e48ba49-fb06-49bd-af3f-5688e5b9fa40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706199436 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.3706199436
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.2791719802
Short name T483
Test name
Test status
Simulation time 14528146 ps
CPU time 0.56 seconds
Started Apr 30 03:11:59 PM PDT 24
Finished Apr 30 03:12:00 PM PDT 24
Peak memory 195812 kb
Host smart-76ec967f-776f-48e2-85ca-4f05bf102402
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791719802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.2791719802
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.2163573748
Short name T1069
Test name
Test status
Simulation time 47817457560 ps
CPU time 84.21 seconds
Started Apr 30 03:11:55 PM PDT 24
Finished Apr 30 03:13:19 PM PDT 24
Peak memory 200368 kb
Host smart-dbb1fe19-6bfa-4dc0-996d-70f12a5746df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163573748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.2163573748
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.2463391648
Short name T904
Test name
Test status
Simulation time 28715929692 ps
CPU time 52.55 seconds
Started Apr 30 03:11:55 PM PDT 24
Finished Apr 30 03:12:48 PM PDT 24
Peak memory 200476 kb
Host smart-bb0916f4-2171-449d-a845-aba829397482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463391648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.2463391648
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.3661436391
Short name T451
Test name
Test status
Simulation time 29839124973 ps
CPU time 14.54 seconds
Started Apr 30 03:11:53 PM PDT 24
Finished Apr 30 03:12:08 PM PDT 24
Peak memory 200356 kb
Host smart-e57e05d1-8c00-444b-9739-4ab129018ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661436391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.3661436391
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.3640949492
Short name T319
Test name
Test status
Simulation time 14631236451 ps
CPU time 29.8 seconds
Started Apr 30 03:11:54 PM PDT 24
Finished Apr 30 03:12:24 PM PDT 24
Peak memory 199484 kb
Host smart-b4fbb237-f1f3-4e2f-a763-5fcae24940a4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640949492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.3640949492
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.3142474406
Short name T355
Test name
Test status
Simulation time 203030157905 ps
CPU time 479.99 seconds
Started Apr 30 03:11:59 PM PDT 24
Finished Apr 30 03:19:59 PM PDT 24
Peak memory 200336 kb
Host smart-8b2dbfff-c2d7-48d7-9014-536ee989519c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3142474406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.3142474406
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.155238804
Short name T1026
Test name
Test status
Simulation time 11920513893 ps
CPU time 16.3 seconds
Started Apr 30 03:12:01 PM PDT 24
Finished Apr 30 03:12:18 PM PDT 24
Peak memory 198916 kb
Host smart-713b0665-aca5-43f9-9233-010a2c3ade18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155238804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.155238804
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.2372290345
Short name T1144
Test name
Test status
Simulation time 171451517186 ps
CPU time 55.03 seconds
Started Apr 30 03:11:54 PM PDT 24
Finished Apr 30 03:12:50 PM PDT 24
Peak memory 200612 kb
Host smart-986edfcc-5ca1-4a06-9f52-9eb99932d58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372290345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.2372290345
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.2135068983
Short name T1065
Test name
Test status
Simulation time 8705554632 ps
CPU time 515.26 seconds
Started Apr 30 03:11:59 PM PDT 24
Finished Apr 30 03:20:35 PM PDT 24
Peak memory 200336 kb
Host smart-26ab2a86-305d-469c-bc84-c0074e008631
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2135068983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2135068983
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.2649415491
Short name T100
Test name
Test status
Simulation time 3839637982 ps
CPU time 26.82 seconds
Started Apr 30 03:11:53 PM PDT 24
Finished Apr 30 03:12:21 PM PDT 24
Peak memory 198732 kb
Host smart-530e2e38-1d94-4932-baf0-004488494a21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2649415491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.2649415491
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.901779262
Short name T544
Test name
Test status
Simulation time 148493690678 ps
CPU time 62.27 seconds
Started Apr 30 03:11:58 PM PDT 24
Finished Apr 30 03:13:01 PM PDT 24
Peak memory 200416 kb
Host smart-da20c7db-a688-4290-b91f-29bbbfdddcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901779262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.901779262
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.3052089342
Short name T787
Test name
Test status
Simulation time 5444939439 ps
CPU time 4.92 seconds
Started Apr 30 03:11:50 PM PDT 24
Finished Apr 30 03:11:56 PM PDT 24
Peak memory 196744 kb
Host smart-38a563e4-feb3-4944-95be-bee816cbd5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052089342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.3052089342
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.3641452119
Short name T854
Test name
Test status
Simulation time 504500016 ps
CPU time 2.89 seconds
Started Apr 30 03:11:52 PM PDT 24
Finished Apr 30 03:11:55 PM PDT 24
Peak memory 199000 kb
Host smart-5260c84d-b5e3-4ebc-ad02-211b0c821229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641452119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.3641452119
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.546787251
Short name T1149
Test name
Test status
Simulation time 126215312201 ps
CPU time 25.03 seconds
Started Apr 30 03:11:59 PM PDT 24
Finished Apr 30 03:12:24 PM PDT 24
Peak memory 200460 kb
Host smart-7125a190-c24e-4974-84ac-9aa183d42870
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546787251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.546787251
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.948631721
Short name T12
Test name
Test status
Simulation time 27507574803 ps
CPU time 322.02 seconds
Started Apr 30 03:11:57 PM PDT 24
Finished Apr 30 03:17:20 PM PDT 24
Peak memory 208620 kb
Host smart-351e39e0-a7db-485f-8a3d-2fe29e20f133
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948631721 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.948631721
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.2454741401
Short name T323
Test name
Test status
Simulation time 7074323495 ps
CPU time 37.8 seconds
Started Apr 30 03:12:03 PM PDT 24
Finished Apr 30 03:12:41 PM PDT 24
Peak memory 200356 kb
Host smart-b582d356-0f97-48b4-993b-b65d49884928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454741401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.2454741401
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.588434026
Short name T946
Test name
Test status
Simulation time 70482982152 ps
CPU time 83.44 seconds
Started Apr 30 03:11:52 PM PDT 24
Finished Apr 30 03:13:16 PM PDT 24
Peak memory 200416 kb
Host smart-900ab7f9-f0fc-42e4-a5cf-1b0c7d99817c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588434026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.588434026
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.187546098
Short name T1025
Test name
Test status
Simulation time 30217578570 ps
CPU time 13.89 seconds
Started Apr 30 03:16:11 PM PDT 24
Finished Apr 30 03:16:25 PM PDT 24
Peak memory 199980 kb
Host smart-730b5daf-b70c-4d92-b557-9454f9dcedac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187546098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.187546098
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.3405433020
Short name T676
Test name
Test status
Simulation time 166298113052 ps
CPU time 277.52 seconds
Started Apr 30 03:16:11 PM PDT 24
Finished Apr 30 03:20:49 PM PDT 24
Peak memory 216428 kb
Host smart-137aa10d-8461-461b-a430-9d00cdc0fc6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405433020 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.3405433020
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.1109740972
Short name T620
Test name
Test status
Simulation time 10175753692 ps
CPU time 14.68 seconds
Started Apr 30 03:16:13 PM PDT 24
Finished Apr 30 03:16:28 PM PDT 24
Peak memory 200372 kb
Host smart-55313fd7-bad5-4a0e-9be2-800f7a8e95f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109740972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.1109740972
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.3762396758
Short name T333
Test name
Test status
Simulation time 72997674898 ps
CPU time 238.74 seconds
Started Apr 30 03:16:13 PM PDT 24
Finished Apr 30 03:20:12 PM PDT 24
Peak memory 216888 kb
Host smart-ef0e3c26-09a5-4f58-849a-b6a7669a11ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762396758 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.3762396758
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.3950192101
Short name T538
Test name
Test status
Simulation time 121760579396 ps
CPU time 267.96 seconds
Started Apr 30 03:16:18 PM PDT 24
Finished Apr 30 03:20:47 PM PDT 24
Peak memory 200296 kb
Host smart-81cefb6c-3a52-4f76-824d-9d3761c4f69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950192101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.3950192101
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.3237178004
Short name T55
Test name
Test status
Simulation time 115146381433 ps
CPU time 276.45 seconds
Started Apr 30 03:16:20 PM PDT 24
Finished Apr 30 03:20:57 PM PDT 24
Peak memory 216892 kb
Host smart-99bc2b32-f529-4c13-b98b-78cb5d5dd96b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237178004 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.3237178004
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.3888360013
Short name T1001
Test name
Test status
Simulation time 16287403705 ps
CPU time 32.93 seconds
Started Apr 30 03:16:31 PM PDT 24
Finished Apr 30 03:17:04 PM PDT 24
Peak memory 200356 kb
Host smart-f755d97a-f702-4750-b8b4-a46485dcd519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888360013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.3888360013
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.2703237729
Short name T892
Test name
Test status
Simulation time 235302245640 ps
CPU time 451.54 seconds
Started Apr 30 03:16:17 PM PDT 24
Finished Apr 30 03:23:50 PM PDT 24
Peak memory 212780 kb
Host smart-12cc22e7-8d47-4901-9f8e-607c7b9df324
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703237729 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.2703237729
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.422271095
Short name T541
Test name
Test status
Simulation time 102866385116 ps
CPU time 50 seconds
Started Apr 30 03:16:18 PM PDT 24
Finished Apr 30 03:17:08 PM PDT 24
Peak memory 200400 kb
Host smart-b5726f62-5e63-4df1-92fb-74bfe790351e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422271095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.422271095
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.1264203478
Short name T60
Test name
Test status
Simulation time 68632396622 ps
CPU time 585.47 seconds
Started Apr 30 03:16:19 PM PDT 24
Finished Apr 30 03:26:05 PM PDT 24
Peak memory 225352 kb
Host smart-c08c25fd-8464-48cc-8fdb-ab65f4b83d50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264203478 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.1264203478
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.1627732841
Short name T206
Test name
Test status
Simulation time 30622365559 ps
CPU time 50.77 seconds
Started Apr 30 03:16:30 PM PDT 24
Finished Apr 30 03:17:22 PM PDT 24
Peak memory 200328 kb
Host smart-66a8f8f4-e750-40d6-870e-decafdda07ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627732841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.1627732841
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.1277587584
Short name T1145
Test name
Test status
Simulation time 13797981576 ps
CPU time 142.87 seconds
Started Apr 30 03:16:17 PM PDT 24
Finished Apr 30 03:18:41 PM PDT 24
Peak memory 210296 kb
Host smart-e28bed08-e3dc-491b-b1b4-d0cc9325ce34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277587584 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.1277587584
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.89594722
Short name T425
Test name
Test status
Simulation time 26664677373 ps
CPU time 9.27 seconds
Started Apr 30 03:16:18 PM PDT 24
Finished Apr 30 03:16:28 PM PDT 24
Peak memory 200196 kb
Host smart-0412f14b-6725-4b3e-b28d-92acbc2e361d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89594722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.89594722
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.2516893760
Short name T112
Test name
Test status
Simulation time 121186900028 ps
CPU time 864.93 seconds
Started Apr 30 03:16:17 PM PDT 24
Finished Apr 30 03:30:42 PM PDT 24
Peak memory 216816 kb
Host smart-82156cd8-8e57-4068-9525-b303faf67be7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516893760 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.2516893760
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.2583262061
Short name T229
Test name
Test status
Simulation time 27572156616 ps
CPU time 48 seconds
Started Apr 30 03:16:30 PM PDT 24
Finished Apr 30 03:17:19 PM PDT 24
Peak memory 200412 kb
Host smart-c8553c37-724e-4ffc-ba58-c29394196f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583262061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.2583262061
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.1538741505
Short name T53
Test name
Test status
Simulation time 109724057132 ps
CPU time 372.16 seconds
Started Apr 30 03:16:17 PM PDT 24
Finished Apr 30 03:22:30 PM PDT 24
Peak memory 217076 kb
Host smart-00a7f7e9-807e-42cb-9bd3-0e0ed339031d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538741505 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.1538741505
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.2191276128
Short name T196
Test name
Test status
Simulation time 21184620124 ps
CPU time 17 seconds
Started Apr 30 03:16:30 PM PDT 24
Finished Apr 30 03:16:48 PM PDT 24
Peak memory 200352 kb
Host smart-d13eaa58-8b91-44bc-99a1-93e881d74c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191276128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.2191276128
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.459192329
Short name T982
Test name
Test status
Simulation time 35761787542 ps
CPU time 77.22 seconds
Started Apr 30 03:16:17 PM PDT 24
Finished Apr 30 03:17:35 PM PDT 24
Peak memory 200376 kb
Host smart-c18e2e11-28de-4481-bab9-1dbc5407aff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459192329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.459192329
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.984546234
Short name T57
Test name
Test status
Simulation time 175450658214 ps
CPU time 713.11 seconds
Started Apr 30 03:16:31 PM PDT 24
Finished Apr 30 03:28:24 PM PDT 24
Peak memory 225320 kb
Host smart-f1c679bc-14a2-4ef5-824f-17b98bc212a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984546234 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.984546234
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.1236214016
Short name T1053
Test name
Test status
Simulation time 13128357 ps
CPU time 0.54 seconds
Started Apr 30 03:12:04 PM PDT 24
Finished Apr 30 03:12:05 PM PDT 24
Peak memory 195788 kb
Host smart-7266363d-e53c-4b2b-8058-2819f3bba7c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236214016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.1236214016
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.959797838
Short name T518
Test name
Test status
Simulation time 114725780226 ps
CPU time 80.48 seconds
Started Apr 30 03:12:02 PM PDT 24
Finished Apr 30 03:13:23 PM PDT 24
Peak memory 200348 kb
Host smart-abaf3e2b-e8e1-4792-a0a4-d26eda64588e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959797838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.959797838
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.223671830
Short name T321
Test name
Test status
Simulation time 18144138030 ps
CPU time 15.89 seconds
Started Apr 30 03:12:00 PM PDT 24
Finished Apr 30 03:12:16 PM PDT 24
Peak memory 199136 kb
Host smart-227d1b49-ad67-4bc3-8863-d6d61919a591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223671830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.223671830
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.2298206938
Short name T1000
Test name
Test status
Simulation time 77661665321 ps
CPU time 187.19 seconds
Started Apr 30 03:12:02 PM PDT 24
Finished Apr 30 03:15:10 PM PDT 24
Peak memory 200364 kb
Host smart-a7df2845-a330-4276-a87a-3279520724de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2298206938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2298206938
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.1206956808
Short name T347
Test name
Test status
Simulation time 10082396813 ps
CPU time 2.09 seconds
Started Apr 30 03:12:01 PM PDT 24
Finished Apr 30 03:12:03 PM PDT 24
Peak memory 198976 kb
Host smart-2dffb337-b030-45c0-99fd-ae068f940b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206956808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.1206956808
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.1328654041
Short name T492
Test name
Test status
Simulation time 189461158794 ps
CPU time 48.6 seconds
Started Apr 30 03:12:01 PM PDT 24
Finished Apr 30 03:12:50 PM PDT 24
Peak memory 200284 kb
Host smart-6ec588c0-70a0-4c57-91f1-65fdd473a124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328654041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.1328654041
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.3107284291
Short name T876
Test name
Test status
Simulation time 11540165375 ps
CPU time 441.02 seconds
Started Apr 30 03:12:03 PM PDT 24
Finished Apr 30 03:19:25 PM PDT 24
Peak memory 200356 kb
Host smart-068a14de-bff0-4af0-b56c-f271499c768e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3107284291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.3107284291
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.3814262483
Short name T905
Test name
Test status
Simulation time 3149449228 ps
CPU time 22.03 seconds
Started Apr 30 03:12:00 PM PDT 24
Finished Apr 30 03:12:22 PM PDT 24
Peak memory 199880 kb
Host smart-b6f8391f-6997-49a6-9fb6-488fd12dc4c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3814262483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.3814262483
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.936403494
Short name T855
Test name
Test status
Simulation time 100436568775 ps
CPU time 51.22 seconds
Started Apr 30 03:12:00 PM PDT 24
Finished Apr 30 03:12:51 PM PDT 24
Peak memory 200456 kb
Host smart-994ed7bd-47d0-4195-badc-fd06c149dd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936403494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.936403494
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.1261806196
Short name T714
Test name
Test status
Simulation time 4411185498 ps
CPU time 2.55 seconds
Started Apr 30 03:12:02 PM PDT 24
Finished Apr 30 03:12:05 PM PDT 24
Peak memory 196444 kb
Host smart-1cf014da-0765-459d-a611-e07a0009a352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261806196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1261806196
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.2772553370
Short name T1087
Test name
Test status
Simulation time 696828362 ps
CPU time 1.43 seconds
Started Apr 30 03:12:00 PM PDT 24
Finished Apr 30 03:12:02 PM PDT 24
Peak memory 200124 kb
Host smart-20f35557-818f-49a0-9220-dc6384f9b363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772553370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.2772553370
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.2706549610
Short name T275
Test name
Test status
Simulation time 217229717460 ps
CPU time 836.86 seconds
Started Apr 30 03:12:04 PM PDT 24
Finished Apr 30 03:26:02 PM PDT 24
Peak memory 200400 kb
Host smart-3b5ac4d6-fc76-464b-b009-e72e099ce766
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706549610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.2706549610
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.2565088333
Short name T1133
Test name
Test status
Simulation time 103410915333 ps
CPU time 606.19 seconds
Started Apr 30 03:12:00 PM PDT 24
Finished Apr 30 03:22:07 PM PDT 24
Peak memory 225292 kb
Host smart-1ec74b14-ab5e-454a-881c-ee07c8d6a201
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565088333 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.2565088333
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.1181118959
Short name T411
Test name
Test status
Simulation time 726967203 ps
CPU time 3.13 seconds
Started Apr 30 03:11:58 PM PDT 24
Finished Apr 30 03:12:01 PM PDT 24
Peak memory 198684 kb
Host smart-9af761c5-0615-4ee1-9730-fef41d9ac525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181118959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.1181118959
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.261752580
Short name T356
Test name
Test status
Simulation time 213203349333 ps
CPU time 60.12 seconds
Started Apr 30 03:12:02 PM PDT 24
Finished Apr 30 03:13:02 PM PDT 24
Peak memory 200312 kb
Host smart-71f1a831-5173-493d-a02e-1f99b7385335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261752580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.261752580
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.3498506425
Short name T879
Test name
Test status
Simulation time 39428898978 ps
CPU time 49.46 seconds
Started Apr 30 03:16:30 PM PDT 24
Finished Apr 30 03:17:20 PM PDT 24
Peak memory 200328 kb
Host smart-a0678e26-def4-46ad-98e3-c3f09d721eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498506425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.3498506425
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.1222143670
Short name T330
Test name
Test status
Simulation time 51835346045 ps
CPU time 702.14 seconds
Started Apr 30 03:16:19 PM PDT 24
Finished Apr 30 03:28:01 PM PDT 24
Peak memory 217012 kb
Host smart-19e5cfef-b7a9-4977-a8df-6296cf112e27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222143670 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.1222143670
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.2444406075
Short name T466
Test name
Test status
Simulation time 132175488320 ps
CPU time 64.03 seconds
Started Apr 30 03:16:19 PM PDT 24
Finished Apr 30 03:17:23 PM PDT 24
Peak memory 200416 kb
Host smart-058f9674-6234-4d5a-b445-8f4a9b8646d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444406075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.2444406075
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.2645279219
Short name T762
Test name
Test status
Simulation time 37199478709 ps
CPU time 333.73 seconds
Started Apr 30 03:16:30 PM PDT 24
Finished Apr 30 03:22:05 PM PDT 24
Peak memory 208676 kb
Host smart-3930b8fe-8f85-45d4-8c9a-c9ebec6ec6ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645279219 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.2645279219
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.3840208362
Short name T559
Test name
Test status
Simulation time 10110219031 ps
CPU time 28.72 seconds
Started Apr 30 03:16:20 PM PDT 24
Finished Apr 30 03:16:49 PM PDT 24
Peak memory 200332 kb
Host smart-7321174e-9838-4d18-a54b-749ebf5c9655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840208362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.3840208362
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.2399484437
Short name T1035
Test name
Test status
Simulation time 176178913272 ps
CPU time 514.23 seconds
Started Apr 30 03:16:35 PM PDT 24
Finished Apr 30 03:25:10 PM PDT 24
Peak memory 216872 kb
Host smart-c8a77397-5513-4f19-981e-d6fea30692ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399484437 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.2399484437
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.917223296
Short name T226
Test name
Test status
Simulation time 71082681559 ps
CPU time 101.12 seconds
Started Apr 30 03:16:24 PM PDT 24
Finished Apr 30 03:18:06 PM PDT 24
Peak memory 200360 kb
Host smart-2aa41d1f-f45e-4c5c-8951-36c59eacdeb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917223296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.917223296
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.3412904339
Short name T960
Test name
Test status
Simulation time 182376572316 ps
CPU time 561.01 seconds
Started Apr 30 03:16:31 PM PDT 24
Finished Apr 30 03:25:52 PM PDT 24
Peak memory 216900 kb
Host smart-79eeb568-2ab1-40c4-b190-cbb785204c77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412904339 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.3412904339
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.3564079108
Short name T264
Test name
Test status
Simulation time 62793181555 ps
CPU time 32.8 seconds
Started Apr 30 03:16:36 PM PDT 24
Finished Apr 30 03:17:09 PM PDT 24
Peak memory 200400 kb
Host smart-392ed812-4804-4f49-9bd0-33805a3622b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564079108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.3564079108
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.1771308639
Short name T811
Test name
Test status
Simulation time 184698102684 ps
CPU time 2019.68 seconds
Started Apr 30 03:16:25 PM PDT 24
Finished Apr 30 03:50:06 PM PDT 24
Peak memory 225232 kb
Host smart-bd746b5a-ca24-42d5-a2d3-fbdae6f8f296
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771308639 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.1771308639
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.1884465590
Short name T383
Test name
Test status
Simulation time 19097763006 ps
CPU time 16.66 seconds
Started Apr 30 03:16:27 PM PDT 24
Finished Apr 30 03:16:44 PM PDT 24
Peak memory 200292 kb
Host smart-2022fd06-df8d-49b5-ba90-60decc874a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884465590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.1884465590
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.2772765787
Short name T505
Test name
Test status
Simulation time 92506106682 ps
CPU time 559.77 seconds
Started Apr 30 03:16:26 PM PDT 24
Finished Apr 30 03:25:46 PM PDT 24
Peak memory 216880 kb
Host smart-7f285228-4f62-40f7-8884-80adcabecae6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772765787 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.2772765787
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.933974211
Short name T738
Test name
Test status
Simulation time 33175024681 ps
CPU time 22.75 seconds
Started Apr 30 03:16:24 PM PDT 24
Finished Apr 30 03:16:48 PM PDT 24
Peak memory 200376 kb
Host smart-ddee1a4b-d0bf-41a6-a50f-555545fcc196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933974211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.933974211
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.2037375617
Short name T634
Test name
Test status
Simulation time 1429493918301 ps
CPU time 1254.38 seconds
Started Apr 30 03:16:27 PM PDT 24
Finished Apr 30 03:37:22 PM PDT 24
Peak memory 233484 kb
Host smart-faa5c60d-5e5d-4ab3-a019-ce02a3fed341
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037375617 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.2037375617
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.1010931605
Short name T109
Test name
Test status
Simulation time 115682824005 ps
CPU time 432.83 seconds
Started Apr 30 03:16:30 PM PDT 24
Finished Apr 30 03:23:43 PM PDT 24
Peak memory 216944 kb
Host smart-2fe4f3e8-36cb-4e78-88d4-594e0936166c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010931605 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.1010931605
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.657300826
Short name T875
Test name
Test status
Simulation time 35939186725 ps
CPU time 16.21 seconds
Started Apr 30 03:16:35 PM PDT 24
Finished Apr 30 03:16:51 PM PDT 24
Peak memory 200464 kb
Host smart-62ae0403-8f73-477e-9447-c7546509b792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657300826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.657300826
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.3525212323
Short name T760
Test name
Test status
Simulation time 76019245305 ps
CPU time 515.13 seconds
Started Apr 30 03:16:35 PM PDT 24
Finished Apr 30 03:25:10 PM PDT 24
Peak memory 217156 kb
Host smart-0e01cb77-657a-42fc-9cee-7d36268e826e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525212323 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.3525212323
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.3651798854
Short name T791
Test name
Test status
Simulation time 132085799433 ps
CPU time 63.55 seconds
Started Apr 30 03:16:35 PM PDT 24
Finished Apr 30 03:17:39 PM PDT 24
Peak memory 200464 kb
Host smart-01a78cd5-4e47-43fc-8846-2dee14f19d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651798854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.3651798854
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.1421247873
Short name T99
Test name
Test status
Simulation time 14252784093 ps
CPU time 308.97 seconds
Started Apr 30 03:16:25 PM PDT 24
Finished Apr 30 03:21:34 PM PDT 24
Peak memory 216400 kb
Host smart-669dfa43-2d36-4dd7-92bd-df40ce5aacb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421247873 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.1421247873
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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