Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	105367	1			T1	11		T2	2		T3	2
all_values[1]	105367	1			T1	11		T2	2		T3	2
all_values[2]	105367	1			T1	11		T2	2		T3	2
all_values[3]	105367	1			T1	11		T2	2		T3	2
all_values[4]	105367	1			T1	11		T2	2		T3	2
all_values[5]	105367	1			T1	11		T2	2		T3	2
all_values[6]	105367	1			T1	11		T2	2		T3	2
all_values[7]	105367	1			T1	11		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

424228

1

T1

45

T2

16

T3

16

auto[1]

418708

1

T1

43

T4

112

T5

5

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

786286

1

T1

77

T2

13

T3

13

auto[1]

56650

1

T1

11

T2

3

T3

3

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	25778	1			T1	2		T4	1		T6	360
all_values[0]	auto[0]	auto[1]	22727	1			T1	7		T2	2		T3	2
all_values[0]	auto[1]	auto[0]	34293	1			T6	85		T9	117		T14	11
all_values[0]	auto[1]	auto[1]	22569	1			T1	2		T4	16		T6	43
all_values[1]	auto[0]	auto[0]	55333	1			T1	7		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	1686	1			T4	4		T6	3		T9	9
all_values[1]	auto[1]	auto[0]	46809	1			T1	4		T5	1		T6	170
all_values[1]	auto[1]	auto[1]	1539	1			T6	2		T9	5		T14	3
all_values[2]	auto[0]	auto[0]	50473	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	2859	1			T1	1		T2	1		T3	1
all_values[2]	auto[1]	auto[0]	49639	1			T1	8		T4	40		T5	1
all_values[2]	auto[1]	auto[1]	2396	1			T1	1		T6	7		T7	1
all_values[3]	auto[0]	auto[0]	55398	1			T1	7		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	305	1			T4	1		T6	3		T9	3
all_values[3]	auto[1]	auto[0]	49339	1			T1	4		T4	16		T6	283
all_values[3]	auto[1]	auto[1]	325	1			T6	3		T9	3		T11	1
all_values[4]	auto[0]	auto[0]	51294	1			T1	4		T2	2		T3	2
all_values[4]	auto[0]	auto[1]	437	1			T6	2		T9	6		T11	6
all_values[4]	auto[1]	auto[0]	53199	1			T1	7		T4	27		T5	1
all_values[4]	auto[1]	auto[1]	437	1			T4	13		T9	1		T17	1
all_values[5]	auto[0]	auto[0]	49871	1			T1	7		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	161	1			T6	3		T17	3		T28	3
all_values[5]	auto[1]	auto[0]	55161	1			T1	4		T5	1		T6	218
all_values[5]	auto[1]	auto[1]	174	1			T6	2		T9	3		T27	1
all_values[6]	auto[0]	auto[0]	52401	1			T1	2		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	158	1			T6	1		T9	1		T17	1
all_values[6]	auto[1]	auto[0]	52641	1			T1	9		T6	242		T7	2
all_values[6]	auto[1]	auto[1]	167	1			T6	4		T9	1		T27	4
all_values[7]	auto[0]	auto[0]	54975	1			T1	7		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	372	1			T6	1		T9	3		T17	1
all_values[7]	auto[1]	auto[0]	49682	1			T1	4		T5	1		T6	219
all_values[7]	auto[1]	auto[1]	338	1			T6	1		T9	4		T14	3