Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2629

1

T1

1

T2

1

T3

1

auto[UartRx]

2629

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4636	1			T1	2		T2	2		T3	2
values[1]	44	1			T6	2		T17	1		T114	1
values[2]	76	1			T6	1		T9	2		T17	1
values[3]	63	1			T24	1		T114	2		T201	1
values[4]	65	1			T6	1		T24	1		T25	1
values[5]	69	1			T24	1		T28	3		T29	2
values[6]	48	1			T6	1		T24	2		T25	1
values[7]	46	1			T6	1		T121	2		T114	1
values[8]	52	1			T17	1		T24	1		T27	2
values[9]	54	1			T9	1		T27	1		T28	1
values[10]	69	1			T6	1		T17	3		T24	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2410	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	13	1			T6	1		T290	1		T302	1
auto[UartTx]	values[2]	30	1			T17	1		T26	1		T27	1
auto[UartTx]	values[3]	24	1			T114	1		T201	1		T113	1
auto[UartTx]	values[4]	20	1			T25	1		T28	1		T30	1
auto[UartTx]	values[5]	26	1			T24	1		T28	1		T114	1
auto[UartTx]	values[6]	16	1			T6	1		T27	1		T114	1
auto[UartTx]	values[7]	17	1			T121	1		T48	1		T49	1
auto[UartTx]	values[8]	18	1			T27	1		T47	1		T48	1
auto[UartTx]	values[9]	16	1			T201	1		T276	2		T246	1
auto[UartTx]	values[10]	27	1			T6	1		T17	1		T24	1
auto[UartRx]	values[0]	2226	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	31	1			T6	1		T17	1		T114	1
auto[UartRx]	values[2]	46	1			T6	1		T9	2		T27	1
auto[UartRx]	values[3]	39	1			T24	1		T114	1		T113	1
auto[UartRx]	values[4]	45	1			T6	1		T24	1		T28	1
auto[UartRx]	values[5]	43	1			T28	2		T29	2		T246	1
auto[UartRx]	values[6]	32	1			T24	2		T25	1		T27	2
auto[UartRx]	values[7]	29	1			T6	1		T121	1		T114	1
auto[UartRx]	values[8]	34	1			T17	1		T24	1		T27	1
auto[UartRx]	values[9]	38	1			T9	1		T27	1		T28	1
auto[UartRx]	values[10]	42	1			T17	2		T26	2		T27	1