Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2252	1			T2	1		T4	2		T6	15
auto[BaudRate115200]	2107	1			T1	1		T2	1		T3	1
auto[BaudRate230400]	2048	1			T1	1		T5	3		T6	21
auto[BaudRate128Kbps]	2051	1			T6	7		T7	1		T8	1
auto[BaudRate256Kbps]	2228	1			T5	3		T6	12		T7	2
auto[BaudRate1Mbps]	1795	1			T1	2		T6	7		T8	1
auto[BaudRate1p5Mbps]	1383	1			T3	1		T6	15		T13	2

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1754	1			T1	4		T6	84		T15	50
freqs[25]	916	1			T11	3		T126	9		T250	6
freqs[48]	470	1			T3	2		T4	2		T249	6
freqs[50]	828	1			T40	7		T16	2		T118	10
freqs[100]	1662	1			T32	6		T17	16		T35	7

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	298	1			T6	15		T15	5		T303	15
auto[BaudRate9600]	freqs[25]	179	1			T126	1		T151	2		T304	9
auto[BaudRate9600]	freqs[48]	64	1			T4	2		T263	3		T125	1
auto[BaudRate9600]	freqs[50]	133	1			T118	1		T30	2		T244	3
auto[BaudRate9600]	freqs[100]	241	1			T17	1		T35	2		T292	2
auto[BaudRate115200]	freqs[24]	287	1			T1	1		T6	7		T15	8
auto[BaudRate115200]	freqs[25]	120	1			T11	1		T126	3		T298	1
auto[BaudRate115200]	freqs[48]	78	1			T3	1		T263	3		T125	1
auto[BaudRate115200]	freqs[50]	133	1			T118	2		T30	4		T244	1
auto[BaudRate115200]	freqs[100]	190	1			T32	2		T17	4		T305	1
auto[BaudRate230400]	freqs[24]	271	1			T1	1		T6	21		T15	6
auto[BaudRate230400]	freqs[25]	119	1			T11	1		T126	1		T298	2
auto[BaudRate230400]	freqs[48]	55	1			T263	1		T125	5		T259	1
auto[BaudRate230400]	freqs[50]	98	1			T118	1		T30	6		T201	3
auto[BaudRate230400]	freqs[100]	257	1			T32	1		T17	1		T292	1
auto[BaudRate128Kbps]	freqs[24]	229	1			T6	7		T15	11		T123	1
auto[BaudRate128Kbps]	freqs[25]	146	1			T11	1		T298	1		T122	2
auto[BaudRate128Kbps]	freqs[48]	66	1			T263	3		T125	1		T259	4
auto[BaudRate128Kbps]	freqs[50]	123	1			T16	2		T118	1		T30	1
auto[BaudRate128Kbps]	freqs[100]	249	1			T35	2		T292	1		T103	3
auto[BaudRate256Kbps]	freqs[24]	258	1			T6	12		T15	8		T123	1
auto[BaudRate256Kbps]	freqs[25]	125	1			T250	1		T298	1		T122	3
auto[BaudRate256Kbps]	freqs[48]	61	1			T249	2		T263	1		T125	1
auto[BaudRate256Kbps]	freqs[50]	102	1			T40	3		T118	1		T30	7
auto[BaudRate256Kbps]	freqs[100]	268	1			T17	5		T103	1		T41	5
auto[BaudRate1Mbps]	freqs[24]	264	1			T1	2		T6	7		T15	5
auto[BaudRate1Mbps]	freqs[25]	142	1			T126	4		T250	2		T122	1
auto[BaudRate1Mbps]	freqs[48]	69	1			T249	3		T263	2		T125	3
auto[BaudRate1Mbps]	freqs[50]	105	1			T40	1		T118	2		T30	2
auto[BaudRate1Mbps]	freqs[100]	224	1			T32	1		T17	2		T35	2
auto[BaudRate1p5Mbps]	freqs[25]	85	1			T250	3		T122	2		T151	3
auto[BaudRate1p5Mbps]	freqs[48]	77	1			T3	1		T249	1		T263	2
auto[BaudRate1p5Mbps]	freqs[50]	134	1			T40	3		T118	2		T30	6
auto[BaudRate1p5Mbps]	freqs[100]	233	1			T32	2		T17	3		T35	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded