Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.45	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	7	123	94.62

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	7	123	94.62	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	27958643	1			T1	60		T4	18		T5	1
all_levels[1]	183345	1			T1	11		T6	2378		T7	6
all_levels[2]	2612	1			T1	3		T6	41		T7	8
all_levels[3]	1105	1			T1	1		T7	1		T9	2
all_levels[4]	742	1			T7	3		T9	3		T14	4
all_levels[5]	583	1			T7	2		T34	1		T35	1
all_levels[6]	440	1			T7	1		T14	3		T13	1
all_levels[7]	328	1			T9	1		T14	2		T13	1
all_levels[8]	282	1			T9	3		T34	1		T36	1
all_levels[9]	257	1			T14	2		T34	2		T12	1
all_levels[10]	219	1			T1	1		T34	1		T36	2
all_levels[11]	195	1			T1	1		T34	2		T38	1
all_levels[12]	176	1			T9	3		T14	2		T34	5
all_levels[13]	131	1			T34	1		T116	2		T25	1
all_levels[14]	126	1			T9	1		T12	1		T38	1
all_levels[15]	111	1			T14	1		T35	2		T117	1
all_levels[16]	109	1			T9	1		T34	2		T38	1
all_levels[17]	126	1			T9	2		T14	1		T24	1
all_levels[18]	83	1			T118	2		T28	1		T119	4
all_levels[19]	92	1			T34	1		T24	1		T42	1
all_levels[20]	63	1			T103	1		T46	1		T29	2
all_levels[21]	80	1			T103	1		T24	2		T117	1
all_levels[22]	64	1			T38	1		T120	2		T121	1
all_levels[23]	68	1			T103	2		T116	1		T122	1
all_levels[24]	55	1			T14	1		T35	1		T24	1
all_levels[25]	56	1			T103	1		T24	1		T121	1
all_levels[26]	52	1			T32	1		T35	1		T103	2
all_levels[27]	45	1			T35	1		T116	1		T123	1
all_levels[28]	37	1			T103	1		T24	1		T124	2
all_levels[29]	44	1			T27	1		T29	1		T125	1
all_levels[30]	34	1			T34	1		T25	1		T123	1
all_levels[31]	49	1			T116	1		T27	1		T117	2
all_levels[32]	37	1			T35	1		T126	1		T42	1
all_levels[33]	34	1			T42	2		T118	4		T121	1
all_levels[34]	23	1			T35	1		T122	1		T127	1
all_levels[35]	31	1			T24	1		T128	2		T129	1
all_levels[36]	24	1			T30	1		T102	1		T130	1
all_levels[37]	28	1			T35	1		T123	1		T131	1
all_levels[38]	15	1			T122	1		T132	2		T133	1
all_levels[39]	14	1			T134	1		T87	1		T135	2
all_levels[40]	28	1			T38	1		T119	1		T136	1
all_levels[41]	19	1			T126	1		T24	1		T129	2
all_levels[42]	30	1			T122	1		T113	1		T137	1
all_levels[43]	19	1			T124	1		T105	2		T138	1
all_levels[44]	20	1			T15	1		T108	2		T139	1
all_levels[45]	19	1			T102	1		T140	1		T141	1
all_levels[46]	15	1			T38	1		T142	2		T143	1
all_levels[47]	13	1			T144	1		T142	2		T145	1
all_levels[48]	20	1			T46	6		T123	1		T146	1
all_levels[49]	18	1			T122	1		T147	3		T148	1
all_levels[50]	8	1			T144	1		T149	1		T150	1
all_levels[51]	15	1			T9	1		T29	1		T151	1
all_levels[52]	9	1			T9	2		T152	1		T153	1
all_levels[53]	10	1			T108	1		T139	1		T154	1
all_levels[54]	8	1			T108	3		T155	1		T156	1
all_levels[55]	10	1			T157	3		T96	1		T87	1
all_levels[56]	5	1			T29	1		T158	1		T159	2
all_levels[57]	10	1			T44	2		T160	1		T146	1
all_levels[58]	8	1			T28	1		T113	1		T134	1
all_levels[59]	15	1			T161	1		T162	2		T163	1
all_levels[60]	5	1			T146	1		T164	1		T52	1
all_levels[61]	6	1			T165	1		T87	1		T166	1
all_levels[62]	12	1			T167	1		T136	1		T87	1
all_levels[63]	10	1			T38	1		T168	1		T169	1
all_levels[64]	132	1			T12	3		T38	1		T42	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28146177

1

T1

77

T6

100477

T7

52

auto[1]

4845

1

T4

18

T5

1

T6

5

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	7	123	94.62	7

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[30]]	[auto[1]]	0	1	1
[all_levels[39]]	[auto[1]]	0	1	1
[all_levels[43]]	[auto[1]]	0	1	1
[all_levels[52] , all_levels[53]]	[auto[1]]	--	--	2
[all_levels[56]]	[auto[1]]	0	1	1
[all_levels[61]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	27954271	1			T1	60		T6	98058		T7	31
all_levels[0]	auto[1]	4372	1			T4	18		T5	1		T6	5
all_levels[1]	auto[0]	183266	1			T1	11		T6	2378		T7	6
all_levels[1]	auto[1]	79	1			T116	1		T24	1		T170	1
all_levels[2]	auto[0]	2576	1			T1	3		T6	41		T7	8
all_levels[2]	auto[1]	36	1			T12	1		T171	1		T172	2
all_levels[3]	auto[0]	1076	1			T1	1		T7	1		T9	2
all_levels[3]	auto[1]	29	1			T12	3		T118	1		T173	2
all_levels[4]	auto[0]	724	1			T7	3		T9	3		T14	4
all_levels[4]	auto[1]	18	1			T170	1		T174	1		T175	1
all_levels[5]	auto[0]	556	1			T7	2		T34	1		T35	1
all_levels[5]	auto[1]	27	1			T27	4		T119	1		T176	2
all_levels[6]	auto[0]	427	1			T7	1		T14	3		T13	1
all_levels[6]	auto[1]	13	1			T177	4		T178	1		T179	2
all_levels[7]	auto[0]	319	1			T9	1		T14	2		T13	1
all_levels[7]	auto[1]	9	1			T117	1		T180	3		T181	1
all_levels[8]	auto[0]	270	1			T9	3		T34	1		T36	1
all_levels[8]	auto[1]	12	1			T116	1		T173	2		T95	1
all_levels[9]	auto[0]	241	1			T14	2		T34	2		T12	1
all_levels[9]	auto[1]	16	1			T117	3		T182	1		T183	1
all_levels[10]	auto[0]	210	1			T1	1		T34	1		T36	2
all_levels[10]	auto[1]	9	1			T155	1		T184	2		T185	1
all_levels[11]	auto[0]	186	1			T1	1		T34	2		T38	1
all_levels[11]	auto[1]	9	1			T186	1		T185	1		T187	2
all_levels[12]	auto[0]	162	1			T9	3		T14	2		T34	2
all_levels[12]	auto[1]	14	1			T34	3		T175	1		T188	1
all_levels[13]	auto[0]	123	1			T34	1		T116	2		T25	1
all_levels[13]	auto[1]	8	1			T189	1		T190	2		T191	1
all_levels[14]	auto[0]	123	1			T9	1		T12	1		T38	1
all_levels[14]	auto[1]	3	1			T116	2		T192	1		-	-
all_levels[15]	auto[0]	107	1			T14	1		T35	2		T117	1
all_levels[15]	auto[1]	4	1			T127	1		T169	1		T193	1
all_levels[16]	auto[0]	98	1			T9	1		T34	2		T38	1
all_levels[16]	auto[1]	11	1			T105	1		T47	1		T194	2
all_levels[17]	auto[0]	112	1			T9	2		T14	1		T24	1
all_levels[17]	auto[1]	14	1			T195	5		T196	1		T197	1
all_levels[18]	auto[0]	79	1			T118	2		T28	1		T119	3
all_levels[18]	auto[1]	4	1			T119	1		T198	1		T175	1
all_levels[19]	auto[0]	89	1			T34	1		T24	1		T42	1
all_levels[19]	auto[1]	3	1			T124	2		T199	1		-	-
all_levels[20]	auto[0]	59	1			T103	1		T46	1		T29	2
all_levels[20]	auto[1]	4	1			T192	1		T200	3		-	-
all_levels[21]	auto[0]	69	1			T103	1		T24	2		T117	1
all_levels[21]	auto[1]	11	1			T201	2		T202	6		T203	3
all_levels[22]	auto[0]	60	1			T38	1		T120	1		T121	1
all_levels[22]	auto[1]	4	1			T120	1		T176	2		T204	1
all_levels[23]	auto[0]	63	1			T103	1		T116	1		T122	1
all_levels[23]	auto[1]	5	1			T103	1		T205	1		T206	1
all_levels[24]	auto[0]	50	1			T14	1		T35	1		T24	1
all_levels[24]	auto[1]	5	1			T207	1		T97	2		T208	1
all_levels[25]	auto[0]	50	1			T103	1		T24	1		T121	1
all_levels[25]	auto[1]	6	1			T192	1		T209	2		T210	1
all_levels[26]	auto[0]	48	1			T32	1		T35	1		T103	2
all_levels[26]	auto[1]	4	1			T162	2		T211	2		-	-
all_levels[27]	auto[0]	38	1			T35	1		T116	1		T123	1
all_levels[27]	auto[1]	7	1			T148	1		T212	1		T213	2
all_levels[28]	auto[0]	32	1			T103	1		T24	1		T124	1
all_levels[28]	auto[1]	5	1			T124	1		T214	1		T215	1
all_levels[29]	auto[0]	37	1			T27	1		T29	1		T125	1
all_levels[29]	auto[1]	7	1			T216	2		T217	1		T89	2
all_levels[30]	auto[0]	34	1			T34	1		T25	1		T123	1
all_levels[31]	auto[0]	41	1			T116	1		T27	1		T117	1
all_levels[31]	auto[1]	8	1			T117	1		T206	2		T218	2
all_levels[32]	auto[0]	35	1			T35	1		T126	1		T42	1
all_levels[32]	auto[1]	2	1			T219	1		T220	1		-	-
all_levels[33]	auto[0]	29	1			T42	2		T118	1		T121	1
all_levels[33]	auto[1]	5	1			T118	3		T221	1		T213	1
all_levels[34]	auto[0]	17	1			T35	1		T122	1		T127	1
all_levels[34]	auto[1]	6	1			T222	4		T223	2		-	-
all_levels[35]	auto[0]	27	1			T24	1		T128	1		T129	1
all_levels[35]	auto[1]	4	1			T128	1		T153	1		T197	1
all_levels[36]	auto[0]	21	1			T30	1		T102	1		T130	1
all_levels[36]	auto[1]	3	1			T224	1		T225	1		T226	1
all_levels[37]	auto[0]	23	1			T35	1		T123	1		T131	1
all_levels[37]	auto[1]	5	1			T199	1		T227	2		T228	1
all_levels[38]	auto[0]	14	1			T122	1		T132	1		T133	1
all_levels[38]	auto[1]	1	1			T132	1		-	-		-	-
all_levels[39]	auto[0]	14	1			T134	1		T87	1		T135	2
all_levels[40]	auto[0]	25	1			T38	1		T119	1		T136	1
all_levels[40]	auto[1]	3	1			T229	1		T230	2		-	-
all_levels[41]	auto[0]	18	1			T126	1		T24	1		T129	2
all_levels[41]	auto[1]	1	1			T231	1		-	-		-	-
all_levels[42]	auto[0]	23	1			T122	1		T113	1		T137	1
all_levels[42]	auto[1]	7	1			T47	4		T219	2		T232	1
all_levels[43]	auto[0]	19	1			T124	1		T105	2		T138	1
all_levels[44]	auto[0]	18	1			T15	1		T108	2		T139	1
all_levels[44]	auto[1]	2	1			T233	1		T234	1		-	-
all_levels[45]	auto[0]	16	1			T102	1		T140	1		T141	1
all_levels[45]	auto[1]	3	1			T235	3		-	-		-	-
all_levels[46]	auto[0]	13	1			T38	1		T142	1		T143	1
all_levels[46]	auto[1]	2	1			T142	1		T223	1		-	-
all_levels[47]	auto[0]	12	1			T144	1		T142	1		T145	1
all_levels[47]	auto[1]	1	1			T142	1		-	-		-	-
all_levels[48]	auto[0]	14	1			T46	1		T123	1		T146	1
all_levels[48]	auto[1]	6	1			T46	5		T236	1		-	-
all_levels[49]	auto[0]	16	1			T122	1		T147	1		T148	1
all_levels[49]	auto[1]	2	1			T147	2		-	-		-	-
all_levels[50]	auto[0]	7	1			T144	1		T149	1		T150	1
all_levels[50]	auto[1]	1	1			T237	1		-	-		-	-
all_levels[51]	auto[0]	13	1			T9	1		T29	1		T151	1
all_levels[51]	auto[1]	2	1			T205	1		T238	1		-	-
all_levels[52]	auto[0]	9	1			T9	2		T152	1		T153	1
all_levels[53]	auto[0]	10	1			T108	1		T139	1		T154	1
all_levels[54]	auto[0]	7	1			T108	2		T155	1		T156	1
all_levels[54]	auto[1]	1	1			T108	1		-	-		-	-
all_levels[55]	auto[0]	8	1			T157	1		T96	1		T87	1
all_levels[55]	auto[1]	2	1			T157	2		-	-		-	-
all_levels[56]	auto[0]	5	1			T29	1		T158	1		T159	2
all_levels[57]	auto[0]	9	1			T44	1		T160	1		T146	1
all_levels[57]	auto[1]	1	1			T44	1		-	-		-	-
all_levels[58]	auto[0]	6	1			T28	1		T113	1		T134	1
all_levels[58]	auto[1]	2	1			T213	2		-	-		-	-
all_levels[59]	auto[0]	12	1			T161	1		T162	1		T163	1
all_levels[59]	auto[1]	3	1			T162	1		T239	2		-	-
all_levels[60]	auto[0]	4	1			T146	1		T164	1		T52	1
all_levels[60]	auto[1]	1	1			T228	1		-	-		-	-
all_levels[61]	auto[0]	6	1			T165	1		T87	1		T166	1
all_levels[62]	auto[0]	8	1			T167	1		T136	1		T87	1
all_levels[62]	auto[1]	4	1			T240	2		T241	2		-	-
all_levels[63]	auto[0]	8	1			T38	1		T168	1		T169	1
all_levels[63]	auto[1]	2	1			T242	2		-	-		-	-
all_levels[64]	auto[0]	115	1			T12	1		T38	1		T42	1
all_levels[64]	auto[1]	17	1			T12	2		T182	2		T132	1