Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	105367	1			T1	11		T2	2		T3	2
all_pins[1]	105367	1			T1	11		T2	2		T3	2
all_pins[2]	105367	1			T1	11		T2	2		T3	2
all_pins[3]	105367	1			T1	11		T2	2		T3	2
all_pins[4]	105367	1			T1	11		T2	2		T3	2
all_pins[5]	105367	1			T1	11		T2	2		T3	2
all_pins[6]	105367	1			T1	11		T2	2		T3	2
all_pins[7]	105367	1			T1	11		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	814091	1			T1	85		T2	16		T3	16
values[0x1]	28845	1			T1	3		T4	30		T6	62
transitions[0x0=>0x1]	27777	1			T1	3		T4	30		T6	59
transitions[0x1=>0x0]	27353	1			T1	2		T4	30		T6	59

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	82729	1			T1	9		T2	2		T3	2
all_pins[0]	values[0x1]	22638	1			T1	2		T4	16		T6	43
all_pins[0]	transitions[0x0=>0x1]	22103	1			T1	2		T4	16		T6	41
all_pins[0]	transitions[0x1=>0x0]	1001	1			T9	5		T14	3		T31	4
all_pins[1]	values[0x0]	103831	1			T1	11		T2	2		T3	2
all_pins[1]	values[0x1]	1536	1			T6	2		T9	5		T14	3
all_pins[1]	transitions[0x0=>0x1]	1445	1			T6	2		T9	5		T14	3
all_pins[1]	transitions[0x1=>0x0]	2366	1			T1	1		T4	1		T6	7
all_pins[2]	values[0x0]	102910	1			T1	10		T2	2		T3	2
all_pins[2]	values[0x1]	2457	1			T1	1		T4	1		T6	7
all_pins[2]	transitions[0x0=>0x1]	2385	1			T1	1		T4	1		T6	6
all_pins[2]	transitions[0x1=>0x0]	253	1			T6	2		T9	3		T11	1
all_pins[3]	values[0x0]	105042	1			T1	11		T2	2		T3	2
all_pins[3]	values[0x1]	325	1			T6	3		T9	3		T11	1
all_pins[3]	transitions[0x0=>0x1]	282	1			T6	3		T9	3		T11	1
all_pins[3]	transitions[0x1=>0x0]	394	1			T4	13		T9	1		T17	1
all_pins[4]	values[0x0]	104930	1			T1	11		T2	2		T3	2
all_pins[4]	values[0x1]	437	1			T4	13		T9	1		T17	1
all_pins[4]	transitions[0x0=>0x1]	358	1			T4	13		T17	1		T15	5
all_pins[4]	transitions[0x1=>0x0]	154	1			T6	2		T9	2		T11	1
all_pins[5]	values[0x0]	105134	1			T1	11		T2	2		T3	2
all_pins[5]	values[0x1]	233	1			T6	2		T9	3		T11	1
all_pins[5]	transitions[0x0=>0x1]	181	1			T6	2		T9	2		T11	1
all_pins[5]	transitions[0x1=>0x0]	829	1			T6	4		T9	4		T31	3
all_pins[6]	values[0x0]	104486	1			T1	11		T2	2		T3	2
all_pins[6]	values[0x1]	881	1			T6	4		T9	5		T31	3
all_pins[6]	transitions[0x0=>0x1]	834	1			T6	4		T9	5		T31	3
all_pins[6]	transitions[0x1=>0x0]	291	1			T6	1		T9	4		T14	3
all_pins[7]	values[0x0]	105029	1			T1	11		T2	2		T3	2
all_pins[7]	values[0x1]	338	1			T6	1		T9	4		T14	3
all_pins[7]	transitions[0x0=>0x1]	189	1			T6	1		T9	2		T14	3
all_pins[7]	transitions[0x1=>0x0]	22065	1			T1	1		T4	16		T6	43