Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	8314303	1			T1	59		T4	16		T6	17393
all_levels[1]	1513945	1			T1	3		T6	1366		T9	144
all_levels[2]	259662	1			T6	975		T9	74		T13	8
all_levels[3]	255975	1			T6	1193		T9	84		T13	11
all_levels[4]	281592	1			T6	1686		T9	7493		T13	4
all_levels[5]	218380	1			T6	1555		T7	8		T9	92
all_levels[6]	204419	1			T6	1368		T9	149		T13	2
all_levels[7]	293830	1			T6	1579		T9	1907		T13	6
all_levels[8]	342420	1			T1	2		T6	1576		T7	3
all_levels[9]	344814	1			T1	6		T6	15986		T9	144
all_levels[10]	217972	1			T6	1738		T9	137		T13	229
all_levels[11]	199809	1			T6	1401		T9	144		T31	74
all_levels[12]	309778	1			T6	1242		T9	147		T13	6
all_levels[13]	188271	1			T6	1455		T9	151		T14	2
all_levels[14]	273385	1			T6	1438		T9	71		T13	18
all_levels[15]	280273	1			T6	1658		T9	76		T31	7
all_levels[16]	231001	1			T1	2		T6	1432		T9	70
all_levels[17]	303218	1			T1	5		T6	1395		T9	72
all_levels[18]	184712	1			T6	1149		T9	6361		T31	11
all_levels[19]	194836	1			T6	1651		T9	145		T31	18
all_levels[20]	282810	1			T6	1311		T9	112		T13	2
all_levels[21]	521903	1			T6	1331		T9	74		T13	15
all_levels[22]	617906	1			T6	984		T9	71		T31	19
all_levels[23]	245322	1			T6	1364		T9	42		T31	22
all_levels[24]	228006	1			T6	1336		T9	156		T31	7
all_levels[25]	289175	1			T6	1436		T9	288		T31	17
all_levels[26]	362229	1			T6	1285		T9	292		T31	20
all_levels[27]	178880	1			T6	1167		T9	13578		T31	18
all_levels[28]	230668	1			T6	1341		T9	272		T31	9
all_levels[29]	277311	1			T6	1509		T9	289		T31	27
all_levels[30]	185078	1			T6	1412		T9	288		T31	15
all_levels[31]	539736	1			T6	2988		T9	392		T31	26
all_levels[32]	9778946	1			T6	23779		T7	2		T9	20656

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28146177

1

T1

77

T6

100477

T7

52

auto[1]

4388

1

T4

16

T6

2

T7

7

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	8311915	1			T1	59		T6	17392		T7	41
all_levels[0]	auto[1]	2388	1			T4	16		T6	1		T7	5
all_levels[1]	auto[0]	1513593	1			T1	3		T6	1366		T9	144
all_levels[1]	auto[1]	352	1			T24	1		T42	1		T117	2
all_levels[2]	auto[0]	259632	1			T6	975		T9	74		T13	8
all_levels[2]	auto[1]	30	1			T201	1		T172	1		T146	1
all_levels[3]	auto[0]	255864	1			T6	1193		T9	77		T13	11
all_levels[3]	auto[1]	111	1			T9	7		T12	1		T118	1
all_levels[4]	auto[0]	281574	1			T6	1686		T9	7493		T13	4
all_levels[4]	auto[1]	18	1			T182	1		T256	1		T127	1
all_levels[5]	auto[0]	218339	1			T6	1555		T7	7		T9	92
all_levels[5]	auto[1]	41	1			T7	1		T38	1		T119	2
all_levels[6]	auto[0]	204397	1			T6	1368		T9	149		T13	2
all_levels[6]	auto[1]	22	1			T116	1		T273	1		T259	1
all_levels[7]	auto[0]	293653	1			T6	1579		T9	1907		T13	6
all_levels[7]	auto[1]	177	1			T104	8		T260	1		T128	1
all_levels[8]	auto[0]	342387	1			T1	2		T6	1576		T7	3
all_levels[8]	auto[1]	33	1			T9	1		T38	1		T260	1
all_levels[9]	auto[0]	344747	1			T1	6		T6	15986		T9	144
all_levels[9]	auto[1]	67	1			T128	1		T262	1		T307	1
all_levels[10]	auto[0]	217943	1			T6	1738		T9	137		T13	229
all_levels[10]	auto[1]	29	1			T102	1		T176	1		T308	1
all_levels[11]	auto[0]	199762	1			T6	1401		T9	144		T31	74
all_levels[11]	auto[1]	47	1			T24	3		T182	1		T309	1
all_levels[12]	auto[0]	309741	1			T6	1242		T9	146		T13	6
all_levels[12]	auto[1]	37	1			T9	1		T263	1		T105	1
all_levels[13]	auto[0]	188244	1			T6	1455		T9	151		T14	2
all_levels[13]	auto[1]	27	1			T310	1		T160	2		T127	1
all_levels[14]	auto[0]	273374	1			T6	1438		T9	71		T13	18
all_levels[14]	auto[1]	11	1			T243	1		T273	1		T291	1
all_levels[15]	auto[0]	280131	1			T6	1658		T9	76		T31	7
all_levels[15]	auto[1]	142	1			T15	6		T195	4		T106	4
all_levels[16]	auto[0]	230980	1			T1	2		T6	1432		T9	70
all_levels[16]	auto[1]	21	1			T275	1		T108	1		T264	1
all_levels[17]	auto[0]	303187	1			T1	5		T6	1395		T9	72
all_levels[17]	auto[1]	31	1			T305	1		T161	2		T311	1
all_levels[18]	auto[0]	184684	1			T6	1149		T9	6361		T31	11
all_levels[18]	auto[1]	28	1			T120	1		T119	1		T124	1
all_levels[19]	auto[0]	194820	1			T6	1651		T9	145		T31	18
all_levels[19]	auto[1]	16	1			T119	1		T127	1		T165	4
all_levels[20]	auto[0]	282790	1			T6	1311		T9	112		T13	2
all_levels[20]	auto[1]	20	1			T32	2		T299	3		T271	1
all_levels[21]	auto[0]	521884	1			T6	1331		T9	73		T13	15
all_levels[21]	auto[1]	19	1			T9	1		T12	2		T171	1
all_levels[22]	auto[0]	617872	1			T6	984		T9	71		T31	19
all_levels[22]	auto[1]	34	1			T120	1		T30	1		T246	17
all_levels[23]	auto[0]	245300	1			T6	1364		T9	42		T31	22
all_levels[23]	auto[1]	22	1			T133	1		T312	3		T191	1
all_levels[24]	auto[0]	227979	1			T6	1336		T9	156		T31	7
all_levels[24]	auto[1]	27	1			T144	1		T313	2		T205	1
all_levels[25]	auto[0]	289149	1			T6	1436		T9	288		T31	17
all_levels[25]	auto[1]	26	1			T300	1		T231	2		T146	1
all_levels[26]	auto[0]	362216	1			T6	1285		T9	292		T31	20
all_levels[26]	auto[1]	13	1			T147	2		T273	3		T127	1
all_levels[27]	auto[0]	178864	1			T6	1167		T9	13578		T31	18
all_levels[27]	auto[1]	16	1			T46	5		T119	1		T314	1
all_levels[28]	auto[0]	230662	1			T6	1341		T9	272		T31	9
all_levels[28]	auto[1]	6	1			T315	1		T185	1		T233	2
all_levels[29]	auto[0]	277298	1			T6	1509		T9	289		T31	27
all_levels[29]	auto[1]	13	1			T289	2		T316	1		T317	2
all_levels[30]	auto[0]	185058	1			T6	1412		T9	288		T31	15
all_levels[30]	auto[1]	20	1			T186	1		T221	1		T318	1
all_levels[31]	auto[0]	539713	1			T6	2988		T9	392		T31	26
all_levels[31]	auto[1]	23	1			T34	1		T201	1		T176	1
all_levels[32]	auto[0]	9778425	1			T6	23778		T7	1		T9	20647
all_levels[32]	auto[1]	521	1			T6	1		T7	1		T9	9