Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	688	1			T6	14		T9	7		T17	4
all_values[1]	688	1			T6	14		T9	7		T17	4
all_values[2]	688	1			T6	14		T9	7		T17	4
all_values[3]	688	1			T6	14		T9	7		T17	4
all_values[4]	688	1			T6	14		T9	7		T17	4
all_values[5]	688	1			T6	14		T9	7		T17	4
all_values[6]	688	1			T6	14		T9	7		T17	4
all_values[7]	688	1			T6	14		T9	7		T17	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2988

1

T6

62

T9

26

T17

18

auto[1]

2516

1

T6

50

T9

30

T17

14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1992

1

T6

45

T9

15

T17

14

auto[1]

3512

1

T6

67

T9

41

T17

18

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3242

1

T6

69

T9

31

T17

20

auto[1]

2262

1

T6

43

T9

25

T17

12

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	4	44	91.67	4
Automatically Generated Cross Bins	48	4	44	91.67	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	223	1			T6	6		T9	1		T17	2
all_values[0]	auto[0]	auto[1]	auto[1]	182	1			T6	3		T9	3		T27	1
all_values[0]	auto[1]	auto[0]	auto[1]	163	1			T6	3		T17	2		T28	3
all_values[0]	auto[1]	auto[1]	auto[1]	120	1			T6	2		T9	3		T27	2
all_values[1]	auto[0]	auto[0]	auto[0]	246	1			T6	5		T9	1		T17	3
all_values[1]	auto[0]	auto[1]	auto[0]	168	1			T6	4		T9	2		T17	1
all_values[1]	auto[1]	auto[0]	auto[1]	155	1			T6	2		T9	3		T28	6
all_values[1]	auto[1]	auto[1]	auto[1]	119	1			T6	3		T9	1		T27	1
all_values[2]	auto[0]	auto[0]	auto[0]	140	1			T6	3		T17	1		T27	2
all_values[2]	auto[0]	auto[0]	auto[1]	79	1			T6	5		T9	1		T28	2
all_values[2]	auto[0]	auto[1]	auto[0]	121	1			T9	4		T17	2		T28	3
all_values[2]	auto[0]	auto[1]	auto[1]	66	1			T6	2		T27	2		T28	1
all_values[2]	auto[1]	auto[0]	auto[1]	151	1			T6	3		T9	1		T27	1
all_values[2]	auto[1]	auto[1]	auto[1]	131	1			T6	1		T9	1		T17	1
all_values[3]	auto[0]	auto[0]	auto[0]	134	1			T6	2		T27	1		T28	4
all_values[3]	auto[0]	auto[0]	auto[1]	61	1			T6	1		T9	2		T17	2
all_values[3]	auto[0]	auto[1]	auto[0]	109	1			T6	3		T9	1		T27	3
all_values[3]	auto[0]	auto[1]	auto[1]	84	1			T6	1		T9	1		T27	1
all_values[3]	auto[1]	auto[0]	auto[1]	167	1			T6	5		T9	3		T17	1
all_values[3]	auto[1]	auto[1]	auto[1]	133	1			T6	2		T17	1		T27	2
all_values[4]	auto[0]	auto[0]	auto[0]	155	1			T6	3		T17	1		T27	2
all_values[4]	auto[0]	auto[0]	auto[1]	77	1			T9	3		T27	1		T28	2
all_values[4]	auto[0]	auto[1]	auto[0]	120	1			T6	5		T17	1		T27	1
all_values[4]	auto[0]	auto[1]	auto[1]	67	1			T17	1		T28	1		T102	1
all_values[4]	auto[1]	auto[0]	auto[1]	136	1			T6	5		T9	3		T27	2
all_values[4]	auto[1]	auto[1]	auto[1]	133	1			T6	1		T9	1		T17	1
all_values[5]	auto[0]	auto[0]	auto[0]	136	1			T6	3		T9	1		T27	4
all_values[5]	auto[0]	auto[0]	auto[1]	59	1			T6	2		T17	1		T113	1
all_values[5]	auto[0]	auto[1]	auto[0]	134	1			T6	2		T9	2		T17	1
all_values[5]	auto[0]	auto[1]	auto[1]	76	1			T6	1		T9	1		T28	5
all_values[5]	auto[1]	auto[0]	auto[1]	152	1			T6	3		T9	1		T17	2
all_values[5]	auto[1]	auto[1]	auto[1]	131	1			T6	3		T9	2		T28	1
all_values[6]	auto[0]	auto[0]	auto[0]	157	1			T6	1		T9	2		T17	2
all_values[6]	auto[0]	auto[0]	auto[1]	74	1			T28	1		T114	2		T115	1
all_values[6]	auto[0]	auto[1]	auto[0]	111	1			T6	7		T9	2		T17	1
all_values[6]	auto[0]	auto[1]	auto[1]	63	1			T6	2		T9	1		T27	2
all_values[6]	auto[1]	auto[0]	auto[1]	147	1			T6	3		T9	1		T17	1
all_values[6]	auto[1]	auto[1]	auto[1]	136	1			T6	1		T9	1		T27	3
all_values[7]	auto[0]	auto[0]	auto[0]	134	1			T6	4		T27	2		T102	1
all_values[7]	auto[0]	auto[0]	auto[1]	77	1			T28	5		T102	1		T114	1
all_values[7]	auto[0]	auto[1]	auto[0]	127	1			T6	3		T17	1		T27	5
all_values[7]	auto[0]	auto[1]	auto[1]	62	1			T6	1		T9	3		T102	1
all_values[7]	auto[1]	auto[0]	auto[1]	165	1			T6	3		T9	3		T28	6
all_values[7]	auto[1]	auto[1]	auto[1]	123	1			T6	3		T9	1		T17	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal