Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.28 99.27 97.95 100.00 98.80 100.00 99.66


Total test records in report: 1319
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T1255 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1655054885 May 02 03:49:27 PM PDT 24 May 02 03:49:29 PM PDT 24 175168284 ps
T1256 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1836101819 May 02 03:49:32 PM PDT 24 May 02 03:49:35 PM PDT 24 186974736 ps
T63 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3472177046 May 02 03:49:15 PM PDT 24 May 02 03:49:17 PM PDT 24 20047594 ps
T1257 /workspace/coverage/cover_reg_top/4.uart_intr_test.4037803552 May 02 03:49:18 PM PDT 24 May 02 03:49:19 PM PDT 24 53029901 ps
T1258 /workspace/coverage/cover_reg_top/33.uart_intr_test.662468663 May 02 03:50:03 PM PDT 24 May 02 03:50:04 PM PDT 24 12978989 ps
T1259 /workspace/coverage/cover_reg_top/23.uart_intr_test.573223088 May 02 03:49:29 PM PDT 24 May 02 03:49:31 PM PDT 24 17351848 ps
T1260 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3931562611 May 02 03:49:16 PM PDT 24 May 02 03:49:18 PM PDT 24 17332176 ps
T1261 /workspace/coverage/cover_reg_top/28.uart_intr_test.2405643838 May 02 03:49:30 PM PDT 24 May 02 03:49:32 PM PDT 24 30786348 ps
T1262 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.4054774888 May 02 03:49:21 PM PDT 24 May 02 03:49:22 PM PDT 24 58031764 ps
T111 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.194876956 May 02 03:49:29 PM PDT 24 May 02 03:49:33 PM PDT 24 68764417 ps
T1263 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.501795690 May 02 03:49:30 PM PDT 24 May 02 03:49:42 PM PDT 24 18332419 ps
T1264 /workspace/coverage/cover_reg_top/47.uart_intr_test.1745764758 May 02 03:49:34 PM PDT 24 May 02 03:49:36 PM PDT 24 30473401 ps
T1265 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1296632828 May 02 03:49:03 PM PDT 24 May 02 03:49:06 PM PDT 24 304798929 ps
T1266 /workspace/coverage/cover_reg_top/10.uart_csr_rw.4249618232 May 02 03:49:29 PM PDT 24 May 02 03:49:32 PM PDT 24 25915047 ps
T1267 /workspace/coverage/cover_reg_top/21.uart_intr_test.2035845657 May 02 03:49:24 PM PDT 24 May 02 03:49:27 PM PDT 24 17638347 ps
T1268 /workspace/coverage/cover_reg_top/29.uart_intr_test.992329897 May 02 03:49:27 PM PDT 24 May 02 03:49:29 PM PDT 24 85812300 ps
T1269 /workspace/coverage/cover_reg_top/26.uart_intr_test.4105298402 May 02 03:49:24 PM PDT 24 May 02 03:49:27 PM PDT 24 12306266 ps
T1270 /workspace/coverage/cover_reg_top/43.uart_intr_test.2398466093 May 02 03:50:09 PM PDT 24 May 02 03:50:11 PM PDT 24 15484883 ps
T1271 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.903255631 May 02 03:49:20 PM PDT 24 May 02 03:49:22 PM PDT 24 46804960 ps
T1272 /workspace/coverage/cover_reg_top/46.uart_intr_test.765366362 May 02 03:49:37 PM PDT 24 May 02 03:49:38 PM PDT 24 79874626 ps
T1273 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3203076009 May 02 03:49:28 PM PDT 24 May 02 03:49:30 PM PDT 24 35861218 ps
T1274 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.2292743126 May 02 03:49:18 PM PDT 24 May 02 03:49:20 PM PDT 24 55020351 ps
T1275 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1676145278 May 02 03:49:26 PM PDT 24 May 02 03:49:29 PM PDT 24 88017787 ps
T1276 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3754434758 May 02 03:49:31 PM PDT 24 May 02 03:49:34 PM PDT 24 42967727 ps
T1277 /workspace/coverage/cover_reg_top/40.uart_intr_test.858937769 May 02 03:49:30 PM PDT 24 May 02 03:49:33 PM PDT 24 32108381 ps
T1278 /workspace/coverage/cover_reg_top/19.uart_intr_test.4147074947 May 02 03:49:30 PM PDT 24 May 02 03:49:33 PM PDT 24 31701925 ps
T1279 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.8803899 May 02 03:49:24 PM PDT 24 May 02 03:49:27 PM PDT 24 104425466 ps
T1280 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3695825573 May 02 03:49:26 PM PDT 24 May 02 03:49:29 PM PDT 24 29711357 ps
T1281 /workspace/coverage/cover_reg_top/12.uart_intr_test.3757316154 May 02 03:49:22 PM PDT 24 May 02 03:49:24 PM PDT 24 17023466 ps
T1282 /workspace/coverage/cover_reg_top/37.uart_intr_test.2708757474 May 02 03:49:31 PM PDT 24 May 02 03:49:34 PM PDT 24 11894252 ps
T62 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.516595828 May 02 03:49:21 PM PDT 24 May 02 03:49:23 PM PDT 24 54676467 ps
T1283 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1094139210 May 02 03:49:29 PM PDT 24 May 02 03:49:31 PM PDT 24 34419218 ps
T1284 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1491242654 May 02 03:49:19 PM PDT 24 May 02 03:49:21 PM PDT 24 33641231 ps
T1285 /workspace/coverage/cover_reg_top/10.uart_tl_errors.531605752 May 02 03:49:28 PM PDT 24 May 02 03:49:32 PM PDT 24 64000294 ps
T64 /workspace/coverage/cover_reg_top/2.uart_csr_rw.545753973 May 02 03:49:20 PM PDT 24 May 02 03:49:22 PM PDT 24 12591248 ps
T1286 /workspace/coverage/cover_reg_top/0.uart_tl_errors.2804610800 May 02 03:49:12 PM PDT 24 May 02 03:49:14 PM PDT 24 87176772 ps
T1287 /workspace/coverage/cover_reg_top/6.uart_intr_test.999511391 May 02 03:49:30 PM PDT 24 May 02 03:49:33 PM PDT 24 13264370 ps
T1288 /workspace/coverage/cover_reg_top/32.uart_intr_test.1299341049 May 02 03:49:23 PM PDT 24 May 02 03:49:24 PM PDT 24 102855728 ps
T1289 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1020372215 May 02 03:49:22 PM PDT 24 May 02 03:49:24 PM PDT 24 69080335 ps
T1290 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3462896862 May 02 03:49:24 PM PDT 24 May 02 03:49:26 PM PDT 24 22028946 ps
T1291 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.203891705 May 02 03:49:32 PM PDT 24 May 02 03:49:35 PM PDT 24 36254332 ps
T1292 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.4206950667 May 02 03:49:17 PM PDT 24 May 02 03:49:20 PM PDT 24 182622722 ps
T1293 /workspace/coverage/cover_reg_top/17.uart_tl_errors.259038239 May 02 03:49:31 PM PDT 24 May 02 03:49:44 PM PDT 24 54539541 ps
T1294 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2266822252 May 02 03:49:25 PM PDT 24 May 02 03:49:29 PM PDT 24 113778118 ps
T1295 /workspace/coverage/cover_reg_top/11.uart_tl_errors.3189408534 May 02 03:49:25 PM PDT 24 May 02 03:49:30 PM PDT 24 159021227 ps
T1296 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.886071338 May 02 03:49:21 PM PDT 24 May 02 03:49:23 PM PDT 24 655295323 ps
T1297 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.4079271777 May 02 03:49:13 PM PDT 24 May 02 03:49:15 PM PDT 24 14086811 ps
T1298 /workspace/coverage/cover_reg_top/24.uart_intr_test.3518274847 May 02 03:49:30 PM PDT 24 May 02 03:49:34 PM PDT 24 71798281 ps
T1299 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1868577565 May 02 03:49:15 PM PDT 24 May 02 03:49:17 PM PDT 24 109827393 ps
T1300 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2436226678 May 02 03:49:11 PM PDT 24 May 02 03:49:13 PM PDT 24 116501965 ps
T1301 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.2059954238 May 02 03:49:28 PM PDT 24 May 02 03:49:31 PM PDT 24 19168055 ps
T1302 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.665910305 May 02 03:49:31 PM PDT 24 May 02 03:49:35 PM PDT 24 40743450 ps
T1303 /workspace/coverage/cover_reg_top/11.uart_intr_test.4019664145 May 02 03:49:27 PM PDT 24 May 02 03:49:29 PM PDT 24 15258646 ps
T1304 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2625520690 May 02 03:49:30 PM PDT 24 May 02 03:49:33 PM PDT 24 67004362 ps
T1305 /workspace/coverage/cover_reg_top/18.uart_csr_rw.4093979533 May 02 03:49:29 PM PDT 24 May 02 03:49:32 PM PDT 24 50777856 ps
T1306 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.4062284982 May 02 03:49:23 PM PDT 24 May 02 03:49:26 PM PDT 24 24152283 ps
T1307 /workspace/coverage/cover_reg_top/6.uart_csr_rw.15433933 May 02 03:49:17 PM PDT 24 May 02 03:49:19 PM PDT 24 16610987 ps
T1308 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1322318185 May 02 03:49:23 PM PDT 24 May 02 03:49:26 PM PDT 24 33539662 ps
T1309 /workspace/coverage/cover_reg_top/13.uart_csr_rw.360563678 May 02 03:49:24 PM PDT 24 May 02 03:49:27 PM PDT 24 38094923 ps
T1310 /workspace/coverage/cover_reg_top/19.uart_tl_errors.3003193350 May 02 03:49:30 PM PDT 24 May 02 03:49:34 PM PDT 24 91136112 ps
T1311 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3761244375 May 02 03:48:56 PM PDT 24 May 02 03:48:59 PM PDT 24 63844629 ps
T1312 /workspace/coverage/cover_reg_top/5.uart_tl_errors.2465696869 May 02 03:49:29 PM PDT 24 May 02 03:49:33 PM PDT 24 120456396 ps
T1313 /workspace/coverage/cover_reg_top/9.uart_csr_rw.282588471 May 02 03:49:22 PM PDT 24 May 02 03:49:24 PM PDT 24 14604647 ps
T1314 /workspace/coverage/cover_reg_top/30.uart_intr_test.2981793784 May 02 03:49:34 PM PDT 24 May 02 03:49:36 PM PDT 24 13999138 ps
T1315 /workspace/coverage/cover_reg_top/45.uart_intr_test.1047616179 May 02 03:49:28 PM PDT 24 May 02 03:49:30 PM PDT 24 13545466 ps
T1316 /workspace/coverage/cover_reg_top/16.uart_csr_rw.1358491934 May 02 03:49:54 PM PDT 24 May 02 03:49:55 PM PDT 24 12524541 ps
T1317 /workspace/coverage/cover_reg_top/0.uart_csr_rw.669658186 May 02 03:49:09 PM PDT 24 May 02 03:49:11 PM PDT 24 58810094 ps
T1318 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3861456523 May 02 03:49:23 PM PDT 24 May 02 03:49:26 PM PDT 24 13863770 ps
T1319 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.321155418 May 02 03:49:12 PM PDT 24 May 02 03:49:14 PM PDT 24 202412629 ps

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.951109025
Short name T9
Test name
Test status
Simulation time 774222821576 ps
CPU time 649.65 seconds
Started May 02 02:30:51 PM PDT 24
Finished May 02 02:41:42 PM PDT 24
Peak memory 225256 kb
Host smart-aa15f899-6820-428b-adf8-b538cd228769
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951109025 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.951109025
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_stress_all.1524214924
Short name T15
Test name
Test status
Simulation time 296962021758 ps
CPU time 237.08 seconds
Started May 02 02:27:28 PM PDT 24
Finished May 02 02:31:28 PM PDT 24
Peak memory 200364 kb
Host smart-b124187d-67b1-49cb-ac82-ae84d0ba6fc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524214924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.1524214924
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.2191242748
Short name T113
Test name
Test status
Simulation time 275684134620 ps
CPU time 1503.87 seconds
Started May 02 02:26:12 PM PDT 24
Finished May 02 02:51:30 PM PDT 24
Peak memory 216884 kb
Host smart-7242ab8f-ef3f-4f32-9ac9-49fbfc16a94e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191242748 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.2191242748
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.2908299754
Short name T24
Test name
Test status
Simulation time 142499588279 ps
CPU time 467.93 seconds
Started May 02 02:29:59 PM PDT 24
Finished May 02 02:37:48 PM PDT 24
Peak memory 216492 kb
Host smart-2f7ed691-bbdc-4121-b780-66da559c0931
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908299754 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.2908299754
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.520988134
Short name T6
Test name
Test status
Simulation time 135179260859 ps
CPU time 604.72 seconds
Started May 02 02:31:41 PM PDT 24
Finished May 02 02:41:48 PM PDT 24
Peak memory 217076 kb
Host smart-b531c136-ad4b-4be7-93d3-b874d048c229
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520988134 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.520988134
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.471879919
Short name T29
Test name
Test status
Simulation time 100409500128 ps
CPU time 460.45 seconds
Started May 02 02:26:32 PM PDT 24
Finished May 02 02:34:18 PM PDT 24
Peak memory 217060 kb
Host smart-13b3b9c9-fafa-48c3-87fd-75bb099c1901
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471879919 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.471879919
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_stress_all.577306443
Short name T127
Test name
Test status
Simulation time 464358739834 ps
CPU time 462.96 seconds
Started May 02 02:26:39 PM PDT 24
Finished May 02 02:34:25 PM PDT 24
Peak memory 216844 kb
Host smart-be1e4d34-0741-4cae-97ca-c9994d54399c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577306443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.577306443
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.3422248637
Short name T246
Test name
Test status
Simulation time 374449042411 ps
CPU time 810 seconds
Started May 02 02:26:24 PM PDT 24
Finished May 02 02:40:04 PM PDT 24
Peak memory 225268 kb
Host smart-35d9d009-4901-40c2-8a29-b33f6a523154
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422248637 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.3422248637
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.3595404030
Short name T27
Test name
Test status
Simulation time 197684220400 ps
CPU time 958.47 seconds
Started May 02 02:24:47 PM PDT 24
Finished May 02 02:40:50 PM PDT 24
Peak memory 225284 kb
Host smart-1ef86b30-2e4d-4a1e-9508-cf1635fc3dc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595404030 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.3595404030
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.2907528380
Short name T78
Test name
Test status
Simulation time 89112812 ps
CPU time 1.36 seconds
Started May 02 03:49:55 PM PDT 24
Finished May 02 03:49:57 PM PDT 24
Peak memory 199608 kb
Host smart-02671f97-a774-4c74-bf2d-34783899aff7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907528380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.2907528380
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/default/11.uart_alert_test.1549280588
Short name T384
Test name
Test status
Simulation time 20900227 ps
CPU time 0.62 seconds
Started May 02 02:25:36 PM PDT 24
Finished May 02 02:25:39 PM PDT 24
Peak memory 194736 kb
Host smart-271190cb-d68e-44db-855f-b3fe0d518b89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549280588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.1549280588
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_stress_all.2287848788
Short name T130
Test name
Test status
Simulation time 317025588136 ps
CPU time 754.63 seconds
Started May 02 02:27:10 PM PDT 24
Finished May 02 02:39:47 PM PDT 24
Peak memory 200416 kb
Host smart-bbf3e8c8-ba57-4647-97a5-9ad6e9af9bbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287848788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.2287848788
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.4211352166
Short name T7
Test name
Test status
Simulation time 129120218050 ps
CPU time 44.67 seconds
Started May 02 02:33:29 PM PDT 24
Finished May 02 02:34:15 PM PDT 24
Peak memory 200320 kb
Host smart-d4517f88-aac3-4ba7-80f5-de35058d8667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211352166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.4211352166
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.961685743
Short name T108
Test name
Test status
Simulation time 407760264014 ps
CPU time 1216.24 seconds
Started May 02 02:25:03 PM PDT 24
Finished May 02 02:45:23 PM PDT 24
Peak memory 225808 kb
Host smart-84a22bf4-1adc-41ab-9c9e-df1825043c68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961685743 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.961685743
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.2029573723
Short name T30
Test name
Test status
Simulation time 46533202155 ps
CPU time 288.93 seconds
Started May 02 02:29:03 PM PDT 24
Finished May 02 02:33:53 PM PDT 24
Peak memory 215960 kb
Host smart-83794572-eb4f-4aea-ac25-a96685123ff5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029573723 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.2029573723
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_sec_cm.3528052026
Short name T21
Test name
Test status
Simulation time 730185911 ps
CPU time 0.85 seconds
Started May 02 02:24:30 PM PDT 24
Finished May 02 02:24:33 PM PDT 24
Peak memory 218648 kb
Host smart-1f4f3983-f007-451f-a1a6-8b925cce4cea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528052026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.3528052026
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.3457828514
Short name T103
Test name
Test status
Simulation time 106808740447 ps
CPU time 187.61 seconds
Started May 02 02:32:04 PM PDT 24
Finished May 02 02:35:13 PM PDT 24
Peak memory 200404 kb
Host smart-eca33d61-0be1-450c-b392-c5052fcba223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457828514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.3457828514
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_stress_all.2099119221
Short name T151
Test name
Test status
Simulation time 218429739902 ps
CPU time 179.45 seconds
Started May 02 02:28:44 PM PDT 24
Finished May 02 02:31:45 PM PDT 24
Peak memory 200460 kb
Host smart-596dc92d-657f-43b4-9a9c-b32b63dd033c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099119221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.2099119221
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.3715784608
Short name T59
Test name
Test status
Simulation time 37204933 ps
CPU time 0.62 seconds
Started May 02 03:49:21 PM PDT 24
Finished May 02 03:49:23 PM PDT 24
Peak memory 195708 kb
Host smart-64fd39aa-b4d8-44df-bf0f-2bab1fe4ec10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715784608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.3715784608
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.911735438
Short name T192
Test name
Test status
Simulation time 211626831782 ps
CPU time 176.56 seconds
Started May 02 02:32:42 PM PDT 24
Finished May 02 02:35:40 PM PDT 24
Peak memory 200312 kb
Host smart-61e167c3-84a4-4262-9537-c45c2694f492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911735438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.911735438
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.1940539780
Short name T35
Test name
Test status
Simulation time 62228158305 ps
CPU time 117.84 seconds
Started May 02 02:26:13 PM PDT 24
Finished May 02 02:28:24 PM PDT 24
Peak memory 200444 kb
Host smart-89ebc28a-137e-46d6-8132-238c3a5eed3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940539780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.1940539780
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.1265070433
Short name T147
Test name
Test status
Simulation time 76834876783 ps
CPU time 38.4 seconds
Started May 02 02:30:50 PM PDT 24
Finished May 02 02:31:29 PM PDT 24
Peak memory 200308 kb
Host smart-f483947e-ab3b-469a-bb49-863248e11584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265070433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.1265070433
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.4222501141
Short name T135
Test name
Test status
Simulation time 76816207934 ps
CPU time 129.92 seconds
Started May 02 02:30:30 PM PDT 24
Finished May 02 02:32:42 PM PDT 24
Peak memory 200332 kb
Host smart-aeb7b04e-3503-4b5e-82b5-8d109493378c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222501141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.4222501141
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.290997437
Short name T118
Test name
Test status
Simulation time 39401209745 ps
CPU time 54.29 seconds
Started May 02 02:24:46 PM PDT 24
Finished May 02 02:25:45 PM PDT 24
Peak memory 200368 kb
Host smart-fe15e667-d6bb-46ea-a837-a913b6f3b9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290997437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.290997437
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.464276034
Short name T119
Test name
Test status
Simulation time 62482238324 ps
CPU time 168.25 seconds
Started May 02 02:32:27 PM PDT 24
Finished May 02 02:35:16 PM PDT 24
Peak memory 200392 kb
Host smart-400b1521-f3b3-4d67-98c2-37fbb311ae03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464276034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.464276034
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.4022875771
Short name T124
Test name
Test status
Simulation time 76091414028 ps
CPU time 21.34 seconds
Started May 02 02:32:51 PM PDT 24
Finished May 02 02:33:13 PM PDT 24
Peak memory 200336 kb
Host smart-cec7aece-8cea-4c46-b8b7-9603cf878f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022875771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.4022875771
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.950379704
Short name T146
Test name
Test status
Simulation time 86785012249 ps
CPU time 25.36 seconds
Started May 02 02:32:57 PM PDT 24
Finished May 02 02:33:23 PM PDT 24
Peak memory 200408 kb
Host smart-b2b35a1e-6b6d-4764-8ca1-522bdf02f560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950379704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.950379704
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.1085486780
Short name T183
Test name
Test status
Simulation time 202975325308 ps
CPU time 93.22 seconds
Started May 02 02:26:59 PM PDT 24
Finished May 02 02:28:34 PM PDT 24
Peak memory 200332 kb
Host smart-75a2022c-81c4-4222-be97-6ec6cf95fb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085486780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.1085486780
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_stress_all.1173718872
Short name T102
Test name
Test status
Simulation time 399974817437 ps
CPU time 119.96 seconds
Started May 02 02:24:46 PM PDT 24
Finished May 02 02:26:50 PM PDT 24
Peak memory 200428 kb
Host smart-6b26a676-69fe-4d6b-809e-fa9e30616412
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173718872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.1173718872
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.2135118913
Short name T87
Test name
Test status
Simulation time 121905363900 ps
CPU time 299.85 seconds
Started May 02 02:31:17 PM PDT 24
Finished May 02 02:36:19 PM PDT 24
Peak memory 209400 kb
Host smart-58480d5b-bc82-45d3-8a1d-c6634fa384cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135118913 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.2135118913
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2600854449
Short name T81
Test name
Test status
Simulation time 314272100 ps
CPU time 1.36 seconds
Started May 02 03:49:31 PM PDT 24
Finished May 02 03:49:35 PM PDT 24
Peak memory 199632 kb
Host smart-d02c82a4-f154-450d-958f-90b8fedbce1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600854449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.2600854449
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.2597065283
Short name T34
Test name
Test status
Simulation time 26922692582 ps
CPU time 52.62 seconds
Started May 02 02:32:44 PM PDT 24
Finished May 02 02:33:38 PM PDT 24
Peak memory 200336 kb
Host smart-8d3563c4-150f-4c74-a896-9e1719efe441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597065283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.2597065283
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.2138616673
Short name T752
Test name
Test status
Simulation time 108721094706 ps
CPU time 668.33 seconds
Started May 02 02:29:17 PM PDT 24
Finished May 02 02:40:27 PM PDT 24
Peak memory 225260 kb
Host smart-117511b9-8338-4032-a18f-d9799f9b39c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138616673 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.2138616673
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.3887519173
Short name T120
Test name
Test status
Simulation time 44635207066 ps
CPU time 115.5 seconds
Started May 02 02:31:33 PM PDT 24
Finished May 02 02:33:31 PM PDT 24
Peak memory 200368 kb
Host smart-6bb60038-6dc5-402e-8927-fabc81c3cd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887519173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.3887519173
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_stress_all.2482383145
Short name T242
Test name
Test status
Simulation time 547103248022 ps
CPU time 769.4 seconds
Started May 02 02:26:00 PM PDT 24
Finished May 02 02:39:03 PM PDT 24
Peak memory 200424 kb
Host smart-0df1d7b0-394c-4ee9-99c8-1d1cd140f5f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482383145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.2482383145
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all.3574945333
Short name T270
Test name
Test status
Simulation time 190925902453 ps
CPU time 323.7 seconds
Started May 02 02:26:01 PM PDT 24
Finished May 02 02:31:39 PM PDT 24
Peak memory 200400 kb
Host smart-cc1a9eca-ac6f-44e4-a285-e7e0331cc7dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574945333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.3574945333
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.1438661181
Short name T486
Test name
Test status
Simulation time 75044471626 ps
CPU time 64.61 seconds
Started May 02 02:32:56 PM PDT 24
Finished May 02 02:34:02 PM PDT 24
Peak memory 200328 kb
Host smart-59f6f8f1-9df6-42d9-bbc5-20eae6d6380e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438661181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1438661181
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.3817738232
Short name T250
Test name
Test status
Simulation time 66294120869 ps
CPU time 118.62 seconds
Started May 02 02:26:38 PM PDT 24
Finished May 02 02:28:40 PM PDT 24
Peak memory 200396 kb
Host smart-723abd70-6ce8-4334-a91d-80ad6758def4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3817738232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.3817738232
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.3046692707
Short name T219
Test name
Test status
Simulation time 54505366012 ps
CPU time 45.18 seconds
Started May 02 02:34:03 PM PDT 24
Finished May 02 02:34:49 PM PDT 24
Peak memory 200420 kb
Host smart-27e2a734-3f22-46fd-bd10-24dcd7a259b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046692707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.3046692707
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.2028583142
Short name T228
Test name
Test status
Simulation time 125723258728 ps
CPU time 62.89 seconds
Started May 02 02:31:56 PM PDT 24
Finished May 02 02:33:00 PM PDT 24
Peak memory 200348 kb
Host smart-35037053-766a-4f11-99ce-ff0eae176324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028583142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.2028583142
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.2923247348
Short name T185
Test name
Test status
Simulation time 60610326076 ps
CPU time 23.71 seconds
Started May 02 02:32:04 PM PDT 24
Finished May 02 02:32:29 PM PDT 24
Peak memory 200384 kb
Host smart-09fb3fea-bf68-41ec-9bd4-be18ec24cf33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923247348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.2923247348
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.2631339254
Short name T128
Test name
Test status
Simulation time 29555850012 ps
CPU time 54.33 seconds
Started May 02 02:32:05 PM PDT 24
Finished May 02 02:33:00 PM PDT 24
Peak memory 200408 kb
Host smart-707d6363-c478-4703-82e9-38e67dabac2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631339254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.2631339254
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.1167267828
Short name T195
Test name
Test status
Simulation time 122382478232 ps
CPU time 61.69 seconds
Started May 02 02:32:41 PM PDT 24
Finished May 02 02:33:44 PM PDT 24
Peak memory 200356 kb
Host smart-c54adb25-df36-41c5-95b5-da6b67355ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167267828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.1167267828
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.2530098155
Short name T237
Test name
Test status
Simulation time 48489221125 ps
CPU time 36.13 seconds
Started May 02 02:32:55 PM PDT 24
Finished May 02 02:33:32 PM PDT 24
Peak memory 200444 kb
Host smart-48f5cc2c-12af-4fa4-b87b-0c9eddc02c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530098155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.2530098155
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_stress_all.1192199631
Short name T125
Test name
Test status
Simulation time 85088329412 ps
CPU time 66.6 seconds
Started May 02 02:28:29 PM PDT 24
Finished May 02 02:29:38 PM PDT 24
Peak memory 200324 kb
Host smart-22ed93cc-0ece-484e-a0a0-d9f53d76fb8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192199631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.1192199631
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.3404820405
Short name T273
Test name
Test status
Simulation time 53126215469 ps
CPU time 96.72 seconds
Started May 02 02:30:57 PM PDT 24
Finished May 02 02:32:36 PM PDT 24
Peak memory 200444 kb
Host smart-adf245b8-a441-4f21-85d5-251156caf9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404820405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.3404820405
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.4232087654
Short name T223
Test name
Test status
Simulation time 25738479724 ps
CPU time 49.46 seconds
Started May 02 02:32:04 PM PDT 24
Finished May 02 02:32:55 PM PDT 24
Peak memory 200312 kb
Host smart-d94311b0-cffd-475d-ad0b-0db7383c6646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232087654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.4232087654
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.3380758783
Short name T229
Test name
Test status
Simulation time 56810150550 ps
CPU time 112.01 seconds
Started May 02 02:32:18 PM PDT 24
Finished May 02 02:34:11 PM PDT 24
Peak memory 200340 kb
Host smart-2900801d-3f81-49e2-9f9e-7a86172388ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380758783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.3380758783
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.1221589302
Short name T208
Test name
Test status
Simulation time 58136890531 ps
CPU time 27.03 seconds
Started May 02 02:32:41 PM PDT 24
Finished May 02 02:33:10 PM PDT 24
Peak memory 200368 kb
Host smart-8b4396f6-4004-4f5e-9548-47afe96b6618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221589302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.1221589302
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.4229444399
Short name T117
Test name
Test status
Simulation time 72550458342 ps
CPU time 38.74 seconds
Started May 02 02:33:05 PM PDT 24
Finished May 02 02:33:46 PM PDT 24
Peak memory 200272 kb
Host smart-99185891-406e-436c-9e75-189b90982a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229444399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.4229444399
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.3891539955
Short name T592
Test name
Test status
Simulation time 224989988249 ps
CPU time 256.56 seconds
Started May 02 02:33:22 PM PDT 24
Finished May 02 02:37:41 PM PDT 24
Peak memory 200420 kb
Host smart-ef48916e-bd47-47e4-9d5a-8e76a5f1d8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891539955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.3891539955
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.2456980852
Short name T191
Test name
Test status
Simulation time 179133867284 ps
CPU time 339.14 seconds
Started May 02 02:27:46 PM PDT 24
Finished May 02 02:33:28 PM PDT 24
Peak memory 200460 kb
Host smart-85cefe86-3856-4487-b729-7af4ea5d178f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456980852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.2456980852
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.3389443973
Short name T225
Test name
Test status
Simulation time 340284070026 ps
CPU time 790.82 seconds
Started May 02 02:31:17 PM PDT 24
Finished May 02 02:44:29 PM PDT 24
Peak memory 225268 kb
Host smart-08c38c24-60fa-4e74-bf13-34d664f7f80f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389443973 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.3389443973
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.1063832206
Short name T162
Test name
Test status
Simulation time 57178649026 ps
CPU time 92.26 seconds
Started May 02 02:31:17 PM PDT 24
Finished May 02 02:32:51 PM PDT 24
Peak memory 200324 kb
Host smart-8e7c749f-d76c-4329-ac6a-b3a31ad27f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063832206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.1063832206
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1296632828
Short name T1265
Test name
Test status
Simulation time 304798929 ps
CPU time 1.33 seconds
Started May 02 03:49:03 PM PDT 24
Finished May 02 03:49:06 PM PDT 24
Peak memory 199500 kb
Host smart-51cff8c4-0248-4bad-bb44-05880da7fcad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296632828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.1296632828
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_tx_rx.1167933881
Short name T311
Test name
Test status
Simulation time 8903549330 ps
CPU time 13.6 seconds
Started May 02 02:24:29 PM PDT 24
Finished May 02 02:24:44 PM PDT 24
Peak memory 197004 kb
Host smart-377d7c3c-acda-4eb2-a7d8-d5a873ddf316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167933881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.1167933881
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.4257861269
Short name T46
Test name
Test status
Simulation time 18131899244 ps
CPU time 20.71 seconds
Started May 02 02:31:57 PM PDT 24
Finished May 02 02:32:20 PM PDT 24
Peak memory 200328 kb
Host smart-a644d27c-fa92-418d-8114-be5eae427d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257861269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.4257861269
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.777728581
Short name T231
Test name
Test status
Simulation time 87909615995 ps
CPU time 35.77 seconds
Started May 02 02:31:57 PM PDT 24
Finished May 02 02:32:35 PM PDT 24
Peak memory 200400 kb
Host smart-9ca46a4f-afef-40fc-ad91-80139240ae42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777728581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.777728581
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.1608475812
Short name T157
Test name
Test status
Simulation time 84670767515 ps
CPU time 73.47 seconds
Started May 02 02:32:00 PM PDT 24
Finished May 02 02:33:15 PM PDT 24
Peak memory 200328 kb
Host smart-114a651e-1dc4-4db8-a05d-c10ccb554852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608475812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.1608475812
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_stress_all.1430511502
Short name T240
Test name
Test status
Simulation time 98995089669 ps
CPU time 51.6 seconds
Started May 02 02:25:53 PM PDT 24
Finished May 02 02:26:57 PM PDT 24
Peak memory 200396 kb
Host smart-bab3bb8c-5b4b-4076-9f51-ab098812c8eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430511502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.1430511502
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.1278489827
Short name T217
Test name
Test status
Simulation time 60292858411 ps
CPU time 83.29 seconds
Started May 02 02:32:28 PM PDT 24
Finished May 02 02:33:52 PM PDT 24
Peak memory 200348 kb
Host smart-885164e2-fdf6-4e00-9e71-11cd9ac378e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278489827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.1278489827
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.3321454034
Short name T314
Test name
Test status
Simulation time 88457451552 ps
CPU time 245.12 seconds
Started May 02 02:32:25 PM PDT 24
Finished May 02 02:36:32 PM PDT 24
Peak memory 200404 kb
Host smart-b2f845e5-8348-45ba-b81d-9befac2ecbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321454034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.3321454034
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.556133550
Short name T28
Test name
Test status
Simulation time 51248537010 ps
CPU time 513.01 seconds
Started May 02 02:26:02 PM PDT 24
Finished May 02 02:34:50 PM PDT 24
Peak memory 216804 kb
Host smart-37d23e52-03c4-4ba7-9916-411fa980f223
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556133550 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.556133550
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.3900294013
Short name T44
Test name
Test status
Simulation time 21040720606 ps
CPU time 15.62 seconds
Started May 02 02:32:55 PM PDT 24
Finished May 02 02:33:12 PM PDT 24
Peak memory 200344 kb
Host smart-eb3370de-56d2-4a13-a46f-5775fa00bddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900294013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.3900294013
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.2868198050
Short name T142
Test name
Test status
Simulation time 32594798257 ps
CPU time 17.02 seconds
Started May 02 02:26:21 PM PDT 24
Finished May 02 02:26:49 PM PDT 24
Peak memory 200240 kb
Host smart-340ab6a3-ea34-4c27-8ac1-67d4e768350d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868198050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.2868198050
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.3552811560
Short name T132
Test name
Test status
Simulation time 162996659807 ps
CPU time 61 seconds
Started May 02 02:26:29 PM PDT 24
Finished May 02 02:27:37 PM PDT 24
Peak memory 200420 kb
Host smart-e1731d6b-c071-46c0-ada5-743d3f96768e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552811560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.3552811560
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.1440891406
Short name T202
Test name
Test status
Simulation time 245340052001 ps
CPU time 31.69 seconds
Started May 02 02:33:30 PM PDT 24
Finished May 02 02:34:04 PM PDT 24
Peak memory 200368 kb
Host smart-523e51b4-f578-4fcb-922b-29712b86d93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440891406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.1440891406
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.2569897577
Short name T205
Test name
Test status
Simulation time 169175860077 ps
CPU time 69.17 seconds
Started May 02 02:33:39 PM PDT 24
Finished May 02 02:34:49 PM PDT 24
Peak memory 200420 kb
Host smart-83b39e78-b4f9-494a-aa9d-f73202a5d478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569897577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.2569897577
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.2305512610
Short name T233
Test name
Test status
Simulation time 143593386664 ps
CPU time 34.24 seconds
Started May 02 02:33:56 PM PDT 24
Finished May 02 02:34:31 PM PDT 24
Peak memory 200360 kb
Host smart-99c40d4f-6bbb-46f1-8d86-1b6c3b5c74f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305512610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.2305512610
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.2121038508
Short name T48
Test name
Test status
Simulation time 88182524136 ps
CPU time 1297.04 seconds
Started May 02 02:28:31 PM PDT 24
Finished May 02 02:50:11 PM PDT 24
Peak memory 225264 kb
Host smart-1a1b8b62-0f18-46b5-b667-f7df1adb7e05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121038508 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.2121038508
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.937423399
Short name T213
Test name
Test status
Simulation time 148481490962 ps
CPU time 84.31 seconds
Started May 02 02:30:50 PM PDT 24
Finished May 02 02:32:15 PM PDT 24
Peak memory 200420 kb
Host smart-9bb12926-1cf2-4849-8443-831d1251e16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937423399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.937423399
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.1989764721
Short name T235
Test name
Test status
Simulation time 114280552357 ps
CPU time 56.49 seconds
Started May 02 02:30:50 PM PDT 24
Finished May 02 02:31:48 PM PDT 24
Peak memory 200440 kb
Host smart-5a93c7f7-be47-4af7-bb86-752aef990e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989764721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1989764721
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3761244375
Short name T1311
Test name
Test status
Simulation time 63844629 ps
CPU time 0.64 seconds
Started May 02 03:48:56 PM PDT 24
Finished May 02 03:48:59 PM PDT 24
Peak memory 194936 kb
Host smart-be3a9ea5-e360-44b9-8d43-6d988379e495
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761244375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.3761244375
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2436226678
Short name T1300
Test name
Test status
Simulation time 116501965 ps
CPU time 1.37 seconds
Started May 02 03:49:11 PM PDT 24
Finished May 02 03:49:13 PM PDT 24
Peak memory 198296 kb
Host smart-4f02ca40-ad5d-49f7-a305-0743a873fba5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436226678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.2436226678
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.2644358784
Short name T60
Test name
Test status
Simulation time 14189257 ps
CPU time 0.62 seconds
Started May 02 03:49:14 PM PDT 24
Finished May 02 03:49:16 PM PDT 24
Peak memory 195764 kb
Host smart-8ae5d005-edee-4a93-bed6-d8d0e1b79935
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644358784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.2644358784
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.4079271777
Short name T1297
Test name
Test status
Simulation time 14086811 ps
CPU time 0.73 seconds
Started May 02 03:49:13 PM PDT 24
Finished May 02 03:49:15 PM PDT 24
Peak memory 198712 kb
Host smart-1afd0905-987f-4e22-bd23-f573a022a3c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079271777 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.4079271777
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.669658186
Short name T1317
Test name
Test status
Simulation time 58810094 ps
CPU time 0.57 seconds
Started May 02 03:49:09 PM PDT 24
Finished May 02 03:49:11 PM PDT 24
Peak memory 195676 kb
Host smart-2afac26c-d27a-461d-9ff8-2c6bc218d2db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669658186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.669658186
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.1354801448
Short name T1203
Test name
Test status
Simulation time 10830647 ps
CPU time 0.55 seconds
Started May 02 03:48:53 PM PDT 24
Finished May 02 03:48:56 PM PDT 24
Peak memory 194688 kb
Host smart-12e1766c-aeb2-44a4-9934-4284092bf2f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354801448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.1354801448
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.3555550099
Short name T1238
Test name
Test status
Simulation time 96810787 ps
CPU time 0.74 seconds
Started May 02 03:49:10 PM PDT 24
Finished May 02 03:49:11 PM PDT 24
Peak memory 197372 kb
Host smart-5ef8598c-fe3e-4090-9fa5-d72abc2ba9e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555550099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.3555550099
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.2804610800
Short name T1286
Test name
Test status
Simulation time 87176772 ps
CPU time 1.28 seconds
Started May 02 03:49:12 PM PDT 24
Finished May 02 03:49:14 PM PDT 24
Peak memory 200352 kb
Host smart-c29beeaa-134b-4fc2-a359-efacd6359341
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804610800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2804610800
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3472177046
Short name T63
Test name
Test status
Simulation time 20047594 ps
CPU time 0.76 seconds
Started May 02 03:49:15 PM PDT 24
Finished May 02 03:49:17 PM PDT 24
Peak memory 196368 kb
Host smart-ef139f7f-87ed-4106-90da-6afd7581b36c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472177046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.3472177046
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.4206950667
Short name T1292
Test name
Test status
Simulation time 182622722 ps
CPU time 1.58 seconds
Started May 02 03:49:17 PM PDT 24
Finished May 02 03:49:20 PM PDT 24
Peak memory 197592 kb
Host smart-983a8d83-8d12-4a91-976a-c1935f12c1a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206950667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.4206950667
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3258466462
Short name T58
Test name
Test status
Simulation time 33219118 ps
CPU time 0.66 seconds
Started May 02 03:49:24 PM PDT 24
Finished May 02 03:49:27 PM PDT 24
Peak memory 195684 kb
Host smart-2f8a83d2-1ad7-4ca9-9288-45c53e6335f9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258466462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.3258466462
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3695825573
Short name T1280
Test name
Test status
Simulation time 29711357 ps
CPU time 1.3 seconds
Started May 02 03:49:26 PM PDT 24
Finished May 02 03:49:29 PM PDT 24
Peak memory 200380 kb
Host smart-d050f83b-9795-48e4-bc96-41f076e7fc06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695825573 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.3695825573
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.1867074509
Short name T67
Test name
Test status
Simulation time 12274509 ps
CPU time 0.58 seconds
Started May 02 03:49:14 PM PDT 24
Finished May 02 03:49:15 PM PDT 24
Peak memory 195684 kb
Host smart-d056e2cc-661d-454f-a371-1e902c4daf17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867074509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.1867074509
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.2271895320
Short name T1212
Test name
Test status
Simulation time 45162511 ps
CPU time 0.58 seconds
Started May 02 03:49:12 PM PDT 24
Finished May 02 03:49:13 PM PDT 24
Peak memory 194716 kb
Host smart-86bffc82-6a37-4d70-9386-4218c9248b57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271895320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.2271895320
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3782950304
Short name T1221
Test name
Test status
Simulation time 28434642 ps
CPU time 0.81 seconds
Started May 02 03:49:24 PM PDT 24
Finished May 02 03:49:27 PM PDT 24
Peak memory 196392 kb
Host smart-6941f67d-835f-4ae8-a57f-da1eb7ed0cdd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782950304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.3782950304
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.1333698886
Short name T1192
Test name
Test status
Simulation time 98278276 ps
CPU time 1.35 seconds
Started May 02 03:49:03 PM PDT 24
Finished May 02 03:49:06 PM PDT 24
Peak memory 200364 kb
Host smart-c57c2979-257a-435c-a96d-ad96c10c4d23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333698886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.1333698886
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1868577565
Short name T1299
Test name
Test status
Simulation time 109827393 ps
CPU time 1.33 seconds
Started May 02 03:49:15 PM PDT 24
Finished May 02 03:49:17 PM PDT 24
Peak memory 199636 kb
Host smart-8390aec1-00f7-4c1a-994d-3c1b8c5ad893
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868577565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.1868577565
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2467092638
Short name T1200
Test name
Test status
Simulation time 58928803 ps
CPU time 0.87 seconds
Started May 02 03:49:29 PM PDT 24
Finished May 02 03:49:32 PM PDT 24
Peak memory 200188 kb
Host smart-cd11e33b-8530-455c-a3f4-bc36fe64e4d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467092638 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.2467092638
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.4249618232
Short name T1266
Test name
Test status
Simulation time 25915047 ps
CPU time 0.61 seconds
Started May 02 03:49:29 PM PDT 24
Finished May 02 03:49:32 PM PDT 24
Peak memory 195692 kb
Host smart-99bc7a73-4d5c-40c3-8ad2-0aa60ffa241f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249618232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.4249618232
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.759982078
Short name T1190
Test name
Test status
Simulation time 23955813 ps
CPU time 0.58 seconds
Started May 02 03:49:23 PM PDT 24
Finished May 02 03:49:24 PM PDT 24
Peak memory 194724 kb
Host smart-f71d4e08-9fd8-4051-a487-5e18bfd324c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759982078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.759982078
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1322318185
Short name T1308
Test name
Test status
Simulation time 33539662 ps
CPU time 0.64 seconds
Started May 02 03:49:23 PM PDT 24
Finished May 02 03:49:26 PM PDT 24
Peak memory 197032 kb
Host smart-156b5124-641a-4c97-bdd0-5bb68196ab6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322318185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.1322318185
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.531605752
Short name T1285
Test name
Test status
Simulation time 64000294 ps
CPU time 1.34 seconds
Started May 02 03:49:28 PM PDT 24
Finished May 02 03:49:32 PM PDT 24
Peak memory 200384 kb
Host smart-ae94f582-4fd3-41f7-a8ee-25ad17afaef5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531605752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.531605752
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.194876956
Short name T111
Test name
Test status
Simulation time 68764417 ps
CPU time 1.33 seconds
Started May 02 03:49:29 PM PDT 24
Finished May 02 03:49:33 PM PDT 24
Peak memory 199540 kb
Host smart-903778f7-0c82-4601-9ed8-d9fab8a50cd3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194876956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.194876956
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1271602552
Short name T1195
Test name
Test status
Simulation time 55970806 ps
CPU time 0.63 seconds
Started May 02 03:49:29 PM PDT 24
Finished May 02 03:49:32 PM PDT 24
Peak memory 197916 kb
Host smart-b486b4a9-237b-49d0-b6cd-7358395cfa4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271602552 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.1271602552
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.471248534
Short name T1214
Test name
Test status
Simulation time 39378784 ps
CPU time 0.58 seconds
Started May 02 03:49:34 PM PDT 24
Finished May 02 03:49:41 PM PDT 24
Peak memory 195696 kb
Host smart-33e95ab1-ed13-4957-b0e5-899feb77d32e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471248534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.471248534
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.4019664145
Short name T1303
Test name
Test status
Simulation time 15258646 ps
CPU time 0.57 seconds
Started May 02 03:49:27 PM PDT 24
Finished May 02 03:49:29 PM PDT 24
Peak memory 194684 kb
Host smart-191d339f-ea9d-4d04-823d-44704221be74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019664145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.4019664145
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.2059954238
Short name T1301
Test name
Test status
Simulation time 19168055 ps
CPU time 0.65 seconds
Started May 02 03:49:28 PM PDT 24
Finished May 02 03:49:31 PM PDT 24
Peak memory 196032 kb
Host smart-6063b997-de4f-4ea5-ab15-342a426e5bb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059954238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.2059954238
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.3189408534
Short name T1295
Test name
Test status
Simulation time 159021227 ps
CPU time 1.9 seconds
Started May 02 03:49:25 PM PDT 24
Finished May 02 03:49:30 PM PDT 24
Peak memory 200328 kb
Host smart-15588548-7796-46ae-b4c1-009c94f162e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189408534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3189408534
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.817184430
Short name T112
Test name
Test status
Simulation time 88997806 ps
CPU time 1.27 seconds
Started May 02 03:49:22 PM PDT 24
Finished May 02 03:49:24 PM PDT 24
Peak memory 199640 kb
Host smart-4e3a7c97-4c0f-4334-a299-8ca1195a8b72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817184430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.817184430
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3203076009
Short name T1273
Test name
Test status
Simulation time 35861218 ps
CPU time 0.7 seconds
Started May 02 03:49:28 PM PDT 24
Finished May 02 03:49:30 PM PDT 24
Peak memory 198752 kb
Host smart-a7245f46-6903-494b-b4aa-7bce5cede3cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203076009 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.3203076009
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.1697939207
Short name T1247
Test name
Test status
Simulation time 27965439 ps
CPU time 0.57 seconds
Started May 02 03:49:28 PM PDT 24
Finished May 02 03:49:31 PM PDT 24
Peak memory 195632 kb
Host smart-76365a99-b973-4f4a-bfdd-b5bfc8b18973
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697939207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.1697939207
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.3757316154
Short name T1281
Test name
Test status
Simulation time 17023466 ps
CPU time 0.6 seconds
Started May 02 03:49:22 PM PDT 24
Finished May 02 03:49:24 PM PDT 24
Peak memory 194700 kb
Host smart-499973a8-dd08-4753-ac5c-bb15b644ba27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757316154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.3757316154
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.931578505
Short name T69
Test name
Test status
Simulation time 65634661 ps
CPU time 0.77 seconds
Started May 02 03:49:30 PM PDT 24
Finished May 02 03:49:33 PM PDT 24
Peak memory 196812 kb
Host smart-f5d3cc29-2b37-4e8d-aa1d-ca49979fef54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931578505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_csr
_outstanding.931578505
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.1429602321
Short name T1186
Test name
Test status
Simulation time 36352640 ps
CPU time 1.79 seconds
Started May 02 03:49:25 PM PDT 24
Finished May 02 03:49:28 PM PDT 24
Peak memory 200368 kb
Host smart-8a62184a-277d-4043-abf7-1306117fa457
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429602321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1429602321
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.1688142847
Short name T77
Test name
Test status
Simulation time 73845804 ps
CPU time 1.31 seconds
Started May 02 03:49:19 PM PDT 24
Finished May 02 03:49:21 PM PDT 24
Peak memory 199548 kb
Host smart-3b03f45a-2864-43d5-87d6-03226b32bfdd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688142847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.1688142847
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1026678859
Short name T1185
Test name
Test status
Simulation time 14350509 ps
CPU time 0.66 seconds
Started May 02 03:49:30 PM PDT 24
Finished May 02 03:49:34 PM PDT 24
Peak memory 197576 kb
Host smart-914b014a-9376-49d8-9a6d-ffa672d46564
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026678859 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.1026678859
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.360563678
Short name T1309
Test name
Test status
Simulation time 38094923 ps
CPU time 0.66 seconds
Started May 02 03:49:24 PM PDT 24
Finished May 02 03:49:27 PM PDT 24
Peak memory 195980 kb
Host smart-6b4bb8de-918d-4c5c-8bbd-2b763bc42ad6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360563678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.360563678
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.187687938
Short name T1202
Test name
Test status
Simulation time 34221534 ps
CPU time 0.55 seconds
Started May 02 03:49:28 PM PDT 24
Finished May 02 03:49:31 PM PDT 24
Peak memory 194740 kb
Host smart-30b6f1de-392d-4c24-b6e2-c0c087b0cb60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187687938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.187687938
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2625520690
Short name T1304
Test name
Test status
Simulation time 67004362 ps
CPU time 0.67 seconds
Started May 02 03:49:30 PM PDT 24
Finished May 02 03:49:33 PM PDT 24
Peak memory 195328 kb
Host smart-5e25bf07-69a1-4752-997a-83ee861e43cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625520690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.2625520690
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.3245057732
Short name T1250
Test name
Test status
Simulation time 61747326 ps
CPU time 1.56 seconds
Started May 02 03:49:24 PM PDT 24
Finished May 02 03:49:27 PM PDT 24
Peak memory 200376 kb
Host smart-796546d0-578a-4215-9f3a-017ecf3897bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245057732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3245057732
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1655054885
Short name T1255
Test name
Test status
Simulation time 175168284 ps
CPU time 0.89 seconds
Started May 02 03:49:27 PM PDT 24
Finished May 02 03:49:29 PM PDT 24
Peak memory 199184 kb
Host smart-d131a0e5-70d9-42e8-8c25-4f566b6690e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655054885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.1655054885
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3861456523
Short name T1318
Test name
Test status
Simulation time 13863770 ps
CPU time 0.7 seconds
Started May 02 03:49:23 PM PDT 24
Finished May 02 03:49:26 PM PDT 24
Peak memory 197788 kb
Host smart-433259a3-dc78-4c4f-b9ab-4010d0485b79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861456523 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.3861456523
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.2388292142
Short name T1241
Test name
Test status
Simulation time 34940933 ps
CPU time 0.56 seconds
Started May 02 03:49:28 PM PDT 24
Finished May 02 03:49:30 PM PDT 24
Peak memory 195700 kb
Host smart-6c3d376c-37c1-41e4-9ecc-14fc0386a36a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388292142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.2388292142
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.890305535
Short name T1199
Test name
Test status
Simulation time 15560093 ps
CPU time 0.58 seconds
Started May 02 03:49:24 PM PDT 24
Finished May 02 03:49:26 PM PDT 24
Peak memory 194740 kb
Host smart-ea868100-9b1b-41ae-acab-4928fdaa0cf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890305535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.890305535
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1079503262
Short name T1252
Test name
Test status
Simulation time 31381995 ps
CPU time 0.64 seconds
Started May 02 03:49:29 PM PDT 24
Finished May 02 03:49:32 PM PDT 24
Peak memory 196056 kb
Host smart-20482a1d-f7f6-4d94-bba4-4d68c65b7592
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079503262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.1079503262
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.1391719890
Short name T1198
Test name
Test status
Simulation time 1221076379 ps
CPU time 1.92 seconds
Started May 02 03:49:27 PM PDT 24
Finished May 02 03:49:30 PM PDT 24
Peak memory 200344 kb
Host smart-93d83200-aa32-4f42-86bc-3932c308772c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391719890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.1391719890
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3627583981
Short name T110
Test name
Test status
Simulation time 44352634 ps
CPU time 0.92 seconds
Started May 02 03:49:30 PM PDT 24
Finished May 02 03:49:33 PM PDT 24
Peak memory 199276 kb
Host smart-9a8524d8-a3e6-486e-8f19-303b42d0242e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627583981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3627583981
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3643238552
Short name T1194
Test name
Test status
Simulation time 52981707 ps
CPU time 0.78 seconds
Started May 02 03:49:31 PM PDT 24
Finished May 02 03:49:34 PM PDT 24
Peak memory 199748 kb
Host smart-7c2a1825-51db-4979-9728-e84c39cd593b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643238552 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.3643238552
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.51201339
Short name T57
Test name
Test status
Simulation time 16999673 ps
CPU time 0.6 seconds
Started May 02 03:49:22 PM PDT 24
Finished May 02 03:49:24 PM PDT 24
Peak memory 195720 kb
Host smart-27bc1ec9-24f8-4427-8d01-14fcc86ff9c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51201339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.51201339
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.2127350205
Short name T1236
Test name
Test status
Simulation time 78402312 ps
CPU time 0.57 seconds
Started May 02 03:49:32 PM PDT 24
Finished May 02 03:49:38 PM PDT 24
Peak memory 194668 kb
Host smart-16f0b6bb-7fff-45e4-ac58-9eb14228d5e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127350205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.2127350205
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1836101819
Short name T1256
Test name
Test status
Simulation time 186974736 ps
CPU time 0.77 seconds
Started May 02 03:49:32 PM PDT 24
Finished May 02 03:49:35 PM PDT 24
Peak memory 197264 kb
Host smart-9c624844-08d5-46f3-b102-b4cfec690480
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836101819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.1836101819
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.3287067357
Short name T1225
Test name
Test status
Simulation time 139159539 ps
CPU time 1.06 seconds
Started May 02 03:49:24 PM PDT 24
Finished May 02 03:49:26 PM PDT 24
Peak memory 200060 kb
Host smart-4b1a4606-5a74-4822-af61-3819d8dfdaa5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287067357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.3287067357
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.415710245
Short name T109
Test name
Test status
Simulation time 206539094 ps
CPU time 1.35 seconds
Started May 02 03:49:26 PM PDT 24
Finished May 02 03:49:29 PM PDT 24
Peak memory 199552 kb
Host smart-74b28130-f800-4e40-87eb-062d4e18901a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415710245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.415710245
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1906672077
Short name T1219
Test name
Test status
Simulation time 37635674 ps
CPU time 0.98 seconds
Started May 02 03:49:35 PM PDT 24
Finished May 02 03:49:37 PM PDT 24
Peak memory 200168 kb
Host smart-3d1bde8b-22e1-44dd-9cc2-9a9ba6b0c3d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906672077 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.1906672077
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.1358491934
Short name T1316
Test name
Test status
Simulation time 12524541 ps
CPU time 0.6 seconds
Started May 02 03:49:54 PM PDT 24
Finished May 02 03:49:55 PM PDT 24
Peak memory 195684 kb
Host smart-f981f2c9-51e4-40e0-b75d-733c8e8b4d50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358491934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.1358491934
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.3284046899
Short name T1208
Test name
Test status
Simulation time 15507517 ps
CPU time 0.56 seconds
Started May 02 03:49:26 PM PDT 24
Finished May 02 03:49:29 PM PDT 24
Peak memory 194696 kb
Host smart-debdfe11-5607-4d9f-a410-cf4a66ddd9a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284046899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.3284046899
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2205896461
Short name T71
Test name
Test status
Simulation time 43615679 ps
CPU time 0.7 seconds
Started May 02 03:49:26 PM PDT 24
Finished May 02 03:49:29 PM PDT 24
Peak memory 197388 kb
Host smart-4d1e2116-3e39-4f32-a8a0-79b82660e83d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205896461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.2205896461
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.1629868109
Short name T1210
Test name
Test status
Simulation time 130747156 ps
CPU time 0.96 seconds
Started May 02 03:49:29 PM PDT 24
Finished May 02 03:49:33 PM PDT 24
Peak memory 200112 kb
Host smart-ec0e0355-11a6-4bc5-922c-823223d08be9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629868109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.1629868109
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3462896862
Short name T1290
Test name
Test status
Simulation time 22028946 ps
CPU time 1.02 seconds
Started May 02 03:49:24 PM PDT 24
Finished May 02 03:49:26 PM PDT 24
Peak memory 200268 kb
Host smart-10c115af-15b0-43b9-8403-32dbf8aacfa0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462896862 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.3462896862
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.2977038480
Short name T73
Test name
Test status
Simulation time 13290052 ps
CPU time 0.6 seconds
Started May 02 03:49:30 PM PDT 24
Finished May 02 03:49:33 PM PDT 24
Peak memory 195704 kb
Host smart-a9f5fa7f-8f8c-4c5f-b72f-3f01a2f6ede3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977038480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.2977038480
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.4054875080
Short name T1189
Test name
Test status
Simulation time 47300958 ps
CPU time 0.57 seconds
Started May 02 03:49:29 PM PDT 24
Finished May 02 03:49:32 PM PDT 24
Peak memory 194700 kb
Host smart-3ba8bad5-8766-4c91-903d-b2aeaaf05e66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054875080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.4054875080
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2080592664
Short name T66
Test name
Test status
Simulation time 74004466 ps
CPU time 0.67 seconds
Started May 02 03:49:53 PM PDT 24
Finished May 02 03:49:55 PM PDT 24
Peak memory 196140 kb
Host smart-2beb3535-2907-40db-a04f-1f2acf51c211
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080592664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.2080592664
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.259038239
Short name T1293
Test name
Test status
Simulation time 54539541 ps
CPU time 1.28 seconds
Started May 02 03:49:31 PM PDT 24
Finished May 02 03:49:44 PM PDT 24
Peak memory 200364 kb
Host smart-130e7ff9-5968-4c52-a805-5f5038de21bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259038239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.259038239
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.793622381
Short name T80
Test name
Test status
Simulation time 126389199 ps
CPU time 0.97 seconds
Started May 02 03:50:03 PM PDT 24
Finished May 02 03:50:05 PM PDT 24
Peak memory 199260 kb
Host smart-af6d3324-efda-4b9a-ab7c-801c2b6da8e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793622381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.793622381
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2586126796
Short name T1193
Test name
Test status
Simulation time 35206541 ps
CPU time 0.69 seconds
Started May 02 03:49:27 PM PDT 24
Finished May 02 03:49:30 PM PDT 24
Peak memory 198120 kb
Host smart-24c03010-cda4-4a09-872e-098bc37e4890
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586126796 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.2586126796
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.4093979533
Short name T1305
Test name
Test status
Simulation time 50777856 ps
CPU time 0.57 seconds
Started May 02 03:49:29 PM PDT 24
Finished May 02 03:49:32 PM PDT 24
Peak memory 195692 kb
Host smart-3bbb4a23-b7f6-42d1-85fb-2fdc6f4c2404
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093979533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.4093979533
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.4193964692
Short name T1248
Test name
Test status
Simulation time 23656791 ps
CPU time 0.56 seconds
Started May 02 03:49:29 PM PDT 24
Finished May 02 03:49:32 PM PDT 24
Peak memory 194792 kb
Host smart-6f1bf95c-45ed-4c79-8cc2-4c76fbc5cfb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193964692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.4193964692
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.203891705
Short name T1291
Test name
Test status
Simulation time 36254332 ps
CPU time 0.62 seconds
Started May 02 03:49:32 PM PDT 24
Finished May 02 03:49:35 PM PDT 24
Peak memory 195920 kb
Host smart-e377bcfb-0f3f-4b8f-8fb4-5b2b302eea32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203891705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr
_outstanding.203891705
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.252346543
Short name T1234
Test name
Test status
Simulation time 366021182 ps
CPU time 1.92 seconds
Started May 02 03:49:28 PM PDT 24
Finished May 02 03:49:32 PM PDT 24
Peak memory 200392 kb
Host smart-41c8d2e6-7c27-41f6-9807-599ea875255a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252346543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.252346543
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1094139210
Short name T1283
Test name
Test status
Simulation time 34419218 ps
CPU time 0.72 seconds
Started May 02 03:49:29 PM PDT 24
Finished May 02 03:49:31 PM PDT 24
Peak memory 198368 kb
Host smart-056224da-c3c8-4d4c-866d-53192ae002f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094139210 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.1094139210
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.282288338
Short name T61
Test name
Test status
Simulation time 15388408 ps
CPU time 0.58 seconds
Started May 02 03:49:33 PM PDT 24
Finished May 02 03:49:35 PM PDT 24
Peak memory 195704 kb
Host smart-f06c5a3b-7bb6-4a52-88fb-f0865f809dd7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282288338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.282288338
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.4147074947
Short name T1278
Test name
Test status
Simulation time 31701925 ps
CPU time 0.59 seconds
Started May 02 03:49:30 PM PDT 24
Finished May 02 03:49:33 PM PDT 24
Peak memory 194672 kb
Host smart-cd03942d-5cca-47f3-988f-4af45368603a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147074947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.4147074947
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.501795690
Short name T1263
Test name
Test status
Simulation time 18332419 ps
CPU time 0.72 seconds
Started May 02 03:49:30 PM PDT 24
Finished May 02 03:49:42 PM PDT 24
Peak memory 196292 kb
Host smart-f77df783-a7ac-4317-aa25-dc8afa974845
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501795690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr
_outstanding.501795690
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.3003193350
Short name T1310
Test name
Test status
Simulation time 91136112 ps
CPU time 1.89 seconds
Started May 02 03:49:30 PM PDT 24
Finished May 02 03:49:34 PM PDT 24
Peak memory 200384 kb
Host smart-a1a3ebec-1282-423b-937c-e9f0d30e9300
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003193350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.3003193350
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1676145278
Short name T1275
Test name
Test status
Simulation time 88017787 ps
CPU time 0.96 seconds
Started May 02 03:49:26 PM PDT 24
Finished May 02 03:49:29 PM PDT 24
Peak memory 199384 kb
Host smart-100638aa-fff7-4090-96b8-bbc7e3f9351a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676145278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.1676145278
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3518621491
Short name T1209
Test name
Test status
Simulation time 36718040 ps
CPU time 0.7 seconds
Started May 02 03:49:09 PM PDT 24
Finished May 02 03:49:11 PM PDT 24
Peak memory 195700 kb
Host smart-d3fc9178-b8a8-4d91-8153-d118bb491d10
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518621491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3518621491
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.4035126215
Short name T1235
Test name
Test status
Simulation time 1654504916 ps
CPU time 2.58 seconds
Started May 02 03:49:14 PM PDT 24
Finished May 02 03:49:18 PM PDT 24
Peak memory 198300 kb
Host smart-c7a74ed4-16cb-4fe4-83da-226bf990da5b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035126215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.4035126215
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3425048405
Short name T1244
Test name
Test status
Simulation time 60252739 ps
CPU time 0.61 seconds
Started May 02 03:49:12 PM PDT 24
Finished May 02 03:49:14 PM PDT 24
Peak memory 195680 kb
Host smart-7f858631-c825-4a59-975a-67db9cf3f367
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425048405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.3425048405
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2161465133
Short name T1224
Test name
Test status
Simulation time 30213384 ps
CPU time 1.43 seconds
Started May 02 03:49:18 PM PDT 24
Finished May 02 03:49:20 PM PDT 24
Peak memory 200344 kb
Host smart-dc7ae88a-7fb8-4769-8147-c88dfba15ccd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161465133 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.2161465133
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.545753973
Short name T64
Test name
Test status
Simulation time 12591248 ps
CPU time 0.63 seconds
Started May 02 03:49:20 PM PDT 24
Finished May 02 03:49:22 PM PDT 24
Peak memory 195664 kb
Host smart-d2839f28-1d96-429f-9c71-3105d75c19c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545753973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.545753973
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.3083396906
Short name T1229
Test name
Test status
Simulation time 48985745 ps
CPU time 0.6 seconds
Started May 02 03:49:16 PM PDT 24
Finished May 02 03:49:18 PM PDT 24
Peak memory 194688 kb
Host smart-72c76d48-aaa8-43b9-9862-dca6e9b5245d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083396906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3083396906
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.1532881325
Short name T65
Test name
Test status
Simulation time 60484205 ps
CPU time 0.73 seconds
Started May 02 03:49:29 PM PDT 24
Finished May 02 03:49:33 PM PDT 24
Peak memory 197476 kb
Host smart-16741326-5c29-4ed9-8e51-f410b46661d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532881325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.1532881325
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.4079263786
Short name T1230
Test name
Test status
Simulation time 440714779 ps
CPU time 1.34 seconds
Started May 02 03:49:08 PM PDT 24
Finished May 02 03:49:10 PM PDT 24
Peak memory 200328 kb
Host smart-7eae5a6c-3d32-44a6-bca4-b73c0cf338c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079263786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.4079263786
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2266822252
Short name T1294
Test name
Test status
Simulation time 113778118 ps
CPU time 1.44 seconds
Started May 02 03:49:25 PM PDT 24
Finished May 02 03:49:29 PM PDT 24
Peak memory 199880 kb
Host smart-14d4c0ab-9d4b-49aa-accc-0b494128b346
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266822252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.2266822252
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.3756179162
Short name T1227
Test name
Test status
Simulation time 14175040 ps
CPU time 0.59 seconds
Started May 02 03:49:24 PM PDT 24
Finished May 02 03:49:27 PM PDT 24
Peak memory 194772 kb
Host smart-7c9f8cd5-8d75-4e34-a883-f3cc76d0f41c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756179162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.3756179162
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.2035845657
Short name T1267
Test name
Test status
Simulation time 17638347 ps
CPU time 0.56 seconds
Started May 02 03:49:24 PM PDT 24
Finished May 02 03:49:27 PM PDT 24
Peak memory 194780 kb
Host smart-e887b841-3525-473c-92cb-38783010b012
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035845657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.2035845657
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.746431560
Short name T1239
Test name
Test status
Simulation time 20847296 ps
CPU time 0.56 seconds
Started May 02 03:49:30 PM PDT 24
Finished May 02 03:49:33 PM PDT 24
Peak memory 194660 kb
Host smart-32706214-2280-424b-b509-5c44d81aad16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746431560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.746431560
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.573223088
Short name T1259
Test name
Test status
Simulation time 17351848 ps
CPU time 0.57 seconds
Started May 02 03:49:29 PM PDT 24
Finished May 02 03:49:31 PM PDT 24
Peak memory 194700 kb
Host smart-106c8d14-b949-4459-9144-691fedf52e7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573223088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.573223088
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.3518274847
Short name T1298
Test name
Test status
Simulation time 71798281 ps
CPU time 0.55 seconds
Started May 02 03:49:30 PM PDT 24
Finished May 02 03:49:34 PM PDT 24
Peak memory 194648 kb
Host smart-0e63eb31-d725-4b0f-889f-abe79d8bccf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518274847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.3518274847
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.2546757133
Short name T1222
Test name
Test status
Simulation time 13479769 ps
CPU time 0.55 seconds
Started May 02 03:49:27 PM PDT 24
Finished May 02 03:49:29 PM PDT 24
Peak memory 194708 kb
Host smart-737866fa-16b7-4301-8121-d61171e486d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546757133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.2546757133
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.4105298402
Short name T1269
Test name
Test status
Simulation time 12306266 ps
CPU time 0.56 seconds
Started May 02 03:49:24 PM PDT 24
Finished May 02 03:49:27 PM PDT 24
Peak memory 194668 kb
Host smart-f1f9be7f-8c00-4c00-a0b7-4a0c13ea9075
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105298402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.4105298402
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.1072640603
Short name T1215
Test name
Test status
Simulation time 17538655 ps
CPU time 0.54 seconds
Started May 02 03:49:28 PM PDT 24
Finished May 02 03:49:35 PM PDT 24
Peak memory 194676 kb
Host smart-2fa8a496-7412-48b5-996c-0bbda59bc90d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072640603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.1072640603
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.2405643838
Short name T1261
Test name
Test status
Simulation time 30786348 ps
CPU time 0.56 seconds
Started May 02 03:49:30 PM PDT 24
Finished May 02 03:49:32 PM PDT 24
Peak memory 194572 kb
Host smart-7a5de348-976d-40ea-a0e7-73955be66db2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405643838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2405643838
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.992329897
Short name T1268
Test name
Test status
Simulation time 85812300 ps
CPU time 0.58 seconds
Started May 02 03:49:27 PM PDT 24
Finished May 02 03:49:29 PM PDT 24
Peak memory 194656 kb
Host smart-20487c52-089d-470b-882f-1b4bcb9a26c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992329897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.992329897
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1425815067
Short name T1220
Test name
Test status
Simulation time 54925615 ps
CPU time 0.65 seconds
Started May 02 03:49:12 PM PDT 24
Finished May 02 03:49:14 PM PDT 24
Peak memory 195076 kb
Host smart-7e0ce4bd-226c-4551-a8e9-f1bee49979a5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425815067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1425815067
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.428677979
Short name T1211
Test name
Test status
Simulation time 1088858763 ps
CPU time 1.57 seconds
Started May 02 03:49:13 PM PDT 24
Finished May 02 03:49:15 PM PDT 24
Peak memory 198140 kb
Host smart-0d2b35dd-8039-48c4-a5c7-f28f571e247f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428677979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.428677979
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2840172853
Short name T1184
Test name
Test status
Simulation time 14996356 ps
CPU time 0.63 seconds
Started May 02 03:49:12 PM PDT 24
Finished May 02 03:49:14 PM PDT 24
Peak memory 195684 kb
Host smart-f660ec21-20a7-4f49-a346-d3acd345afd4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840172853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.2840172853
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3931562611
Short name T1260
Test name
Test status
Simulation time 17332176 ps
CPU time 0.68 seconds
Started May 02 03:49:16 PM PDT 24
Finished May 02 03:49:18 PM PDT 24
Peak memory 198316 kb
Host smart-6cae459e-8baf-4d1a-b62b-b9b161074a46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931562611 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.3931562611
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.712254320
Short name T1207
Test name
Test status
Simulation time 39655419 ps
CPU time 0.56 seconds
Started May 02 03:49:11 PM PDT 24
Finished May 02 03:49:13 PM PDT 24
Peak memory 194680 kb
Host smart-0557bc76-cee8-4296-afb3-e3a7ced992cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712254320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.712254320
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.4062284982
Short name T1306
Test name
Test status
Simulation time 24152283 ps
CPU time 0.69 seconds
Started May 02 03:49:23 PM PDT 24
Finished May 02 03:49:26 PM PDT 24
Peak memory 196120 kb
Host smart-506c76e3-2311-4c16-91e4-ea892202ae8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062284982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.4062284982
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.1438301349
Short name T1205
Test name
Test status
Simulation time 34940014 ps
CPU time 1.71 seconds
Started May 02 03:49:23 PM PDT 24
Finished May 02 03:49:26 PM PDT 24
Peak memory 200368 kb
Host smart-eed254ef-83a2-43bf-8ee9-841211f6784a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438301349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.1438301349
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.2292743126
Short name T1274
Test name
Test status
Simulation time 55020351 ps
CPU time 0.94 seconds
Started May 02 03:49:18 PM PDT 24
Finished May 02 03:49:20 PM PDT 24
Peak memory 199368 kb
Host smart-ed13b3ac-ba15-4938-b90c-24762a0447b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292743126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.2292743126
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.2981793784
Short name T1314
Test name
Test status
Simulation time 13999138 ps
CPU time 0.57 seconds
Started May 02 03:49:34 PM PDT 24
Finished May 02 03:49:36 PM PDT 24
Peak memory 194720 kb
Host smart-11da77f4-1e1d-4f3f-b5c5-c6befa398e3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981793784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.2981793784
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.1555177505
Short name T1243
Test name
Test status
Simulation time 26086304 ps
CPU time 0.57 seconds
Started May 02 03:50:06 PM PDT 24
Finished May 02 03:50:07 PM PDT 24
Peak memory 194632 kb
Host smart-d718c555-abda-4186-b484-4e90e0b4c5a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555177505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.1555177505
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.1299341049
Short name T1288
Test name
Test status
Simulation time 102855728 ps
CPU time 0.58 seconds
Started May 02 03:49:23 PM PDT 24
Finished May 02 03:49:24 PM PDT 24
Peak memory 194716 kb
Host smart-2c917eda-9a0b-455d-8e38-5c9ecb9c9d0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299341049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.1299341049
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.662468663
Short name T1258
Test name
Test status
Simulation time 12978989 ps
CPU time 0.57 seconds
Started May 02 03:50:03 PM PDT 24
Finished May 02 03:50:04 PM PDT 24
Peak memory 194628 kb
Host smart-8d326d5e-4099-4e63-85f2-98d8826d97b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662468663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.662468663
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.285485958
Short name T1206
Test name
Test status
Simulation time 45357481 ps
CPU time 0.6 seconds
Started May 02 03:49:29 PM PDT 24
Finished May 02 03:49:31 PM PDT 24
Peak memory 194708 kb
Host smart-2b80eb27-6b32-4687-bba3-1c1519907f28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285485958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.285485958
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.2693476233
Short name T1188
Test name
Test status
Simulation time 29708535 ps
CPU time 0.61 seconds
Started May 02 03:49:33 PM PDT 24
Finished May 02 03:49:35 PM PDT 24
Peak memory 194792 kb
Host smart-654e952c-e985-4223-927b-c8d2d193813e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693476233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.2693476233
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.478799165
Short name T1187
Test name
Test status
Simulation time 11509206 ps
CPU time 0.57 seconds
Started May 02 03:50:15 PM PDT 24
Finished May 02 03:50:16 PM PDT 24
Peak memory 194724 kb
Host smart-7e605cd3-67bd-448d-beee-7001f57a6945
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478799165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.478799165
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.2708757474
Short name T1282
Test name
Test status
Simulation time 11894252 ps
CPU time 0.59 seconds
Started May 02 03:49:31 PM PDT 24
Finished May 02 03:49:34 PM PDT 24
Peak memory 194728 kb
Host smart-26a56199-9f97-456c-ba42-6b222ece5756
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708757474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.2708757474
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.4222086497
Short name T1249
Test name
Test status
Simulation time 15682338 ps
CPU time 0.61 seconds
Started May 02 03:50:22 PM PDT 24
Finished May 02 03:50:24 PM PDT 24
Peak memory 194680 kb
Host smart-08216c13-c67d-4fc0-85b3-5cc6ef0eaa27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222086497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.4222086497
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.3715239860
Short name T1232
Test name
Test status
Simulation time 80194128 ps
CPU time 0.56 seconds
Started May 02 03:49:33 PM PDT 24
Finished May 02 03:49:35 PM PDT 24
Peak memory 194660 kb
Host smart-2e26123d-fd31-490c-9532-4a6aa9d8a3c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715239860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3715239860
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.516595828
Short name T62
Test name
Test status
Simulation time 54676467 ps
CPU time 0.8 seconds
Started May 02 03:49:21 PM PDT 24
Finished May 02 03:49:23 PM PDT 24
Peak memory 196888 kb
Host smart-551f309a-194a-4e76-b2f9-54580ebce56b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516595828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.516595828
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3340434332
Short name T1231
Test name
Test status
Simulation time 201625184 ps
CPU time 2.21 seconds
Started May 02 03:49:24 PM PDT 24
Finished May 02 03:49:29 PM PDT 24
Peak memory 198252 kb
Host smart-204b472d-ab6d-4575-b4c9-0a83f0bd35a9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340434332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.3340434332
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2156374712
Short name T1218
Test name
Test status
Simulation time 15042485 ps
CPU time 0.6 seconds
Started May 02 03:49:25 PM PDT 24
Finished May 02 03:49:28 PM PDT 24
Peak memory 195688 kb
Host smart-bad55336-ebb3-42a9-84bc-b29a7a96b919
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156374712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.2156374712
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.665910305
Short name T1302
Test name
Test status
Simulation time 40743450 ps
CPU time 0.83 seconds
Started May 02 03:49:31 PM PDT 24
Finished May 02 03:49:35 PM PDT 24
Peak memory 200132 kb
Host smart-c7964d7b-ff0f-4e4a-8546-a2ff2907918d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665910305 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.665910305
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.3848409592
Short name T1242
Test name
Test status
Simulation time 40322712 ps
CPU time 0.6 seconds
Started May 02 03:49:20 PM PDT 24
Finished May 02 03:49:22 PM PDT 24
Peak memory 195628 kb
Host smart-a1687bc1-04be-4911-b69d-fc6878b84a97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848409592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.3848409592
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.4037803552
Short name T1257
Test name
Test status
Simulation time 53029901 ps
CPU time 0.61 seconds
Started May 02 03:49:18 PM PDT 24
Finished May 02 03:49:19 PM PDT 24
Peak memory 194608 kb
Host smart-7eb06318-749a-4ac0-ae80-50bea8636d17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037803552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.4037803552
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.4265051300
Short name T1233
Test name
Test status
Simulation time 95588812 ps
CPU time 0.73 seconds
Started May 02 03:49:33 PM PDT 24
Finished May 02 03:49:35 PM PDT 24
Peak memory 196892 kb
Host smart-254e83aa-ee9d-4a1c-8a48-bc7b89c888a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265051300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.4265051300
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.2395863477
Short name T1204
Test name
Test status
Simulation time 27988509 ps
CPU time 1.47 seconds
Started May 02 03:49:22 PM PDT 24
Finished May 02 03:49:25 PM PDT 24
Peak memory 200352 kb
Host smart-71adaea4-d4cd-4c46-ab34-7515d146a36a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395863477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.2395863477
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2372782215
Short name T76
Test name
Test status
Simulation time 86386531 ps
CPU time 1.32 seconds
Started May 02 03:49:10 PM PDT 24
Finished May 02 03:49:12 PM PDT 24
Peak memory 199748 kb
Host smart-e86e7423-2e5f-4fdd-b2fc-82195b3b4051
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372782215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.2372782215
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.858937769
Short name T1277
Test name
Test status
Simulation time 32108381 ps
CPU time 0.55 seconds
Started May 02 03:49:30 PM PDT 24
Finished May 02 03:49:33 PM PDT 24
Peak memory 194740 kb
Host smart-eb695314-e264-4be5-9ba0-5bc0ab3bc2e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858937769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.858937769
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.1949359106
Short name T1191
Test name
Test status
Simulation time 16874544 ps
CPU time 0.62 seconds
Started May 02 03:49:57 PM PDT 24
Finished May 02 03:49:58 PM PDT 24
Peak memory 194672 kb
Host smart-cba16789-7e48-4768-8f6b-7e88d1071f3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949359106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.1949359106
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.2646991112
Short name T1228
Test name
Test status
Simulation time 13816391 ps
CPU time 0.57 seconds
Started May 02 03:49:27 PM PDT 24
Finished May 02 03:49:29 PM PDT 24
Peak memory 194644 kb
Host smart-dfc904e0-39d1-401c-ad1f-1f8c7bdcfd15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646991112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.2646991112
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.2398466093
Short name T1270
Test name
Test status
Simulation time 15484883 ps
CPU time 0.62 seconds
Started May 02 03:50:09 PM PDT 24
Finished May 02 03:50:11 PM PDT 24
Peak memory 194764 kb
Host smart-2f707a85-38f5-4305-854c-aa605eceea2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398466093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.2398466093
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.3650270213
Short name T1217
Test name
Test status
Simulation time 18866648 ps
CPU time 0.57 seconds
Started May 02 03:49:33 PM PDT 24
Finished May 02 03:49:35 PM PDT 24
Peak memory 194708 kb
Host smart-24680afa-1a7a-4c4e-95c3-12dac5d1a976
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650270213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3650270213
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.1047616179
Short name T1315
Test name
Test status
Simulation time 13545466 ps
CPU time 0.59 seconds
Started May 02 03:49:28 PM PDT 24
Finished May 02 03:49:30 PM PDT 24
Peak memory 194680 kb
Host smart-40b4e419-18f9-4e4b-a4d8-a05ad2f5bf21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047616179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.1047616179
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.765366362
Short name T1272
Test name
Test status
Simulation time 79874626 ps
CPU time 0.57 seconds
Started May 02 03:49:37 PM PDT 24
Finished May 02 03:49:38 PM PDT 24
Peak memory 194676 kb
Host smart-19c4859c-34cc-43f8-86db-0edec314705b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765366362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.765366362
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.1745764758
Short name T1264
Test name
Test status
Simulation time 30473401 ps
CPU time 0.64 seconds
Started May 02 03:49:34 PM PDT 24
Finished May 02 03:49:36 PM PDT 24
Peak memory 194656 kb
Host smart-0528a058-01e8-445c-90a1-6fd61969dfa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745764758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.1745764758
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.3082871516
Short name T1253
Test name
Test status
Simulation time 46643576 ps
CPU time 0.6 seconds
Started May 02 03:49:33 PM PDT 24
Finished May 02 03:49:35 PM PDT 24
Peak memory 194672 kb
Host smart-08ccf7f3-cfe3-4787-95dd-05445c1fdf67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082871516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.3082871516
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.3603598090
Short name T1201
Test name
Test status
Simulation time 42168552 ps
CPU time 0.64 seconds
Started May 02 03:50:04 PM PDT 24
Finished May 02 03:50:05 PM PDT 24
Peak memory 194728 kb
Host smart-2198cb4f-4253-40f0-81e1-d24df80d7026
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603598090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3603598090
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.4054774888
Short name T1262
Test name
Test status
Simulation time 58031764 ps
CPU time 0.75 seconds
Started May 02 03:49:21 PM PDT 24
Finished May 02 03:49:22 PM PDT 24
Peak memory 198340 kb
Host smart-e9d195da-ac4f-4a11-ba28-eeee53320725
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054774888 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.4054774888
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.2102329787
Short name T68
Test name
Test status
Simulation time 30216402 ps
CPU time 0.56 seconds
Started May 02 03:49:15 PM PDT 24
Finished May 02 03:49:17 PM PDT 24
Peak memory 195708 kb
Host smart-3250305c-eb97-4719-b2f7-35d63f6e8cc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102329787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.2102329787
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.2375950804
Short name T1216
Test name
Test status
Simulation time 14675824 ps
CPU time 0.62 seconds
Started May 02 03:49:15 PM PDT 24
Finished May 02 03:49:17 PM PDT 24
Peak memory 194704 kb
Host smart-2abe54ed-eaec-4abd-84d5-14036a46ea5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375950804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.2375950804
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2963084633
Short name T72
Test name
Test status
Simulation time 127502160 ps
CPU time 0.85 seconds
Started May 02 03:49:17 PM PDT 24
Finished May 02 03:49:19 PM PDT 24
Peak memory 197316 kb
Host smart-80ffa990-7738-4f38-96f0-3124c343a23f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963084633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.2963084633
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.2465696869
Short name T1312
Test name
Test status
Simulation time 120456396 ps
CPU time 1.52 seconds
Started May 02 03:49:29 PM PDT 24
Finished May 02 03:49:33 PM PDT 24
Peak memory 200360 kb
Host smart-c8a9d7d8-1180-44f7-bf40-c4146ea453c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465696869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.2465696869
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1092856312
Short name T79
Test name
Test status
Simulation time 40060429 ps
CPU time 0.98 seconds
Started May 02 03:49:27 PM PDT 24
Finished May 02 03:49:29 PM PDT 24
Peak memory 199104 kb
Host smart-85c7301b-1252-4d1d-ba72-1125baaf8175
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092856312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.1092856312
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.95871558
Short name T1226
Test name
Test status
Simulation time 43920906 ps
CPU time 1.02 seconds
Started May 02 03:49:28 PM PDT 24
Finished May 02 03:49:32 PM PDT 24
Peak memory 200108 kb
Host smart-52e1dc50-7024-4630-953f-b4fcb4c8c6f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95871558 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.95871558
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.15433933
Short name T1307
Test name
Test status
Simulation time 16610987 ps
CPU time 0.59 seconds
Started May 02 03:49:17 PM PDT 24
Finished May 02 03:49:19 PM PDT 24
Peak memory 195656 kb
Host smart-6781501d-7c03-466d-8718-1c3019175723
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15433933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.15433933
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.999511391
Short name T1287
Test name
Test status
Simulation time 13264370 ps
CPU time 0.66 seconds
Started May 02 03:49:30 PM PDT 24
Finished May 02 03:49:33 PM PDT 24
Peak memory 194632 kb
Host smart-3dece0f8-a5ae-43f2-a3f8-37ab6b28fd78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999511391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.999511391
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.8803899
Short name T1279
Test name
Test status
Simulation time 104425466 ps
CPU time 0.72 seconds
Started May 02 03:49:24 PM PDT 24
Finished May 02 03:49:27 PM PDT 24
Peak memory 197260 kb
Host smart-863909b2-c39f-4954-b57c-1a43ff4af9a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8803899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_ou
tstanding.8803899
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.1931449928
Short name T1213
Test name
Test status
Simulation time 192366901 ps
CPU time 1.25 seconds
Started May 02 03:49:24 PM PDT 24
Finished May 02 03:49:28 PM PDT 24
Peak memory 200292 kb
Host smart-b7789ba0-c3bf-4f6b-9ba8-2653ba0af2aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931449928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1931449928
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.886071338
Short name T1296
Test name
Test status
Simulation time 655295323 ps
CPU time 1.64 seconds
Started May 02 03:49:21 PM PDT 24
Finished May 02 03:49:23 PM PDT 24
Peak memory 199856 kb
Host smart-e110bcbb-282e-4247-b082-e8ff68947c17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886071338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.886071338
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1491242654
Short name T1284
Test name
Test status
Simulation time 33641231 ps
CPU time 1.3 seconds
Started May 02 03:49:19 PM PDT 24
Finished May 02 03:49:21 PM PDT 24
Peak memory 200364 kb
Host smart-74398ca8-a02e-47ff-bcbb-ef017b59d2a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491242654 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.1491242654
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.1374658107
Short name T1197
Test name
Test status
Simulation time 49348072 ps
CPU time 0.58 seconds
Started May 02 03:49:29 PM PDT 24
Finished May 02 03:49:31 PM PDT 24
Peak memory 195712 kb
Host smart-65d5ef05-2ff9-49af-a275-2a514af64f2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374658107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.1374658107
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.1348717609
Short name T1240
Test name
Test status
Simulation time 14428676 ps
CPU time 0.56 seconds
Started May 02 03:49:24 PM PDT 24
Finished May 02 03:49:26 PM PDT 24
Peak memory 194764 kb
Host smart-7a99ae7d-fd5b-4ce1-ac72-9e5895ad75e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348717609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.1348717609
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.903255631
Short name T1271
Test name
Test status
Simulation time 46804960 ps
CPU time 0.7 seconds
Started May 02 03:49:20 PM PDT 24
Finished May 02 03:49:22 PM PDT 24
Peak memory 197324 kb
Host smart-0989feb1-94bd-4b5b-9247-eb8bff881a3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903255631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_
outstanding.903255631
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.1142113609
Short name T1223
Test name
Test status
Simulation time 61083904 ps
CPU time 1.23 seconds
Started May 02 03:49:22 PM PDT 24
Finished May 02 03:49:24 PM PDT 24
Peak memory 200404 kb
Host smart-7a2c4662-bc3c-483a-a9d5-84d852c80d9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142113609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.1142113609
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.842826550
Short name T75
Test name
Test status
Simulation time 96000340 ps
CPU time 1.31 seconds
Started May 02 03:49:28 PM PDT 24
Finished May 02 03:49:32 PM PDT 24
Peak memory 199600 kb
Host smart-b9bf48a3-9d0d-4b28-8756-efb8e4b31473
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842826550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.842826550
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1020372215
Short name T1289
Test name
Test status
Simulation time 69080335 ps
CPU time 0.81 seconds
Started May 02 03:49:22 PM PDT 24
Finished May 02 03:49:24 PM PDT 24
Peak memory 199768 kb
Host smart-94692bf7-750c-40b9-8405-98a0e913bdab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020372215 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1020372215
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.2443987029
Short name T70
Test name
Test status
Simulation time 36736859 ps
CPU time 0.56 seconds
Started May 02 03:49:30 PM PDT 24
Finished May 02 03:49:33 PM PDT 24
Peak memory 195640 kb
Host smart-be620017-988b-4f0e-9990-d26a23f0773a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443987029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.2443987029
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.3331328743
Short name T1237
Test name
Test status
Simulation time 14547570 ps
CPU time 0.57 seconds
Started May 02 03:49:16 PM PDT 24
Finished May 02 03:49:18 PM PDT 24
Peak memory 194700 kb
Host smart-5cbfbb7f-dfad-4306-9dd2-8c7f2e2b26fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331328743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.3331328743
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.136894501
Short name T1245
Test name
Test status
Simulation time 18430123 ps
CPU time 0.75 seconds
Started May 02 03:49:23 PM PDT 24
Finished May 02 03:49:26 PM PDT 24
Peak memory 197968 kb
Host smart-c264c0d1-7dce-4feb-be5e-eb57977ee864
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136894501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_
outstanding.136894501
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.970652305
Short name T1196
Test name
Test status
Simulation time 42016264 ps
CPU time 2.12 seconds
Started May 02 03:49:19 PM PDT 24
Finished May 02 03:49:22 PM PDT 24
Peak memory 200344 kb
Host smart-c448e965-49bf-4879-ac46-93ed6ed67128
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970652305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.970652305
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.321155418
Short name T1319
Test name
Test status
Simulation time 202412629 ps
CPU time 1.35 seconds
Started May 02 03:49:12 PM PDT 24
Finished May 02 03:49:14 PM PDT 24
Peak memory 199476 kb
Host smart-468e1f26-b75a-4e17-86e4-ed6724e18840
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321155418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.321155418
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3754434758
Short name T1276
Test name
Test status
Simulation time 42967727 ps
CPU time 0.73 seconds
Started May 02 03:49:31 PM PDT 24
Finished May 02 03:49:34 PM PDT 24
Peak memory 199460 kb
Host smart-196bcf6f-dbf3-417b-85e1-0951b0b058bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754434758 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.3754434758
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.282588471
Short name T1313
Test name
Test status
Simulation time 14604647 ps
CPU time 0.6 seconds
Started May 02 03:49:22 PM PDT 24
Finished May 02 03:49:24 PM PDT 24
Peak memory 195772 kb
Host smart-56d106a0-c1e8-4323-9f4e-10650341eb07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282588471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.282588471
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.2030509713
Short name T1246
Test name
Test status
Simulation time 15294975 ps
CPU time 0.55 seconds
Started May 02 03:49:27 PM PDT 24
Finished May 02 03:49:29 PM PDT 24
Peak memory 194640 kb
Host smart-6800c4ff-8d9c-487e-bf09-2207d95deaa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030509713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.2030509713
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.98671522
Short name T1254
Test name
Test status
Simulation time 14313129 ps
CPU time 0.65 seconds
Started May 02 03:49:25 PM PDT 24
Finished May 02 03:49:28 PM PDT 24
Peak memory 196892 kb
Host smart-79a8ab89-6bd1-4411-bcad-993c77d2775b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98671522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_o
utstanding.98671522
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.1052055978
Short name T1251
Test name
Test status
Simulation time 141977031 ps
CPU time 1.08 seconds
Started May 02 03:49:26 PM PDT 24
Finished May 02 03:49:29 PM PDT 24
Peak memory 200148 kb
Host smart-a4484b8d-b481-465b-ae7a-816b291428d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052055978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1052055978
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.223611077
Short name T74
Test name
Test status
Simulation time 74140418 ps
CPU time 1.31 seconds
Started May 02 03:49:27 PM PDT 24
Finished May 02 03:49:30 PM PDT 24
Peak memory 199804 kb
Host smart-bf6d562f-12e1-40ee-aa8c-33b5cf3a4f70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223611077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.223611077
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.2779612916
Short name T735
Test name
Test status
Simulation time 11351705 ps
CPU time 0.54 seconds
Started May 02 02:24:34 PM PDT 24
Finished May 02 02:24:38 PM PDT 24
Peak memory 195152 kb
Host smart-ec4c6d8e-4e64-47e2-8206-837454f1de8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779612916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2779612916
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.1645372541
Short name T139
Test name
Test status
Simulation time 143469295429 ps
CPU time 84.12 seconds
Started May 02 02:24:24 PM PDT 24
Finished May 02 02:25:50 PM PDT 24
Peak memory 200324 kb
Host smart-cc556686-b5d4-443e-a871-d8649851e1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645372541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.1645372541
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.3584368499
Short name T537
Test name
Test status
Simulation time 40014407472 ps
CPU time 45.8 seconds
Started May 02 02:24:30 PM PDT 24
Finished May 02 02:25:18 PM PDT 24
Peak memory 200376 kb
Host smart-4fc85038-1dea-45c5-8230-cefb0303fccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584368499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.3584368499
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.3475363677
Short name T617
Test name
Test status
Simulation time 100406098767 ps
CPU time 258.59 seconds
Started May 02 02:24:24 PM PDT 24
Finished May 02 02:28:45 PM PDT 24
Peak memory 200392 kb
Host smart-82dc6e3d-8711-43c4-a77f-506d06c3eed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475363677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.3475363677
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.1387991434
Short name T352
Test name
Test status
Simulation time 49608364807 ps
CPU time 22.93 seconds
Started May 02 02:24:30 PM PDT 24
Finished May 02 02:24:55 PM PDT 24
Peak memory 200128 kb
Host smart-2520d98e-4651-4481-ad3f-412a9f019d9f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387991434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.1387991434
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.1634750086
Short name T897
Test name
Test status
Simulation time 65832492921 ps
CPU time 391.73 seconds
Started May 02 02:24:31 PM PDT 24
Finished May 02 02:31:05 PM PDT 24
Peak memory 200420 kb
Host smart-8207ab9a-c0d4-4245-84b8-154b29ebfc63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1634750086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.1634750086
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.2613868914
Short name T5
Test name
Test status
Simulation time 1226628997 ps
CPU time 0.96 seconds
Started May 02 02:24:33 PM PDT 24
Finished May 02 02:24:38 PM PDT 24
Peak memory 196268 kb
Host smart-5a7ce776-b339-4596-aa5a-a918f7026f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613868914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.2613868914
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.1489166287
Short name T1009
Test name
Test status
Simulation time 68865853103 ps
CPU time 63.83 seconds
Started May 02 02:24:32 PM PDT 24
Finished May 02 02:25:39 PM PDT 24
Peak memory 208696 kb
Host smart-3ea682b0-38ac-42e8-8b6e-f19363989838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489166287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.1489166287
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.3020048879
Short name T1149
Test name
Test status
Simulation time 23410280210 ps
CPU time 165.41 seconds
Started May 02 02:24:33 PM PDT 24
Finished May 02 02:27:21 PM PDT 24
Peak memory 200344 kb
Host smart-6758ee3f-1629-46ad-accb-b97e7fdf201e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3020048879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.3020048879
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.141566023
Short name T549
Test name
Test status
Simulation time 6258467831 ps
CPU time 20.89 seconds
Started May 02 02:24:29 PM PDT 24
Finished May 02 02:24:52 PM PDT 24
Peak memory 199364 kb
Host smart-d92c9a8c-b9bd-49de-80af-dd70997a3773
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=141566023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.141566023
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.2132598883
Short name T964
Test name
Test status
Simulation time 111271954764 ps
CPU time 88.72 seconds
Started May 02 02:24:31 PM PDT 24
Finished May 02 02:26:03 PM PDT 24
Peak memory 200360 kb
Host smart-1c9e9f85-5a7b-4317-b3dd-5cc61a2779af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132598883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.2132598883
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.1222441853
Short name T462
Test name
Test status
Simulation time 48604688238 ps
CPU time 18.35 seconds
Started May 02 02:24:33 PM PDT 24
Finished May 02 02:24:54 PM PDT 24
Peak memory 196128 kb
Host smart-dcdc1b2e-2578-49fb-8407-6210666289eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222441853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.1222441853
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.1970371541
Short name T792
Test name
Test status
Simulation time 5393882632 ps
CPU time 6.65 seconds
Started May 02 02:24:29 PM PDT 24
Finished May 02 02:24:38 PM PDT 24
Peak memory 200384 kb
Host smart-56ff3323-6d76-48c9-969a-f0fe713a129e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970371541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.1970371541
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.2257337534
Short name T797
Test name
Test status
Simulation time 394551573758 ps
CPU time 358.74 seconds
Started May 02 02:24:31 PM PDT 24
Finished May 02 02:30:33 PM PDT 24
Peak memory 208904 kb
Host smart-48522664-0720-4ecc-88ab-836bd74684eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257337534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.2257337534
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.1071092256
Short name T707
Test name
Test status
Simulation time 32541489859 ps
CPU time 352.96 seconds
Started May 02 02:24:33 PM PDT 24
Finished May 02 02:30:29 PM PDT 24
Peak memory 208696 kb
Host smart-9e1b5e38-7ea8-4117-80bb-49c3eaface00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071092256 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.1071092256
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.16777676
Short name T439
Test name
Test status
Simulation time 540079160 ps
CPU time 1.81 seconds
Started May 02 02:24:32 PM PDT 24
Finished May 02 02:24:37 PM PDT 24
Peak memory 199132 kb
Host smart-cc29264d-c6d2-4c4c-9bbe-301b9fbc2f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16777676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.16777676
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_alert_test.4243016462
Short name T884
Test name
Test status
Simulation time 21462962 ps
CPU time 0.64 seconds
Started May 02 02:24:33 PM PDT 24
Finished May 02 02:24:37 PM PDT 24
Peak memory 195784 kb
Host smart-3f4c15ee-f005-499b-b59c-d31eb6816f2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243016462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.4243016462
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.539039970
Short name T131
Test name
Test status
Simulation time 121166818534 ps
CPU time 121.79 seconds
Started May 02 02:24:30 PM PDT 24
Finished May 02 02:26:35 PM PDT 24
Peak memory 200352 kb
Host smart-57a54990-e904-4ed1-bfa2-27e7d2ca1c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539039970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.539039970
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.2207989986
Short name T278
Test name
Test status
Simulation time 103416795312 ps
CPU time 165.66 seconds
Started May 02 02:24:32 PM PDT 24
Finished May 02 02:27:21 PM PDT 24
Peak memory 200372 kb
Host smart-ecf849d2-5741-4ba6-961a-3d6c63da71e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207989986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.2207989986
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.2373301612
Short name T644
Test name
Test status
Simulation time 101399335982 ps
CPU time 83.79 seconds
Started May 02 02:24:32 PM PDT 24
Finished May 02 02:25:58 PM PDT 24
Peak memory 200404 kb
Host smart-cf25cbbc-892e-49ef-83c6-daa39c17c3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373301612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.2373301612
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.1689202342
Short name T799
Test name
Test status
Simulation time 58296458723 ps
CPU time 29.01 seconds
Started May 02 02:24:34 PM PDT 24
Finished May 02 02:25:07 PM PDT 24
Peak memory 200404 kb
Host smart-83eea03c-8cce-4345-9b3c-fd32391382f8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689202342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.1689202342
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.2725808624
Short name T585
Test name
Test status
Simulation time 87844860160 ps
CPU time 216.62 seconds
Started May 02 02:24:32 PM PDT 24
Finished May 02 02:28:12 PM PDT 24
Peak memory 200400 kb
Host smart-31c04796-ad26-42b0-8727-2be3b33b12ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2725808624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.2725808624
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.48532409
Short name T989
Test name
Test status
Simulation time 1326425212 ps
CPU time 2.73 seconds
Started May 02 02:24:32 PM PDT 24
Finished May 02 02:24:38 PM PDT 24
Peak memory 197704 kb
Host smart-b4e26a18-eead-47cd-b3bb-896b4dcb1482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48532409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.48532409
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.3501416805
Short name T450
Test name
Test status
Simulation time 15737664636 ps
CPU time 24.28 seconds
Started May 02 02:24:30 PM PDT 24
Finished May 02 02:24:57 PM PDT 24
Peak memory 194972 kb
Host smart-c696879b-0bfa-4dd5-9d3a-9ba5fdeffcf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501416805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.3501416805
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.2068307590
Short name T990
Test name
Test status
Simulation time 22417509368 ps
CPU time 342.93 seconds
Started May 02 02:24:32 PM PDT 24
Finished May 02 02:30:18 PM PDT 24
Peak memory 200304 kb
Host smart-c16f0156-79c6-4803-b609-93ef4a7af089
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2068307590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.2068307590
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.3968629939
Short name T501
Test name
Test status
Simulation time 3397602616 ps
CPU time 3.05 seconds
Started May 02 02:24:31 PM PDT 24
Finished May 02 02:24:38 PM PDT 24
Peak memory 198492 kb
Host smart-904d5574-aa79-489d-b951-5459e8d6529c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3968629939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.3968629939
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.3551916340
Short name T126
Test name
Test status
Simulation time 126175127997 ps
CPU time 49.15 seconds
Started May 02 02:24:30 PM PDT 24
Finished May 02 02:25:22 PM PDT 24
Peak memory 200352 kb
Host smart-2da22f02-0b5b-4532-ae25-17d2c65dea59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551916340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.3551916340
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.135612252
Short name T978
Test name
Test status
Simulation time 44280711726 ps
CPU time 16.54 seconds
Started May 02 02:24:35 PM PDT 24
Finished May 02 02:24:55 PM PDT 24
Peak memory 196388 kb
Host smart-b7880f5e-55a3-4da4-9038-7e442d43ecac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135612252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.135612252
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.971040935
Short name T83
Test name
Test status
Simulation time 298171365 ps
CPU time 0.87 seconds
Started May 02 02:24:32 PM PDT 24
Finished May 02 02:24:37 PM PDT 24
Peak memory 218784 kb
Host smart-16953890-15c2-4579-9e75-688e428b05d1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971040935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.971040935
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.1602542831
Short name T729
Test name
Test status
Simulation time 496019474 ps
CPU time 1.4 seconds
Started May 02 02:24:29 PM PDT 24
Finished May 02 02:24:33 PM PDT 24
Peak memory 198796 kb
Host smart-d8403e1d-7a15-4161-9247-842f00c970d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602542831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.1602542831
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.3654036440
Short name T1109
Test name
Test status
Simulation time 349268097424 ps
CPU time 299.54 seconds
Started May 02 02:24:30 PM PDT 24
Finished May 02 02:29:32 PM PDT 24
Peak memory 200456 kb
Host smart-e2ddca9a-64fb-4579-a335-0f62a514add4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654036440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.3654036440
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.863886425
Short name T295
Test name
Test status
Simulation time 99538347863 ps
CPU time 824.07 seconds
Started May 02 02:24:31 PM PDT 24
Finished May 02 02:38:18 PM PDT 24
Peak memory 217080 kb
Host smart-b49964a6-fe0a-4c48-8b1c-7f7f20011607
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863886425 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.863886425
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.2942265742
Short name T656
Test name
Test status
Simulation time 1591416512 ps
CPU time 1.65 seconds
Started May 02 02:24:31 PM PDT 24
Finished May 02 02:24:35 PM PDT 24
Peak memory 198976 kb
Host smart-d11aecfd-db9d-4775-828c-517ee1d63e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942265742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.2942265742
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.357656092
Short name T641
Test name
Test status
Simulation time 72413713220 ps
CPU time 117.16 seconds
Started May 02 02:24:34 PM PDT 24
Finished May 02 02:26:35 PM PDT 24
Peak memory 200396 kb
Host smart-0ca63e4a-39e1-4baf-87fa-b9a03312c155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357656092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.357656092
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.55874829
Short name T1147
Test name
Test status
Simulation time 14829797 ps
CPU time 0.51 seconds
Started May 02 02:25:28 PM PDT 24
Finished May 02 02:25:31 PM PDT 24
Peak memory 194752 kb
Host smart-9302b7cb-cd0f-4b7b-9d8e-04e0d3c29ba2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55874829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.55874829
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.3923101059
Short name T783
Test name
Test status
Simulation time 211773013201 ps
CPU time 488.65 seconds
Started May 02 02:25:21 PM PDT 24
Finished May 02 02:33:31 PM PDT 24
Peak memory 200356 kb
Host smart-4271660a-4101-4915-b7c9-94c126d72b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923101059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.3923101059
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.3504773361
Short name T36
Test name
Test status
Simulation time 83607400128 ps
CPU time 17.74 seconds
Started May 02 02:25:19 PM PDT 24
Finished May 02 02:25:38 PM PDT 24
Peak memory 200372 kb
Host smart-0106a0a6-a8a7-45bf-8ae6-54837331bfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504773361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.3504773361
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.3525727067
Short name T786
Test name
Test status
Simulation time 18418051623 ps
CPU time 15.22 seconds
Started May 02 02:25:26 PM PDT 24
Finished May 02 02:25:44 PM PDT 24
Peak memory 200168 kb
Host smart-060fcad4-711e-4c2c-baac-222aa7faf3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525727067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.3525727067
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.2228007884
Short name T919
Test name
Test status
Simulation time 59043879101 ps
CPU time 94.89 seconds
Started May 02 02:25:23 PM PDT 24
Finished May 02 02:27:00 PM PDT 24
Peak memory 200192 kb
Host smart-9388caee-dfac-4798-b333-7515dc2490b4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228007884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.2228007884
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.2901605212
Short name T415
Test name
Test status
Simulation time 268927263405 ps
CPU time 132.35 seconds
Started May 02 02:25:30 PM PDT 24
Finished May 02 02:27:44 PM PDT 24
Peak memory 200340 kb
Host smart-d772f7ea-5ee6-4240-ba25-a01fa726d611
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2901605212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.2901605212
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.3169302786
Short name T754
Test name
Test status
Simulation time 2254052197 ps
CPU time 1.42 seconds
Started May 02 02:25:28 PM PDT 24
Finished May 02 02:25:32 PM PDT 24
Peak memory 196540 kb
Host smart-3451c6d3-0d0d-42d0-aec5-2f0ce4ef4136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169302786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.3169302786
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.2546465615
Short name T824
Test name
Test status
Simulation time 56472971818 ps
CPU time 81.15 seconds
Started May 02 02:25:20 PM PDT 24
Finished May 02 02:26:43 PM PDT 24
Peak memory 200544 kb
Host smart-fab0faa0-16db-4f82-97dc-7bebc8466152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546465615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.2546465615
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.449422888
Short name T497
Test name
Test status
Simulation time 16095971962 ps
CPU time 935.47 seconds
Started May 02 02:25:28 PM PDT 24
Finished May 02 02:41:06 PM PDT 24
Peak memory 200368 kb
Host smart-b8b4ff9d-8ae0-4715-83fe-5060a6aeb689
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=449422888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.449422888
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.4111361999
Short name T345
Test name
Test status
Simulation time 4530374969 ps
CPU time 16.67 seconds
Started May 02 02:25:26 PM PDT 24
Finished May 02 02:25:45 PM PDT 24
Peak memory 199620 kb
Host smart-d7fe3e0b-ab4d-4290-959d-fddaea9f931d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4111361999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.4111361999
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.792178955
Short name T1030
Test name
Test status
Simulation time 116499451526 ps
CPU time 39.53 seconds
Started May 02 02:25:21 PM PDT 24
Finished May 02 02:26:03 PM PDT 24
Peak memory 199748 kb
Host smart-9a5aa801-2cf0-402e-bf73-6d56589b434d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792178955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.792178955
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.1195924281
Short name T659
Test name
Test status
Simulation time 2183766703 ps
CPU time 4.44 seconds
Started May 02 02:25:21 PM PDT 24
Finished May 02 02:25:27 PM PDT 24
Peak memory 195208 kb
Host smart-ab65dbab-6154-4195-a46d-4c3da1c6d629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195924281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.1195924281
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.3883318588
Short name T399
Test name
Test status
Simulation time 692780480 ps
CPU time 4.5 seconds
Started May 02 02:25:20 PM PDT 24
Finished May 02 02:25:26 PM PDT 24
Peak memory 198640 kb
Host smart-c1beb493-bc16-422d-b051-88d1eead734b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883318588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.3883318588
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.111158533
Short name T41
Test name
Test status
Simulation time 28891828666 ps
CPU time 943.95 seconds
Started May 02 02:25:27 PM PDT 24
Finished May 02 02:41:14 PM PDT 24
Peak memory 200652 kb
Host smart-80e4a977-179b-422c-8f03-5ffd69738f6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111158533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.111158533
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.998161431
Short name T700
Test name
Test status
Simulation time 93383535845 ps
CPU time 1219.89 seconds
Started May 02 02:25:28 PM PDT 24
Finished May 02 02:45:50 PM PDT 24
Peak memory 216880 kb
Host smart-80fe58b0-41e4-4312-ae21-bf996332e826
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998161431 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.998161431
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.762925241
Short name T733
Test name
Test status
Simulation time 1206298907 ps
CPU time 3.53 seconds
Started May 02 02:25:28 PM PDT 24
Finished May 02 02:25:33 PM PDT 24
Peak memory 198920 kb
Host smart-2c74202d-e5ec-41af-92ce-fc84260ea90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762925241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.762925241
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.2693865768
Short name T429
Test name
Test status
Simulation time 59192957723 ps
CPU time 55.36 seconds
Started May 02 02:25:27 PM PDT 24
Finished May 02 02:26:25 PM PDT 24
Peak memory 200424 kb
Host smart-b73b8253-0d4e-4de7-bbe8-655aa33d57b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693865768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.2693865768
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.4219015864
Short name T966
Test name
Test status
Simulation time 31383014659 ps
CPU time 20.3 seconds
Started May 02 02:31:49 PM PDT 24
Finished May 02 02:32:11 PM PDT 24
Peak memory 200376 kb
Host smart-866f5365-7fd3-4464-be41-4bf00bcb72bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219015864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.4219015864
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.49022185
Short name T951
Test name
Test status
Simulation time 53477770508 ps
CPU time 24.1 seconds
Started May 02 02:31:49 PM PDT 24
Finished May 02 02:32:15 PM PDT 24
Peak memory 200448 kb
Host smart-7bccba94-c426-4bb2-a11f-7983689ef395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49022185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.49022185
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.45255410
Short name T148
Test name
Test status
Simulation time 200098897309 ps
CPU time 192.35 seconds
Started May 02 02:31:49 PM PDT 24
Finished May 02 02:35:03 PM PDT 24
Peak memory 200460 kb
Host smart-1d413276-b58a-4035-82d0-9381b97d148b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45255410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.45255410
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.1252854734
Short name T922
Test name
Test status
Simulation time 48434242668 ps
CPU time 69.43 seconds
Started May 02 02:31:49 PM PDT 24
Finished May 02 02:33:00 PM PDT 24
Peak memory 200440 kb
Host smart-66e2134c-2792-4f74-85a6-577525067e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252854734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.1252854734
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.2428141569
Short name T554
Test name
Test status
Simulation time 93181724281 ps
CPU time 77.13 seconds
Started May 02 02:31:57 PM PDT 24
Finished May 02 02:33:16 PM PDT 24
Peak memory 200356 kb
Host smart-5c6792bf-8b59-4d42-ba80-f91684b4ae92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428141569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.2428141569
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.3802039033
Short name T492
Test name
Test status
Simulation time 45691093983 ps
CPU time 67.44 seconds
Started May 02 02:31:56 PM PDT 24
Finished May 02 02:33:06 PM PDT 24
Peak memory 200376 kb
Host smart-82de7111-f0b7-4161-906b-4b3f313b352b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802039033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.3802039033
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.3302650945
Short name T787
Test name
Test status
Simulation time 200895256698 ps
CPU time 28.41 seconds
Started May 02 02:31:56 PM PDT 24
Finished May 02 02:32:26 PM PDT 24
Peak memory 200416 kb
Host smart-514f84aa-8167-496d-b6a9-c224e819f0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302650945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.3302650945
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.2729078506
Short name T681
Test name
Test status
Simulation time 58073147955 ps
CPU time 24.88 seconds
Started May 02 02:31:57 PM PDT 24
Finished May 02 02:32:24 PM PDT 24
Peak memory 200444 kb
Host smart-dca2ca9a-738d-40d7-ba0c-f10c6b8cef38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729078506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.2729078506
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_fifo_full.459589772
Short name T1031
Test name
Test status
Simulation time 71854978454 ps
CPU time 19.14 seconds
Started May 02 02:25:28 PM PDT 24
Finished May 02 02:25:49 PM PDT 24
Peak memory 200424 kb
Host smart-138d3dbe-424a-4ede-8c74-56877d24e8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459589772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.459589772
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.1143210241
Short name T961
Test name
Test status
Simulation time 5751195650 ps
CPU time 9.54 seconds
Started May 02 02:25:29 PM PDT 24
Finished May 02 02:25:41 PM PDT 24
Peak memory 200336 kb
Host smart-2a48a361-bae3-4a23-8438-2150d884b22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143210241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.1143210241
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.4156310150
Short name T578
Test name
Test status
Simulation time 13106090790 ps
CPU time 13.96 seconds
Started May 02 02:25:26 PM PDT 24
Finished May 02 02:25:42 PM PDT 24
Peak memory 200136 kb
Host smart-aa9d9a4c-ac32-459b-a436-12540431e76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156310150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.4156310150
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.3793397499
Short name T301
Test name
Test status
Simulation time 106481574306 ps
CPU time 156.51 seconds
Started May 02 02:25:35 PM PDT 24
Finished May 02 02:28:14 PM PDT 24
Peak memory 199104 kb
Host smart-b5d6d581-132d-4a3f-986a-f127336d261c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793397499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.3793397499
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.665542143
Short name T1181
Test name
Test status
Simulation time 51906782320 ps
CPU time 222 seconds
Started May 02 02:25:36 PM PDT 24
Finished May 02 02:29:21 PM PDT 24
Peak memory 200348 kb
Host smart-c0417a91-7b3d-40e3-85e5-bfb5554c52bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=665542143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.665542143
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.3016527864
Short name T33
Test name
Test status
Simulation time 11949850591 ps
CPU time 5.81 seconds
Started May 02 02:25:39 PM PDT 24
Finished May 02 02:25:48 PM PDT 24
Peak memory 197572 kb
Host smart-929966a6-fd80-45c8-b59d-1aadf69a82d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016527864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.3016527864
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.1017178158
Short name T685
Test name
Test status
Simulation time 50598591494 ps
CPU time 20.08 seconds
Started May 02 02:25:37 PM PDT 24
Finished May 02 02:25:59 PM PDT 24
Peak memory 197728 kb
Host smart-67ce1812-4802-44cf-b3e0-90c7d0a0df7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017178158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.1017178158
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.1079535643
Short name T925
Test name
Test status
Simulation time 25342000609 ps
CPU time 657.94 seconds
Started May 02 02:25:38 PM PDT 24
Finished May 02 02:36:38 PM PDT 24
Peak memory 200468 kb
Host smart-1af656d4-f913-4bbf-af70-1314aa02c07f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1079535643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.1079535643
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.2712579830
Short name T440
Test name
Test status
Simulation time 5655869951 ps
CPU time 35.85 seconds
Started May 02 02:25:37 PM PDT 24
Finished May 02 02:26:15 PM PDT 24
Peak memory 199500 kb
Host smart-70e5bc2b-5cf4-47fe-9f2f-d304029fa88f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2712579830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.2712579830
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.2413739548
Short name T168
Test name
Test status
Simulation time 31035712237 ps
CPU time 58.69 seconds
Started May 02 02:25:36 PM PDT 24
Finished May 02 02:26:36 PM PDT 24
Peak memory 200404 kb
Host smart-ad56a41c-07a5-4f30-8d1d-e9bf6e81561c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413739548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.2413739548
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.1172867224
Short name T421
Test name
Test status
Simulation time 27529888892 ps
CPU time 11.64 seconds
Started May 02 02:25:36 PM PDT 24
Finished May 02 02:25:50 PM PDT 24
Peak memory 196172 kb
Host smart-f9d7cb50-6b30-4bca-bab7-18a0c398c746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172867224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.1172867224
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.1300843965
Short name T732
Test name
Test status
Simulation time 685829416 ps
CPU time 2.03 seconds
Started May 02 02:25:29 PM PDT 24
Finished May 02 02:25:33 PM PDT 24
Peak memory 200304 kb
Host smart-0ad7b36f-a13a-49e1-95f4-87d6cdacf3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300843965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.1300843965
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.225001819
Short name T855
Test name
Test status
Simulation time 176679404430 ps
CPU time 405.93 seconds
Started May 02 02:25:36 PM PDT 24
Finished May 02 02:32:24 PM PDT 24
Peak memory 200456 kb
Host smart-7100fb85-1e9e-458d-afa6-40612d2cbc52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225001819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.225001819
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.3014649020
Short name T95
Test name
Test status
Simulation time 72540736354 ps
CPU time 602.06 seconds
Started May 02 02:25:37 PM PDT 24
Finished May 02 02:35:41 PM PDT 24
Peak memory 216572 kb
Host smart-18454791-8c76-4359-bc46-078f5206be1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014649020 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.3014649020
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.2035604928
Short name T480
Test name
Test status
Simulation time 1845934714 ps
CPU time 2.55 seconds
Started May 02 02:25:35 PM PDT 24
Finished May 02 02:25:40 PM PDT 24
Peak memory 199440 kb
Host smart-54d7b418-8d79-4d40-8506-b689404f2a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035604928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.2035604928
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.3828068866
Short name T956
Test name
Test status
Simulation time 21873056109 ps
CPU time 39.63 seconds
Started May 02 02:25:27 PM PDT 24
Finished May 02 02:26:09 PM PDT 24
Peak memory 200420 kb
Host smart-6176781c-e9c4-4713-958b-620bf8ef9689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828068866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.3828068866
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.1292441801
Short name T570
Test name
Test status
Simulation time 105522893609 ps
CPU time 40.03 seconds
Started May 02 02:31:57 PM PDT 24
Finished May 02 02:32:39 PM PDT 24
Peak memory 200308 kb
Host smart-ad598470-3e1b-4bbd-99cb-0d378b564c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292441801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1292441801
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.3462260672
Short name T1082
Test name
Test status
Simulation time 60390188419 ps
CPU time 25.39 seconds
Started May 02 02:31:58 PM PDT 24
Finished May 02 02:32:25 PM PDT 24
Peak memory 200380 kb
Host smart-927e9745-4af9-4bae-8578-3bcccda2716d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462260672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.3462260672
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.3127148533
Short name T745
Test name
Test status
Simulation time 175159275506 ps
CPU time 265.47 seconds
Started May 02 02:31:57 PM PDT 24
Finished May 02 02:36:24 PM PDT 24
Peak memory 200420 kb
Host smart-ca5f8c4c-bb60-4205-ab17-e8012fc2ddda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127148533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.3127148533
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.2944477710
Short name T1084
Test name
Test status
Simulation time 21694484284 ps
CPU time 38.99 seconds
Started May 02 02:31:57 PM PDT 24
Finished May 02 02:32:38 PM PDT 24
Peak memory 200344 kb
Host smart-ca536af8-7e8a-4e7d-8ad6-321177e53365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944477710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.2944477710
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.2459740013
Short name T1171
Test name
Test status
Simulation time 43397801775 ps
CPU time 18.94 seconds
Started May 02 02:31:59 PM PDT 24
Finished May 02 02:32:19 PM PDT 24
Peak memory 200376 kb
Host smart-62559a10-7444-4318-86a5-5fba0618ffb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459740013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.2459740013
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.3677209802
Short name T633
Test name
Test status
Simulation time 40126084191 ps
CPU time 19.42 seconds
Started May 02 02:32:04 PM PDT 24
Finished May 02 02:32:25 PM PDT 24
Peak memory 200376 kb
Host smart-906e6db8-8ccd-494b-8524-39bc690cc948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677209802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.3677209802
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.4061104574
Short name T472
Test name
Test status
Simulation time 11479019 ps
CPU time 0.6 seconds
Started May 02 02:25:43 PM PDT 24
Finished May 02 02:25:48 PM PDT 24
Peak memory 194792 kb
Host smart-2a1c01e8-b58f-4ece-82f4-cd799f161599
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061104574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.4061104574
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.2808757530
Short name T1114
Test name
Test status
Simulation time 392240278081 ps
CPU time 112.35 seconds
Started May 02 02:25:37 PM PDT 24
Finished May 02 02:27:32 PM PDT 24
Peak memory 200360 kb
Host smart-38e2faa9-991b-4501-807b-c12dfd0b1e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808757530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2808757530
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.2756205305
Short name T136
Test name
Test status
Simulation time 107101406000 ps
CPU time 14.93 seconds
Started May 02 02:25:37 PM PDT 24
Finished May 02 02:25:54 PM PDT 24
Peak memory 199984 kb
Host smart-cb1e42f1-37ec-432a-9d31-b4967ec08355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756205305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2756205305
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.3721615869
Short name T608
Test name
Test status
Simulation time 33961351309 ps
CPU time 57.79 seconds
Started May 02 02:25:36 PM PDT 24
Finished May 02 02:26:36 PM PDT 24
Peak memory 200364 kb
Host smart-ae4eb1a9-5ace-4091-994b-597a0d038a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721615869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.3721615869
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.3210340438
Short name T11
Test name
Test status
Simulation time 33847893504 ps
CPU time 16.86 seconds
Started May 02 02:25:37 PM PDT 24
Finished May 02 02:25:56 PM PDT 24
Peak memory 198920 kb
Host smart-a96ddefe-4ae4-4f47-8548-ebfc9f301b87
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210340438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.3210340438
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.3760395241
Short name T1081
Test name
Test status
Simulation time 128624934776 ps
CPU time 210.52 seconds
Started May 02 02:25:43 PM PDT 24
Finished May 02 02:29:17 PM PDT 24
Peak memory 200436 kb
Host smart-1d3bf340-efd3-4f5b-a809-74cebf41250d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3760395241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.3760395241
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.3179312576
Short name T894
Test name
Test status
Simulation time 1542991229 ps
CPU time 0.97 seconds
Started May 02 02:25:38 PM PDT 24
Finished May 02 02:25:42 PM PDT 24
Peak memory 195868 kb
Host smart-f6c6d09b-6098-4280-8145-731b5b263ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179312576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.3179312576
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.912164342
Short name T264
Test name
Test status
Simulation time 53030346873 ps
CPU time 79.39 seconds
Started May 02 02:25:38 PM PDT 24
Finished May 02 02:27:01 PM PDT 24
Peak memory 198852 kb
Host smart-44e46759-65e2-4641-a13f-e8b5d210026b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912164342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.912164342
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.2557079095
Short name T768
Test name
Test status
Simulation time 17815903225 ps
CPU time 67.02 seconds
Started May 02 02:25:35 PM PDT 24
Finished May 02 02:26:45 PM PDT 24
Peak memory 200336 kb
Host smart-179c8860-482d-45a5-8f7b-164c1cf1f905
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2557079095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.2557079095
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.488180964
Short name T319
Test name
Test status
Simulation time 1374211871 ps
CPU time 3.14 seconds
Started May 02 02:25:38 PM PDT 24
Finished May 02 02:25:44 PM PDT 24
Peak memory 198608 kb
Host smart-7641b123-08b7-4690-ac01-35dc4cf9c720
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=488180964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.488180964
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.2237034015
Short name T410
Test name
Test status
Simulation time 10226203636 ps
CPU time 17.14 seconds
Started May 02 02:25:38 PM PDT 24
Finished May 02 02:25:57 PM PDT 24
Peak memory 199636 kb
Host smart-0ffc8411-0c13-4bb0-9674-9b87fe96f60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237034015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.2237034015
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.2867441270
Short name T529
Test name
Test status
Simulation time 4781889881 ps
CPU time 1.7 seconds
Started May 02 02:25:38 PM PDT 24
Finished May 02 02:25:42 PM PDT 24
Peak memory 196452 kb
Host smart-a3ed0fab-ad9f-45be-8c3d-a70dd051a010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867441270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.2867441270
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.60381466
Short name T843
Test name
Test status
Simulation time 467268048 ps
CPU time 1.1 seconds
Started May 02 02:25:35 PM PDT 24
Finished May 02 02:25:38 PM PDT 24
Peak memory 198788 kb
Host smart-f1509108-a98f-4f44-a9eb-f2c99b906e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60381466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.60381466
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.2692351710
Short name T930
Test name
Test status
Simulation time 245089581429 ps
CPU time 330.02 seconds
Started May 02 02:25:44 PM PDT 24
Finished May 02 02:31:19 PM PDT 24
Peak memory 200336 kb
Host smart-024b7bfa-ed60-4c68-a246-0754b3c03e8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692351710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.2692351710
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.2705055060
Short name T385
Test name
Test status
Simulation time 79547419973 ps
CPU time 1103.36 seconds
Started May 02 02:25:44 PM PDT 24
Finished May 02 02:44:12 PM PDT 24
Peak memory 225188 kb
Host smart-0ed7a91e-8581-42c9-b3e3-b8ca0fc1ca75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705055060 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.2705055060
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.2658372218
Short name T527
Test name
Test status
Simulation time 558936272 ps
CPU time 2.54 seconds
Started May 02 02:25:37 PM PDT 24
Finished May 02 02:25:42 PM PDT 24
Peak memory 199820 kb
Host smart-e10c87d2-70e6-4736-98cf-9fbb92ca80c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658372218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.2658372218
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.2550329204
Short name T838
Test name
Test status
Simulation time 41948644269 ps
CPU time 42.25 seconds
Started May 02 02:25:38 PM PDT 24
Finished May 02 02:26:23 PM PDT 24
Peak memory 200368 kb
Host smart-cba241db-2442-413d-890e-149bc71d7d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550329204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.2550329204
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.1292635334
Short name T691
Test name
Test status
Simulation time 26572165203 ps
CPU time 40.22 seconds
Started May 02 02:32:05 PM PDT 24
Finished May 02 02:32:47 PM PDT 24
Peak memory 200344 kb
Host smart-0702d7ec-e24e-4ce4-aa58-7ffd5ae85e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292635334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.1292635334
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.1315306446
Short name T813
Test name
Test status
Simulation time 38740965879 ps
CPU time 15.85 seconds
Started May 02 02:32:04 PM PDT 24
Finished May 02 02:32:21 PM PDT 24
Peak memory 200364 kb
Host smart-b363d52e-4654-4976-8952-4f92b692d8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315306446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.1315306446
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.3595685440
Short name T568
Test name
Test status
Simulation time 8959701043 ps
CPU time 10.72 seconds
Started May 02 02:32:04 PM PDT 24
Finished May 02 02:32:16 PM PDT 24
Peak memory 200272 kb
Host smart-c5b1cf0a-2dea-4d96-b943-acd01f44a721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595685440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.3595685440
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.1847972722
Short name T105
Test name
Test status
Simulation time 90130174079 ps
CPU time 36.59 seconds
Started May 02 02:32:12 PM PDT 24
Finished May 02 02:32:50 PM PDT 24
Peak memory 200384 kb
Host smart-5eb455ff-ec53-4b04-9fb0-eb9154a60d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847972722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.1847972722
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.92061965
Short name T1026
Test name
Test status
Simulation time 31627342765 ps
CPU time 57.07 seconds
Started May 02 02:32:10 PM PDT 24
Finished May 02 02:33:09 PM PDT 24
Peak memory 200380 kb
Host smart-5e163027-8ffb-4142-a8ba-1e8f3bfe35d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92061965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.92061965
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.4230318639
Short name T749
Test name
Test status
Simulation time 80618536616 ps
CPU time 86.01 seconds
Started May 02 02:32:17 PM PDT 24
Finished May 02 02:33:44 PM PDT 24
Peak memory 200324 kb
Host smart-5f5338f7-9947-490d-927a-fe0eef710dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230318639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.4230318639
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.3461389853
Short name T348
Test name
Test status
Simulation time 38448314558 ps
CPU time 19.25 seconds
Started May 02 02:32:19 PM PDT 24
Finished May 02 02:32:39 PM PDT 24
Peak memory 200372 kb
Host smart-34127cfe-e0ee-4f62-bc13-4772d7a4c558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461389853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3461389853
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.2617554762
Short name T475
Test name
Test status
Simulation time 106251221193 ps
CPU time 47.98 seconds
Started May 02 02:32:22 PM PDT 24
Finished May 02 02:33:11 PM PDT 24
Peak memory 200436 kb
Host smart-5eeb2bb3-be83-45ab-8156-3a032c74336a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617554762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2617554762
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.2207492435
Short name T502
Test name
Test status
Simulation time 13666608 ps
CPU time 0.56 seconds
Started May 02 02:25:52 PM PDT 24
Finished May 02 02:26:05 PM PDT 24
Peak memory 195192 kb
Host smart-8748e32d-fca3-4275-bc7b-f9661dc9b3e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207492435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.2207492435
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.1588793334
Short name T563
Test name
Test status
Simulation time 19249643643 ps
CPU time 45.9 seconds
Started May 02 02:25:44 PM PDT 24
Finished May 02 02:26:35 PM PDT 24
Peak memory 200400 kb
Host smart-0dcf3fca-a831-4a9b-a939-2713f98b61a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588793334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.1588793334
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.2141192755
Short name T566
Test name
Test status
Simulation time 55784322452 ps
CPU time 83.91 seconds
Started May 02 02:25:44 PM PDT 24
Finished May 02 02:27:13 PM PDT 24
Peak memory 200432 kb
Host smart-ea174a03-c70d-404a-a585-483242200469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141192755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2141192755
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.3591338203
Short name T962
Test name
Test status
Simulation time 61321903999 ps
CPU time 21.92 seconds
Started May 02 02:25:46 PM PDT 24
Finished May 02 02:26:13 PM PDT 24
Peak memory 200360 kb
Host smart-0b748985-0264-4a02-9331-7f7c32c9b8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591338203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.3591338203
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.1824215463
Short name T1098
Test name
Test status
Simulation time 33999707276 ps
CPU time 16.26 seconds
Started May 02 02:25:44 PM PDT 24
Finished May 02 02:26:05 PM PDT 24
Peak memory 200356 kb
Host smart-da64021c-1d80-4cb3-8713-e50fa21e15a8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824215463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.1824215463
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.2243528685
Short name T92
Test name
Test status
Simulation time 75813840400 ps
CPU time 215.81 seconds
Started May 02 02:25:54 PM PDT 24
Finished May 02 02:29:43 PM PDT 24
Peak memory 200408 kb
Host smart-fff9a378-263d-4ab5-9025-05690579fc66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2243528685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.2243528685
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.3446474766
Short name T1032
Test name
Test status
Simulation time 6612134987 ps
CPU time 22.51 seconds
Started May 02 02:25:45 PM PDT 24
Finished May 02 02:26:12 PM PDT 24
Peak memory 199292 kb
Host smart-14d66d2e-f77a-4109-8aac-2c33406a2fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446474766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.3446474766
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.2419691392
Short name T532
Test name
Test status
Simulation time 109669313412 ps
CPU time 60.11 seconds
Started May 02 02:25:44 PM PDT 24
Finished May 02 02:26:49 PM PDT 24
Peak memory 216260 kb
Host smart-ef489778-78d8-4266-812f-60e087c84587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419691392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.2419691392
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.1201002755
Short name T807
Test name
Test status
Simulation time 16435247018 ps
CPU time 369.89 seconds
Started May 02 02:25:44 PM PDT 24
Finished May 02 02:31:59 PM PDT 24
Peak memory 200372 kb
Host smart-40fe8b8a-c1b4-417d-8218-f610a03f925b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1201002755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.1201002755
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.3897895927
Short name T796
Test name
Test status
Simulation time 6451519128 ps
CPU time 15.81 seconds
Started May 02 02:25:44 PM PDT 24
Finished May 02 02:26:04 PM PDT 24
Peak memory 198480 kb
Host smart-92ca34c7-8a7e-422f-b347-9b5befc06717
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3897895927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.3897895927
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.4046532243
Short name T892
Test name
Test status
Simulation time 27454996843 ps
CPU time 57.24 seconds
Started May 02 02:25:45 PM PDT 24
Finished May 02 02:26:47 PM PDT 24
Peak memory 200416 kb
Host smart-889e2e19-abd3-4ea9-b984-06fe7bde1f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046532243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.4046532243
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.675040679
Short name T885
Test name
Test status
Simulation time 2771620322 ps
CPU time 1.82 seconds
Started May 02 02:25:44 PM PDT 24
Finished May 02 02:25:51 PM PDT 24
Peak memory 196132 kb
Host smart-6644d822-78c8-4b3e-93ab-15a49a565f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675040679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.675040679
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.1737665765
Short name T622
Test name
Test status
Simulation time 666550711 ps
CPU time 4.18 seconds
Started May 02 02:25:45 PM PDT 24
Finished May 02 02:25:54 PM PDT 24
Peak memory 199140 kb
Host smart-14a71dbc-dc49-4d19-ba6b-3dcf405b5713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737665765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.1737665765
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.1083439130
Short name T99
Test name
Test status
Simulation time 132029579384 ps
CPU time 439.98 seconds
Started May 02 02:25:52 PM PDT 24
Finished May 02 02:33:24 PM PDT 24
Peak memory 217060 kb
Host smart-97a63b07-8795-4297-ae11-19a8f5e824e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083439130 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.1083439130
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.2734868777
Short name T607
Test name
Test status
Simulation time 1313382702 ps
CPU time 2.68 seconds
Started May 02 02:25:43 PM PDT 24
Finished May 02 02:25:51 PM PDT 24
Peak memory 200256 kb
Host smart-0b004c2b-a6fd-46ed-8543-2297916ed766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734868777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.2734868777
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.1494812923
Short name T248
Test name
Test status
Simulation time 47700906322 ps
CPU time 25.7 seconds
Started May 02 02:25:44 PM PDT 24
Finished May 02 02:26:14 PM PDT 24
Peak memory 200400 kb
Host smart-8fbca311-b00c-4cb3-91bf-15bac017e8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494812923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.1494812923
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.1627349616
Short name T751
Test name
Test status
Simulation time 96301316942 ps
CPU time 37.19 seconds
Started May 02 02:32:19 PM PDT 24
Finished May 02 02:32:57 PM PDT 24
Peak memory 200408 kb
Host smart-3509ad86-889d-4c70-bfbc-2c2ff3ef83fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627349616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.1627349616
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.4001652621
Short name T442
Test name
Test status
Simulation time 18282578014 ps
CPU time 15.55 seconds
Started May 02 02:32:17 PM PDT 24
Finished May 02 02:32:34 PM PDT 24
Peak memory 200436 kb
Host smart-401213eb-5514-4abd-914e-acb758762cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001652621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.4001652621
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.46490537
Short name T1010
Test name
Test status
Simulation time 72746713049 ps
CPU time 66.93 seconds
Started May 02 02:32:19 PM PDT 24
Finished May 02 02:33:27 PM PDT 24
Peak memory 200392 kb
Host smart-468a34a1-83fb-4b50-a760-a5e82b4a1b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46490537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.46490537
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.1138274315
Short name T825
Test name
Test status
Simulation time 81346060627 ps
CPU time 29.71 seconds
Started May 02 02:32:20 PM PDT 24
Finished May 02 02:32:51 PM PDT 24
Peak memory 200180 kb
Host smart-de455f11-66c6-4ffc-b0ec-67fff6b15914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138274315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1138274315
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.495033118
Short name T613
Test name
Test status
Simulation time 63372727229 ps
CPU time 60.79 seconds
Started May 02 02:32:28 PM PDT 24
Finished May 02 02:33:29 PM PDT 24
Peak memory 200328 kb
Host smart-4d3d4260-9382-4102-a963-2f729a89e700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495033118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.495033118
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.36080637
Short name T200
Test name
Test status
Simulation time 153591492366 ps
CPU time 59.54 seconds
Started May 02 02:32:30 PM PDT 24
Finished May 02 02:33:30 PM PDT 24
Peak memory 200244 kb
Host smart-916ae878-2f2a-4bc0-bea3-3d5ea94ee1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36080637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.36080637
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.2062594067
Short name T662
Test name
Test status
Simulation time 102595992682 ps
CPU time 70.43 seconds
Started May 02 02:32:29 PM PDT 24
Finished May 02 02:33:40 PM PDT 24
Peak memory 200392 kb
Host smart-000d6c92-6de4-4add-8a95-f749754f8465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062594067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.2062594067
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.2157806488
Short name T856
Test name
Test status
Simulation time 105573445968 ps
CPU time 23.06 seconds
Started May 02 02:32:27 PM PDT 24
Finished May 02 02:32:51 PM PDT 24
Peak memory 200376 kb
Host smart-94aca772-38d1-4b94-b978-a601a821e973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157806488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.2157806488
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.2705042370
Short name T1052
Test name
Test status
Simulation time 28455754 ps
CPU time 0.56 seconds
Started May 02 02:26:00 PM PDT 24
Finished May 02 02:26:15 PM PDT 24
Peak memory 195752 kb
Host smart-beaf4cfb-6c55-4c2d-91e6-df04b00c17d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705042370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.2705042370
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.3431955474
Short name T1000
Test name
Test status
Simulation time 113715911762 ps
CPU time 217 seconds
Started May 02 02:25:52 PM PDT 24
Finished May 02 02:29:41 PM PDT 24
Peak memory 200440 kb
Host smart-bb14f1d7-7588-4da0-88c1-02e5884bc5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431955474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.3431955474
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.3808194843
Short name T810
Test name
Test status
Simulation time 32271323148 ps
CPU time 25.61 seconds
Started May 02 02:25:53 PM PDT 24
Finished May 02 02:26:32 PM PDT 24
Peak memory 200300 kb
Host smart-ed9b5572-0f24-4e2d-96c0-3d6ea0f9599d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808194843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.3808194843
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.248950199
Short name T226
Test name
Test status
Simulation time 27406286407 ps
CPU time 26.17 seconds
Started May 02 02:25:54 PM PDT 24
Finished May 02 02:26:34 PM PDT 24
Peak memory 200368 kb
Host smart-73c228d6-9083-40c3-80a2-7d03c823c409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248950199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.248950199
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.3161904467
Short name T336
Test name
Test status
Simulation time 403516396961 ps
CPU time 165.4 seconds
Started May 02 02:25:52 PM PDT 24
Finished May 02 02:28:50 PM PDT 24
Peak memory 200332 kb
Host smart-89c0ce07-e296-44eb-9f19-8be60dc7def2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161904467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.3161904467
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.3249506270
Short name T430
Test name
Test status
Simulation time 69746610060 ps
CPU time 168.15 seconds
Started May 02 02:26:01 PM PDT 24
Finished May 02 02:29:04 PM PDT 24
Peak memory 200408 kb
Host smart-114bc25a-f787-4c0d-a324-aa8956ffb733
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3249506270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.3249506270
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.1358554941
Short name T1014
Test name
Test status
Simulation time 4032081280 ps
CPU time 4.5 seconds
Started May 02 02:25:52 PM PDT 24
Finished May 02 02:26:08 PM PDT 24
Peak memory 199800 kb
Host smart-b71974d4-d508-454b-8f84-4afbe5e83f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358554941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.1358554941
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.3232812218
Short name T247
Test name
Test status
Simulation time 198935614738 ps
CPU time 95.16 seconds
Started May 02 02:25:54 PM PDT 24
Finished May 02 02:27:42 PM PDT 24
Peak memory 208772 kb
Host smart-4925a309-699f-4b32-9473-f20686e51cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232812218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.3232812218
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.1435435390
Short name T535
Test name
Test status
Simulation time 24480737035 ps
CPU time 617.3 seconds
Started May 02 02:25:51 PM PDT 24
Finished May 02 02:36:20 PM PDT 24
Peak memory 200428 kb
Host smart-5b1f9c0a-a031-46ce-9c95-1f9e0f0d0f7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1435435390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.1435435390
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.2571055666
Short name T805
Test name
Test status
Simulation time 3192309989 ps
CPU time 5.48 seconds
Started May 02 02:25:51 PM PDT 24
Finished May 02 02:26:08 PM PDT 24
Peak memory 199324 kb
Host smart-a662afc3-038e-4af1-9295-9704bcd1a000
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2571055666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.2571055666
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.679508434
Short name T803
Test name
Test status
Simulation time 18302328951 ps
CPU time 16.03 seconds
Started May 02 02:25:51 PM PDT 24
Finished May 02 02:26:19 PM PDT 24
Peak memory 200180 kb
Host smart-74b83ba0-be81-42ce-9fcf-c73078086fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679508434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.679508434
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.1473805421
Short name T546
Test name
Test status
Simulation time 6124438242 ps
CPU time 3.24 seconds
Started May 02 02:25:53 PM PDT 24
Finished May 02 02:26:10 PM PDT 24
Peak memory 196420 kb
Host smart-62fd6271-fd20-45b1-8234-b7a2d9b876f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473805421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.1473805421
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.488592598
Short name T413
Test name
Test status
Simulation time 6324289356 ps
CPU time 10.75 seconds
Started May 02 02:25:51 PM PDT 24
Finished May 02 02:26:14 PM PDT 24
Peak memory 199568 kb
Host smart-a88f9fb4-a50e-4205-a96d-cab5d6f4a848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488592598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.488592598
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.3338897776
Short name T115
Test name
Test status
Simulation time 58196434055 ps
CPU time 875.14 seconds
Started May 02 02:26:03 PM PDT 24
Finished May 02 02:40:54 PM PDT 24
Peak memory 225300 kb
Host smart-aea092cc-b87d-4c48-a381-382f42fc0a11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338897776 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.3338897776
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.4241005794
Short name T1043
Test name
Test status
Simulation time 1971532815 ps
CPU time 2.16 seconds
Started May 02 02:25:53 PM PDT 24
Finished May 02 02:26:07 PM PDT 24
Peak memory 200324 kb
Host smart-4dcf048c-5083-44f7-b536-92adb99d4f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241005794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.4241005794
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.1657017401
Short name T565
Test name
Test status
Simulation time 82464963572 ps
CPU time 67.96 seconds
Started May 02 02:25:52 PM PDT 24
Finished May 02 02:27:13 PM PDT 24
Peak memory 200432 kb
Host smart-61ae9ed4-3410-437f-a9d0-e675b9961ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657017401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.1657017401
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.1395023865
Short name T308
Test name
Test status
Simulation time 40084511433 ps
CPU time 16.93 seconds
Started May 02 02:32:25 PM PDT 24
Finished May 02 02:32:43 PM PDT 24
Peak memory 200160 kb
Host smart-419f5f2f-3d20-4dee-9dec-1a71e23792ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395023865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1395023865
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.2038126103
Short name T298
Test name
Test status
Simulation time 37886842185 ps
CPU time 13.28 seconds
Started May 02 02:32:26 PM PDT 24
Finished May 02 02:32:41 PM PDT 24
Peak memory 199820 kb
Host smart-5b73c934-d32e-4d60-b2a0-419637d058ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038126103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.2038126103
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.3902990110
Short name T979
Test name
Test status
Simulation time 12989885438 ps
CPU time 27.01 seconds
Started May 02 02:32:27 PM PDT 24
Finished May 02 02:32:55 PM PDT 24
Peak memory 200388 kb
Host smart-677b1ae4-4db6-49b7-8613-39547a53cff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902990110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3902990110
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.3705358209
Short name T403
Test name
Test status
Simulation time 119855485498 ps
CPU time 39.3 seconds
Started May 02 02:32:28 PM PDT 24
Finished May 02 02:33:08 PM PDT 24
Peak memory 200348 kb
Host smart-5a631d40-3abe-4ea5-895f-a006f8672712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705358209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.3705358209
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.948871991
Short name T996
Test name
Test status
Simulation time 91112349213 ps
CPU time 95.53 seconds
Started May 02 02:32:26 PM PDT 24
Finished May 02 02:34:03 PM PDT 24
Peak memory 200328 kb
Host smart-2ec68014-8998-45fa-9766-6f3e4579aee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948871991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.948871991
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.744221772
Short name T784
Test name
Test status
Simulation time 60761421766 ps
CPU time 16.74 seconds
Started May 02 02:33:04 PM PDT 24
Finished May 02 02:33:22 PM PDT 24
Peak memory 200348 kb
Host smart-2d86ce7f-9256-4166-961c-0d86780b7338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744221772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.744221772
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.4194847220
Short name T161
Test name
Test status
Simulation time 47536351715 ps
CPU time 49.9 seconds
Started May 02 02:32:29 PM PDT 24
Finished May 02 02:33:20 PM PDT 24
Peak memory 200396 kb
Host smart-c4ca4b43-a2a8-41e5-a622-c13278c0aa84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194847220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.4194847220
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.174002338
Short name T84
Test name
Test status
Simulation time 25015214883 ps
CPU time 25 seconds
Started May 02 02:32:35 PM PDT 24
Finished May 02 02:33:02 PM PDT 24
Peak memory 200364 kb
Host smart-97e87e78-616f-4957-ae61-216dab738fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174002338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.174002338
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.3878076017
Short name T862
Test name
Test status
Simulation time 39806023 ps
CPU time 0.56 seconds
Started May 02 02:26:04 PM PDT 24
Finished May 02 02:26:20 PM PDT 24
Peak memory 195828 kb
Host smart-1c2ba006-87c7-40ac-8617-b05348d794a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878076017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.3878076017
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.3088248551
Short name T937
Test name
Test status
Simulation time 26734969107 ps
CPU time 20.93 seconds
Started May 02 02:26:02 PM PDT 24
Finished May 02 02:26:37 PM PDT 24
Peak memory 200420 kb
Host smart-8a5adec8-0325-4b6e-86b3-a920008d0660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088248551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.3088248551
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.1571154303
Short name T974
Test name
Test status
Simulation time 79553748694 ps
CPU time 19.95 seconds
Started May 02 02:26:00 PM PDT 24
Finished May 02 02:26:34 PM PDT 24
Peak memory 200420 kb
Host smart-d129678e-ee7b-48aa-8ebc-ad58fe5955a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571154303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.1571154303
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.237017588
Short name T184
Test name
Test status
Simulation time 29702552843 ps
CPU time 15.13 seconds
Started May 02 02:26:02 PM PDT 24
Finished May 02 02:26:32 PM PDT 24
Peak memory 200312 kb
Host smart-69683028-94c1-49ba-99c7-c8b7af177779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237017588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.237017588
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.2923549045
Short name T800
Test name
Test status
Simulation time 7285575899 ps
CPU time 3.78 seconds
Started May 02 02:26:04 PM PDT 24
Finished May 02 02:26:23 PM PDT 24
Peak memory 198168 kb
Host smart-95e2991c-f526-428b-9fe4-96814bdcf349
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923549045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.2923549045
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.2244733068
Short name T400
Test name
Test status
Simulation time 62725143985 ps
CPU time 226.53 seconds
Started May 02 02:26:01 PM PDT 24
Finished May 02 02:30:02 PM PDT 24
Peak memory 200328 kb
Host smart-f593d840-d100-449f-a46d-7e5c45890481
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2244733068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.2244733068
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.2797995561
Short name T946
Test name
Test status
Simulation time 245032234 ps
CPU time 0.69 seconds
Started May 02 02:25:59 PM PDT 24
Finished May 02 02:26:14 PM PDT 24
Peak memory 196292 kb
Host smart-5cbfdcde-b45d-4d3b-959d-8aebba1ddb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797995561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.2797995561
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.653022964
Short name T494
Test name
Test status
Simulation time 58092547944 ps
CPU time 108.01 seconds
Started May 02 02:26:02 PM PDT 24
Finished May 02 02:28:04 PM PDT 24
Peak memory 200536 kb
Host smart-8a5a5c08-35bd-4308-b22f-851a19d00795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653022964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.653022964
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.1104635978
Short name T723
Test name
Test status
Simulation time 5253437641 ps
CPU time 80.86 seconds
Started May 02 02:26:04 PM PDT 24
Finished May 02 02:27:40 PM PDT 24
Peak memory 200408 kb
Host smart-4c7d421e-1cf7-4ca4-8712-03a247095ec9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1104635978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1104635978
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.3845098299
Short name T911
Test name
Test status
Simulation time 4212450570 ps
CPU time 2.93 seconds
Started May 02 02:26:02 PM PDT 24
Finished May 02 02:26:20 PM PDT 24
Peak memory 198420 kb
Host smart-809a5e19-ec6f-497c-a530-0054c3e9546d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3845098299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3845098299
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.2547611185
Short name T366
Test name
Test status
Simulation time 78551742289 ps
CPU time 69.41 seconds
Started May 02 02:25:59 PM PDT 24
Finished May 02 02:27:23 PM PDT 24
Peak memory 200344 kb
Host smart-3d682dc3-20d3-4149-9665-ad04da24e552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547611185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.2547611185
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.154553010
Short name T1103
Test name
Test status
Simulation time 4298484526 ps
CPU time 3.56 seconds
Started May 02 02:26:01 PM PDT 24
Finished May 02 02:26:19 PM PDT 24
Peak memory 196432 kb
Host smart-347490ac-0713-44db-b019-7420dee0320c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154553010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.154553010
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.4239146790
Short name T438
Test name
Test status
Simulation time 6091901614 ps
CPU time 8.98 seconds
Started May 02 02:26:00 PM PDT 24
Finished May 02 02:26:23 PM PDT 24
Peak memory 200348 kb
Host smart-9dacc80c-9a75-4ad2-96a3-33b85e559d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239146790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.4239146790
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.2744157769
Short name T1119
Test name
Test status
Simulation time 642271466 ps
CPU time 2.36 seconds
Started May 02 02:26:01 PM PDT 24
Finished May 02 02:26:18 PM PDT 24
Peak memory 199208 kb
Host smart-4ad3fcec-9868-43ed-b7dc-515dc8874384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744157769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.2744157769
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.3369481926
Short name T726
Test name
Test status
Simulation time 44648508728 ps
CPU time 72.47 seconds
Started May 02 02:26:03 PM PDT 24
Finished May 02 02:27:30 PM PDT 24
Peak memory 200392 kb
Host smart-363dab7b-095c-45a9-90e9-24460d143724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369481926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.3369481926
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.1713040110
Short name T241
Test name
Test status
Simulation time 61162530967 ps
CPU time 36.39 seconds
Started May 02 02:32:35 PM PDT 24
Finished May 02 02:33:13 PM PDT 24
Peak memory 200356 kb
Host smart-74a11d2c-c424-4e4d-a884-fe04dfcca4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713040110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.1713040110
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.4023997093
Short name T655
Test name
Test status
Simulation time 91213639607 ps
CPU time 50.7 seconds
Started May 02 02:32:34 PM PDT 24
Finished May 02 02:33:27 PM PDT 24
Peak memory 200420 kb
Host smart-e503e6ad-d1c8-4678-a65e-ca179e18c890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023997093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.4023997093
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.1045243881
Short name T467
Test name
Test status
Simulation time 204459862482 ps
CPU time 85.54 seconds
Started May 02 02:32:32 PM PDT 24
Finished May 02 02:34:00 PM PDT 24
Peak memory 200456 kb
Host smart-20f0f681-1173-47d9-bf80-6fbf9da448dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045243881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.1045243881
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.3559124126
Short name T1059
Test name
Test status
Simulation time 170714561187 ps
CPU time 32.93 seconds
Started May 02 02:32:38 PM PDT 24
Finished May 02 02:33:12 PM PDT 24
Peak memory 200392 kb
Host smart-cd874888-2319-4930-a654-76d51b224b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559124126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.3559124126
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.407708319
Short name T603
Test name
Test status
Simulation time 80325972251 ps
CPU time 32.13 seconds
Started May 02 02:32:36 PM PDT 24
Finished May 02 02:33:10 PM PDT 24
Peak memory 200168 kb
Host smart-3eb42da7-6164-408d-8c30-f39f5480e64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407708319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.407708319
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.604801993
Short name T220
Test name
Test status
Simulation time 59705729841 ps
CPU time 30.22 seconds
Started May 02 02:32:33 PM PDT 24
Finished May 02 02:33:06 PM PDT 24
Peak memory 200396 kb
Host smart-b4c1d1c7-c476-48e5-9f30-17fe788faa39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604801993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.604801993
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.3877274545
Short name T207
Test name
Test status
Simulation time 51963512198 ps
CPU time 90.78 seconds
Started May 02 02:32:33 PM PDT 24
Finished May 02 02:34:06 PM PDT 24
Peak memory 200284 kb
Host smart-04bf9dd0-b6b0-4e55-8c05-08a6ef610943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877274545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.3877274545
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.4022683953
Short name T628
Test name
Test status
Simulation time 29016570151 ps
CPU time 13.65 seconds
Started May 02 02:32:36 PM PDT 24
Finished May 02 02:32:52 PM PDT 24
Peak memory 199372 kb
Host smart-2c0e0d4b-58c6-4abd-9778-1c1010dddef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022683953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.4022683953
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.3923322675
Short name T227
Test name
Test status
Simulation time 120731238655 ps
CPU time 167.86 seconds
Started May 02 02:32:36 PM PDT 24
Finished May 02 02:35:25 PM PDT 24
Peak memory 200380 kb
Host smart-d600ce50-7040-4bdb-b47f-72b7bff453f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923322675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.3923322675
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.961430933
Short name T887
Test name
Test status
Simulation time 36505706 ps
CPU time 0.54 seconds
Started May 02 02:26:10 PM PDT 24
Finished May 02 02:26:25 PM PDT 24
Peak memory 195284 kb
Host smart-e6fbd7ec-8723-4a44-990d-5f09f3945707
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961430933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.961430933
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.212383089
Short name T154
Test name
Test status
Simulation time 24001950318 ps
CPU time 10.62 seconds
Started May 02 02:26:00 PM PDT 24
Finished May 02 02:26:24 PM PDT 24
Peak memory 200320 kb
Host smart-a77c1937-bf04-4335-931d-cc814e8d40fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212383089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.212383089
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.2071646997
Short name T137
Test name
Test status
Simulation time 24400553406 ps
CPU time 57.42 seconds
Started May 02 02:25:59 PM PDT 24
Finished May 02 02:27:10 PM PDT 24
Peak memory 200360 kb
Host smart-13397599-663c-4434-a3a6-9bfe982f0425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071646997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2071646997
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.2979502663
Short name T419
Test name
Test status
Simulation time 111705870410 ps
CPU time 403.11 seconds
Started May 02 02:26:02 PM PDT 24
Finished May 02 02:32:59 PM PDT 24
Peak memory 200444 kb
Host smart-0dd71a2b-92b4-4b5f-b807-37777663c23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979502663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.2979502663
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.3187394883
Short name T973
Test name
Test status
Simulation time 18323749160 ps
CPU time 17.18 seconds
Started May 02 02:26:02 PM PDT 24
Finished May 02 02:26:34 PM PDT 24
Peak memory 200364 kb
Host smart-0e092a9b-888f-459b-9973-a427e785a71f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187394883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.3187394883
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.88024809
Short name T370
Test name
Test status
Simulation time 136024179436 ps
CPU time 336.86 seconds
Started May 02 02:26:11 PM PDT 24
Finished May 02 02:32:02 PM PDT 24
Peak memory 200416 kb
Host smart-fc192a2f-b46d-474d-b536-766f70b51f35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=88024809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.88024809
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.717989345
Short name T953
Test name
Test status
Simulation time 5004063434 ps
CPU time 3.09 seconds
Started May 02 02:26:12 PM PDT 24
Finished May 02 02:26:29 PM PDT 24
Peak memory 200232 kb
Host smart-18637b98-7a32-4c81-a0e5-a193695728a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717989345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.717989345
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.1405121450
Short name T881
Test name
Test status
Simulation time 50960873505 ps
CPU time 82.42 seconds
Started May 02 02:26:00 PM PDT 24
Finished May 02 02:27:37 PM PDT 24
Peak memory 200596 kb
Host smart-20274ea5-714b-4aa0-86c1-701007b76986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405121450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.1405121450
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.4028789330
Short name T980
Test name
Test status
Simulation time 19850645700 ps
CPU time 450.62 seconds
Started May 02 02:26:10 PM PDT 24
Finished May 02 02:33:55 PM PDT 24
Peak memory 200396 kb
Host smart-e6ed4650-5712-4890-8b04-2a13b9d9eb52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4028789330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.4028789330
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.487627094
Short name T847
Test name
Test status
Simulation time 1508619605 ps
CPU time 1.88 seconds
Started May 02 02:26:00 PM PDT 24
Finished May 02 02:26:16 PM PDT 24
Peak memory 197656 kb
Host smart-c6124d4d-577e-4954-8f71-8f403a49f728
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=487627094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.487627094
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.3104095507
Short name T1049
Test name
Test status
Simulation time 157779818561 ps
CPU time 41.33 seconds
Started May 02 02:26:14 PM PDT 24
Finished May 02 02:27:08 PM PDT 24
Peak memory 200428 kb
Host smart-0fddeaeb-c16f-40ee-8034-8146370a8d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104095507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.3104095507
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.950486701
Short name T1110
Test name
Test status
Simulation time 45752333136 ps
CPU time 7.83 seconds
Started May 02 02:26:11 PM PDT 24
Finished May 02 02:26:33 PM PDT 24
Peak memory 196148 kb
Host smart-41ce5071-7d2e-452c-a3db-10ee2b64004f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950486701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.950486701
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.4028630945
Short name T449
Test name
Test status
Simulation time 108998509 ps
CPU time 1.04 seconds
Started May 02 02:26:01 PM PDT 24
Finished May 02 02:26:17 PM PDT 24
Peak memory 199028 kb
Host smart-00273b51-3bcb-4825-9c7a-e7471a69adf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028630945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.4028630945
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.84774595
Short name T611
Test name
Test status
Simulation time 1416681022 ps
CPU time 3.04 seconds
Started May 02 02:26:13 PM PDT 24
Finished May 02 02:26:30 PM PDT 24
Peak memory 200256 kb
Host smart-e48089a2-0914-4cd0-bb5d-b55d612cdf6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84774595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.84774595
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.2242496651
Short name T16
Test name
Test status
Simulation time 999484787 ps
CPU time 3.15 seconds
Started May 02 02:26:10 PM PDT 24
Finished May 02 02:26:28 PM PDT 24
Peak memory 200320 kb
Host smart-3d20035c-82ee-4169-9eec-2c1da79a8bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242496651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.2242496651
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.1824471173
Short name T815
Test name
Test status
Simulation time 51773415480 ps
CPU time 94.46 seconds
Started May 02 02:26:02 PM PDT 24
Finished May 02 02:27:52 PM PDT 24
Peak memory 200392 kb
Host smart-36fdb5ae-58f6-4458-8bc1-c121977eec9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824471173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.1824471173
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.1554294017
Short name T369
Test name
Test status
Simulation time 15146380299 ps
CPU time 15.17 seconds
Started May 02 02:32:42 PM PDT 24
Finished May 02 02:32:59 PM PDT 24
Peak memory 200428 kb
Host smart-e900117e-663c-4e6b-94b1-3fa49cc2e9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554294017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.1554294017
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.1977985550
Short name T222
Test name
Test status
Simulation time 17970537251 ps
CPU time 8.42 seconds
Started May 02 02:32:40 PM PDT 24
Finished May 02 02:32:50 PM PDT 24
Peak memory 200452 kb
Host smart-ffc20333-c817-4d4c-9d3c-95a041656762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977985550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.1977985550
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.2713794892
Short name T424
Test name
Test status
Simulation time 18021417759 ps
CPU time 20.39 seconds
Started May 02 02:32:45 PM PDT 24
Finished May 02 02:33:07 PM PDT 24
Peak memory 200428 kb
Host smart-a8656fd2-535c-48ef-88b4-f1a4a59c711d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713794892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.2713794892
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.4163296091
Short name T814
Test name
Test status
Simulation time 40722397890 ps
CPU time 20.62 seconds
Started May 02 02:32:43 PM PDT 24
Finished May 02 02:33:05 PM PDT 24
Peak memory 200336 kb
Host smart-403b7ba6-e22d-469d-8984-2441933c3df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163296091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.4163296091
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.2347091035
Short name T1180
Test name
Test status
Simulation time 6869338569 ps
CPU time 10.64 seconds
Started May 02 02:32:44 PM PDT 24
Finished May 02 02:32:56 PM PDT 24
Peak memory 200288 kb
Host smart-b234d4f7-c519-4ed4-a1e6-393e640f6f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347091035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.2347091035
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.3585822233
Short name T1088
Test name
Test status
Simulation time 59825670429 ps
CPU time 9.6 seconds
Started May 02 02:32:41 PM PDT 24
Finished May 02 02:32:52 PM PDT 24
Peak memory 200376 kb
Host smart-0d7c5fc1-bda5-4d9a-a4f7-51ef19728f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585822233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.3585822233
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.4176351987
Short name T877
Test name
Test status
Simulation time 14780760675 ps
CPU time 11.72 seconds
Started May 02 02:32:42 PM PDT 24
Finished May 02 02:32:55 PM PDT 24
Peak memory 200432 kb
Host smart-a7f48030-2446-474c-9029-75cf1b8c8611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176351987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.4176351987
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.116641555
Short name T551
Test name
Test status
Simulation time 13282305 ps
CPU time 0.54 seconds
Started May 02 02:26:19 PM PDT 24
Finished May 02 02:26:31 PM PDT 24
Peak memory 195796 kb
Host smart-b3281a08-9b09-4351-b2de-532be9a16caf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116641555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.116641555
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.1164723780
Short name T143
Test name
Test status
Simulation time 32901884914 ps
CPU time 12.35 seconds
Started May 02 02:26:11 PM PDT 24
Finished May 02 02:26:37 PM PDT 24
Peak memory 200408 kb
Host smart-67e0d18b-6f6d-44f4-b977-e23daf63b1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164723780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1164723780
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.1660132634
Short name T841
Test name
Test status
Simulation time 8358004989 ps
CPU time 13.59 seconds
Started May 02 02:26:11 PM PDT 24
Finished May 02 02:26:39 PM PDT 24
Peak memory 199776 kb
Host smart-896821c9-31c8-49fd-a715-c664f610797b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660132634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.1660132634
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.2164039531
Short name T164
Test name
Test status
Simulation time 8712402837 ps
CPU time 14.13 seconds
Started May 02 02:26:11 PM PDT 24
Finished May 02 02:26:39 PM PDT 24
Peak memory 200348 kb
Host smart-6b2c0d9d-57f7-49f8-b032-0676e916d61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164039531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.2164039531
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.3912629303
Short name T706
Test name
Test status
Simulation time 75879120725 ps
CPU time 35.61 seconds
Started May 02 02:26:11 PM PDT 24
Finished May 02 02:27:01 PM PDT 24
Peak memory 200188 kb
Host smart-719dd96c-a712-4ba7-b089-620667bcdee3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912629303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.3912629303
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.509795365
Short name T457
Test name
Test status
Simulation time 106998703135 ps
CPU time 405.65 seconds
Started May 02 02:26:16 PM PDT 24
Finished May 02 02:33:14 PM PDT 24
Peak memory 200420 kb
Host smart-4ccd01f0-b7ea-4b47-bb5d-fa6c364708fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=509795365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.509795365
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.2025474078
Short name T605
Test name
Test status
Simulation time 7808047563 ps
CPU time 17.19 seconds
Started May 02 02:26:10 PM PDT 24
Finished May 02 02:26:42 PM PDT 24
Peak memory 200416 kb
Host smart-2e66c16c-1288-49a0-8fcc-e2d4e731aaa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025474078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.2025474078
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.1123653646
Short name T1102
Test name
Test status
Simulation time 134802764028 ps
CPU time 304.23 seconds
Started May 02 02:26:11 PM PDT 24
Finished May 02 02:31:29 PM PDT 24
Peak memory 200604 kb
Host smart-e445701e-0142-4cdf-9dbf-d9c2b916642d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123653646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.1123653646
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.140747005
Short name T676
Test name
Test status
Simulation time 13633583883 ps
CPU time 609.69 seconds
Started May 02 02:26:13 PM PDT 24
Finished May 02 02:36:36 PM PDT 24
Peak memory 200424 kb
Host smart-37283867-2bc6-400b-87f9-33acec265223
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=140747005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.140747005
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.3311907215
Short name T322
Test name
Test status
Simulation time 3494849241 ps
CPU time 6.01 seconds
Started May 02 02:26:10 PM PDT 24
Finished May 02 02:26:30 PM PDT 24
Peak memory 198744 kb
Host smart-cf369556-3403-4254-99b5-593e38c3274b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3311907215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.3311907215
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.1184496492
Short name T556
Test name
Test status
Simulation time 25370895277 ps
CPU time 44.59 seconds
Started May 02 02:26:10 PM PDT 24
Finished May 02 02:27:09 PM PDT 24
Peak memory 196704 kb
Host smart-8d3030b0-73d3-43a8-87d2-a56f51a3770c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184496492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.1184496492
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.3746356583
Short name T987
Test name
Test status
Simulation time 651858734 ps
CPU time 2.99 seconds
Started May 02 02:26:12 PM PDT 24
Finished May 02 02:26:29 PM PDT 24
Peak memory 198716 kb
Host smart-52c5c38f-bb42-458f-a00b-c0e3b56a3063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746356583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.3746356583
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.3378057072
Short name T236
Test name
Test status
Simulation time 223441165818 ps
CPU time 135.02 seconds
Started May 02 02:26:15 PM PDT 24
Finished May 02 02:28:43 PM PDT 24
Peak memory 216800 kb
Host smart-0bc64d2a-3114-4a0b-b5af-d2f6f29e368b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378057072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.3378057072
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.3963485638
Short name T47
Test name
Test status
Simulation time 91493778529 ps
CPU time 627.91 seconds
Started May 02 02:26:21 PM PDT 24
Finished May 02 02:37:00 PM PDT 24
Peak memory 216860 kb
Host smart-2e592719-1e8b-4a1f-b4c8-0ad1ea6714ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963485638 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.3963485638
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.3029798978
Short name T674
Test name
Test status
Simulation time 1120918402 ps
CPU time 3.56 seconds
Started May 02 02:26:14 PM PDT 24
Finished May 02 02:26:31 PM PDT 24
Peak memory 199840 kb
Host smart-78a1bd66-3986-45ab-b5c6-a951db1ba59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029798978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.3029798978
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.1815876588
Short name T274
Test name
Test status
Simulation time 64754724500 ps
CPU time 109.82 seconds
Started May 02 02:26:11 PM PDT 24
Finished May 02 02:28:15 PM PDT 24
Peak memory 200424 kb
Host smart-f067f969-b229-45d0-a531-9ac729009945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815876588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.1815876588
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.948372228
Short name T718
Test name
Test status
Simulation time 24933459470 ps
CPU time 18.86 seconds
Started May 02 02:32:42 PM PDT 24
Finished May 02 02:33:02 PM PDT 24
Peak memory 200420 kb
Host smart-a9e11a6c-889e-42f0-b5b8-c01856ccd2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948372228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.948372228
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.2344199962
Short name T1047
Test name
Test status
Simulation time 143499649290 ps
CPU time 227 seconds
Started May 02 02:32:42 PM PDT 24
Finished May 02 02:36:30 PM PDT 24
Peak memory 200404 kb
Host smart-be8090b7-5f5d-4059-ac4e-b73f33b93a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344199962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.2344199962
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.3322857448
Short name T933
Test name
Test status
Simulation time 126569363919 ps
CPU time 51.75 seconds
Started May 02 02:32:50 PM PDT 24
Finished May 02 02:33:42 PM PDT 24
Peak memory 200380 kb
Host smart-c7ae94ec-391d-444a-b260-40acf85cbd08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322857448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.3322857448
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.2214331010
Short name T1087
Test name
Test status
Simulation time 82619740838 ps
CPU time 27.3 seconds
Started May 02 02:32:50 PM PDT 24
Finished May 02 02:33:19 PM PDT 24
Peak memory 200432 kb
Host smart-40cb2bea-b966-45e2-977f-032a4d11489f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214331010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.2214331010
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.4115049901
Short name T211
Test name
Test status
Simulation time 142448055488 ps
CPU time 54.37 seconds
Started May 02 02:32:51 PM PDT 24
Finished May 02 02:33:46 PM PDT 24
Peak memory 200472 kb
Host smart-213209bc-941f-4b82-ba63-d974a2866289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115049901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.4115049901
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.3856165576
Short name T920
Test name
Test status
Simulation time 169803993639 ps
CPU time 183.54 seconds
Started May 02 02:32:50 PM PDT 24
Finished May 02 02:35:55 PM PDT 24
Peak memory 200440 kb
Host smart-aedb6797-9d76-401a-b2cb-4a50bd04229a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856165576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.3856165576
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.253850046
Short name T921
Test name
Test status
Simulation time 159113671689 ps
CPU time 72.1 seconds
Started May 02 02:32:48 PM PDT 24
Finished May 02 02:34:01 PM PDT 24
Peak memory 200388 kb
Host smart-b5065057-a91d-4293-b26c-1b1b9eca5c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253850046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.253850046
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.3468966831
Short name T1025
Test name
Test status
Simulation time 116072354893 ps
CPU time 52.13 seconds
Started May 02 02:32:58 PM PDT 24
Finished May 02 02:33:52 PM PDT 24
Peak memory 200364 kb
Host smart-1ea9a70b-e29e-4bec-be91-e7b041ea76ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468966831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.3468966831
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.1226542541
Short name T917
Test name
Test status
Simulation time 17471432 ps
CPU time 0.54 seconds
Started May 02 02:26:21 PM PDT 24
Finished May 02 02:26:33 PM PDT 24
Peak memory 195796 kb
Host smart-c159ccee-d6bb-4b57-ab4b-c497e3d5e9fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226542541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.1226542541
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.3256463824
Short name T1008
Test name
Test status
Simulation time 39159755309 ps
CPU time 66.24 seconds
Started May 02 02:26:20 PM PDT 24
Finished May 02 02:27:37 PM PDT 24
Peak memory 200424 kb
Host smart-ef7f04fa-6498-4a7c-a0b6-0c6794b010a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256463824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3256463824
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.1496172362
Short name T134
Test name
Test status
Simulation time 36983513227 ps
CPU time 28.29 seconds
Started May 02 02:26:20 PM PDT 24
Finished May 02 02:26:59 PM PDT 24
Peak memory 200388 kb
Host smart-3d0c9c82-2527-4d37-b3d3-5d1755294c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496172362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.1496172362
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_intr.4253650692
Short name T458
Test name
Test status
Simulation time 83714937977 ps
CPU time 42.21 seconds
Started May 02 02:26:18 PM PDT 24
Finished May 02 02:27:12 PM PDT 24
Peak memory 200412 kb
Host smart-e4189dfc-3a32-4b00-9ad4-e7d441b8f718
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253650692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.4253650692
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.3844016583
Short name T344
Test name
Test status
Simulation time 203133918238 ps
CPU time 1529.2 seconds
Started May 02 02:26:24 PM PDT 24
Finished May 02 02:52:03 PM PDT 24
Peak memory 200424 kb
Host smart-4e349122-b4c0-4acf-ab35-4800b8c42508
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3844016583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.3844016583
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.2997458033
Short name T736
Test name
Test status
Simulation time 4922230896 ps
CPU time 10.65 seconds
Started May 02 02:26:17 PM PDT 24
Finished May 02 02:26:40 PM PDT 24
Peak memory 199528 kb
Host smart-4701a78a-2f9c-4b8e-8eb5-9a6e814d393e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997458033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2997458033
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.3616681335
Short name T263
Test name
Test status
Simulation time 113040257837 ps
CPU time 133.75 seconds
Started May 02 02:26:22 PM PDT 24
Finished May 02 02:28:46 PM PDT 24
Peak memory 199384 kb
Host smart-7bef89f0-4f1b-4d0a-a2ab-e5f709f55c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616681335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.3616681335
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.476143826
Short name T1183
Test name
Test status
Simulation time 34762083933 ps
CPU time 445.34 seconds
Started May 02 02:26:21 PM PDT 24
Finished May 02 02:33:57 PM PDT 24
Peak memory 200444 kb
Host smart-9741b0ec-4db6-49a2-a536-4d95dd1ed32c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=476143826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.476143826
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.2956367733
Short name T929
Test name
Test status
Simulation time 2977945790 ps
CPU time 1.96 seconds
Started May 02 02:26:22 PM PDT 24
Finished May 02 02:26:34 PM PDT 24
Peak memory 198564 kb
Host smart-3c67a630-2b84-4011-a09d-b0a91d8285ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2956367733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.2956367733
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.630064823
Short name T1135
Test name
Test status
Simulation time 151289279216 ps
CPU time 62.97 seconds
Started May 02 02:26:16 PM PDT 24
Finished May 02 02:27:31 PM PDT 24
Peak memory 200060 kb
Host smart-ed810436-548a-4fa2-a0d2-69d66f1409b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630064823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.630064823
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.2596682978
Short name T325
Test name
Test status
Simulation time 4027935103 ps
CPU time 2.18 seconds
Started May 02 02:26:18 PM PDT 24
Finished May 02 02:26:32 PM PDT 24
Peak memory 196740 kb
Host smart-7510ed11-a84c-4a16-827c-10456d9529a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596682978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.2596682978
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.760609210
Short name T630
Test name
Test status
Simulation time 5877059535 ps
CPU time 10.56 seconds
Started May 02 02:26:17 PM PDT 24
Finished May 02 02:26:40 PM PDT 24
Peak memory 200372 kb
Host smart-2e88513d-237a-4b42-9972-24897b179fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760609210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.760609210
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.1816110280
Short name T928
Test name
Test status
Simulation time 77894984814 ps
CPU time 20.97 seconds
Started May 02 02:26:23 PM PDT 24
Finished May 02 02:26:54 PM PDT 24
Peak memory 200352 kb
Host smart-86ec6baa-f13e-48cc-b9a3-fa4fa83c2bf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816110280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.1816110280
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.1864977255
Short name T722
Test name
Test status
Simulation time 1481358238 ps
CPU time 2.37 seconds
Started May 02 02:26:16 PM PDT 24
Finished May 02 02:26:31 PM PDT 24
Peak memory 199468 kb
Host smart-c4d3ace1-d4f3-46de-bd8f-4082a986516a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864977255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.1864977255
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.2496568534
Short name T1131
Test name
Test status
Simulation time 70292076575 ps
CPU time 35.75 seconds
Started May 02 02:26:17 PM PDT 24
Finished May 02 02:27:05 PM PDT 24
Peak memory 200436 kb
Host smart-c0052833-9c8e-4960-a0ba-f85fadc04452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496568534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.2496568534
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.411196121
Short name T804
Test name
Test status
Simulation time 127640660768 ps
CPU time 90.12 seconds
Started May 02 02:32:58 PM PDT 24
Finished May 02 02:34:30 PM PDT 24
Peak memory 200380 kb
Host smart-e1327938-9f2a-4609-a1be-4a115f5195c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411196121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.411196121
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.88360706
Short name T1092
Test name
Test status
Simulation time 288407881873 ps
CPU time 119.61 seconds
Started May 02 02:32:59 PM PDT 24
Finished May 02 02:35:00 PM PDT 24
Peak memory 200372 kb
Host smart-017343cd-1bb4-4d39-932f-5f0d07b65b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88360706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.88360706
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.1979257133
Short name T982
Test name
Test status
Simulation time 76227192592 ps
CPU time 39.44 seconds
Started May 02 02:32:56 PM PDT 24
Finished May 02 02:33:36 PM PDT 24
Peak memory 200308 kb
Host smart-15fc9b4d-48d5-4758-90fb-e31db0f4ab3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979257133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1979257133
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.519839041
Short name T189
Test name
Test status
Simulation time 30160523909 ps
CPU time 27.93 seconds
Started May 02 02:32:57 PM PDT 24
Finished May 02 02:33:26 PM PDT 24
Peak memory 200364 kb
Host smart-5bc80c5f-1204-4f97-b7fc-40a0c9a0a950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519839041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.519839041
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.2514710177
Short name T197
Test name
Test status
Simulation time 179026975617 ps
CPU time 73.35 seconds
Started May 02 02:32:57 PM PDT 24
Finished May 02 02:34:11 PM PDT 24
Peak memory 200400 kb
Host smart-d5957393-d2ad-4d74-961c-9a42cefd330e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514710177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.2514710177
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.610200927
Short name T1063
Test name
Test status
Simulation time 10136450889 ps
CPU time 5.82 seconds
Started May 02 02:32:57 PM PDT 24
Finished May 02 02:33:04 PM PDT 24
Peak memory 200376 kb
Host smart-d3d0226d-e41f-4c48-ae2a-2f53d6286fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610200927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.610200927
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.3033084781
Short name T1175
Test name
Test status
Simulation time 16246816804 ps
CPU time 6.08 seconds
Started May 02 02:32:57 PM PDT 24
Finished May 02 02:33:04 PM PDT 24
Peak memory 200112 kb
Host smart-4375a5ca-4f04-4acb-a7a2-8d5889558db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033084781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.3033084781
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.1075812839
Short name T672
Test name
Test status
Simulation time 24074902 ps
CPU time 0.56 seconds
Started May 02 02:26:32 PM PDT 24
Finished May 02 02:26:38 PM PDT 24
Peak memory 195760 kb
Host smart-fda9e287-2154-417c-996d-93b8ed2da6a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075812839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.1075812839
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.1274668221
Short name T1001
Test name
Test status
Simulation time 112371541717 ps
CPU time 39.97 seconds
Started May 02 02:26:24 PM PDT 24
Finished May 02 02:27:14 PM PDT 24
Peak memory 200312 kb
Host smart-79f77bb4-89e2-4de2-9d57-07a0003b492b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274668221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.1274668221
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.774704790
Short name T976
Test name
Test status
Simulation time 19147919698 ps
CPU time 41.79 seconds
Started May 02 02:26:22 PM PDT 24
Finished May 02 02:27:15 PM PDT 24
Peak memory 200360 kb
Host smart-f0a64598-b63a-4cd6-9309-763ef7b66028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774704790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.774704790
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.105243008
Short name T1073
Test name
Test status
Simulation time 21084848560 ps
CPU time 37.14 seconds
Started May 02 02:26:22 PM PDT 24
Finished May 02 02:27:09 PM PDT 24
Peak memory 200100 kb
Host smart-6711121e-2fe3-4108-989c-e642b8e9b73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105243008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.105243008
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.3137936438
Short name T542
Test name
Test status
Simulation time 25229076280 ps
CPU time 44.3 seconds
Started May 02 02:26:20 PM PDT 24
Finished May 02 02:27:16 PM PDT 24
Peak memory 200280 kb
Host smart-5bc42999-df6d-4615-8391-11b013a310cc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137936438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.3137936438
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.3641208155
Short name T844
Test name
Test status
Simulation time 37128573181 ps
CPU time 166.84 seconds
Started May 02 02:26:30 PM PDT 24
Finished May 02 02:29:23 PM PDT 24
Peak memory 200400 kb
Host smart-76bbf565-0d79-4c8e-9f1a-ca1416a9d29a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3641208155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.3641208155
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.1235169476
Short name T394
Test name
Test status
Simulation time 9457053387 ps
CPU time 6.31 seconds
Started May 02 02:26:21 PM PDT 24
Finished May 02 02:26:38 PM PDT 24
Peak memory 199740 kb
Host smart-5f2d37b0-e86a-4293-b67f-f67471e92e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235169476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.1235169476
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.3341371342
Short name T39
Test name
Test status
Simulation time 28723167588 ps
CPU time 45.92 seconds
Started May 02 02:26:22 PM PDT 24
Finished May 02 02:27:18 PM PDT 24
Peak memory 200112 kb
Host smart-4e6bd22f-0c6a-4888-b876-92ec748f92da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341371342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.3341371342
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.3128599272
Short name T376
Test name
Test status
Simulation time 13045727186 ps
CPU time 363.83 seconds
Started May 02 02:26:22 PM PDT 24
Finished May 02 02:32:36 PM PDT 24
Peak memory 200404 kb
Host smart-66575d3b-9551-43ee-b64b-e1b2a113e9d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3128599272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3128599272
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.3689231869
Short name T334
Test name
Test status
Simulation time 6623028756 ps
CPU time 21.62 seconds
Started May 02 02:26:22 PM PDT 24
Finished May 02 02:26:54 PM PDT 24
Peak memory 200380 kb
Host smart-596f9683-d61c-4576-8be3-8f02785e365e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3689231869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.3689231869
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.2506111791
Short name T1024
Test name
Test status
Simulation time 30657252664 ps
CPU time 46.58 seconds
Started May 02 02:26:22 PM PDT 24
Finished May 02 02:27:19 PM PDT 24
Peak memory 200352 kb
Host smart-4aa3c130-ddd6-482d-a155-a442b4ece226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506111791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.2506111791
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.3783254968
Short name T340
Test name
Test status
Simulation time 3104009921 ps
CPU time 0.87 seconds
Started May 02 02:26:24 PM PDT 24
Finished May 02 02:26:35 PM PDT 24
Peak memory 196188 kb
Host smart-f96c0ad6-58d9-4ed6-aaa8-6215aef973be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783254968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.3783254968
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.3558668449
Short name T509
Test name
Test status
Simulation time 873444615 ps
CPU time 2.32 seconds
Started May 02 02:26:23 PM PDT 24
Finished May 02 02:26:35 PM PDT 24
Peak memory 199668 kb
Host smart-e201dbe9-36c6-43b2-aaa0-525b45f98179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558668449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.3558668449
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.3257615019
Short name T671
Test name
Test status
Simulation time 284943444045 ps
CPU time 212.84 seconds
Started May 02 02:26:31 PM PDT 24
Finished May 02 02:30:10 PM PDT 24
Peak memory 208736 kb
Host smart-e3581ada-92a9-488c-849d-6689eaac10c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257615019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.3257615019
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.1457376981
Short name T667
Test name
Test status
Simulation time 1820671358 ps
CPU time 1.74 seconds
Started May 02 02:26:21 PM PDT 24
Finished May 02 02:26:33 PM PDT 24
Peak memory 199064 kb
Host smart-850bd73b-8aa2-4e95-b6ac-f5b756fd2d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457376981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.1457376981
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.33839314
Short name T1124
Test name
Test status
Simulation time 54074116907 ps
CPU time 42.14 seconds
Started May 02 02:26:23 PM PDT 24
Finished May 02 02:27:15 PM PDT 24
Peak memory 200420 kb
Host smart-17e591ee-87c4-41ae-b9bf-a907bedd4f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33839314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.33839314
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.836991554
Short name T1159
Test name
Test status
Simulation time 71825616653 ps
CPU time 11.08 seconds
Started May 02 02:33:07 PM PDT 24
Finished May 02 02:33:19 PM PDT 24
Peak memory 200320 kb
Host smart-76e2240e-b491-4a1f-9671-25baff84cfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836991554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.836991554
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.769481288
Short name T224
Test name
Test status
Simulation time 194018645956 ps
CPU time 35.62 seconds
Started May 02 02:33:05 PM PDT 24
Finished May 02 02:33:42 PM PDT 24
Peak memory 200428 kb
Host smart-a1a49d1e-03be-4913-bd63-d781ccdddc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769481288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.769481288
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.417436774
Short name T863
Test name
Test status
Simulation time 38525904950 ps
CPU time 38.52 seconds
Started May 02 02:33:06 PM PDT 24
Finished May 02 02:33:46 PM PDT 24
Peak memory 200284 kb
Host smart-66730dfd-5739-44b3-9457-582f77e5cc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417436774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.417436774
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.4233774999
Short name T198
Test name
Test status
Simulation time 111465965775 ps
CPU time 197.98 seconds
Started May 02 02:33:05 PM PDT 24
Finished May 02 02:36:24 PM PDT 24
Peak memory 200416 kb
Host smart-245d939e-15b7-4ff4-88f2-90867fe6317f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233774999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.4233774999
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.906077810
Short name T1172
Test name
Test status
Simulation time 125735756391 ps
CPU time 27.93 seconds
Started May 02 02:33:06 PM PDT 24
Finished May 02 02:33:35 PM PDT 24
Peak memory 200424 kb
Host smart-b104afc6-e94f-4a45-a068-cb39a07ef9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906077810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.906077810
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.3675109875
Short name T589
Test name
Test status
Simulation time 64771087931 ps
CPU time 15.53 seconds
Started May 02 02:33:05 PM PDT 24
Finished May 02 02:33:23 PM PDT 24
Peak memory 200352 kb
Host smart-00d5dac3-83bc-4fd7-be07-d94b4d6c1207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675109875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3675109875
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.147105827
Short name T658
Test name
Test status
Simulation time 153396159628 ps
CPU time 59.67 seconds
Started May 02 02:33:06 PM PDT 24
Finished May 02 02:34:08 PM PDT 24
Peak memory 200368 kb
Host smart-e50ea3ca-6b19-443c-8084-912986f98431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147105827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.147105827
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.1692473280
Short name T721
Test name
Test status
Simulation time 105934169386 ps
CPU time 194.35 seconds
Started May 02 02:33:06 PM PDT 24
Finished May 02 02:36:22 PM PDT 24
Peak memory 200352 kb
Host smart-026538ab-130f-4bf9-af42-3d3004beb515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692473280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.1692473280
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.1924826649
Short name T271
Test name
Test status
Simulation time 105832777980 ps
CPU time 198.36 seconds
Started May 02 02:33:13 PM PDT 24
Finished May 02 02:36:33 PM PDT 24
Peak memory 200324 kb
Host smart-c96d4aac-175e-4152-8000-0cddad4916e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924826649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.1924826649
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.3692664541
Short name T379
Test name
Test status
Simulation time 23885416 ps
CPU time 0.57 seconds
Started May 02 02:24:38 PM PDT 24
Finished May 02 02:24:43 PM PDT 24
Peak memory 195788 kb
Host smart-ec1127dc-8fc9-4382-aaff-4be8086e8f7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692664541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.3692664541
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.1652033152
Short name T632
Test name
Test status
Simulation time 34595491734 ps
CPU time 16.32 seconds
Started May 02 02:24:34 PM PDT 24
Finished May 02 02:24:54 PM PDT 24
Peak memory 200432 kb
Host smart-67e6a91a-24c2-4f87-905a-5e0272e514ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652033152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.1652033152
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.3115195438
Short name T500
Test name
Test status
Simulation time 132020936921 ps
CPU time 12.03 seconds
Started May 02 02:24:40 PM PDT 24
Finished May 02 02:24:56 PM PDT 24
Peak memory 200436 kb
Host smart-255bf303-ea81-4fac-9089-ca361f9ce3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115195438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3115195438
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.3839340308
Short name T163
Test name
Test status
Simulation time 380619178337 ps
CPU time 35.13 seconds
Started May 02 02:24:40 PM PDT 24
Finished May 02 02:25:20 PM PDT 24
Peak memory 200340 kb
Host smart-a4736330-05ce-4c9f-bb98-77b8a41c722f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839340308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.3839340308
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.4084232231
Short name T904
Test name
Test status
Simulation time 35055580518 ps
CPU time 33.14 seconds
Started May 02 02:24:39 PM PDT 24
Finished May 02 02:25:17 PM PDT 24
Peak memory 200380 kb
Host smart-29d28e50-2d0d-4402-a8a3-43a518b6bcb7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084232231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.4084232231
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.3006505105
Short name T1022
Test name
Test status
Simulation time 154453797650 ps
CPU time 333.97 seconds
Started May 02 02:24:42 PM PDT 24
Finished May 02 02:30:20 PM PDT 24
Peak memory 200404 kb
Host smart-7088a8ff-88ba-4ebd-84d0-7b41ddb7a382
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3006505105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.3006505105
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.3975469418
Short name T878
Test name
Test status
Simulation time 4858790937 ps
CPU time 4.26 seconds
Started May 02 02:24:38 PM PDT 24
Finished May 02 02:24:46 PM PDT 24
Peak memory 200020 kb
Host smart-272144e8-eb7b-48e1-8d9c-0f39ec93b662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975469418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.3975469418
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.1047641160
Short name T1054
Test name
Test status
Simulation time 37386623955 ps
CPU time 66.72 seconds
Started May 02 02:24:42 PM PDT 24
Finished May 02 02:25:53 PM PDT 24
Peak memory 200560 kb
Host smart-a1d87cd0-9d02-4acc-b95c-0a94e7eed5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047641160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.1047641160
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.1528637988
Short name T544
Test name
Test status
Simulation time 23315569425 ps
CPU time 1155.63 seconds
Started May 02 02:24:39 PM PDT 24
Finished May 02 02:43:59 PM PDT 24
Peak memory 200424 kb
Host smart-f1d7fecd-ed70-4a75-95b4-390a1d08a388
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1528637988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.1528637988
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.2152744780
Short name T351
Test name
Test status
Simulation time 2324385156 ps
CPU time 11.33 seconds
Started May 02 02:24:40 PM PDT 24
Finished May 02 02:24:56 PM PDT 24
Peak memory 200388 kb
Host smart-452082d4-9eb5-42a9-ad15-31831d18a88b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2152744780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.2152744780
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.1436567989
Short name T1107
Test name
Test status
Simulation time 34631605773 ps
CPU time 26.58 seconds
Started May 02 02:24:39 PM PDT 24
Finished May 02 02:25:10 PM PDT 24
Peak memory 200020 kb
Host smart-519ed46b-32ee-4c20-ad14-6baa89567ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436567989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1436567989
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.880978452
Short name T454
Test name
Test status
Simulation time 7151545591 ps
CPU time 6.05 seconds
Started May 02 02:24:38 PM PDT 24
Finished May 02 02:24:49 PM PDT 24
Peak memory 196428 kb
Host smart-1609a577-ebf2-40e8-9e4b-bc60aa69ec1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880978452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.880978452
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.2181016619
Short name T82
Test name
Test status
Simulation time 112561743 ps
CPU time 0.89 seconds
Started May 02 02:24:39 PM PDT 24
Finished May 02 02:24:44 PM PDT 24
Peak memory 218616 kb
Host smart-6d955d18-db3e-4c1b-8ad5-950eee160391
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181016619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.2181016619
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.965016706
Short name T503
Test name
Test status
Simulation time 627883694 ps
CPU time 2.16 seconds
Started May 02 02:24:34 PM PDT 24
Finished May 02 02:24:40 PM PDT 24
Peak memory 198668 kb
Host smart-215b175d-f080-4b40-a7a0-6d3017a3e2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965016706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.965016706
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.1420396045
Short name T100
Test name
Test status
Simulation time 173218787498 ps
CPU time 509.46 seconds
Started May 02 02:24:44 PM PDT 24
Finished May 02 02:33:17 PM PDT 24
Peak memory 208856 kb
Host smart-4f5fe0fe-8091-4ae3-976f-6cdb029d27bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420396045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.1420396045
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.2307941932
Short name T215
Test name
Test status
Simulation time 158580141100 ps
CPU time 449.97 seconds
Started May 02 02:24:40 PM PDT 24
Finished May 02 02:32:15 PM PDT 24
Peak memory 225576 kb
Host smart-93a29afe-58e3-4d3a-802c-0825f9e7c02b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307941932 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.2307941932
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.3664123190
Short name T941
Test name
Test status
Simulation time 6204026096 ps
CPU time 22.7 seconds
Started May 02 02:24:44 PM PDT 24
Finished May 02 02:25:11 PM PDT 24
Peak memory 200368 kb
Host smart-37450398-c9f6-4ea4-91f8-6f7d0cd2a826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664123190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.3664123190
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.1614946220
Short name T1169
Test name
Test status
Simulation time 41446892002 ps
CPU time 42.06 seconds
Started May 02 02:24:34 PM PDT 24
Finished May 02 02:25:20 PM PDT 24
Peak memory 200392 kb
Host smart-699045f8-d88f-4e14-9ce5-6f264ab69f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614946220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.1614946220
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.3437080057
Short name T940
Test name
Test status
Simulation time 29731812 ps
CPU time 0.6 seconds
Started May 02 02:26:40 PM PDT 24
Finished May 02 02:26:43 PM PDT 24
Peak memory 195812 kb
Host smart-6f06a777-07c1-4589-8f98-13d8c81eefb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437080057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.3437080057
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.4012731338
Short name T401
Test name
Test status
Simulation time 62858275820 ps
CPU time 66.56 seconds
Started May 02 02:26:30 PM PDT 24
Finished May 02 02:27:43 PM PDT 24
Peak memory 200392 kb
Host smart-c8ee9ac9-e600-4154-af6b-79e74c126a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012731338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.4012731338
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.1728287651
Short name T832
Test name
Test status
Simulation time 70734572091 ps
CPU time 123.83 seconds
Started May 02 02:26:30 PM PDT 24
Finished May 02 02:28:40 PM PDT 24
Peak memory 200392 kb
Host smart-002553bd-43ef-409a-9366-5ead312ad6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728287651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.1728287651
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_intr.2584788001
Short name T435
Test name
Test status
Simulation time 186398154690 ps
CPU time 69.87 seconds
Started May 02 02:26:32 PM PDT 24
Finished May 02 02:27:47 PM PDT 24
Peak memory 199080 kb
Host smart-691aa72b-e34e-4955-a058-3293b58b8192
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584788001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.2584788001
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_loopback.2631535557
Short name T1064
Test name
Test status
Simulation time 4874997474 ps
CPU time 1.87 seconds
Started May 02 02:26:39 PM PDT 24
Finished May 02 02:26:44 PM PDT 24
Peak memory 199644 kb
Host smart-f3b046c1-153d-4f84-ae82-db8d2b5b50de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631535557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2631535557
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.2629527444
Short name T330
Test name
Test status
Simulation time 4076200844 ps
CPU time 7.91 seconds
Started May 02 02:26:31 PM PDT 24
Finished May 02 02:26:45 PM PDT 24
Peak memory 200332 kb
Host smart-41295873-18b6-4030-8a50-32bec547026d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629527444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.2629527444
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.3406142004
Short name T296
Test name
Test status
Simulation time 10523079845 ps
CPU time 570.08 seconds
Started May 02 02:26:38 PM PDT 24
Finished May 02 02:36:11 PM PDT 24
Peak memory 200396 kb
Host smart-8b55efb5-e587-44b1-b12b-953cf721fa59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3406142004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.3406142004
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.4088994133
Short name T1164
Test name
Test status
Simulation time 7474507343 ps
CPU time 36.39 seconds
Started May 02 02:26:31 PM PDT 24
Finished May 02 02:27:13 PM PDT 24
Peak memory 198772 kb
Host smart-91089868-fac4-4a2d-afe1-0998377fb5fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4088994133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.4088994133
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.611278290
Short name T1142
Test name
Test status
Simulation time 116873944618 ps
CPU time 31.72 seconds
Started May 02 02:26:31 PM PDT 24
Finished May 02 02:27:09 PM PDT 24
Peak memory 200428 kb
Host smart-5043baab-21df-4621-96a9-003ca6ed53a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611278290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.611278290
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.4239306348
Short name T323
Test name
Test status
Simulation time 31368772731 ps
CPU time 35.68 seconds
Started May 02 02:26:30 PM PDT 24
Finished May 02 02:27:12 PM PDT 24
Peak memory 196652 kb
Host smart-f4c37cdf-29ef-45cb-bc44-fb116fde06ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239306348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.4239306348
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.2359665603
Short name T341
Test name
Test status
Simulation time 718437803 ps
CPU time 1.21 seconds
Started May 02 02:26:33 PM PDT 24
Finished May 02 02:26:39 PM PDT 24
Peak memory 199668 kb
Host smart-64e1e5f5-0293-4b06-b5df-31ae145e4407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359665603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.2359665603
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.817855692
Short name T1144
Test name
Test status
Simulation time 17086302956 ps
CPU time 152.04 seconds
Started May 02 02:26:39 PM PDT 24
Finished May 02 02:29:14 PM PDT 24
Peak memory 208692 kb
Host smart-86f5557b-49d8-4e87-8521-ab1ed4c9c17a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817855692 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.817855692
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.2950811630
Short name T428
Test name
Test status
Simulation time 7540375944 ps
CPU time 19.55 seconds
Started May 02 02:26:29 PM PDT 24
Finished May 02 02:26:56 PM PDT 24
Peak memory 200152 kb
Host smart-823c49d9-e457-4929-b680-a80e6459b9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950811630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.2950811630
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.1545538383
Short name T533
Test name
Test status
Simulation time 61794595203 ps
CPU time 30.53 seconds
Started May 02 02:26:30 PM PDT 24
Finished May 02 02:27:07 PM PDT 24
Peak memory 200424 kb
Host smart-38fccca4-5d08-4a95-ac57-8b1a0f6618ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545538383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.1545538383
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.3627207526
Short name T1108
Test name
Test status
Simulation time 15156515427 ps
CPU time 38.96 seconds
Started May 02 02:33:14 PM PDT 24
Finished May 02 02:33:55 PM PDT 24
Peak memory 200420 kb
Host smart-3e8d4cd4-af17-4c24-9a54-32f460250a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627207526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.3627207526
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.2920083031
Short name T456
Test name
Test status
Simulation time 84382878517 ps
CPU time 36.6 seconds
Started May 02 02:33:13 PM PDT 24
Finished May 02 02:33:51 PM PDT 24
Peak memory 199164 kb
Host smart-7422433a-0c82-469a-90fe-e24c8da7a994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920083031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.2920083031
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.3244216228
Short name T679
Test name
Test status
Simulation time 28295642487 ps
CPU time 54.62 seconds
Started May 02 02:33:14 PM PDT 24
Finished May 02 02:34:10 PM PDT 24
Peak memory 200340 kb
Host smart-b8fe15b8-0229-439d-b1b7-f2dba47401e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244216228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.3244216228
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.3481608254
Short name T186
Test name
Test status
Simulation time 109168811401 ps
CPU time 215.04 seconds
Started May 02 02:33:12 PM PDT 24
Finished May 02 02:36:49 PM PDT 24
Peak memory 200432 kb
Host smart-68ef1482-5b75-4f3c-b0c7-0ced4ef0b6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481608254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.3481608254
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.534233173
Short name T900
Test name
Test status
Simulation time 188871202082 ps
CPU time 40.26 seconds
Started May 02 02:33:15 PM PDT 24
Finished May 02 02:33:56 PM PDT 24
Peak memory 200388 kb
Host smart-f4bf6574-3fdb-4a6e-a25e-4106d2c8e064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534233173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.534233173
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.3291489394
Short name T1174
Test name
Test status
Simulation time 57524716195 ps
CPU time 106.8 seconds
Started May 02 02:33:14 PM PDT 24
Finished May 02 02:35:02 PM PDT 24
Peak memory 200380 kb
Host smart-ee67ee3a-670f-43e2-a53b-2e1b0d2d190a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291489394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.3291489394
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.121272266
Short name T1176
Test name
Test status
Simulation time 105028023426 ps
CPU time 31.96 seconds
Started May 02 02:33:14 PM PDT 24
Finished May 02 02:33:47 PM PDT 24
Peak memory 200324 kb
Host smart-3bf8062c-e2d1-4198-8809-48061ae8e4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121272266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.121272266
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.3489588060
Short name T666
Test name
Test status
Simulation time 72254922873 ps
CPU time 127.92 seconds
Started May 02 02:33:13 PM PDT 24
Finished May 02 02:35:23 PM PDT 24
Peak memory 200384 kb
Host smart-c9f9015a-fc97-4a26-84d5-042ed64c26c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489588060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.3489588060
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.2942365395
Short name T543
Test name
Test status
Simulation time 137947747834 ps
CPU time 154.14 seconds
Started May 02 02:33:12 PM PDT 24
Finished May 02 02:35:48 PM PDT 24
Peak memory 200440 kb
Host smart-0dbfe4f5-e3ae-42bc-b5ec-42469884380c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942365395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.2942365395
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.3164950093
Short name T277
Test name
Test status
Simulation time 21567297321 ps
CPU time 43.64 seconds
Started May 02 02:33:22 PM PDT 24
Finished May 02 02:34:07 PM PDT 24
Peak memory 200344 kb
Host smart-6855b916-cb27-4c19-8ebb-ff951876f255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164950093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.3164950093
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.2621409117
Short name T18
Test name
Test status
Simulation time 13970122 ps
CPU time 0.59 seconds
Started May 02 02:26:54 PM PDT 24
Finished May 02 02:26:57 PM PDT 24
Peak memory 195836 kb
Host smart-4d88a160-8cca-4e22-be83-0d0b77e1a602
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621409117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.2621409117
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.2812824599
Short name T411
Test name
Test status
Simulation time 72942144181 ps
CPU time 149.04 seconds
Started May 02 02:26:40 PM PDT 24
Finished May 02 02:29:12 PM PDT 24
Peak memory 200420 kb
Host smart-e55e0714-2165-4716-b156-0663195e637c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812824599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2812824599
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.3738856151
Short name T1157
Test name
Test status
Simulation time 189090882320 ps
CPU time 21.97 seconds
Started May 02 02:26:41 PM PDT 24
Finished May 02 02:27:05 PM PDT 24
Peak memory 200328 kb
Host smart-05efbed8-ffce-4c3f-a71e-375363f4183f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738856151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.3738856151
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.1427318072
Short name T1132
Test name
Test status
Simulation time 66036309978 ps
CPU time 81.29 seconds
Started May 02 02:26:38 PM PDT 24
Finished May 02 02:28:03 PM PDT 24
Peak memory 200336 kb
Host smart-29b2cad6-2527-418b-a30c-5f76fbbdafc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427318072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.1427318072
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.2165360005
Short name T488
Test name
Test status
Simulation time 281306092861 ps
CPU time 270.46 seconds
Started May 02 02:26:39 PM PDT 24
Finished May 02 02:31:13 PM PDT 24
Peak memory 200396 kb
Host smart-ab1a330e-132d-41c3-b0a5-ab5322e63c19
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165360005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2165360005
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.3229944184
Short name T880
Test name
Test status
Simulation time 75276277727 ps
CPU time 857.63 seconds
Started May 02 02:26:55 PM PDT 24
Finished May 02 02:41:15 PM PDT 24
Peak memory 200396 kb
Host smart-21fe3965-56b2-45c9-9756-2bcb2518a6fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3229944184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.3229944184
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.3892797858
Short name T567
Test name
Test status
Simulation time 4977904253 ps
CPU time 11.48 seconds
Started May 02 02:26:59 PM PDT 24
Finished May 02 02:27:14 PM PDT 24
Peak memory 200060 kb
Host smart-b219b5e8-dd85-4a5c-8421-9b8dc0aab8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892797858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.3892797858
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.883072150
Short name T573
Test name
Test status
Simulation time 51108375124 ps
CPU time 46.84 seconds
Started May 02 02:26:40 PM PDT 24
Finished May 02 02:27:29 PM PDT 24
Peak memory 199172 kb
Host smart-0921c6dc-9411-4bf1-8bb4-b710e7741b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883072150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.883072150
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.774393518
Short name T452
Test name
Test status
Simulation time 19012504461 ps
CPU time 1005.48 seconds
Started May 02 02:26:47 PM PDT 24
Finished May 02 02:43:34 PM PDT 24
Peak memory 200404 kb
Host smart-9c920c78-7a59-4dc5-a81d-38eab21b06fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=774393518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.774393518
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.553181791
Short name T615
Test name
Test status
Simulation time 4793964669 ps
CPU time 10.67 seconds
Started May 02 02:26:37 PM PDT 24
Finished May 02 02:26:51 PM PDT 24
Peak memory 199568 kb
Host smart-ad8585c8-436f-4d02-9fac-9bcc74182c8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=553181791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.553181791
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.2165362067
Short name T1162
Test name
Test status
Simulation time 35616299751 ps
CPU time 63.29 seconds
Started May 02 02:26:47 PM PDT 24
Finished May 02 02:27:52 PM PDT 24
Peak memory 200436 kb
Host smart-55d1aade-a485-4b05-b274-8336a02d4786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165362067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.2165362067
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.783976518
Short name T759
Test name
Test status
Simulation time 4250273172 ps
CPU time 7.04 seconds
Started May 02 02:26:38 PM PDT 24
Finished May 02 02:26:49 PM PDT 24
Peak memory 196348 kb
Host smart-497aade9-aa8d-4fb5-95a8-69cb60ca04d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783976518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.783976518
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.1079019548
Short name T678
Test name
Test status
Simulation time 5461115246 ps
CPU time 14.04 seconds
Started May 02 02:26:40 PM PDT 24
Finished May 02 02:26:56 PM PDT 24
Peak memory 200044 kb
Host smart-31a0250b-5050-4fe4-8718-db6c91388f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079019548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.1079019548
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.2266528745
Short name T657
Test name
Test status
Simulation time 407248465770 ps
CPU time 393.03 seconds
Started May 02 02:26:49 PM PDT 24
Finished May 02 02:33:24 PM PDT 24
Peak memory 208760 kb
Host smart-70b9df81-8a6e-49f8-8b34-3f83621edee6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266528745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2266528745
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.209416754
Short name T958
Test name
Test status
Simulation time 149880831718 ps
CPU time 1242.64 seconds
Started May 02 02:26:59 PM PDT 24
Finished May 02 02:47:44 PM PDT 24
Peak memory 225092 kb
Host smart-ff8056f6-1eb5-4457-879f-69a68df56abf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209416754 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.209416754
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.219385688
Short name T741
Test name
Test status
Simulation time 6121537465 ps
CPU time 14.19 seconds
Started May 02 02:27:00 PM PDT 24
Finished May 02 02:27:17 PM PDT 24
Peak memory 200332 kb
Host smart-e638d630-4da2-46f6-b629-6a85d8eaf4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219385688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.219385688
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.1654190678
Short name T339
Test name
Test status
Simulation time 10092703385 ps
CPU time 20.94 seconds
Started May 02 02:26:39 PM PDT 24
Finished May 02 02:27:03 PM PDT 24
Peak memory 200400 kb
Host smart-a71a50de-7c16-4ad9-9f44-1c56c41182f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654190678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.1654190678
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.3221421217
Short name T957
Test name
Test status
Simulation time 11840070881 ps
CPU time 16.56 seconds
Started May 02 02:33:21 PM PDT 24
Finished May 02 02:33:39 PM PDT 24
Peak memory 200392 kb
Host smart-6fa05451-70f7-4b18-a6c8-9d69f78bc816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221421217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.3221421217
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.1179407337
Short name T482
Test name
Test status
Simulation time 87207628601 ps
CPU time 49.23 seconds
Started May 02 02:33:20 PM PDT 24
Finished May 02 02:34:12 PM PDT 24
Peak memory 200372 kb
Host smart-e86e179d-40bd-4e1d-82de-5e0120fb27a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179407337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.1179407337
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.106204468
Short name T212
Test name
Test status
Simulation time 23769377513 ps
CPU time 22.81 seconds
Started May 02 02:33:22 PM PDT 24
Finished May 02 02:33:47 PM PDT 24
Peak memory 199308 kb
Host smart-a22c2653-0c79-4053-8114-4c65b16dd201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106204468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.106204468
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.2136054254
Short name T599
Test name
Test status
Simulation time 50718222953 ps
CPU time 58.82 seconds
Started May 02 02:33:19 PM PDT 24
Finished May 02 02:34:20 PM PDT 24
Peak memory 200364 kb
Host smart-0c87f13d-0ed0-46a0-906b-30f96eb3b8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136054254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.2136054254
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.1872049032
Short name T172
Test name
Test status
Simulation time 82757175610 ps
CPU time 126.69 seconds
Started May 02 02:33:21 PM PDT 24
Finished May 02 02:35:29 PM PDT 24
Peak memory 200388 kb
Host smart-7a3746a5-244a-49bf-84cc-b7e77716c723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872049032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.1872049032
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.3294723009
Short name T199
Test name
Test status
Simulation time 181286466150 ps
CPU time 38 seconds
Started May 02 02:33:20 PM PDT 24
Finished May 02 02:34:00 PM PDT 24
Peak memory 200412 kb
Host smart-17037a64-f78b-4471-91f2-81e58c4fd1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294723009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.3294723009
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.1630697050
Short name T835
Test name
Test status
Simulation time 241107097418 ps
CPU time 43.23 seconds
Started May 02 02:33:20 PM PDT 24
Finished May 02 02:34:05 PM PDT 24
Peak memory 200384 kb
Host smart-8d67ac0e-ca00-4def-b8a7-c1251491a364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630697050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1630697050
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.499677397
Short name T673
Test name
Test status
Simulation time 68251407635 ps
CPU time 30.93 seconds
Started May 02 02:33:21 PM PDT 24
Finished May 02 02:33:54 PM PDT 24
Peak memory 200448 kb
Host smart-e5f4d153-88fc-4b0c-8801-efcfd4d98083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499677397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.499677397
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.1618882473
Short name T170
Test name
Test status
Simulation time 50277024687 ps
CPU time 75.35 seconds
Started May 02 02:33:30 PM PDT 24
Finished May 02 02:34:47 PM PDT 24
Peak memory 200336 kb
Host smart-74c95839-cd4e-4435-b334-4cfee1202d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618882473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1618882473
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.1402563879
Short name T1072
Test name
Test status
Simulation time 16945318 ps
CPU time 0.59 seconds
Started May 02 02:27:00 PM PDT 24
Finished May 02 02:27:04 PM PDT 24
Peak memory 195772 kb
Host smart-52062655-7f59-48c8-b5ec-c042baeddb5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402563879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.1402563879
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.1945464492
Short name T621
Test name
Test status
Simulation time 44188250053 ps
CPU time 38.54 seconds
Started May 02 02:26:46 PM PDT 24
Finished May 02 02:27:26 PM PDT 24
Peak memory 200380 kb
Host smart-1ce84e2b-89c4-4e25-a003-ad09947c6db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945464492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.1945464492
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.1140022693
Short name T701
Test name
Test status
Simulation time 83582274339 ps
CPU time 120.82 seconds
Started May 02 02:27:01 PM PDT 24
Finished May 02 02:29:04 PM PDT 24
Peak memory 200152 kb
Host smart-5a242dee-d3c6-45ba-acf2-ffad58e6e318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140022693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.1140022693
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.727813277
Short name T1151
Test name
Test status
Simulation time 107303137021 ps
CPU time 30.27 seconds
Started May 02 02:26:46 PM PDT 24
Finished May 02 02:27:17 PM PDT 24
Peak memory 200436 kb
Host smart-d11c2b46-af78-453c-8e37-37d6be71a8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727813277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.727813277
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.458352224
Short name T967
Test name
Test status
Simulation time 9045061329 ps
CPU time 13.62 seconds
Started May 02 02:26:49 PM PDT 24
Finished May 02 02:27:04 PM PDT 24
Peak memory 199724 kb
Host smart-e3bf9dc4-0a6c-49e0-85fc-3995a27fa209
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458352224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.458352224
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.357930751
Short name T389
Test name
Test status
Simulation time 36266043371 ps
CPU time 101.85 seconds
Started May 02 02:27:00 PM PDT 24
Finished May 02 02:28:44 PM PDT 24
Peak memory 200444 kb
Host smart-a9ed75fd-5242-4711-bb65-aa3f6ca697ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=357930751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.357930751
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.1271921908
Short name T602
Test name
Test status
Simulation time 8572320670 ps
CPU time 5.75 seconds
Started May 02 02:26:59 PM PDT 24
Finished May 02 02:27:08 PM PDT 24
Peak memory 196284 kb
Host smart-9e28dd6d-1b2a-425e-8b30-42c28db030d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271921908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1271921908
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.2463877900
Short name T244
Test name
Test status
Simulation time 103964326664 ps
CPU time 115.86 seconds
Started May 02 02:26:55 PM PDT 24
Finished May 02 02:28:53 PM PDT 24
Peak memory 200788 kb
Host smart-43de3f47-4f66-4d7d-8127-9bcefbf37bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463877900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.2463877900
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.3367714216
Short name T1068
Test name
Test status
Simulation time 16208739240 ps
CPU time 199.29 seconds
Started May 02 02:26:59 PM PDT 24
Finished May 02 02:30:20 PM PDT 24
Peak memory 200380 kb
Host smart-180ef7cc-8cdb-4b1c-ac7a-d3a2d7fad814
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3367714216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.3367714216
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.187598768
Short name T338
Test name
Test status
Simulation time 2322463795 ps
CPU time 13.38 seconds
Started May 02 02:26:46 PM PDT 24
Finished May 02 02:27:00 PM PDT 24
Peak memory 199244 kb
Host smart-4a5fde89-f4fd-4098-8bf7-2577f8bd187a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=187598768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.187598768
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.1732666392
Short name T588
Test name
Test status
Simulation time 35406657595 ps
CPU time 15.13 seconds
Started May 02 02:26:55 PM PDT 24
Finished May 02 02:27:13 PM PDT 24
Peak memory 200460 kb
Host smart-e26d9959-ef0c-4909-97e4-804387386619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732666392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.1732666392
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.1124360348
Short name T349
Test name
Test status
Simulation time 4437645110 ps
CPU time 8.05 seconds
Started May 02 02:27:01 PM PDT 24
Finished May 02 02:27:12 PM PDT 24
Peak memory 196676 kb
Host smart-7b993a99-abe1-4674-b878-6684962a693b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124360348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.1124360348
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.785667764
Short name T564
Test name
Test status
Simulation time 6203560308 ps
CPU time 3.89 seconds
Started May 02 02:26:48 PM PDT 24
Finished May 02 02:26:54 PM PDT 24
Peak memory 200336 kb
Host smart-f5f232c3-518f-4f64-aa83-87a0ec57ddc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785667764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.785667764
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.1570368476
Short name T159
Test name
Test status
Simulation time 238865380199 ps
CPU time 222.66 seconds
Started May 02 02:26:59 PM PDT 24
Finished May 02 02:30:45 PM PDT 24
Peak memory 208800 kb
Host smart-c09b8c56-7614-4a0e-9dcc-37059f1e83b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570368476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.1570368476
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.3744366838
Short name T860
Test name
Test status
Simulation time 244853566315 ps
CPU time 849.61 seconds
Started May 02 02:27:01 PM PDT 24
Finished May 02 02:41:13 PM PDT 24
Peak memory 225264 kb
Host smart-816f6798-d87d-4360-ad29-875e837bfea8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744366838 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.3744366838
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.231034391
Short name T288
Test name
Test status
Simulation time 6266357575 ps
CPU time 12.96 seconds
Started May 02 02:26:59 PM PDT 24
Finished May 02 02:27:15 PM PDT 24
Peak memory 200356 kb
Host smart-f39118c0-504c-4e81-a20d-445d6ddffdba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231034391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.231034391
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.1245802407
Short name T1021
Test name
Test status
Simulation time 234549760431 ps
CPU time 52.88 seconds
Started May 02 02:26:55 PM PDT 24
Finished May 02 02:27:51 PM PDT 24
Peak memory 200448 kb
Host smart-47740241-4d4f-4097-b393-9ee174bbf0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245802407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.1245802407
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.194759234
Short name T648
Test name
Test status
Simulation time 33009060355 ps
CPU time 38.47 seconds
Started May 02 02:33:29 PM PDT 24
Finished May 02 02:34:09 PM PDT 24
Peak memory 200368 kb
Host smart-a6c9be22-74ba-4a90-8798-62fe42ee810e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194759234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.194759234
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.2029404825
Short name T275
Test name
Test status
Simulation time 132767147607 ps
CPU time 180.55 seconds
Started May 02 02:33:30 PM PDT 24
Finished May 02 02:36:32 PM PDT 24
Peak memory 200320 kb
Host smart-a85d6a0c-6ace-429c-8233-d8316721452e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029404825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.2029404825
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.4219840537
Short name T479
Test name
Test status
Simulation time 135360534498 ps
CPU time 57.29 seconds
Started May 02 02:33:31 PM PDT 24
Finished May 02 02:34:30 PM PDT 24
Peak memory 200380 kb
Host smart-0d6fcde4-a3fc-4b53-aef1-422c1de2d80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219840537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.4219840537
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.817542751
Short name T436
Test name
Test status
Simulation time 22535929333 ps
CPU time 39.32 seconds
Started May 02 02:33:29 PM PDT 24
Finished May 02 02:34:10 PM PDT 24
Peak memory 200432 kb
Host smart-a21fa20a-d3fa-4056-9bab-2655e63e2c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817542751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.817542751
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.1748753444
Short name T724
Test name
Test status
Simulation time 96612746203 ps
CPU time 79.1 seconds
Started May 02 02:33:29 PM PDT 24
Finished May 02 02:34:50 PM PDT 24
Peak memory 200384 kb
Host smart-91fb7f26-8c9d-40ff-9312-c5f2efcfd1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748753444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1748753444
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.1048077316
Short name T513
Test name
Test status
Simulation time 251286233956 ps
CPU time 54.11 seconds
Started May 02 02:33:29 PM PDT 24
Finished May 02 02:34:24 PM PDT 24
Peak memory 200388 kb
Host smart-1c766ed9-2e14-434d-b48c-5a34011ac0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048077316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.1048077316
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.3864218028
Short name T174
Test name
Test status
Simulation time 14577817962 ps
CPU time 22.34 seconds
Started May 02 02:33:29 PM PDT 24
Finished May 02 02:33:53 PM PDT 24
Peak memory 200428 kb
Host smart-9ed54b25-e2ee-40fc-8980-c885b5646098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864218028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.3864218028
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.1664925381
Short name T165
Test name
Test status
Simulation time 24993318331 ps
CPU time 10.47 seconds
Started May 02 02:33:31 PM PDT 24
Finished May 02 02:33:43 PM PDT 24
Peak memory 200024 kb
Host smart-39b3e480-1b4f-46c4-866d-cd6e3be5f7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664925381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1664925381
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.590625031
Short name T20
Test name
Test status
Simulation time 13597502 ps
CPU time 0.56 seconds
Started May 02 02:26:59 PM PDT 24
Finished May 02 02:27:02 PM PDT 24
Peak memory 195820 kb
Host smart-9bb4f235-0582-4556-8bc5-f8327fc9aece
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590625031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.590625031
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.3480575046
Short name T1039
Test name
Test status
Simulation time 129012379328 ps
CPU time 38.3 seconds
Started May 02 02:26:58 PM PDT 24
Finished May 02 02:27:39 PM PDT 24
Peak memory 200352 kb
Host smart-2a06e2ca-68b5-4953-8553-92681bffb363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480575046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.3480575046
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.511874711
Short name T283
Test name
Test status
Simulation time 96932669751 ps
CPU time 232.85 seconds
Started May 02 02:27:01 PM PDT 24
Finished May 02 02:30:56 PM PDT 24
Peak memory 200376 kb
Host smart-f47c3086-c2e6-45c4-a799-20361c5337d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511874711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.511874711
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_intr.4267654519
Short name T696
Test name
Test status
Simulation time 32511464855 ps
CPU time 6.34 seconds
Started May 02 02:26:59 PM PDT 24
Finished May 02 02:27:08 PM PDT 24
Peak memory 200316 kb
Host smart-bbde2b45-1cd1-41f6-b6d1-fc9294148b53
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267654519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.4267654519
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.953100398
Short name T257
Test name
Test status
Simulation time 78406123539 ps
CPU time 223.89 seconds
Started May 02 02:26:59 PM PDT 24
Finished May 02 02:30:46 PM PDT 24
Peak memory 200324 kb
Host smart-62470842-3ef5-4162-86d0-8b5805bf4e59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=953100398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.953100398
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.3538535361
Short name T508
Test name
Test status
Simulation time 1728670780 ps
CPU time 1.42 seconds
Started May 02 02:27:01 PM PDT 24
Finished May 02 02:27:05 PM PDT 24
Peak memory 196516 kb
Host smart-bd17b3b1-3ec4-4313-9a68-76dd2a09fc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538535361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.3538535361
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.4230284769
Short name T539
Test name
Test status
Simulation time 53612477748 ps
CPU time 46.17 seconds
Started May 02 02:27:00 PM PDT 24
Finished May 02 02:27:49 PM PDT 24
Peak memory 200628 kb
Host smart-ee157a11-2f13-42d6-82a4-086a3e87cd90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230284769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.4230284769
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.3994240491
Short name T417
Test name
Test status
Simulation time 25900780219 ps
CPU time 546.74 seconds
Started May 02 02:27:00 PM PDT 24
Finished May 02 02:36:10 PM PDT 24
Peak memory 200428 kb
Host smart-2651b3cf-1e30-4c04-bf01-676ce8e26949
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3994240491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.3994240491
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.300475115
Short name T812
Test name
Test status
Simulation time 5179196265 ps
CPU time 11.85 seconds
Started May 02 02:27:01 PM PDT 24
Finished May 02 02:27:16 PM PDT 24
Peak memory 199544 kb
Host smart-62321fc4-2167-43ba-ba52-f7cd127c276d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=300475115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.300475115
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.3041080888
Short name T258
Test name
Test status
Simulation time 77158023564 ps
CPU time 40.26 seconds
Started May 02 02:26:59 PM PDT 24
Finished May 02 02:27:41 PM PDT 24
Peak memory 200416 kb
Host smart-664dbe4b-36f6-4c8d-8d9c-f94afb50da7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041080888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.3041080888
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.416877187
Short name T1126
Test name
Test status
Simulation time 685585008 ps
CPU time 1.22 seconds
Started May 02 02:27:01 PM PDT 24
Finished May 02 02:27:05 PM PDT 24
Peak memory 195824 kb
Host smart-fdb226b1-9c13-490b-9c8e-265c6d5fa5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416877187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.416877187
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.2592866230
Short name T327
Test name
Test status
Simulation time 737614378 ps
CPU time 2.42 seconds
Started May 02 02:27:01 PM PDT 24
Finished May 02 02:27:06 PM PDT 24
Peak memory 199752 kb
Host smart-27ebe3c8-484e-40c6-8821-727fe28fe9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592866230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.2592866230
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.1740031026
Short name T949
Test name
Test status
Simulation time 205481900783 ps
CPU time 76.61 seconds
Started May 02 02:26:59 PM PDT 24
Finished May 02 02:28:19 PM PDT 24
Peak memory 200348 kb
Host smart-a08b6cd0-95b5-4893-9f89-dd44eb4dc09a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740031026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.1740031026
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.3302793214
Short name T935
Test name
Test status
Simulation time 122832267643 ps
CPU time 423.19 seconds
Started May 02 02:26:59 PM PDT 24
Finished May 02 02:34:04 PM PDT 24
Peak memory 217024 kb
Host smart-c9efc596-77b8-403f-a8cf-aaa1453f4ad4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302793214 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.3302793214
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.992368079
Short name T507
Test name
Test status
Simulation time 2022210336 ps
CPU time 1.73 seconds
Started May 02 02:26:59 PM PDT 24
Finished May 02 02:27:02 PM PDT 24
Peak memory 199004 kb
Host smart-c3363e7d-441d-499d-a378-a217f6df715c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992368079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.992368079
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.1957926145
Short name T918
Test name
Test status
Simulation time 114378874697 ps
CPU time 320.31 seconds
Started May 02 02:26:59 PM PDT 24
Finished May 02 02:32:22 PM PDT 24
Peak memory 200336 kb
Host smart-e192244e-4386-4101-99bd-46edf79f4217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957926145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.1957926145
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.1451188382
Short name T601
Test name
Test status
Simulation time 20504819116 ps
CPU time 25.76 seconds
Started May 02 02:33:30 PM PDT 24
Finished May 02 02:33:57 PM PDT 24
Peak memory 200436 kb
Host smart-985fb08b-bc7b-40f1-8f92-ee042e67e487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451188382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.1451188382
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.1582330362
Short name T300
Test name
Test status
Simulation time 100118714383 ps
CPU time 141.73 seconds
Started May 02 02:33:29 PM PDT 24
Finished May 02 02:35:52 PM PDT 24
Peak memory 200396 kb
Host smart-baf68c69-83e3-4e5b-a524-c6945bed2f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582330362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1582330362
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.1672912528
Short name T178
Test name
Test status
Simulation time 36292256013 ps
CPU time 54.12 seconds
Started May 02 02:33:31 PM PDT 24
Finished May 02 02:34:27 PM PDT 24
Peak memory 200352 kb
Host smart-134c4015-d7a3-43c5-9405-dd1420c4b56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672912528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.1672912528
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.3764266847
Short name T517
Test name
Test status
Simulation time 29397556652 ps
CPU time 47.25 seconds
Started May 02 02:33:39 PM PDT 24
Finished May 02 02:34:28 PM PDT 24
Peak memory 200360 kb
Host smart-ff1962fe-1199-4482-8e79-98ecd1db987d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764266847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.3764266847
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.375983968
Short name T1140
Test name
Test status
Simulation time 44272982997 ps
CPU time 17.76 seconds
Started May 02 02:33:38 PM PDT 24
Finished May 02 02:33:57 PM PDT 24
Peak memory 200384 kb
Host smart-a058ab06-ed5e-4a11-b3ed-67b71aaa7fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375983968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.375983968
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.3577213732
Short name T755
Test name
Test status
Simulation time 155489878670 ps
CPU time 151.1 seconds
Started May 02 02:33:39 PM PDT 24
Finished May 02 02:36:12 PM PDT 24
Peak memory 200332 kb
Host smart-0b071602-954d-43ee-8e92-88c9e6cb8e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577213732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.3577213732
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.2992548611
Short name T317
Test name
Test status
Simulation time 66748891817 ps
CPU time 21.64 seconds
Started May 02 02:33:38 PM PDT 24
Finished May 02 02:34:01 PM PDT 24
Peak memory 200304 kb
Host smart-adc52b5a-5fec-4d9e-8afd-742695103884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992548611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.2992548611
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.1901428998
Short name T153
Test name
Test status
Simulation time 23394783475 ps
CPU time 35.6 seconds
Started May 02 02:33:39 PM PDT 24
Finished May 02 02:34:17 PM PDT 24
Peak memory 200384 kb
Host smart-4ddacf9b-587f-419a-a1d3-71903f408e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901428998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.1901428998
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.1556593147
Short name T316
Test name
Test status
Simulation time 118065145878 ps
CPU time 193.74 seconds
Started May 02 02:33:38 PM PDT 24
Finished May 02 02:36:54 PM PDT 24
Peak memory 200384 kb
Host smart-19a3c4c7-e38a-496e-9e49-b1eabaa450d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556593147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.1556593147
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.46569492
Short name T1048
Test name
Test status
Simulation time 30813736 ps
CPU time 0.55 seconds
Started May 02 02:27:13 PM PDT 24
Finished May 02 02:27:15 PM PDT 24
Peak memory 194768 kb
Host smart-630f9228-e1ec-4297-b2da-f65e299b9bf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46569492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.46569492
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.2395670781
Short name T780
Test name
Test status
Simulation time 34171573440 ps
CPU time 57.12 seconds
Started May 02 02:27:04 PM PDT 24
Finished May 02 02:28:03 PM PDT 24
Peak memory 200432 kb
Host smart-bb086ff3-3ee1-4387-981e-66d75fc0ffe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395670781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.2395670781
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.1094986238
Short name T697
Test name
Test status
Simulation time 243505581543 ps
CPU time 96.31 seconds
Started May 02 02:27:05 PM PDT 24
Finished May 02 02:28:43 PM PDT 24
Peak memory 200416 kb
Host smart-4ba7ccd2-43b6-4aa1-a600-f5003eb58150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094986238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.1094986238
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.1492028306
Short name T414
Test name
Test status
Simulation time 14468498857 ps
CPU time 24.85 seconds
Started May 02 02:27:06 PM PDT 24
Finished May 02 02:27:32 PM PDT 24
Peak memory 200360 kb
Host smart-1a7b1472-6d90-41d1-8489-965834426436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492028306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.1492028306
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.3500461389
Short name T1128
Test name
Test status
Simulation time 55189103756 ps
CPU time 24.18 seconds
Started May 02 02:27:05 PM PDT 24
Finished May 02 02:27:31 PM PDT 24
Peak memory 200388 kb
Host smart-54a7e632-e4a3-40fa-a8b3-fbab777410d2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500461389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.3500461389
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.2929435791
Short name T1006
Test name
Test status
Simulation time 72864067237 ps
CPU time 253.69 seconds
Started May 02 02:27:10 PM PDT 24
Finished May 02 02:31:25 PM PDT 24
Peak memory 200388 kb
Host smart-a5c4ebc8-c899-4c66-9b49-5bae5f2d51ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2929435791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.2929435791
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.801177171
Short name T833
Test name
Test status
Simulation time 5824010081 ps
CPU time 5.19 seconds
Started May 02 02:27:04 PM PDT 24
Finished May 02 02:27:11 PM PDT 24
Peak memory 200360 kb
Host smart-1155bb98-22d5-4329-abc7-2ff2cb570ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801177171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.801177171
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.1589195551
Short name T618
Test name
Test status
Simulation time 64197241375 ps
CPU time 108.87 seconds
Started May 02 02:27:07 PM PDT 24
Finished May 02 02:28:57 PM PDT 24
Peak memory 200364 kb
Host smart-1e4bf0cd-960e-4af2-b7f2-30a12448ee70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589195551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.1589195551
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.3809796535
Short name T405
Test name
Test status
Simulation time 23476326224 ps
CPU time 256.81 seconds
Started May 02 02:27:02 PM PDT 24
Finished May 02 02:31:21 PM PDT 24
Peak memory 200336 kb
Host smart-39b2826a-ca2d-41c3-985d-78bcbcc60acf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3809796535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.3809796535
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.3368681146
Short name T1065
Test name
Test status
Simulation time 1706481849 ps
CPU time 4.85 seconds
Started May 02 02:27:02 PM PDT 24
Finished May 02 02:27:09 PM PDT 24
Peak memory 199732 kb
Host smart-9b4f8b13-cebb-4b06-8192-a2eb35b05599
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3368681146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.3368681146
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.2601213841
Short name T373
Test name
Test status
Simulation time 138668040039 ps
CPU time 14.53 seconds
Started May 02 02:27:03 PM PDT 24
Finished May 02 02:27:20 PM PDT 24
Peak memory 200344 kb
Host smart-eeb14dad-d392-4b8f-97af-7ee3591c51e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601213841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.2601213841
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.1719043527
Short name T1153
Test name
Test status
Simulation time 33393219463 ps
CPU time 46.99 seconds
Started May 02 02:27:02 PM PDT 24
Finished May 02 02:27:52 PM PDT 24
Peak memory 196720 kb
Host smart-8f945beb-1a32-494a-9ff0-0cb4595a8ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719043527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.1719043527
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.2769504602
Short name T645
Test name
Test status
Simulation time 5714577943 ps
CPU time 13.38 seconds
Started May 02 02:27:02 PM PDT 24
Finished May 02 02:27:18 PM PDT 24
Peak memory 200212 kb
Host smart-ac1c9ac0-0865-49ca-b384-dcf843f9bb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769504602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.2769504602
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.532514835
Short name T606
Test name
Test status
Simulation time 372624698872 ps
CPU time 91.67 seconds
Started May 02 02:27:13 PM PDT 24
Finished May 02 02:28:47 PM PDT 24
Peak memory 208772 kb
Host smart-9feea70f-0c9a-4f96-8a15-59e990521583
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532514835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.532514835
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.2451436627
Short name T522
Test name
Test status
Simulation time 78457685528 ps
CPU time 528.75 seconds
Started May 02 02:27:12 PM PDT 24
Finished May 02 02:36:03 PM PDT 24
Peak memory 216904 kb
Host smart-f5d9088c-7e12-40ae-a0b4-d104c495056d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451436627 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.2451436627
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.3972803138
Short name T893
Test name
Test status
Simulation time 2054217338 ps
CPU time 2.69 seconds
Started May 02 02:27:02 PM PDT 24
Finished May 02 02:27:08 PM PDT 24
Peak memory 199308 kb
Host smart-91e8a52e-648b-48f8-ae34-7e797d32081d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972803138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.3972803138
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.2700117064
Short name T705
Test name
Test status
Simulation time 53420843105 ps
CPU time 99.75 seconds
Started May 02 02:27:07 PM PDT 24
Finished May 02 02:28:48 PM PDT 24
Peak memory 200480 kb
Host smart-a18eff22-a96c-4a6c-bc01-06954526729c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700117064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.2700117064
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.2063998759
Short name T1004
Test name
Test status
Simulation time 233330677311 ps
CPU time 118.73 seconds
Started May 02 02:33:37 PM PDT 24
Finished May 02 02:35:37 PM PDT 24
Peak memory 200376 kb
Host smart-b871d412-4e01-4b5e-a4a5-5f8a8098173c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063998759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.2063998759
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.3891608771
Short name T176
Test name
Test status
Simulation time 29299524754 ps
CPU time 80.89 seconds
Started May 02 02:33:37 PM PDT 24
Finished May 02 02:35:00 PM PDT 24
Peak memory 200464 kb
Host smart-1804e12e-f928-4299-8676-dd81e7d78e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891608771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.3891608771
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.4046340392
Short name T318
Test name
Test status
Simulation time 44628201411 ps
CPU time 29.09 seconds
Started May 02 02:33:39 PM PDT 24
Finished May 02 02:34:11 PM PDT 24
Peak memory 200344 kb
Host smart-d3ab349d-b7f5-4028-b7cd-ce3a404dee53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046340392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.4046340392
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.3159535842
Short name T1113
Test name
Test status
Simulation time 104856261352 ps
CPU time 432.06 seconds
Started May 02 02:33:39 PM PDT 24
Finished May 02 02:40:53 PM PDT 24
Peak memory 200324 kb
Host smart-81ddcf15-9201-4f24-9732-bcde2812f54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159535842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.3159535842
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.631018242
Short name T968
Test name
Test status
Simulation time 162697542015 ps
CPU time 278.51 seconds
Started May 02 02:33:40 PM PDT 24
Finished May 02 02:38:20 PM PDT 24
Peak memory 200408 kb
Host smart-b41b4e93-7eea-45a2-bb13-d98751defcb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631018242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.631018242
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.4077369148
Short name T190
Test name
Test status
Simulation time 30082729245 ps
CPU time 60.64 seconds
Started May 02 02:33:38 PM PDT 24
Finished May 02 02:34:40 PM PDT 24
Peak memory 200420 kb
Host smart-ef4e733b-7373-4160-b854-8b74e5b1638b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077369148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.4077369148
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.3503589815
Short name T945
Test name
Test status
Simulation time 170246227676 ps
CPU time 50.26 seconds
Started May 02 02:33:37 PM PDT 24
Finished May 02 02:34:29 PM PDT 24
Peak memory 200288 kb
Host smart-d98a8f50-bed9-4207-9655-bfd8f8a0cc33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503589815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.3503589815
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.3352371261
Short name T624
Test name
Test status
Simulation time 217146853574 ps
CPU time 202.83 seconds
Started May 02 02:33:39 PM PDT 24
Finished May 02 02:37:04 PM PDT 24
Peak memory 200424 kb
Host smart-efa8b0cc-72d5-47c5-8404-67a71e27e5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352371261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.3352371261
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.3198794294
Short name T574
Test name
Test status
Simulation time 15434566457 ps
CPU time 26.16 seconds
Started May 02 02:33:39 PM PDT 24
Finished May 02 02:34:08 PM PDT 24
Peak memory 200336 kb
Host smart-83405e4b-5ed9-4b6b-89c9-08ba59c855ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198794294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.3198794294
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.2650789684
Short name T214
Test name
Test status
Simulation time 14822060300 ps
CPU time 30.63 seconds
Started May 02 02:33:38 PM PDT 24
Finished May 02 02:34:10 PM PDT 24
Peak memory 200392 kb
Host smart-71aeb489-10bb-44dc-a225-10819fe0fbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650789684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.2650789684
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.2892786800
Short name T391
Test name
Test status
Simulation time 41481668 ps
CPU time 0.52 seconds
Started May 02 02:27:10 PM PDT 24
Finished May 02 02:27:13 PM PDT 24
Peak memory 195776 kb
Host smart-c1faea2f-d363-4535-b6e6-af1389da7e9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892786800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.2892786800
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.3486125167
Short name T279
Test name
Test status
Simulation time 55614778831 ps
CPU time 51.37 seconds
Started May 02 02:27:10 PM PDT 24
Finished May 02 02:28:04 PM PDT 24
Peak memory 200308 kb
Host smart-1dc38254-bdb2-4c3e-a9f6-f08d8fab6d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486125167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.3486125167
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.3597186950
Short name T725
Test name
Test status
Simulation time 58395414668 ps
CPU time 83.1 seconds
Started May 02 02:27:09 PM PDT 24
Finished May 02 02:28:34 PM PDT 24
Peak memory 200340 kb
Host smart-4af696b0-6640-40b1-aca6-ecd49aa64792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597186950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.3597186950
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.1809698567
Short name T612
Test name
Test status
Simulation time 47489005300 ps
CPU time 12.3 seconds
Started May 02 02:27:09 PM PDT 24
Finished May 02 02:27:23 PM PDT 24
Peak memory 200004 kb
Host smart-009ac1ce-e266-410f-89db-d36435087ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809698567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.1809698567
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.4209671197
Short name T788
Test name
Test status
Simulation time 87542702207 ps
CPU time 33.32 seconds
Started May 02 02:27:10 PM PDT 24
Finished May 02 02:27:45 PM PDT 24
Peak memory 196484 kb
Host smart-3cdbb776-13b3-4ebf-8b36-74f15931b180
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209671197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.4209671197
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.3765701048
Short name T778
Test name
Test status
Simulation time 132788700276 ps
CPU time 367.15 seconds
Started May 02 02:27:11 PM PDT 24
Finished May 02 02:33:20 PM PDT 24
Peak memory 200368 kb
Host smart-a175dad9-59ac-46ca-a17e-c11184d1745a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3765701048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.3765701048
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.107237721
Short name T304
Test name
Test status
Simulation time 7629427641 ps
CPU time 6.38 seconds
Started May 02 02:27:11 PM PDT 24
Finished May 02 02:27:20 PM PDT 24
Peak memory 199940 kb
Host smart-6e6b512c-8b72-4400-a18e-a1dd9a3daf3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107237721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.107237721
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.1883602053
Short name T437
Test name
Test status
Simulation time 42088837152 ps
CPU time 16.16 seconds
Started May 02 02:27:11 PM PDT 24
Finished May 02 02:27:29 PM PDT 24
Peak memory 196192 kb
Host smart-4c0a1c4a-c81d-40ed-910d-c9a9eec62272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883602053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.1883602053
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.3656447092
Short name T253
Test name
Test status
Simulation time 35336000494 ps
CPU time 338.26 seconds
Started May 02 02:27:11 PM PDT 24
Finished May 02 02:32:51 PM PDT 24
Peak memory 200436 kb
Host smart-844b4928-a089-45a8-8249-e9d5fe25afcb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3656447092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.3656447092
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.3631991371
Short name T320
Test name
Test status
Simulation time 3214376777 ps
CPU time 23.87 seconds
Started May 02 02:27:12 PM PDT 24
Finished May 02 02:27:38 PM PDT 24
Peak memory 199364 kb
Host smart-e1294840-de24-4863-8470-971c10a1e49c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3631991371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.3631991371
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.2431423240
Short name T997
Test name
Test status
Simulation time 34594698849 ps
CPU time 16.42 seconds
Started May 02 02:27:10 PM PDT 24
Finished May 02 02:27:28 PM PDT 24
Peak memory 200452 kb
Host smart-e9b419ba-b5ad-41a0-9ee2-ac981c8f9bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431423240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.2431423240
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.336515481
Short name T748
Test name
Test status
Simulation time 2307951105 ps
CPU time 4.25 seconds
Started May 02 02:27:11 PM PDT 24
Finished May 02 02:27:17 PM PDT 24
Peak memory 195924 kb
Host smart-c07e2ae5-336c-45d3-856a-b6938b845ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336515481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.336515481
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.1950278655
Short name T818
Test name
Test status
Simulation time 714540706 ps
CPU time 2.87 seconds
Started May 02 02:27:10 PM PDT 24
Finished May 02 02:27:15 PM PDT 24
Peak memory 199360 kb
Host smart-0d43ae28-8e3c-4c87-988c-d52d29a0a399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950278655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.1950278655
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.370571712
Short name T992
Test name
Test status
Simulation time 84240212042 ps
CPU time 182.28 seconds
Started May 02 02:27:11 PM PDT 24
Finished May 02 02:30:15 PM PDT 24
Peak memory 216980 kb
Host smart-4ed1d04c-be22-4bed-a3f9-49a73366f44e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370571712 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.370571712
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.1225852168
Short name T939
Test name
Test status
Simulation time 13045207788 ps
CPU time 14.79 seconds
Started May 02 02:27:11 PM PDT 24
Finished May 02 02:27:28 PM PDT 24
Peak memory 200360 kb
Host smart-a3e69949-2380-45f9-9b01-cd010d505b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225852168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.1225852168
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.3944555247
Short name T474
Test name
Test status
Simulation time 150171017148 ps
CPU time 74.64 seconds
Started May 02 02:27:11 PM PDT 24
Finished May 02 02:28:28 PM PDT 24
Peak memory 200416 kb
Host smart-942c32e4-cbc7-4e84-b31a-afd27def63d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944555247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.3944555247
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.132919481
Short name T511
Test name
Test status
Simulation time 13055534998 ps
CPU time 22.43 seconds
Started May 02 02:33:46 PM PDT 24
Finished May 02 02:34:10 PM PDT 24
Peak memory 200436 kb
Host smart-9c784f97-be9f-496a-9e94-c3670f1423af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132919481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.132919481
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.2343966992
Short name T188
Test name
Test status
Simulation time 120034843027 ps
CPU time 194.07 seconds
Started May 02 02:33:46 PM PDT 24
Finished May 02 02:37:01 PM PDT 24
Peak memory 200420 kb
Host smart-0ebf563c-8fa9-4295-a47e-f0feec07c4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343966992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.2343966992
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.2821408077
Short name T994
Test name
Test status
Simulation time 12745589582 ps
CPU time 29.89 seconds
Started May 02 02:33:49 PM PDT 24
Finished May 02 02:34:20 PM PDT 24
Peak memory 200416 kb
Host smart-e15fd415-7ad7-4eef-8778-b2d269c51b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821408077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.2821408077
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.1096407538
Short name T728
Test name
Test status
Simulation time 25840423770 ps
CPU time 75.47 seconds
Started May 02 02:33:45 PM PDT 24
Finished May 02 02:35:02 PM PDT 24
Peak memory 200344 kb
Host smart-83a5e370-03e3-4d08-ac01-b8efad915aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096407538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.1096407538
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.3655699751
Short name T695
Test name
Test status
Simulation time 42221694059 ps
CPU time 72.27 seconds
Started May 02 02:33:46 PM PDT 24
Finished May 02 02:35:00 PM PDT 24
Peak memory 200404 kb
Host smart-f0481fbe-baed-4a1a-9786-bf8954a22aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655699751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.3655699751
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.701451136
Short name T1018
Test name
Test status
Simulation time 111552073894 ps
CPU time 22.19 seconds
Started May 02 02:33:49 PM PDT 24
Finished May 02 02:34:12 PM PDT 24
Peak memory 200344 kb
Host smart-a7bff96c-d26c-48a1-b150-62b5df0ef302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701451136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.701451136
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.2431134250
Short name T750
Test name
Test status
Simulation time 26467272903 ps
CPU time 13.97 seconds
Started May 02 02:33:46 PM PDT 24
Finished May 02 02:34:02 PM PDT 24
Peak memory 200376 kb
Host smart-231a296c-d09a-4979-9e3c-ff9305c41ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431134250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.2431134250
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.2396221018
Short name T260
Test name
Test status
Simulation time 90725351973 ps
CPU time 57.69 seconds
Started May 02 02:33:49 PM PDT 24
Finished May 02 02:34:48 PM PDT 24
Peak memory 200388 kb
Host smart-7f37338c-fbeb-4bdd-8db6-2e9ca7a50185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396221018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.2396221018
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.714363511
Short name T1104
Test name
Test status
Simulation time 14973606785 ps
CPU time 23.8 seconds
Started May 02 02:33:47 PM PDT 24
Finished May 02 02:34:12 PM PDT 24
Peak memory 199824 kb
Host smart-7f86305b-bf4c-445f-8cba-978aa2692037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714363511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.714363511
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.3081421041
Short name T795
Test name
Test status
Simulation time 22670539233 ps
CPU time 15.52 seconds
Started May 02 02:33:45 PM PDT 24
Finished May 02 02:34:02 PM PDT 24
Peak memory 200432 kb
Host smart-e8d9449a-278b-4e2b-86d0-2d67e19d5159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081421041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.3081421041
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.4193193753
Short name T776
Test name
Test status
Simulation time 34638045 ps
CPU time 0.54 seconds
Started May 02 02:27:21 PM PDT 24
Finished May 02 02:27:24 PM PDT 24
Peak memory 195824 kb
Host smart-911c6ed0-069b-4bd0-a628-dcd3737e8593
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193193753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.4193193753
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.3745995920
Short name T1078
Test name
Test status
Simulation time 62945884324 ps
CPU time 101.1 seconds
Started May 02 02:27:13 PM PDT 24
Finished May 02 02:28:56 PM PDT 24
Peak memory 200420 kb
Host smart-1ff06e2f-7b69-465c-b670-d74d7ad94120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745995920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.3745995920
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.3802521077
Short name T731
Test name
Test status
Simulation time 90331088487 ps
CPU time 563.42 seconds
Started May 02 02:27:23 PM PDT 24
Finished May 02 02:36:50 PM PDT 24
Peak memory 200360 kb
Host smart-0c511215-8e1b-4656-ae52-c294ebf9227b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802521077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.3802521077
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.2523660924
Short name T831
Test name
Test status
Simulation time 13554589323 ps
CPU time 23.9 seconds
Started May 02 02:27:23 PM PDT 24
Finished May 02 02:27:51 PM PDT 24
Peak memory 200392 kb
Host smart-44174555-161b-4c1c-b2d4-6a2e0a835fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523660924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.2523660924
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.189615924
Short name T579
Test name
Test status
Simulation time 21544022368 ps
CPU time 16.47 seconds
Started May 02 02:27:23 PM PDT 24
Finished May 02 02:27:43 PM PDT 24
Peak memory 197296 kb
Host smart-1a81edd6-7b85-48a0-8069-c0660f401f56
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189615924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.189615924
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.1898020707
Short name T249
Test name
Test status
Simulation time 101580195164 ps
CPU time 601.36 seconds
Started May 02 02:27:23 PM PDT 24
Finished May 02 02:37:27 PM PDT 24
Peak memory 200380 kb
Host smart-36dbf506-2362-4645-8df5-9646a3920f7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1898020707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1898020707
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.1888770316
Short name T849
Test name
Test status
Simulation time 4014278026 ps
CPU time 8.3 seconds
Started May 02 02:27:23 PM PDT 24
Finished May 02 02:27:34 PM PDT 24
Peak memory 200308 kb
Host smart-1e3a363f-0ab3-4f5e-a99e-943b4d856f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888770316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.1888770316
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.2652484088
Short name T712
Test name
Test status
Simulation time 169196589059 ps
CPU time 64.29 seconds
Started May 02 02:27:22 PM PDT 24
Finished May 02 02:28:29 PM PDT 24
Peak memory 208816 kb
Host smart-e63fb6c2-4c07-446d-8c1b-8b5e8d0bb9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652484088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.2652484088
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.256579500
Short name T600
Test name
Test status
Simulation time 33693333527 ps
CPU time 406.59 seconds
Started May 02 02:27:22 PM PDT 24
Finished May 02 02:34:12 PM PDT 24
Peak memory 200400 kb
Host smart-536becdb-f53b-4cbd-9100-87647bdc7531
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=256579500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.256579500
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.1516389158
Short name T769
Test name
Test status
Simulation time 4080067037 ps
CPU time 24.59 seconds
Started May 02 02:27:22 PM PDT 24
Finished May 02 02:27:50 PM PDT 24
Peak memory 200356 kb
Host smart-4ab57075-5207-4f11-8e86-aa16b1cbd908
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1516389158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.1516389158
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.2726192697
Short name T541
Test name
Test status
Simulation time 85779231279 ps
CPU time 19.2 seconds
Started May 02 02:27:23 PM PDT 24
Finished May 02 02:27:46 PM PDT 24
Peak memory 200252 kb
Host smart-ae24ea77-f90b-4894-a54d-94957f7e1617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726192697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.2726192697
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.3439810033
Short name T356
Test name
Test status
Simulation time 43165243033 ps
CPU time 20.26 seconds
Started May 02 02:27:22 PM PDT 24
Finished May 02 02:27:46 PM PDT 24
Peak memory 196092 kb
Host smart-35feb757-f87f-4296-8875-d7d5c3da6911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439810033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.3439810033
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.365161657
Short name T355
Test name
Test status
Simulation time 661092573 ps
CPU time 2.03 seconds
Started May 02 02:27:15 PM PDT 24
Finished May 02 02:27:19 PM PDT 24
Peak memory 198784 kb
Host smart-bdb81bcc-33ec-4c70-9a92-af8a72d7b384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365161657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.365161657
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.3933002107
Short name T230
Test name
Test status
Simulation time 433327692130 ps
CPU time 361.54 seconds
Started May 02 02:27:21 PM PDT 24
Finished May 02 02:33:25 PM PDT 24
Peak memory 200412 kb
Host smart-15e11266-56f0-4bbd-8646-57328f01f89e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933002107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.3933002107
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.3859085266
Short name T1173
Test name
Test status
Simulation time 87128773200 ps
CPU time 793.62 seconds
Started May 02 02:27:22 PM PDT 24
Finished May 02 02:40:38 PM PDT 24
Peak memory 225272 kb
Host smart-c424013d-af80-43fc-901c-6d7f5cd21adf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859085266 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.3859085266
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.3187840165
Short name T534
Test name
Test status
Simulation time 6955797633 ps
CPU time 31.52 seconds
Started May 02 02:27:23 PM PDT 24
Finished May 02 02:27:57 PM PDT 24
Peak memory 200264 kb
Host smart-fe1af735-217d-43dc-89b4-a5944be031ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187840165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.3187840165
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.1332548902
Short name T538
Test name
Test status
Simulation time 51993969815 ps
CPU time 67.38 seconds
Started May 02 02:27:11 PM PDT 24
Finished May 02 02:28:21 PM PDT 24
Peak memory 200420 kb
Host smart-e4822fa6-66f4-4d7a-af92-978277579fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332548902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1332548902
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.1814054461
Short name T889
Test name
Test status
Simulation time 40739657035 ps
CPU time 46.66 seconds
Started May 02 02:33:46 PM PDT 24
Finished May 02 02:34:34 PM PDT 24
Peak memory 200420 kb
Host smart-0c81d2a1-2a16-48c5-84a8-67b91ecf77fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814054461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.1814054461
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.41596583
Short name T619
Test name
Test status
Simulation time 57288291250 ps
CPU time 32.76 seconds
Started May 02 02:33:49 PM PDT 24
Finished May 02 02:34:23 PM PDT 24
Peak memory 200368 kb
Host smart-ec24416a-a539-402a-ae3b-14ea8b3a869b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41596583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.41596583
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.4273350825
Short name T182
Test name
Test status
Simulation time 127714596169 ps
CPU time 226.96 seconds
Started May 02 02:33:47 PM PDT 24
Finished May 02 02:37:35 PM PDT 24
Peak memory 200332 kb
Host smart-60a9e8bd-59aa-4b5c-98f0-d30ae7c4c6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273350825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.4273350825
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.4028297009
Short name T828
Test name
Test status
Simulation time 124272953153 ps
CPU time 209.09 seconds
Started May 02 02:33:47 PM PDT 24
Finished May 02 02:37:17 PM PDT 24
Peak memory 200396 kb
Host smart-57184faa-469e-4a6b-9223-269879e7c510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028297009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.4028297009
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.3217475805
Short name T708
Test name
Test status
Simulation time 140414076673 ps
CPU time 301.86 seconds
Started May 02 02:33:49 PM PDT 24
Finished May 02 02:38:52 PM PDT 24
Peak memory 200388 kb
Host smart-abd4d18a-0266-42b9-aa10-2bc845d11f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217475805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.3217475805
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.1963147901
Short name T193
Test name
Test status
Simulation time 23627433545 ps
CPU time 28.7 seconds
Started May 02 02:33:46 PM PDT 24
Finished May 02 02:34:16 PM PDT 24
Peak memory 200400 kb
Host smart-ac302c6f-de0a-4227-8853-ac7a3ece13c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963147901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.1963147901
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.4160295453
Short name T203
Test name
Test status
Simulation time 11518442986 ps
CPU time 17.04 seconds
Started May 02 02:33:47 PM PDT 24
Finished May 02 02:34:06 PM PDT 24
Peak memory 200420 kb
Host smart-3a1d1d4f-f62d-4a35-b531-9320a39532c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160295453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.4160295453
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.2456189953
Short name T292
Test name
Test status
Simulation time 41098796908 ps
CPU time 64.72 seconds
Started May 02 02:33:46 PM PDT 24
Finished May 02 02:34:52 PM PDT 24
Peak memory 200204 kb
Host smart-7cd3565b-7126-42d5-90b2-e16bbda278fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456189953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.2456189953
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.750113443
Short name T596
Test name
Test status
Simulation time 35208334651 ps
CPU time 64.59 seconds
Started May 02 02:33:48 PM PDT 24
Finished May 02 02:34:54 PM PDT 24
Peak memory 200352 kb
Host smart-9515d5da-3ec0-48a8-b0a4-45afbe48ff4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750113443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.750113443
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.632805298
Short name T1057
Test name
Test status
Simulation time 142100957132 ps
CPU time 63.82 seconds
Started May 02 02:33:49 PM PDT 24
Finished May 02 02:34:54 PM PDT 24
Peak memory 200464 kb
Host smart-f50ab3d6-0d14-4a49-9ad1-f31cd393644a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632805298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.632805298
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.3685317650
Short name T360
Test name
Test status
Simulation time 14902616 ps
CPU time 0.56 seconds
Started May 02 02:27:29 PM PDT 24
Finished May 02 02:27:32 PM PDT 24
Peak memory 195804 kb
Host smart-e4bf4f7c-97fe-44c4-9362-6ab497b5a84c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685317650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.3685317650
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.1976651145
Short name T852
Test name
Test status
Simulation time 274120749886 ps
CPU time 258.34 seconds
Started May 02 02:27:21 PM PDT 24
Finished May 02 02:31:42 PM PDT 24
Peak memory 200412 kb
Host smart-43dcacdb-81f0-4986-97bf-35e2c566e5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976651145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.1976651145
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.461025329
Short name T487
Test name
Test status
Simulation time 99385787691 ps
CPU time 142.01 seconds
Started May 02 02:27:22 PM PDT 24
Finished May 02 02:29:47 PM PDT 24
Peak memory 200292 kb
Host smart-42016c30-fb79-40a6-8dca-f17ac312a12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461025329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.461025329
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.673636002
Short name T620
Test name
Test status
Simulation time 24909986702 ps
CPU time 46.39 seconds
Started May 02 02:27:33 PM PDT 24
Finished May 02 02:28:22 PM PDT 24
Peak memory 200364 kb
Host smart-7a336cb7-b0d5-4fcd-9585-c9196fc194cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673636002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.673636002
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.80262840
Short name T587
Test name
Test status
Simulation time 126919160677 ps
CPU time 94.78 seconds
Started May 02 02:27:29 PM PDT 24
Finished May 02 02:29:07 PM PDT 24
Peak memory 200040 kb
Host smart-419a8666-eaff-4a89-be61-8fe20f3477d8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80262840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.80262840
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.42446260
Short name T455
Test name
Test status
Simulation time 32937725458 ps
CPU time 141.19 seconds
Started May 02 02:27:29 PM PDT 24
Finished May 02 02:29:52 PM PDT 24
Peak memory 200436 kb
Host smart-5401b9f3-61e7-4596-ba39-0e06f3cfca6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=42446260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.42446260
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.2361510574
Short name T801
Test name
Test status
Simulation time 9082556903 ps
CPU time 4.08 seconds
Started May 02 02:27:30 PM PDT 24
Finished May 02 02:27:37 PM PDT 24
Peak memory 199336 kb
Host smart-c8dc5bc5-3416-4eb8-9df6-63ba3ea877ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361510574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.2361510574
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.3869595854
Short name T331
Test name
Test status
Simulation time 75919412613 ps
CPU time 38.1 seconds
Started May 02 02:27:30 PM PDT 24
Finished May 02 02:28:11 PM PDT 24
Peak memory 200520 kb
Host smart-bca2ca95-93cd-4cf2-bc0e-868e8cd4ba87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869595854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.3869595854
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.2754847639
Short name T734
Test name
Test status
Simulation time 8343042603 ps
CPU time 229.16 seconds
Started May 02 02:27:30 PM PDT 24
Finished May 02 02:31:22 PM PDT 24
Peak memory 200412 kb
Host smart-dbbf6bb4-9f72-4b13-b086-bdf8b40fb8b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2754847639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2754847639
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.2627663166
Short name T1038
Test name
Test status
Simulation time 5348838933 ps
CPU time 10.98 seconds
Started May 02 02:27:32 PM PDT 24
Finished May 02 02:27:46 PM PDT 24
Peak memory 198492 kb
Host smart-c1d83764-bd9a-4fcb-bc37-25d178d31923
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2627663166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.2627663166
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.3809099855
Short name T453
Test name
Test status
Simulation time 88751521425 ps
CPU time 130.77 seconds
Started May 02 02:27:31 PM PDT 24
Finished May 02 02:29:45 PM PDT 24
Peak memory 200424 kb
Host smart-06083a6c-c723-4546-b1a9-260a7b1502ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809099855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.3809099855
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.3845205283
Short name T10
Test name
Test status
Simulation time 36157380626 ps
CPU time 53.78 seconds
Started May 02 02:27:29 PM PDT 24
Finished May 02 02:28:26 PM PDT 24
Peak memory 196712 kb
Host smart-fd7c18d9-4a6e-435c-890d-f702d72ba999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845205283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.3845205283
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.1292510628
Short name T883
Test name
Test status
Simulation time 5365683412 ps
CPU time 15.68 seconds
Started May 02 02:27:23 PM PDT 24
Finished May 02 02:27:41 PM PDT 24
Peak memory 200212 kb
Host smart-7cca5683-0494-4709-a4f0-ee4d070eb948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292510628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.1292510628
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.915350357
Short name T25
Test name
Test status
Simulation time 21824268139 ps
CPU time 256.81 seconds
Started May 02 02:27:33 PM PDT 24
Finished May 02 02:31:53 PM PDT 24
Peak memory 216868 kb
Host smart-618c8c4e-1f18-46a7-8e71-f0496cd73100
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915350357 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.915350357
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.2292215265
Short name T879
Test name
Test status
Simulation time 6259899482 ps
CPU time 17.91 seconds
Started May 02 02:27:28 PM PDT 24
Finished May 02 02:27:49 PM PDT 24
Peak memory 200360 kb
Host smart-41642668-2078-4a21-879d-9ae28ee7e999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292215265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.2292215265
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.2925284757
Short name T1061
Test name
Test status
Simulation time 55371312183 ps
CPU time 92.48 seconds
Started May 02 02:27:22 PM PDT 24
Finished May 02 02:28:58 PM PDT 24
Peak memory 200372 kb
Host smart-a2a1dab5-d5fb-4f55-8d64-42228ef1e995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925284757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.2925284757
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.1342806722
Short name T209
Test name
Test status
Simulation time 96786460408 ps
CPU time 11.64 seconds
Started May 02 02:33:47 PM PDT 24
Finished May 02 02:34:00 PM PDT 24
Peak memory 200304 kb
Host smart-a726a175-4142-43a1-b982-e43d7b35156a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342806722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.1342806722
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.1404907411
Short name T876
Test name
Test status
Simulation time 10952170877 ps
CPU time 19.56 seconds
Started May 02 02:33:46 PM PDT 24
Finished May 02 02:34:07 PM PDT 24
Peak memory 200336 kb
Host smart-dbcbb404-83a1-4533-892b-f8049732afa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404907411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.1404907411
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.1195598199
Short name T1139
Test name
Test status
Simulation time 82084413462 ps
CPU time 129.02 seconds
Started May 02 02:33:54 PM PDT 24
Finished May 02 02:36:04 PM PDT 24
Peak memory 200388 kb
Host smart-518e370d-9770-4829-9219-597c29a73a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195598199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.1195598199
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.3356934662
Short name T299
Test name
Test status
Simulation time 79486457317 ps
CPU time 28.53 seconds
Started May 02 02:33:53 PM PDT 24
Finished May 02 02:34:23 PM PDT 24
Peak memory 199920 kb
Host smart-3beb4bd2-5b42-4384-9712-18443c26ca24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356934662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.3356934662
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.971657702
Short name T493
Test name
Test status
Simulation time 108955343094 ps
CPU time 469.67 seconds
Started May 02 02:33:53 PM PDT 24
Finished May 02 02:41:44 PM PDT 24
Peak memory 200352 kb
Host smart-4644bb71-f9a9-4767-8002-e16ba2df24f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971657702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.971657702
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.3400654599
Short name T218
Test name
Test status
Simulation time 100242303281 ps
CPU time 89.51 seconds
Started May 02 02:34:01 PM PDT 24
Finished May 02 02:35:32 PM PDT 24
Peak memory 200384 kb
Host smart-98d051df-a080-415d-a1c6-fb482a4b2c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400654599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.3400654599
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.1922698513
Short name T1166
Test name
Test status
Simulation time 13811261531 ps
CPU time 14.45 seconds
Started May 02 02:33:54 PM PDT 24
Finished May 02 02:34:10 PM PDT 24
Peak memory 200392 kb
Host smart-c7ff61a1-ce68-47a5-9877-01a8b6d7c00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922698513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.1922698513
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.4246597583
Short name T232
Test name
Test status
Simulation time 41774453257 ps
CPU time 21.02 seconds
Started May 02 02:33:57 PM PDT 24
Finished May 02 02:34:19 PM PDT 24
Peak memory 200412 kb
Host smart-862a85a0-908e-4955-9d9e-fd64b05deecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246597583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.4246597583
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.1715229242
Short name T116
Test name
Test status
Simulation time 115374151892 ps
CPU time 184.38 seconds
Started May 02 02:33:56 PM PDT 24
Finished May 02 02:37:02 PM PDT 24
Peak memory 200396 kb
Host smart-1195efdb-29da-478d-b0ee-2926aa51dc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715229242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.1715229242
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.2533659263
Short name T155
Test name
Test status
Simulation time 7723236772 ps
CPU time 13.54 seconds
Started May 02 02:33:54 PM PDT 24
Finished May 02 02:34:08 PM PDT 24
Peak memory 200344 kb
Host smart-a06a9433-d9dc-48a6-832a-adf8f97d4806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533659263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.2533659263
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.1551907765
Short name T375
Test name
Test status
Simulation time 44318006 ps
CPU time 0.55 seconds
Started May 02 02:27:38 PM PDT 24
Finished May 02 02:27:41 PM PDT 24
Peak memory 195772 kb
Host smart-aab3fc0f-5199-40ab-b9a5-94c01ac3b866
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551907765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.1551907765
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.2543603831
Short name T839
Test name
Test status
Simulation time 81156556190 ps
CPU time 17.97 seconds
Started May 02 02:27:37 PM PDT 24
Finished May 02 02:27:58 PM PDT 24
Peak memory 200452 kb
Host smart-3dbd2ae7-c540-4ed7-8284-c3d366be34fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543603831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.2543603831
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.3686602761
Short name T746
Test name
Test status
Simulation time 158503535259 ps
CPU time 424.7 seconds
Started May 02 02:27:39 PM PDT 24
Finished May 02 02:34:46 PM PDT 24
Peak memory 200356 kb
Host smart-70212e93-a420-43ad-81dd-d91afe525f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686602761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.3686602761
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.3888786659
Short name T313
Test name
Test status
Simulation time 28914257167 ps
CPU time 50.96 seconds
Started May 02 02:27:38 PM PDT 24
Finished May 02 02:28:32 PM PDT 24
Peak memory 200384 kb
Host smart-699ea424-5381-4b23-a98d-f2a160dbda27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888786659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.3888786659
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.875915644
Short name T642
Test name
Test status
Simulation time 40974498317 ps
CPU time 66.96 seconds
Started May 02 02:27:37 PM PDT 24
Finished May 02 02:28:47 PM PDT 24
Peak memory 200324 kb
Host smart-9bd39502-94c1-40dc-9cfc-b83838729969
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875915644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.875915644
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.2246784558
Short name T766
Test name
Test status
Simulation time 108958429483 ps
CPU time 1077.73 seconds
Started May 02 02:27:39 PM PDT 24
Finished May 02 02:45:39 PM PDT 24
Peak memory 200372 kb
Host smart-ebadddf2-020a-4837-b323-b030c4d04a54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2246784558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2246784558
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.4136408301
Short name T377
Test name
Test status
Simulation time 4203032739 ps
CPU time 3.83 seconds
Started May 02 02:27:38 PM PDT 24
Finished May 02 02:27:44 PM PDT 24
Peak memory 198960 kb
Host smart-1a774922-a63d-4bef-b610-5e3a8bdaf18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136408301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.4136408301
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.2992409870
Short name T586
Test name
Test status
Simulation time 167325302478 ps
CPU time 24.58 seconds
Started May 02 02:27:44 PM PDT 24
Finished May 02 02:28:11 PM PDT 24
Peak memory 216144 kb
Host smart-e89b87db-a7db-4e77-bf93-2ffa33b7f4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992409870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.2992409870
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.3286488275
Short name T811
Test name
Test status
Simulation time 27969231005 ps
CPU time 402.98 seconds
Started May 02 02:27:36 PM PDT 24
Finished May 02 02:34:22 PM PDT 24
Peak memory 200416 kb
Host smart-5a2edb11-3769-4f5d-b151-30d1c7754088
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3286488275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.3286488275
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.3302721281
Short name T408
Test name
Test status
Simulation time 4708346943 ps
CPU time 37.2 seconds
Started May 02 02:27:44 PM PDT 24
Finished May 02 02:28:24 PM PDT 24
Peak memory 198684 kb
Host smart-4d9bfe94-1908-4288-8da6-f1425e5e2050
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3302721281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.3302721281
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.1042203725
Short name T850
Test name
Test status
Simulation time 21335020358 ps
CPU time 13.45 seconds
Started May 02 02:27:43 PM PDT 24
Finished May 02 02:27:58 PM PDT 24
Peak memory 200308 kb
Host smart-63dacc37-4f13-4c7b-a35e-1e00d367009e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042203725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.1042203725
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.1335083407
Short name T575
Test name
Test status
Simulation time 1954868990 ps
CPU time 1.49 seconds
Started May 02 02:27:36 PM PDT 24
Finished May 02 02:27:40 PM PDT 24
Peak memory 195796 kb
Host smart-f8f09d4e-edb1-43c1-9383-fe830c841a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335083407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.1335083407
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.3713761335
Short name T332
Test name
Test status
Simulation time 89708257 ps
CPU time 0.86 seconds
Started May 02 02:27:29 PM PDT 24
Finished May 02 02:27:32 PM PDT 24
Peak memory 197396 kb
Host smart-364f650b-7a56-4a3c-b257-5b1b2183d895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713761335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.3713761335
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.949163838
Short name T1012
Test name
Test status
Simulation time 461881959020 ps
CPU time 498.04 seconds
Started May 02 02:27:39 PM PDT 24
Finished May 02 02:36:00 PM PDT 24
Peak memory 200424 kb
Host smart-8027014e-5e2c-4595-83be-ac9fb1f84ef1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949163838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.949163838
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.3201848048
Short name T1080
Test name
Test status
Simulation time 39580644424 ps
CPU time 217.66 seconds
Started May 02 02:27:37 PM PDT 24
Finished May 02 02:31:18 PM PDT 24
Peak memory 217076 kb
Host smart-4f1657b1-0bbc-420b-83c0-95bcad4665e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201848048 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.3201848048
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.3066322662
Short name T425
Test name
Test status
Simulation time 1194395255 ps
CPU time 2.14 seconds
Started May 02 02:27:44 PM PDT 24
Finished May 02 02:27:49 PM PDT 24
Peak memory 198960 kb
Host smart-16c8ea49-8b13-4c75-8f83-3a95fbe54c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066322662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.3066322662
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.3596843310
Short name T1134
Test name
Test status
Simulation time 117872967083 ps
CPU time 143.06 seconds
Started May 02 02:27:31 PM PDT 24
Finished May 02 02:29:58 PM PDT 24
Peak memory 200336 kb
Host smart-4202cdc2-aef1-4362-ac7f-333618923da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596843310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.3596843310
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.499791933
Short name T365
Test name
Test status
Simulation time 30297972821 ps
CPU time 32.19 seconds
Started May 02 02:33:53 PM PDT 24
Finished May 02 02:34:27 PM PDT 24
Peak memory 200396 kb
Host smart-dbe05f3a-9108-4df2-8f87-0ffbd57b5443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499791933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.499791933
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.3871307187
Short name T525
Test name
Test status
Simulation time 142250788993 ps
CPU time 62 seconds
Started May 02 02:33:56 PM PDT 24
Finished May 02 02:34:59 PM PDT 24
Peak memory 200392 kb
Host smart-5a26ccfc-3b1b-45b4-818b-291ffbd9eb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871307187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.3871307187
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.199424763
Short name T470
Test name
Test status
Simulation time 290044528491 ps
CPU time 57.42 seconds
Started May 02 02:33:55 PM PDT 24
Finished May 02 02:34:54 PM PDT 24
Peak memory 200444 kb
Host smart-08b9f99f-3861-4672-86c3-8db2f73c362b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199424763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.199424763
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.1076894490
Short name T171
Test name
Test status
Simulation time 10502637112 ps
CPU time 17.98 seconds
Started May 02 02:33:54 PM PDT 24
Finished May 02 02:34:13 PM PDT 24
Peak memory 200060 kb
Host smart-73e25c74-7a3a-4150-b0e8-6940a641a438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076894490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.1076894490
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.3876823931
Short name T582
Test name
Test status
Simulation time 61888101594 ps
CPU time 46.48 seconds
Started May 02 02:33:58 PM PDT 24
Finished May 02 02:34:46 PM PDT 24
Peak memory 200360 kb
Host smart-b093ed6e-77fb-49ca-ade4-8de7b2c8a6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876823931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.3876823931
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.896188967
Short name T594
Test name
Test status
Simulation time 145033059137 ps
CPU time 260.99 seconds
Started May 02 02:33:53 PM PDT 24
Finished May 02 02:38:16 PM PDT 24
Peak memory 200428 kb
Host smart-14b1d016-1b01-49db-af11-9772cfc03bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896188967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.896188967
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.505481149
Short name T915
Test name
Test status
Simulation time 97282649836 ps
CPU time 78 seconds
Started May 02 02:33:53 PM PDT 24
Finished May 02 02:35:12 PM PDT 24
Peak memory 200372 kb
Host smart-0d4dc111-0543-420c-a404-0e3ce197ed98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505481149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.505481149
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.1191734029
Short name T238
Test name
Test status
Simulation time 94607795655 ps
CPU time 45.02 seconds
Started May 02 02:33:54 PM PDT 24
Finished May 02 02:34:40 PM PDT 24
Peak memory 200380 kb
Host smart-57e8ab93-4bf1-4a1d-9461-eb18020405d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191734029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.1191734029
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.1263814677
Short name T514
Test name
Test status
Simulation time 65278329716 ps
CPU time 52.17 seconds
Started May 02 02:33:57 PM PDT 24
Finished May 02 02:34:50 PM PDT 24
Peak memory 200164 kb
Host smart-3d84e700-1977-4028-8e42-b0d2780f35ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263814677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.1263814677
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.1413188430
Short name T716
Test name
Test status
Simulation time 20472110 ps
CPU time 0.57 seconds
Started May 02 02:27:47 PM PDT 24
Finished May 02 02:27:50 PM PDT 24
Peak memory 195776 kb
Host smart-529abc89-82b5-4d73-b53e-1e760cfed6d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413188430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.1413188430
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.4164555241
Short name T942
Test name
Test status
Simulation time 159397209705 ps
CPU time 133.41 seconds
Started May 02 02:27:45 PM PDT 24
Finished May 02 02:30:01 PM PDT 24
Peak memory 200420 kb
Host smart-73ab829c-f7f5-4323-8286-c415deb3f363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164555241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.4164555241
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.1113028427
Short name T808
Test name
Test status
Simulation time 144720834812 ps
CPU time 231.6 seconds
Started May 02 02:27:53 PM PDT 24
Finished May 02 02:31:47 PM PDT 24
Peak memory 200396 kb
Host smart-43c20ec1-dd2b-428a-9251-53c0355001b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113028427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.1113028427
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_intr.2204639749
Short name T675
Test name
Test status
Simulation time 48482484284 ps
CPU time 73.38 seconds
Started May 02 02:27:44 PM PDT 24
Finished May 02 02:29:00 PM PDT 24
Peak memory 200420 kb
Host smart-caa31524-4836-4c1e-a692-0ef4f36640ca
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204639749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.2204639749
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.530867196
Short name T561
Test name
Test status
Simulation time 70851942430 ps
CPU time 419.22 seconds
Started May 02 02:27:45 PM PDT 24
Finished May 02 02:34:47 PM PDT 24
Peak memory 200408 kb
Host smart-a28b5e66-b7fc-45b7-882f-8691685266c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=530867196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.530867196
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.229979943
Short name T1003
Test name
Test status
Simulation time 2802410498 ps
CPU time 3.22 seconds
Started May 02 02:27:46 PM PDT 24
Finished May 02 02:27:52 PM PDT 24
Peak memory 197780 kb
Host smart-10a0c14d-53cb-4cc7-952e-6e9636465e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229979943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.229979943
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.3098437791
Short name T1158
Test name
Test status
Simulation time 6572725043 ps
CPU time 12.23 seconds
Started May 02 02:27:47 PM PDT 24
Finished May 02 02:28:02 PM PDT 24
Peak memory 196428 kb
Host smart-fe9d9f11-26e9-4add-9dbc-2bbf66734d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098437791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.3098437791
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.2251694233
Short name T315
Test name
Test status
Simulation time 10114618806 ps
CPU time 608.03 seconds
Started May 02 02:27:47 PM PDT 24
Finished May 02 02:37:57 PM PDT 24
Peak memory 200332 kb
Host smart-ffa883e2-1479-4eba-9ed4-454edece7b1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2251694233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.2251694233
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.3663265063
Short name T869
Test name
Test status
Simulation time 4879323573 ps
CPU time 42.68 seconds
Started May 02 02:27:45 PM PDT 24
Finished May 02 02:28:31 PM PDT 24
Peak memory 198512 kb
Host smart-d05be2b1-cb24-4d4d-a1ef-4f55c8a47359
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3663265063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.3663265063
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.723968265
Short name T1076
Test name
Test status
Simulation time 21968276729 ps
CPU time 34.92 seconds
Started May 02 02:27:47 PM PDT 24
Finished May 02 02:28:24 PM PDT 24
Peak memory 200360 kb
Host smart-357dd75a-d4b8-4ee9-ab21-18efaad78ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723968265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.723968265
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.331581594
Short name T418
Test name
Test status
Simulation time 24958218255 ps
CPU time 43.8 seconds
Started May 02 02:27:45 PM PDT 24
Finished May 02 02:28:32 PM PDT 24
Peak memory 195344 kb
Host smart-ec8be900-b325-425d-aeac-2ec13ee99536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331581594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.331581594
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.1106249584
Short name T350
Test name
Test status
Simulation time 665199735 ps
CPU time 2.81 seconds
Started May 02 02:27:44 PM PDT 24
Finished May 02 02:27:48 PM PDT 24
Peak memory 198916 kb
Host smart-7a839c20-add0-44b3-80e9-a96229068f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106249584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1106249584
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.2968752740
Short name T175
Test name
Test status
Simulation time 292274644178 ps
CPU time 706.37 seconds
Started May 02 02:27:47 PM PDT 24
Finished May 02 02:39:35 PM PDT 24
Peak memory 200400 kb
Host smart-10bbc025-4bdc-4e83-ab04-2a06cabee48e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968752740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.2968752740
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.138392412
Short name T1056
Test name
Test status
Simulation time 16011542826 ps
CPU time 197.48 seconds
Started May 02 02:27:45 PM PDT 24
Finished May 02 02:31:04 PM PDT 24
Peak memory 208720 kb
Host smart-8e4ef7e8-f77b-4d2a-aa52-775440ecf14a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138392412 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.138392412
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.378262263
Short name T1106
Test name
Test status
Simulation time 12106741277 ps
CPU time 16.85 seconds
Started May 02 02:27:45 PM PDT 24
Finished May 02 02:28:05 PM PDT 24
Peak memory 200332 kb
Host smart-acc78bf0-c08d-46cd-aa7e-41328e966e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378262263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.378262263
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.1099195291
Short name T268
Test name
Test status
Simulation time 52129938508 ps
CPU time 32.28 seconds
Started May 02 02:27:44 PM PDT 24
Finished May 02 02:28:18 PM PDT 24
Peak memory 200360 kb
Host smart-7bf7ae41-1369-43be-a2c2-e3f07746a6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099195291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.1099195291
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.314984613
Short name T312
Test name
Test status
Simulation time 91688811697 ps
CPU time 83.54 seconds
Started May 02 02:34:01 PM PDT 24
Finished May 02 02:35:26 PM PDT 24
Peak memory 200416 kb
Host smart-c9bccbb1-1fdf-4a43-a877-a94bf6f4cc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314984613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.314984613
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1288723445
Short name T239
Test name
Test status
Simulation time 47608543694 ps
CPU time 11.25 seconds
Started May 02 02:34:10 PM PDT 24
Finished May 02 02:34:23 PM PDT 24
Peak memory 200372 kb
Host smart-aadfb75f-e2c9-45a5-bd5f-13ef997830b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288723445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1288723445
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.3071706653
Short name T471
Test name
Test status
Simulation time 6441149742 ps
CPU time 17.59 seconds
Started May 02 02:34:10 PM PDT 24
Finished May 02 02:34:29 PM PDT 24
Peak memory 200428 kb
Host smart-dda0a425-1816-4bd7-8d87-8df9dabedef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071706653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.3071706653
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.3853255372
Short name T576
Test name
Test status
Simulation time 117779151660 ps
CPU time 204.55 seconds
Started May 02 02:34:02 PM PDT 24
Finished May 02 02:37:28 PM PDT 24
Peak memory 200360 kb
Host smart-0fa88fdd-c111-41ed-8040-dc15714d4ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853255372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.3853255372
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.2119487450
Short name T891
Test name
Test status
Simulation time 133144552011 ps
CPU time 231.38 seconds
Started May 02 02:34:02 PM PDT 24
Finished May 02 02:37:55 PM PDT 24
Peak memory 200404 kb
Host smart-66869e46-6431-4000-a184-9c7379b8d2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119487450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2119487450
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.4185117671
Short name T569
Test name
Test status
Simulation time 116306464271 ps
CPU time 41.76 seconds
Started May 02 02:34:10 PM PDT 24
Finished May 02 02:34:53 PM PDT 24
Peak memory 200332 kb
Host smart-170e8fc4-2cce-4b59-8d5e-5620ff81b4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185117671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.4185117671
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.675787508
Short name T289
Test name
Test status
Simulation time 86021350018 ps
CPU time 186.44 seconds
Started May 02 02:34:02 PM PDT 24
Finished May 02 02:37:10 PM PDT 24
Peak memory 200376 kb
Host smart-718d3b67-80ef-4a5a-8fc2-e59db7ba132f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675787508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.675787508
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.996816527
Short name T1077
Test name
Test status
Simulation time 40854273878 ps
CPU time 77.06 seconds
Started May 02 02:34:05 PM PDT 24
Finished May 02 02:35:23 PM PDT 24
Peak memory 200360 kb
Host smart-6e21718b-d40a-4ac4-9ae3-2b51cd4a8d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996816527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.996816527
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.3469417799
Short name T595
Test name
Test status
Simulation time 47629018316 ps
CPU time 21.42 seconds
Started May 02 02:34:03 PM PDT 24
Finished May 02 02:34:26 PM PDT 24
Peak memory 200436 kb
Host smart-b1394e9f-5bcd-4de9-8455-89ac21b12376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469417799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3469417799
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.1114791117
Short name T466
Test name
Test status
Simulation time 11831559 ps
CPU time 0.57 seconds
Started May 02 02:24:49 PM PDT 24
Finished May 02 02:24:53 PM PDT 24
Peak memory 195800 kb
Host smart-f98e53ae-3b4d-4497-b2e6-95e183d6284c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114791117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1114791117
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.3436226625
Short name T848
Test name
Test status
Simulation time 62259329979 ps
CPU time 94.59 seconds
Started May 02 02:24:37 PM PDT 24
Finished May 02 02:26:15 PM PDT 24
Peak memory 200396 kb
Host smart-25bd092b-5ef4-4a9d-a870-c617042a8499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436226625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.3436226625
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.1771942753
Short name T789
Test name
Test status
Simulation time 111882866380 ps
CPU time 45.92 seconds
Started May 02 02:24:44 PM PDT 24
Finished May 02 02:25:34 PM PDT 24
Peak memory 200284 kb
Host smart-5420531f-af87-49dd-b419-2a28860342c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771942753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.1771942753
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_intr.2669983370
Short name T1085
Test name
Test status
Simulation time 40905530417 ps
CPU time 20.6 seconds
Started May 02 02:24:38 PM PDT 24
Finished May 02 02:25:03 PM PDT 24
Peak memory 200340 kb
Host smart-bd8f0319-f6ef-4803-b9cc-f9cd6e8ae305
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669983370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.2669983370
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.2613442442
Short name T252
Test name
Test status
Simulation time 197578298970 ps
CPU time 330.12 seconds
Started May 02 02:24:48 PM PDT 24
Finished May 02 02:30:22 PM PDT 24
Peak memory 200408 kb
Host smart-f8be5c39-e0e8-45a6-859b-6d3a22619b46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2613442442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.2613442442
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.2200088903
Short name T1042
Test name
Test status
Simulation time 7997941562 ps
CPU time 7.74 seconds
Started May 02 02:24:39 PM PDT 24
Finished May 02 02:24:51 PM PDT 24
Peak memory 200412 kb
Host smart-71dfcf64-a0cc-4ea5-9e0f-5978def1ab2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200088903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.2200088903
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.1399983250
Short name T473
Test name
Test status
Simulation time 69889209079 ps
CPU time 30.09 seconds
Started May 02 02:24:38 PM PDT 24
Finished May 02 02:25:12 PM PDT 24
Peak memory 200340 kb
Host smart-052af9da-c3c4-46e2-b9aa-828c34ec857c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399983250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.1399983250
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.1091562402
Short name T970
Test name
Test status
Simulation time 7735222978 ps
CPU time 466.37 seconds
Started May 02 02:24:39 PM PDT 24
Finished May 02 02:32:30 PM PDT 24
Peak memory 200420 kb
Host smart-522e1f53-8c58-45b7-bdac-d9af38a84f76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1091562402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.1091562402
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.2894096860
Short name T827
Test name
Test status
Simulation time 4456883712 ps
CPU time 18.26 seconds
Started May 02 02:24:41 PM PDT 24
Finished May 02 02:25:03 PM PDT 24
Peak memory 198492 kb
Host smart-c88a7cf2-6a80-4d6d-843f-2d1af89f98a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2894096860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.2894096860
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.722381746
Short name T383
Test name
Test status
Simulation time 156476268395 ps
CPU time 72.25 seconds
Started May 02 02:24:39 PM PDT 24
Finished May 02 02:25:56 PM PDT 24
Peak memory 199796 kb
Host smart-56bcb848-5f6d-4373-b2b3-781820bd83c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722381746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.722381746
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.872752018
Short name T446
Test name
Test status
Simulation time 4326712390 ps
CPU time 2.42 seconds
Started May 02 02:24:38 PM PDT 24
Finished May 02 02:24:44 PM PDT 24
Peak memory 196716 kb
Host smart-83cfcbc5-b77e-4720-a351-4131e0b9f1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872752018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.872752018
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.1270735703
Short name T23
Test name
Test status
Simulation time 38865040 ps
CPU time 0.79 seconds
Started May 02 02:24:45 PM PDT 24
Finished May 02 02:24:49 PM PDT 24
Peak memory 218636 kb
Host smart-4cb73fc6-0719-496c-a5bd-e41393e186cc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270735703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.1270735703
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.2433450465
Short name T354
Test name
Test status
Simulation time 717002003 ps
CPU time 1.51 seconds
Started May 02 02:24:41 PM PDT 24
Finished May 02 02:24:47 PM PDT 24
Peak memory 199628 kb
Host smart-c0fff011-e174-4ac4-b15c-a01cc2b46457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433450465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.2433450465
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.2378210304
Short name T684
Test name
Test status
Simulation time 172908474245 ps
CPU time 460.52 seconds
Started May 02 02:24:47 PM PDT 24
Finished May 02 02:32:32 PM PDT 24
Peak memory 216844 kb
Host smart-50621807-d2c7-4c85-8065-38bede206061
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378210304 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.2378210304
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.3699481371
Short name T717
Test name
Test status
Simulation time 894841629 ps
CPU time 3.18 seconds
Started May 02 02:24:44 PM PDT 24
Finished May 02 02:24:51 PM PDT 24
Peak memory 200040 kb
Host smart-4d50c731-618d-4898-ab19-034d29a73a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699481371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.3699481371
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.2680778557
Short name T45
Test name
Test status
Simulation time 49682047767 ps
CPU time 42.79 seconds
Started May 02 02:24:40 PM PDT 24
Finished May 02 02:25:27 PM PDT 24
Peak memory 200320 kb
Host smart-9b932624-0c3f-4294-89a7-cef38e324e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680778557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.2680778557
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.2015431016
Short name T560
Test name
Test status
Simulation time 14996378 ps
CPU time 0.53 seconds
Started May 02 02:27:53 PM PDT 24
Finished May 02 02:27:56 PM PDT 24
Peak memory 195284 kb
Host smart-256710f1-7a0e-4152-8548-bd9114cc36ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015431016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.2015431016
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.3908654027
Short name T898
Test name
Test status
Simulation time 46810759642 ps
CPU time 35.07 seconds
Started May 02 02:27:50 PM PDT 24
Finished May 02 02:28:27 PM PDT 24
Peak memory 200352 kb
Host smart-2698f03d-4fdb-4d70-87ae-38c321beac19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908654027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3908654027
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.3712274940
Short name T152
Test name
Test status
Simulation time 10440721870 ps
CPU time 17.6 seconds
Started May 02 02:27:45 PM PDT 24
Finished May 02 02:28:06 PM PDT 24
Peak memory 199544 kb
Host smart-29fb285c-fa31-4eb1-8115-15a0ccbb7d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712274940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.3712274940
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.1361598902
Short name T194
Test name
Test status
Simulation time 14394294442 ps
CPU time 26.17 seconds
Started May 02 02:27:46 PM PDT 24
Finished May 02 02:28:14 PM PDT 24
Peak memory 200424 kb
Host smart-a6ef23db-b116-4426-8d34-0d5926914536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361598902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.1361598902
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.1872062852
Short name T1152
Test name
Test status
Simulation time 56113764325 ps
CPU time 55.19 seconds
Started May 02 02:27:55 PM PDT 24
Finished May 02 02:28:52 PM PDT 24
Peak memory 200364 kb
Host smart-f9366ebc-86d6-426a-984e-efd33e28e5d8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872062852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.1872062852
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.1294456
Short name T932
Test name
Test status
Simulation time 96970833281 ps
CPU time 421.19 seconds
Started May 02 02:27:53 PM PDT 24
Finished May 02 02:34:56 PM PDT 24
Peak memory 200436 kb
Host smart-fc69346f-1d0c-4ec4-93ed-a856e68cc1ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1294456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1294456
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.3461700740
Short name T614
Test name
Test status
Simulation time 1119516534 ps
CPU time 3.26 seconds
Started May 02 02:27:54 PM PDT 24
Finished May 02 02:28:00 PM PDT 24
Peak memory 197680 kb
Host smart-4b1a998d-a347-40b2-98ec-d48e79e19098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461700740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.3461700740
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.1878707110
Short name T572
Test name
Test status
Simulation time 41342730918 ps
CPU time 76.11 seconds
Started May 02 02:27:53 PM PDT 24
Finished May 02 02:29:11 PM PDT 24
Peak memory 200660 kb
Host smart-5a67d7cb-bca6-4ee9-b59f-3c7ee1f1c776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878707110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.1878707110
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.2081418916
Short name T692
Test name
Test status
Simulation time 12495506418 ps
CPU time 126.82 seconds
Started May 02 02:27:53 PM PDT 24
Finished May 02 02:30:02 PM PDT 24
Peak memory 200312 kb
Host smart-01f6bc94-d1bc-47a7-9100-3f6d0604baf4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2081418916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.2081418916
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.3533465105
Short name T536
Test name
Test status
Simulation time 1384568740 ps
CPU time 3.07 seconds
Started May 02 02:27:44 PM PDT 24
Finished May 02 02:27:50 PM PDT 24
Peak memory 198472 kb
Host smart-138e446a-dd81-4cfa-be7d-c8ece8f683fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3533465105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.3533465105
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.1698984856
Short name T640
Test name
Test status
Simulation time 122396119971 ps
CPU time 29.47 seconds
Started May 02 02:27:52 PM PDT 24
Finished May 02 02:28:24 PM PDT 24
Peak memory 200252 kb
Host smart-7e72b218-5ecc-40a2-9975-274eee766a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698984856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.1698984856
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.429650689
Short name T398
Test name
Test status
Simulation time 4702002970 ps
CPU time 4.61 seconds
Started May 02 02:27:55 PM PDT 24
Finished May 02 02:28:02 PM PDT 24
Peak memory 196440 kb
Host smart-617dc83c-ca5a-4f23-8131-471216964415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429650689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.429650689
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.2448425817
Short name T947
Test name
Test status
Simulation time 710251980 ps
CPU time 3.17 seconds
Started May 02 02:27:46 PM PDT 24
Finished May 02 02:27:52 PM PDT 24
Peak memory 198736 kb
Host smart-a8c55d27-bcb7-41fe-9733-f2aae03a96eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448425817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.2448425817
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.3655856338
Short name T907
Test name
Test status
Simulation time 73839874891 ps
CPU time 29.16 seconds
Started May 02 02:27:54 PM PDT 24
Finished May 02 02:28:25 PM PDT 24
Peak memory 200348 kb
Host smart-4dc6b5fd-2977-4c00-9acb-f08670387be9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655856338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.3655856338
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.586364089
Short name T445
Test name
Test status
Simulation time 159387064993 ps
CPU time 696.16 seconds
Started May 02 02:27:56 PM PDT 24
Finished May 02 02:39:35 PM PDT 24
Peak memory 217028 kb
Host smart-3d77f7a5-76bc-4218-8f08-c0bdfe38295d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586364089 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.586364089
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.3492339722
Short name T1002
Test name
Test status
Simulation time 6692468411 ps
CPU time 13.27 seconds
Started May 02 02:27:54 PM PDT 24
Finished May 02 02:28:10 PM PDT 24
Peak memory 200392 kb
Host smart-ecf86e0a-8d06-483b-8caa-33cb4cad83b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492339722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.3492339722
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.1807267443
Short name T817
Test name
Test status
Simulation time 32190376200 ps
CPU time 29.47 seconds
Started May 02 02:27:50 PM PDT 24
Finished May 02 02:28:22 PM PDT 24
Peak memory 200428 kb
Host smart-62679dd0-9302-44f2-9cb6-80f0368848f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807267443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.1807267443
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.3235920189
Short name T1075
Test name
Test status
Simulation time 21854756 ps
CPU time 0.55 seconds
Started May 02 02:28:05 PM PDT 24
Finished May 02 02:28:07 PM PDT 24
Peak memory 195824 kb
Host smart-8d7c4877-78b9-4162-919b-f798bbf70e06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235920189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.3235920189
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.994035043
Short name T1055
Test name
Test status
Simulation time 20879412753 ps
CPU time 10.69 seconds
Started May 02 02:27:53 PM PDT 24
Finished May 02 02:28:06 PM PDT 24
Peak memory 200340 kb
Host smart-1fdbfb66-d84e-44fe-bba3-f3f7ea2325e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994035043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.994035043
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.1877065248
Short name T944
Test name
Test status
Simulation time 19621998526 ps
CPU time 17.73 seconds
Started May 02 02:27:53 PM PDT 24
Finished May 02 02:28:13 PM PDT 24
Peak memory 200308 kb
Host smart-3ff17f89-e8b2-497b-83fd-ca2914a51d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877065248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.1877065248
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.1125052418
Short name T986
Test name
Test status
Simulation time 26758430113 ps
CPU time 51.79 seconds
Started May 02 02:27:55 PM PDT 24
Finished May 02 02:28:50 PM PDT 24
Peak memory 200404 kb
Host smart-48cd221b-d113-45a5-84f0-2e864602d7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125052418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.1125052418
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.4230581724
Short name T346
Test name
Test status
Simulation time 39947279330 ps
CPU time 60.49 seconds
Started May 02 02:27:54 PM PDT 24
Finished May 02 02:28:57 PM PDT 24
Peak memory 200436 kb
Host smart-ef42bf06-feeb-4245-abde-76bca19b87cf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230581724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.4230581724
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.767148985
Short name T865
Test name
Test status
Simulation time 146689675889 ps
CPU time 1197.59 seconds
Started May 02 02:28:01 PM PDT 24
Finished May 02 02:48:00 PM PDT 24
Peak memory 200372 kb
Host smart-3851c689-c9bb-48c6-a231-4e33261a2bad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=767148985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.767148985
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.2571171448
Short name T1091
Test name
Test status
Simulation time 3738171549 ps
CPU time 11.92 seconds
Started May 02 02:27:55 PM PDT 24
Finished May 02 02:28:09 PM PDT 24
Peak memory 199620 kb
Host smart-d52e968f-8c22-4941-9b2b-ee96f7f4e186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571171448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.2571171448
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.2433589393
Short name T829
Test name
Test status
Simulation time 24404754883 ps
CPU time 25.73 seconds
Started May 02 02:27:54 PM PDT 24
Finished May 02 02:28:22 PM PDT 24
Peak memory 200544 kb
Host smart-10997888-183c-4184-ae51-d629fb16ce1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433589393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.2433589393
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.662410690
Short name T983
Test name
Test status
Simulation time 20065377061 ps
CPU time 199.2 seconds
Started May 02 02:27:54 PM PDT 24
Finished May 02 02:31:15 PM PDT 24
Peak memory 200312 kb
Host smart-69f53ca2-f50b-4498-b848-669f02b71b53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=662410690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.662410690
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.4286685002
Short name T388
Test name
Test status
Simulation time 7366557494 ps
CPU time 13.58 seconds
Started May 02 02:27:54 PM PDT 24
Finished May 02 02:28:10 PM PDT 24
Peak memory 200360 kb
Host smart-8bb3e1fe-1da1-4059-b06e-6700fb3f0261
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4286685002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.4286685002
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.760224954
Short name T141
Test name
Test status
Simulation time 217764555158 ps
CPU time 23.02 seconds
Started May 02 02:27:54 PM PDT 24
Finished May 02 02:28:19 PM PDT 24
Peak memory 200288 kb
Host smart-6cfd8338-7183-46fc-9bb6-97e85666a3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760224954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.760224954
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.3529260406
Short name T899
Test name
Test status
Simulation time 2012817447 ps
CPU time 2.01 seconds
Started May 02 02:27:54 PM PDT 24
Finished May 02 02:27:58 PM PDT 24
Peak memory 196088 kb
Host smart-0b9ea1c5-7926-4633-bce3-b532088fbdf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529260406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.3529260406
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.1719797605
Short name T1122
Test name
Test status
Simulation time 444106130 ps
CPU time 1.89 seconds
Started May 02 02:27:54 PM PDT 24
Finished May 02 02:27:58 PM PDT 24
Peak memory 200092 kb
Host smart-54aad2b4-1712-45a0-97b6-f28b6f670eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719797605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.1719797605
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.993459057
Short name T1155
Test name
Test status
Simulation time 37200002553 ps
CPU time 109.22 seconds
Started May 02 02:28:02 PM PDT 24
Finished May 02 02:29:53 PM PDT 24
Peak memory 200380 kb
Host smart-17396163-abbc-4cc4-99ca-0cf5c13e6c23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993459057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.993459057
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.2903036214
Short name T55
Test name
Test status
Simulation time 54174464073 ps
CPU time 472.56 seconds
Started May 02 02:28:02 PM PDT 24
Finished May 02 02:35:56 PM PDT 24
Peak memory 208672 kb
Host smart-5114a910-383f-4ee4-8fa5-2aa56d12315d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903036214 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.2903036214
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.2267274104
Short name T357
Test name
Test status
Simulation time 580886761 ps
CPU time 2.27 seconds
Started May 02 02:27:54 PM PDT 24
Finished May 02 02:27:58 PM PDT 24
Peak memory 198760 kb
Host smart-6b70c534-2b12-4868-9c0b-c75e803b6a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267274104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.2267274104
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.45491632
Short name T447
Test name
Test status
Simulation time 62601468181 ps
CPU time 63.05 seconds
Started May 02 02:27:55 PM PDT 24
Finished May 02 02:29:01 PM PDT 24
Peak memory 200388 kb
Host smart-8920fce4-d2c5-4452-aeb0-0550b61362e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45491632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.45491632
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.1437470751
Short name T663
Test name
Test status
Simulation time 23823380 ps
CPU time 0.55 seconds
Started May 02 02:28:08 PM PDT 24
Finished May 02 02:28:09 PM PDT 24
Peak memory 195784 kb
Host smart-273e083f-aa00-4ab4-bc9c-e966d038eefe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437470751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.1437470751
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.3177977082
Short name T690
Test name
Test status
Simulation time 201895699518 ps
CPU time 91.05 seconds
Started May 02 02:28:00 PM PDT 24
Finished May 02 02:29:33 PM PDT 24
Peak memory 200364 kb
Host smart-0b72f125-0609-475c-8a05-5e91f6db86cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177977082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.3177977082
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.189677789
Short name T149
Test name
Test status
Simulation time 33919325351 ps
CPU time 17.46 seconds
Started May 02 02:28:02 PM PDT 24
Finished May 02 02:28:21 PM PDT 24
Peak memory 200336 kb
Host smart-ce570bc3-a02f-40a7-853a-27a9d4fd1663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189677789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.189677789
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.2906131722
Short name T367
Test name
Test status
Simulation time 29693145647 ps
CPU time 13.19 seconds
Started May 02 02:28:00 PM PDT 24
Finished May 02 02:28:15 PM PDT 24
Peak memory 200328 kb
Host smart-fddb94b9-16f3-43c3-aa8a-54fe80ff0060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906131722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.2906131722
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.2403173898
Short name T634
Test name
Test status
Simulation time 11980428177 ps
CPU time 9.38 seconds
Started May 02 02:28:05 PM PDT 24
Finished May 02 02:28:16 PM PDT 24
Peak memory 197500 kb
Host smart-3750a6ed-d8bf-4f0d-b9ea-cb135dc4477f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403173898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.2403173898
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.2526433654
Short name T553
Test name
Test status
Simulation time 37763040338 ps
CPU time 194.22 seconds
Started May 02 02:28:09 PM PDT 24
Finished May 02 02:31:25 PM PDT 24
Peak memory 200332 kb
Host smart-70b4e1e2-7388-4ab1-8364-6aa375956d5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2526433654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.2526433654
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.2586664342
Short name T861
Test name
Test status
Simulation time 13236232942 ps
CPU time 31.73 seconds
Started May 02 02:28:09 PM PDT 24
Finished May 02 02:28:43 PM PDT 24
Peak memory 200404 kb
Host smart-c0cac371-e0f9-4a0e-b8f5-18c6b13de5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586664342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.2586664342
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.71450735
Short name T998
Test name
Test status
Simulation time 146010105290 ps
CPU time 59.92 seconds
Started May 02 02:28:01 PM PDT 24
Finished May 02 02:29:02 PM PDT 24
Peak memory 200360 kb
Host smart-1259a7e4-aaab-41bd-8e50-070f73d81509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71450735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.71450735
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.1819231588
Short name T265
Test name
Test status
Simulation time 18538360120 ps
CPU time 211.16 seconds
Started May 02 02:28:11 PM PDT 24
Finished May 02 02:31:43 PM PDT 24
Peak memory 200436 kb
Host smart-6f3ed41c-34c8-4717-b79b-39a443356d5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1819231588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.1819231588
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.3979172060
Short name T321
Test name
Test status
Simulation time 5714989729 ps
CPU time 49.13 seconds
Started May 02 02:28:05 PM PDT 24
Finished May 02 02:28:55 PM PDT 24
Peak memory 198576 kb
Host smart-3cea6b9b-d32e-4988-bee2-aba4906dc6d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3979172060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3979172060
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.4155828855
Short name T150
Test name
Test status
Simulation time 79242307314 ps
CPU time 33.33 seconds
Started May 02 02:28:09 PM PDT 24
Finished May 02 02:28:43 PM PDT 24
Peak memory 200424 kb
Host smart-320e0dde-b205-4ff0-8474-6728eec10c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155828855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.4155828855
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.2029182743
Short name T8
Test name
Test status
Simulation time 2796086088 ps
CPU time 3.05 seconds
Started May 02 02:28:00 PM PDT 24
Finished May 02 02:28:05 PM PDT 24
Peak memory 196164 kb
Host smart-ece5c11d-04b7-443b-93f1-bf0280deaaa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029182743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.2029182743
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.2463327393
Short name T926
Test name
Test status
Simulation time 439551315 ps
CPU time 1.21 seconds
Started May 02 02:28:03 PM PDT 24
Finished May 02 02:28:05 PM PDT 24
Peak memory 199748 kb
Host smart-d333bd89-b86f-4eb4-8ef8-1b0fd1f4b4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463327393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.2463327393
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.255743376
Short name T760
Test name
Test status
Simulation time 47161425216 ps
CPU time 163.07 seconds
Started May 02 02:28:09 PM PDT 24
Finished May 02 02:30:53 PM PDT 24
Peak memory 200428 kb
Host smart-aecec1ff-9053-4d4a-8d18-04995f96741d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255743376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.255743376
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.234055035
Short name T713
Test name
Test status
Simulation time 40204488249 ps
CPU time 457.9 seconds
Started May 02 02:28:09 PM PDT 24
Finished May 02 02:35:49 PM PDT 24
Peak memory 216948 kb
Host smart-caaa6518-4045-453f-85c8-3fb15cb84beb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234055035 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.234055035
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.55799809
Short name T364
Test name
Test status
Simulation time 2283225980 ps
CPU time 2.39 seconds
Started May 02 02:28:09 PM PDT 24
Finished May 02 02:28:13 PM PDT 24
Peak memory 199192 kb
Host smart-a3415ff6-9fc1-4cd9-a161-5c39ca5886e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55799809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.55799809
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.3376622211
Short name T309
Test name
Test status
Simulation time 9751199083 ps
CPU time 8.6 seconds
Started May 02 02:28:01 PM PDT 24
Finished May 02 02:28:11 PM PDT 24
Peak memory 198108 kb
Host smart-10bc2c0b-775a-449f-bec9-451d929e8937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376622211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.3376622211
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.807765880
Short name T651
Test name
Test status
Simulation time 78569904 ps
CPU time 0.55 seconds
Started May 02 02:28:24 PM PDT 24
Finished May 02 02:28:27 PM PDT 24
Peak memory 195188 kb
Host smart-4021efd8-767e-4183-9fd4-6f899c06e562
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807765880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.807765880
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.631096503
Short name T1037
Test name
Test status
Simulation time 285111413732 ps
CPU time 583.89 seconds
Started May 02 02:28:09 PM PDT 24
Finished May 02 02:37:54 PM PDT 24
Peak memory 200416 kb
Host smart-57b00f6c-9cd2-4a4f-b616-c2459ff2ccd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631096503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.631096503
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.1867797435
Short name T775
Test name
Test status
Simulation time 17317937342 ps
CPU time 37.19 seconds
Started May 02 02:28:11 PM PDT 24
Finished May 02 02:28:49 PM PDT 24
Peak memory 200396 kb
Host smart-9c5a34ad-13de-4a85-a700-9f85a7767cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867797435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.1867797435
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.411835940
Short name T927
Test name
Test status
Simulation time 10348764937 ps
CPU time 15.63 seconds
Started May 02 02:28:15 PM PDT 24
Finished May 02 02:28:32 PM PDT 24
Peak memory 200400 kb
Host smart-ad701dca-4125-4c53-b019-f5a95e5580f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411835940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.411835940
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.1447888854
Short name T965
Test name
Test status
Simulation time 39609735673 ps
CPU time 16.02 seconds
Started May 02 02:28:15 PM PDT 24
Finished May 02 02:28:32 PM PDT 24
Peak memory 200280 kb
Host smart-2600098a-33ae-49d4-9b70-ac8515a4851d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447888854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.1447888854
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.1987413517
Short name T798
Test name
Test status
Simulation time 65938900361 ps
CPU time 389.79 seconds
Started May 02 02:28:15 PM PDT 24
Finished May 02 02:34:46 PM PDT 24
Peak memory 200416 kb
Host smart-7c0cf5ef-facb-4289-8b53-255cf50f050f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1987413517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.1987413517
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.3256744078
Short name T777
Test name
Test status
Simulation time 5714086324 ps
CPU time 11 seconds
Started May 02 02:28:14 PM PDT 24
Finished May 02 02:28:26 PM PDT 24
Peak memory 196892 kb
Host smart-8004eee7-797c-4fcc-beb0-14e0091412c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256744078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.3256744078
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.1539281817
Short name T86
Test name
Test status
Simulation time 132098418214 ps
CPU time 61.33 seconds
Started May 02 02:28:15 PM PDT 24
Finished May 02 02:29:19 PM PDT 24
Peak memory 208792 kb
Host smart-22e22f38-7fd7-4894-8c02-724f570de41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539281817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.1539281817
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.3864666504
Short name T715
Test name
Test status
Simulation time 21464709799 ps
CPU time 632.82 seconds
Started May 02 02:28:15 PM PDT 24
Finished May 02 02:38:50 PM PDT 24
Peak memory 200412 kb
Host smart-7fececec-1c64-46e5-a1f6-7604297437e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3864666504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.3864666504
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.2821220828
Short name T1020
Test name
Test status
Simulation time 7319621732 ps
CPU time 31.75 seconds
Started May 02 02:28:14 PM PDT 24
Finished May 02 02:28:47 PM PDT 24
Peak memory 199644 kb
Host smart-8b4e1711-1a11-4220-93df-86fff545c416
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2821220828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.2821220828
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.3804148555
Short name T683
Test name
Test status
Simulation time 24529344265 ps
CPU time 37.22 seconds
Started May 02 02:28:15 PM PDT 24
Finished May 02 02:28:54 PM PDT 24
Peak memory 200300 kb
Host smart-6a011eb5-2685-4f2e-8442-63092e561abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804148555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.3804148555
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.4287378550
Short name T387
Test name
Test status
Simulation time 2307962911 ps
CPU time 1.1 seconds
Started May 02 02:28:15 PM PDT 24
Finished May 02 02:28:18 PM PDT 24
Peak memory 195940 kb
Host smart-679fad5e-202b-462d-bb98-51f3280b9cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287378550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.4287378550
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.1001961428
Short name T333
Test name
Test status
Simulation time 459949160 ps
CPU time 1.77 seconds
Started May 02 02:28:07 PM PDT 24
Finished May 02 02:28:10 PM PDT 24
Peak memory 200104 kb
Host smart-3e45f225-1692-4ffe-89de-b381f25a7437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001961428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.1001961428
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.1165907276
Short name T167
Test name
Test status
Simulation time 175995447319 ps
CPU time 70.39 seconds
Started May 02 02:28:15 PM PDT 24
Finished May 02 02:29:27 PM PDT 24
Peak memory 200380 kb
Host smart-22472811-e431-4ced-9337-1c05ffd9716f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165907276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.1165907276
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.624811902
Short name T1019
Test name
Test status
Simulation time 63541308917 ps
CPU time 351.31 seconds
Started May 02 02:28:16 PM PDT 24
Finished May 02 02:34:10 PM PDT 24
Peak memory 216956 kb
Host smart-1b24b1ac-83c6-4b3b-8383-4973c2c51c50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624811902 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.624811902
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.1300714077
Short name T1036
Test name
Test status
Simulation time 6815999076 ps
CPU time 18.39 seconds
Started May 02 02:28:15 PM PDT 24
Finished May 02 02:28:35 PM PDT 24
Peak memory 200388 kb
Host smart-0592065b-5f88-4847-8186-b16e6776f360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300714077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.1300714077
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.733436082
Short name T402
Test name
Test status
Simulation time 98567229746 ps
CPU time 129.22 seconds
Started May 02 02:28:08 PM PDT 24
Finished May 02 02:30:18 PM PDT 24
Peak memory 200352 kb
Host smart-3afca8f7-38c8-4a1a-9a9c-af41d4042bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733436082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.733436082
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.2151122354
Short name T938
Test name
Test status
Simulation time 13611818 ps
CPU time 0.54 seconds
Started May 02 02:28:23 PM PDT 24
Finished May 02 02:28:25 PM PDT 24
Peak memory 195824 kb
Host smart-ae54629e-44fc-4a4b-8a54-00794868501f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151122354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.2151122354
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.1158786088
Short name T158
Test name
Test status
Simulation time 68732869641 ps
CPU time 34.07 seconds
Started May 02 02:28:26 PM PDT 24
Finished May 02 02:29:03 PM PDT 24
Peak memory 200324 kb
Host smart-d30bed79-c001-4194-932b-da3c4310aa22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158786088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.1158786088
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.2330712068
Short name T806
Test name
Test status
Simulation time 72026688593 ps
CPU time 62.55 seconds
Started May 02 02:28:33 PM PDT 24
Finished May 02 02:29:38 PM PDT 24
Peak memory 200368 kb
Host smart-ee4b09de-4df0-440d-b925-a364787a4709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330712068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.2330712068
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.4008889266
Short name T38
Test name
Test status
Simulation time 41306964014 ps
CPU time 14.78 seconds
Started May 02 02:28:27 PM PDT 24
Finished May 02 02:28:44 PM PDT 24
Peak memory 200412 kb
Host smart-6107922a-c56f-46c5-ac9f-dacb4da3ac4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008889266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.4008889266
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.4192183200
Short name T652
Test name
Test status
Simulation time 315798243117 ps
CPU time 440.98 seconds
Started May 02 02:28:23 PM PDT 24
Finished May 02 02:35:45 PM PDT 24
Peak memory 200356 kb
Host smart-2fabd460-3bfb-4088-b306-ca7eac9c4050
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192183200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.4192183200
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.1665974158
Short name T347
Test name
Test status
Simulation time 104241016085 ps
CPU time 201.94 seconds
Started May 02 02:28:24 PM PDT 24
Finished May 02 02:31:48 PM PDT 24
Peak memory 200388 kb
Host smart-64844e57-e905-4351-8492-7b1affe89fc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1665974158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.1665974158
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.4135818965
Short name T902
Test name
Test status
Simulation time 10458507071 ps
CPU time 7.64 seconds
Started May 02 02:28:25 PM PDT 24
Finished May 02 02:28:36 PM PDT 24
Peak memory 199612 kb
Host smart-03a31f7b-bd6c-4094-97e2-9bb2beaf9ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135818965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.4135818965
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.289021481
Short name T285
Test name
Test status
Simulation time 24415443366 ps
CPU time 21.45 seconds
Started May 02 02:28:25 PM PDT 24
Finished May 02 02:28:50 PM PDT 24
Peak memory 199132 kb
Host smart-7b41975c-1597-4e46-b063-b57737107c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289021481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.289021481
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.4118379112
Short name T361
Test name
Test status
Simulation time 5465231959 ps
CPU time 72.02 seconds
Started May 02 02:28:26 PM PDT 24
Finished May 02 02:29:41 PM PDT 24
Peak memory 200444 kb
Host smart-89b51b17-42cd-49de-a6c4-e44ccfc9650b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4118379112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.4118379112
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.702561233
Short name T518
Test name
Test status
Simulation time 3061915654 ps
CPU time 3.94 seconds
Started May 02 02:28:24 PM PDT 24
Finished May 02 02:28:31 PM PDT 24
Peak memory 199308 kb
Host smart-866faf1b-1a1c-4f7d-9247-f43b27b2df22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=702561233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.702561233
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.1782730851
Short name T123
Test name
Test status
Simulation time 75522816166 ps
CPU time 38.85 seconds
Started May 02 02:28:26 PM PDT 24
Finished May 02 02:29:08 PM PDT 24
Peak memory 200424 kb
Host smart-beb28c3f-44d0-4c09-8e41-ee9e680524c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782730851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1782730851
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.344753464
Short name T836
Test name
Test status
Simulation time 6889804445 ps
CPU time 5.51 seconds
Started May 02 02:28:25 PM PDT 24
Finished May 02 02:28:33 PM PDT 24
Peak memory 196420 kb
Host smart-aba4e0f6-7bc0-469e-94de-e1c2f0614a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344753464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.344753464
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.939551458
Short name T654
Test name
Test status
Simulation time 147631990 ps
CPU time 0.82 seconds
Started May 02 02:28:24 PM PDT 24
Finished May 02 02:28:27 PM PDT 24
Peak memory 198352 kb
Host smart-e97511bf-29bf-49ef-b2f1-b647330243f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939551458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.939551458
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.1152648498
Short name T858
Test name
Test status
Simulation time 231855492630 ps
CPU time 329.02 seconds
Started May 02 02:28:26 PM PDT 24
Finished May 02 02:33:58 PM PDT 24
Peak memory 200360 kb
Host smart-7a26591c-ab70-45ff-89d2-2ec8098f8b7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152648498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.1152648498
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.3058449675
Short name T762
Test name
Test status
Simulation time 51528113144 ps
CPU time 1133.57 seconds
Started May 02 02:28:26 PM PDT 24
Finished May 02 02:47:22 PM PDT 24
Peak memory 216868 kb
Host smart-67be0771-1ac8-478f-a148-8036445c6f30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058449675 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.3058449675
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.3652778055
Short name T1111
Test name
Test status
Simulation time 7537447960 ps
CPU time 11.34 seconds
Started May 02 02:28:26 PM PDT 24
Finished May 02 02:28:40 PM PDT 24
Peak memory 200304 kb
Host smart-d8c3fe1c-9be7-428a-80dd-e0eb05476f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652778055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.3652778055
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.1147948672
Short name T297
Test name
Test status
Simulation time 62426840713 ps
CPU time 140.18 seconds
Started May 02 02:28:24 PM PDT 24
Finished May 02 02:30:47 PM PDT 24
Peak memory 200444 kb
Host smart-3148fad5-73e8-4ba9-a9e8-e494acf3cf58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147948672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.1147948672
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.691125151
Short name T809
Test name
Test status
Simulation time 28057793 ps
CPU time 0.56 seconds
Started May 02 02:28:36 PM PDT 24
Finished May 02 02:28:38 PM PDT 24
Peak memory 195792 kb
Host smart-113bb7ae-8038-4131-9089-328ca5666afb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691125151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.691125151
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.2131409229
Short name T1045
Test name
Test status
Simulation time 133040563848 ps
CPU time 59.88 seconds
Started May 02 02:28:30 PM PDT 24
Finished May 02 02:29:32 PM PDT 24
Peak memory 200440 kb
Host smart-1c3c025e-be75-4525-bbd5-6bcda868df82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131409229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.2131409229
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.1528369539
Short name T680
Test name
Test status
Simulation time 197603312260 ps
CPU time 611.87 seconds
Started May 02 02:28:31 PM PDT 24
Finished May 02 02:38:45 PM PDT 24
Peak memory 200416 kb
Host smart-f9d64062-41d0-4bd9-a71f-f065264464b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528369539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.1528369539
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.1452951290
Short name T1066
Test name
Test status
Simulation time 183121621789 ps
CPU time 303.61 seconds
Started May 02 02:28:33 PM PDT 24
Finished May 02 02:33:39 PM PDT 24
Peak memory 200360 kb
Host smart-a7e22e48-1c8c-445d-a57d-771a41c2124e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452951290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.1452951290
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.2492034950
Short name T505
Test name
Test status
Simulation time 34396498229 ps
CPU time 13.33 seconds
Started May 02 02:28:29 PM PDT 24
Finished May 02 02:28:44 PM PDT 24
Peak memory 200024 kb
Host smart-6d805bd7-09c0-4250-b8e9-a6a038c074fc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492034950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.2492034950
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.2477250402
Short name T931
Test name
Test status
Simulation time 150711172629 ps
CPU time 398.91 seconds
Started May 02 02:28:33 PM PDT 24
Finished May 02 02:35:15 PM PDT 24
Peak memory 200364 kb
Host smart-acb481b5-3834-4a75-8456-89ca235883f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2477250402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.2477250402
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.40825549
Short name T374
Test name
Test status
Simulation time 5022023525 ps
CPU time 4.16 seconds
Started May 02 02:28:31 PM PDT 24
Finished May 02 02:28:37 PM PDT 24
Peak memory 199368 kb
Host smart-539d8b34-c8ae-4641-8277-a8afe13cda59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40825549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.40825549
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.4138840689
Short name T43
Test name
Test status
Simulation time 52892069638 ps
CPU time 48.11 seconds
Started May 02 02:28:32 PM PDT 24
Finished May 02 02:29:22 PM PDT 24
Peak memory 200644 kb
Host smart-9f985a53-7cce-4106-86bf-f34337d3a18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138840689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.4138840689
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.2916354364
Short name T1148
Test name
Test status
Simulation time 33995896879 ps
CPU time 406.96 seconds
Started May 02 02:28:29 PM PDT 24
Finished May 02 02:35:18 PM PDT 24
Peak memory 200440 kb
Host smart-7f86cef3-e254-4b27-b2e8-77e724c0ea43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2916354364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.2916354364
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.1148187114
Short name T420
Test name
Test status
Simulation time 3372627514 ps
CPU time 2.19 seconds
Started May 02 02:28:30 PM PDT 24
Finished May 02 02:28:34 PM PDT 24
Peak memory 198548 kb
Host smart-f434aedd-cdd9-4de9-8476-4e89ea6f373a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1148187114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.1148187114
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.2933126917
Short name T638
Test name
Test status
Simulation time 68987065668 ps
CPU time 33.69 seconds
Started May 02 02:28:31 PM PDT 24
Finished May 02 02:29:07 PM PDT 24
Peak memory 200416 kb
Host smart-3d275bda-eb81-46ce-bdce-91795690fb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933126917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.2933126917
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.2456905231
Short name T660
Test name
Test status
Simulation time 5397551273 ps
CPU time 1.79 seconds
Started May 02 02:28:28 PM PDT 24
Finished May 02 02:28:32 PM PDT 24
Peak memory 196412 kb
Host smart-d35cb564-c284-4475-8866-2af5f1fb1f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456905231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.2456905231
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.3064911852
Short name T460
Test name
Test status
Simulation time 5737065359 ps
CPU time 22.61 seconds
Started May 02 02:28:30 PM PDT 24
Finished May 02 02:28:55 PM PDT 24
Peak memory 200072 kb
Host smart-c9e66048-399e-49e1-ac2e-e5b86f8f12ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064911852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.3064911852
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.2062806907
Short name T489
Test name
Test status
Simulation time 1346366112 ps
CPU time 2.18 seconds
Started May 02 02:28:29 PM PDT 24
Finished May 02 02:28:34 PM PDT 24
Peak memory 199284 kb
Host smart-ef786905-548f-4db8-9019-de45ee5dc391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062806907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.2062806907
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.1423701564
Short name T251
Test name
Test status
Simulation time 148123091013 ps
CPU time 377.12 seconds
Started May 02 02:28:33 PM PDT 24
Finished May 02 02:34:53 PM PDT 24
Peak memory 200268 kb
Host smart-16f8a5de-5a35-4083-9ba9-1d00b9f0dc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423701564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.1423701564
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.2936111573
Short name T1089
Test name
Test status
Simulation time 57791810 ps
CPU time 0.53 seconds
Started May 02 02:28:45 PM PDT 24
Finished May 02 02:28:48 PM PDT 24
Peak memory 195204 kb
Host smart-64463cf0-19cc-4850-a41f-3b4afe0c7777
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936111573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.2936111573
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.2426791815
Short name T790
Test name
Test status
Simulation time 31304757336 ps
CPU time 57.34 seconds
Started May 02 02:28:40 PM PDT 24
Finished May 02 02:29:38 PM PDT 24
Peak memory 200300 kb
Host smart-20ce9bdf-cf56-4539-a590-6ddd149a66ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426791815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2426791815
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.1868424558
Short name T730
Test name
Test status
Simulation time 177121980173 ps
CPU time 84.34 seconds
Started May 02 02:28:37 PM PDT 24
Finished May 02 02:30:03 PM PDT 24
Peak memory 200360 kb
Host smart-40f929e6-3c48-40a6-ad04-3b1596744329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868424558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.1868424558
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.2331061214
Short name T853
Test name
Test status
Simulation time 80269267774 ps
CPU time 44.31 seconds
Started May 02 02:28:37 PM PDT 24
Finished May 02 02:29:23 PM PDT 24
Peak memory 200284 kb
Host smart-b997755c-075b-4e8e-ab1e-4f5cf82f8e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331061214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.2331061214
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.3002590047
Short name T791
Test name
Test status
Simulation time 491923321471 ps
CPU time 286.48 seconds
Started May 02 02:28:35 PM PDT 24
Finished May 02 02:33:23 PM PDT 24
Peak memory 199092 kb
Host smart-5ad01f7e-dc29-4428-947e-b6273859869d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002590047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.3002590047
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.1113775468
Short name T591
Test name
Test status
Simulation time 188102421937 ps
CPU time 657.07 seconds
Started May 02 02:28:45 PM PDT 24
Finished May 02 02:39:44 PM PDT 24
Peak memory 200344 kb
Host smart-67a1b947-80fc-4dbb-a341-bea6c06e949d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1113775468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.1113775468
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.2275626314
Short name T516
Test name
Test status
Simulation time 2833723162 ps
CPU time 4.44 seconds
Started May 02 02:28:44 PM PDT 24
Finished May 02 02:28:50 PM PDT 24
Peak memory 198820 kb
Host smart-fb39a368-6e64-44f0-9506-37f62bd2e0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275626314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.2275626314
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.1389449689
Short name T1067
Test name
Test status
Simulation time 158820898026 ps
CPU time 138.49 seconds
Started May 02 02:28:37 PM PDT 24
Finished May 02 02:30:57 PM PDT 24
Peak memory 200524 kb
Host smart-66be6eaf-f840-4f49-a1b1-d585ef406b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389449689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.1389449689
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.1737630003
Short name T441
Test name
Test status
Simulation time 9334140339 ps
CPU time 144.08 seconds
Started May 02 02:28:43 PM PDT 24
Finished May 02 02:31:09 PM PDT 24
Peak memory 200408 kb
Host smart-7b8b872e-0bb6-4167-9280-5269e21145eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1737630003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.1737630003
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.2956796389
Short name T443
Test name
Test status
Simulation time 2105032149 ps
CPU time 9.99 seconds
Started May 02 02:28:37 PM PDT 24
Finished May 02 02:28:48 PM PDT 24
Peak memory 198968 kb
Host smart-a627b1a5-8e1a-4ef6-a749-35f3fa767fe7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2956796389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.2956796389
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.3107071407
Short name T1033
Test name
Test status
Simulation time 53850911946 ps
CPU time 95 seconds
Started May 02 02:28:38 PM PDT 24
Finished May 02 02:30:14 PM PDT 24
Peak memory 200352 kb
Host smart-e02b5853-1a31-4a7f-9ab4-584f745655bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107071407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.3107071407
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.3001783156
Short name T1071
Test name
Test status
Simulation time 2605708480 ps
CPU time 4.39 seconds
Started May 02 02:28:38 PM PDT 24
Finished May 02 02:28:44 PM PDT 24
Peak memory 196144 kb
Host smart-8170b967-0994-43e7-ba89-76fc0a8de3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001783156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3001783156
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.4110825855
Short name T1050
Test name
Test status
Simulation time 624134975 ps
CPU time 2.73 seconds
Started May 02 02:28:36 PM PDT 24
Finished May 02 02:28:41 PM PDT 24
Peak memory 199036 kb
Host smart-281d579f-2fd2-42cb-8a07-0f710808dad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110825855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.4110825855
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.4187869013
Short name T201
Test name
Test status
Simulation time 36707867712 ps
CPU time 568.78 seconds
Started May 02 02:28:51 PM PDT 24
Finished May 02 02:38:21 PM PDT 24
Peak memory 216492 kb
Host smart-6dbdb354-2f81-4e23-a5a1-19cd4337e3f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187869013 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.4187869013
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.2858226429
Short name T359
Test name
Test status
Simulation time 1030766723 ps
CPU time 3.5 seconds
Started May 02 02:28:45 PM PDT 24
Finished May 02 02:28:51 PM PDT 24
Peak memory 199944 kb
Host smart-78456a50-4149-470e-82cf-b5e1a01e1578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858226429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.2858226429
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.1382509978
Short name T245
Test name
Test status
Simulation time 232152649092 ps
CPU time 44.3 seconds
Started May 02 02:28:38 PM PDT 24
Finished May 02 02:29:23 PM PDT 24
Peak memory 200428 kb
Host smart-0413b01c-e08c-492c-97c1-099b5f144a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382509978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.1382509978
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.3975035527
Short name T504
Test name
Test status
Simulation time 40251207 ps
CPU time 0.55 seconds
Started May 02 02:28:55 PM PDT 24
Finished May 02 02:28:57 PM PDT 24
Peak memory 195820 kb
Host smart-b388d247-9e72-49f3-846b-26bb9a4e7d8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975035527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.3975035527
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.3904857542
Short name T138
Test name
Test status
Simulation time 281145097576 ps
CPU time 44.75 seconds
Started May 02 02:28:44 PM PDT 24
Finished May 02 02:29:31 PM PDT 24
Peak memory 200304 kb
Host smart-a1648bcc-ae2e-4bc8-8083-b95f0f9cbae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904857542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.3904857542
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.2010891122
Short name T407
Test name
Test status
Simulation time 47626606233 ps
CPU time 80.12 seconds
Started May 02 02:28:45 PM PDT 24
Finished May 02 02:30:07 PM PDT 24
Peak memory 200352 kb
Host smart-78094758-a203-420c-aebb-11241c211831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010891122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.2010891122
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.3964113756
Short name T177
Test name
Test status
Simulation time 5601031328 ps
CPU time 9.65 seconds
Started May 02 02:28:47 PM PDT 24
Finished May 02 02:28:58 PM PDT 24
Peak memory 200372 kb
Host smart-defcdf65-b33c-42be-8804-d601e09f9605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964113756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.3964113756
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.1246792523
Short name T901
Test name
Test status
Simulation time 184719643551 ps
CPU time 76.36 seconds
Started May 02 02:28:45 PM PDT 24
Finished May 02 02:30:03 PM PDT 24
Peak memory 197288 kb
Host smart-7c67896d-7730-4834-a90c-6fd2313f567c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246792523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.1246792523
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.1945567785
Short name T834
Test name
Test status
Simulation time 38192425333 ps
CPU time 173.15 seconds
Started May 02 02:28:54 PM PDT 24
Finished May 02 02:31:49 PM PDT 24
Peak memory 200352 kb
Host smart-460bee90-8fff-4b41-8594-f9ee2f85bf0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1945567785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.1945567785
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.1512731758
Short name T934
Test name
Test status
Simulation time 7684858470 ps
CPU time 16.38 seconds
Started May 02 02:28:58 PM PDT 24
Finished May 02 02:29:16 PM PDT 24
Peak memory 200264 kb
Host smart-6d63920d-a40f-4f25-90a3-809e88e48914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512731758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.1512731758
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.2102663101
Short name T993
Test name
Test status
Simulation time 89356410470 ps
CPU time 36.74 seconds
Started May 02 02:28:44 PM PDT 24
Finished May 02 02:29:23 PM PDT 24
Peak memory 216228 kb
Host smart-bfede9c2-8dbd-45a7-b843-39e10a8ffb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102663101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.2102663101
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.2885822442
Short name T324
Test name
Test status
Simulation time 18285067421 ps
CPU time 1115.28 seconds
Started May 02 02:28:56 PM PDT 24
Finished May 02 02:47:33 PM PDT 24
Peak memory 200384 kb
Host smart-20430e69-bde0-48aa-b9da-926f4c1b099e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2885822442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.2885822442
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.1526995360
Short name T1112
Test name
Test status
Simulation time 2658087448 ps
CPU time 12.21 seconds
Started May 02 02:28:46 PM PDT 24
Finished May 02 02:29:00 PM PDT 24
Peak memory 199560 kb
Host smart-89fbaeea-fdb5-4c46-a717-e6cd9d62c432
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1526995360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.1526995360
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.4138753002
Short name T779
Test name
Test status
Simulation time 71651323226 ps
CPU time 35.48 seconds
Started May 02 02:28:54 PM PDT 24
Finished May 02 02:29:31 PM PDT 24
Peak memory 200372 kb
Host smart-9137ac5d-85b4-4d12-b0d4-b827e89adcbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138753002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.4138753002
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.4181100959
Short name T631
Test name
Test status
Simulation time 4947000537 ps
CPU time 4.66 seconds
Started May 02 02:28:48 PM PDT 24
Finished May 02 02:28:54 PM PDT 24
Peak memory 196432 kb
Host smart-de8884f5-e937-4edf-98ac-57506126a9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181100959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.4181100959
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.2165557947
Short name T1129
Test name
Test status
Simulation time 248156852 ps
CPU time 1.45 seconds
Started May 02 02:28:45 PM PDT 24
Finished May 02 02:28:48 PM PDT 24
Peak memory 198700 kb
Host smart-498e327f-aa5b-4246-9714-c6ab9cbf7e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165557947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.2165557947
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.2938631017
Short name T782
Test name
Test status
Simulation time 202407666291 ps
CPU time 188.16 seconds
Started May 02 02:28:55 PM PDT 24
Finished May 02 02:32:04 PM PDT 24
Peak memory 200376 kb
Host smart-fd5ab76d-823f-41b0-9942-0c6e6476e18e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938631017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.2938631017
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.1200959938
Short name T739
Test name
Test status
Simulation time 20280198230 ps
CPU time 447.43 seconds
Started May 02 02:28:55 PM PDT 24
Finished May 02 02:36:24 PM PDT 24
Peak memory 216876 kb
Host smart-29f273bb-60a4-45ba-a359-ac00792333c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200959938 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.1200959938
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.87493006
Short name T558
Test name
Test status
Simulation time 3022446474 ps
CPU time 2.37 seconds
Started May 02 02:28:55 PM PDT 24
Finished May 02 02:28:59 PM PDT 24
Peak memory 200348 kb
Host smart-c2b9a867-18bd-4473-a982-ef18803c1b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87493006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.87493006
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.909290314
Short name T243
Test name
Test status
Simulation time 86388777044 ps
CPU time 108.39 seconds
Started May 02 02:28:46 PM PDT 24
Finished May 02 02:30:36 PM PDT 24
Peak memory 200436 kb
Host smart-9e42779d-23c7-4593-84ff-3819dcc764a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909290314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.909290314
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.1416673572
Short name T687
Test name
Test status
Simulation time 46777709 ps
CPU time 0.59 seconds
Started May 02 02:29:01 PM PDT 24
Finished May 02 02:29:03 PM PDT 24
Peak memory 195776 kb
Host smart-543924de-23fa-4aac-8c71-531eb844b4a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416673572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.1416673572
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.780402175
Short name T874
Test name
Test status
Simulation time 128195951917 ps
CPU time 173.91 seconds
Started May 02 02:28:55 PM PDT 24
Finished May 02 02:31:50 PM PDT 24
Peak memory 200416 kb
Host smart-aa4d4fcb-88c3-4621-8c0b-856fe52eae1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780402175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.780402175
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.2733465398
Short name T378
Test name
Test status
Simulation time 22824420052 ps
CPU time 38.44 seconds
Started May 02 02:28:55 PM PDT 24
Finished May 02 02:29:35 PM PDT 24
Peak memory 200428 kb
Host smart-8b55d0cf-fa7a-4e51-a8b5-08827639823b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733465398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.2733465398
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.2323580172
Short name T196
Test name
Test status
Simulation time 80710648280 ps
CPU time 35.78 seconds
Started May 02 02:28:55 PM PDT 24
Finished May 02 02:29:33 PM PDT 24
Peak memory 200356 kb
Host smart-1f8e06d3-ffb8-44ab-806b-551bf4c0a852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323580172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.2323580172
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.2021658561
Short name T406
Test name
Test status
Simulation time 61570196133 ps
CPU time 17.9 seconds
Started May 02 02:29:00 PM PDT 24
Finished May 02 02:29:19 PM PDT 24
Peak memory 200228 kb
Host smart-f7e191ed-7915-472d-928f-a381deb40e6f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021658561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.2021658561
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.2541628614
Short name T481
Test name
Test status
Simulation time 139458681633 ps
CPU time 1116.02 seconds
Started May 02 02:29:02 PM PDT 24
Finished May 02 02:47:39 PM PDT 24
Peak memory 200436 kb
Host smart-0d7df96c-be5c-42dc-80f7-bcc12e88aa6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2541628614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.2541628614
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.3552576083
Short name T909
Test name
Test status
Simulation time 6987279307 ps
CPU time 7.86 seconds
Started May 02 02:29:01 PM PDT 24
Finished May 02 02:29:10 PM PDT 24
Peak memory 200068 kb
Host smart-09672abd-6cbe-4c9c-8bb6-61324d363a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552576083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.3552576083
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.2670331284
Short name T872
Test name
Test status
Simulation time 91904835469 ps
CPU time 76.84 seconds
Started May 02 02:29:03 PM PDT 24
Finished May 02 02:30:21 PM PDT 24
Peak memory 200264 kb
Host smart-694a233f-8e6d-4e36-a1e0-45e1fd623a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670331284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.2670331284
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.3381722210
Short name T1040
Test name
Test status
Simulation time 14501627882 ps
CPU time 913.91 seconds
Started May 02 02:29:04 PM PDT 24
Finished May 02 02:44:19 PM PDT 24
Peak memory 200328 kb
Host smart-0b53a025-ca39-4da6-b92f-c440caa8a8ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3381722210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.3381722210
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.2849936638
Short name T353
Test name
Test status
Simulation time 5056799467 ps
CPU time 9.87 seconds
Started May 02 02:28:56 PM PDT 24
Finished May 02 02:29:07 PM PDT 24
Peak memory 199052 kb
Host smart-f8a82c9e-cc61-4c40-8bd4-f0889fb4a57e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2849936638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.2849936638
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.4291154205
Short name T821
Test name
Test status
Simulation time 219441061466 ps
CPU time 98.32 seconds
Started May 02 02:29:04 PM PDT 24
Finished May 02 02:30:43 PM PDT 24
Peak memory 200380 kb
Host smart-73cb7ef7-1c94-4fde-8df6-18cac8d7e44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291154205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.4291154205
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.3092111702
Short name T913
Test name
Test status
Simulation time 3258064368 ps
CPU time 2.13 seconds
Started May 02 02:29:02 PM PDT 24
Finished May 02 02:29:06 PM PDT 24
Peak memory 196208 kb
Host smart-6ac94b3b-84bb-443f-a1de-14f5f03ef563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092111702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.3092111702
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.3163728771
Short name T461
Test name
Test status
Simulation time 5685500585 ps
CPU time 19.12 seconds
Started May 02 02:28:54 PM PDT 24
Finished May 02 02:29:15 PM PDT 24
Peak memory 200168 kb
Host smart-7fc6d3da-c43f-4246-97f4-c7b1b3b67b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163728771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.3163728771
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.3146593100
Short name T963
Test name
Test status
Simulation time 115615887393 ps
CPU time 454.42 seconds
Started May 02 02:29:02 PM PDT 24
Finished May 02 02:36:37 PM PDT 24
Peak memory 200436 kb
Host smart-f2560d70-abce-4f88-b41b-3a5d14d2610c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146593100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.3146593100
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.2773062869
Short name T914
Test name
Test status
Simulation time 6789050637 ps
CPU time 18.87 seconds
Started May 02 02:29:01 PM PDT 24
Finished May 02 02:29:21 PM PDT 24
Peak memory 199604 kb
Host smart-ef301407-a690-4521-80ea-87c0b9409f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773062869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.2773062869
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.3989608320
Short name T515
Test name
Test status
Simulation time 141023612948 ps
CPU time 123.22 seconds
Started May 02 02:28:56 PM PDT 24
Finished May 02 02:31:01 PM PDT 24
Peak memory 200384 kb
Host smart-e8ee6452-e244-4f1b-baaf-867bda88c88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989608320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.3989608320
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.3561282213
Short name T550
Test name
Test status
Simulation time 142215839 ps
CPU time 0.55 seconds
Started May 02 02:29:11 PM PDT 24
Finished May 02 02:29:13 PM PDT 24
Peak memory 195804 kb
Host smart-de7ce1ad-005c-48bd-bcb0-09a5b60647fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561282213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.3561282213
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.3409660000
Short name T381
Test name
Test status
Simulation time 110173474717 ps
CPU time 138.33 seconds
Started May 02 02:29:02 PM PDT 24
Finished May 02 02:31:22 PM PDT 24
Peak memory 200384 kb
Host smart-b9f79886-9189-4355-b489-b82d1936f14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409660000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.3409660000
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.1282579676
Short name T694
Test name
Test status
Simulation time 103134658507 ps
CPU time 43.29 seconds
Started May 02 02:29:02 PM PDT 24
Finished May 02 02:29:47 PM PDT 24
Peak memory 200416 kb
Host smart-df09d249-0238-4de6-9d64-091652ce890f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282579676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.1282579676
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.3937537171
Short name T952
Test name
Test status
Simulation time 34482127400 ps
CPU time 14.02 seconds
Started May 02 02:29:03 PM PDT 24
Finished May 02 02:29:18 PM PDT 24
Peak memory 200376 kb
Host smart-97a09d86-a64d-4251-a874-f20c4b0b0e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937537171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.3937537171
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.3218570218
Short name T774
Test name
Test status
Simulation time 69390104794 ps
CPU time 99.79 seconds
Started May 02 02:29:01 PM PDT 24
Finished May 02 02:30:43 PM PDT 24
Peak memory 200440 kb
Host smart-465c1762-e433-4d42-b7af-61c7fec26698
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218570218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.3218570218
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.1186758247
Short name T625
Test name
Test status
Simulation time 296205160132 ps
CPU time 784.16 seconds
Started May 02 02:29:09 PM PDT 24
Finished May 02 02:42:15 PM PDT 24
Peak memory 200368 kb
Host smart-d59ed907-d42d-474e-a663-aefd5eb1be63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1186758247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.1186758247
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.943253671
Short name T950
Test name
Test status
Simulation time 4400733967 ps
CPU time 9.35 seconds
Started May 02 02:29:11 PM PDT 24
Finished May 02 02:29:23 PM PDT 24
Peak memory 199272 kb
Host smart-5627cb64-ac3c-470c-b6cc-5b9db2814731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943253671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.943253671
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.530825114
Short name T13
Test name
Test status
Simulation time 45438588954 ps
CPU time 84.18 seconds
Started May 02 02:29:11 PM PDT 24
Finished May 02 02:30:37 PM PDT 24
Peak memory 208724 kb
Host smart-f46619de-a9f3-4a6e-ab88-be99e8e4ee8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530825114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.530825114
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.3977572916
Short name T286
Test name
Test status
Simulation time 20557738912 ps
CPU time 205.39 seconds
Started May 02 02:29:09 PM PDT 24
Finished May 02 02:32:36 PM PDT 24
Peak memory 200436 kb
Host smart-08319480-a251-48f0-994d-b3094be26931
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3977572916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.3977572916
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.3554150342
Short name T1013
Test name
Test status
Simulation time 6232355001 ps
CPU time 14.01 seconds
Started May 02 02:29:02 PM PDT 24
Finished May 02 02:29:18 PM PDT 24
Peak memory 199876 kb
Host smart-fd7158e8-7c81-4086-8d72-d306708eb924
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3554150342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.3554150342
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.2201917916
Short name T156
Test name
Test status
Simulation time 67750051125 ps
CPU time 14.41 seconds
Started May 02 02:29:14 PM PDT 24
Finished May 02 02:29:30 PM PDT 24
Peak memory 200324 kb
Host smart-c69dbfbb-ac0b-4497-b618-8eb875193d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201917916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.2201917916
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.3085050495
Short name T668
Test name
Test status
Simulation time 42155070803 ps
CPU time 16.01 seconds
Started May 02 02:29:09 PM PDT 24
Finished May 02 02:29:27 PM PDT 24
Peak memory 196668 kb
Host smart-314db8b1-4330-40be-9771-5ccc7aae6e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085050495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.3085050495
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.1924950251
Short name T747
Test name
Test status
Simulation time 6308605145 ps
CPU time 30.77 seconds
Started May 02 02:29:02 PM PDT 24
Finished May 02 02:29:35 PM PDT 24
Peak memory 200368 kb
Host smart-d7839bcd-e51f-4363-91fb-7c6106026d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924950251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1924950251
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.2946606291
Short name T1182
Test name
Test status
Simulation time 164915823574 ps
CPU time 182.78 seconds
Started May 02 02:29:09 PM PDT 24
Finished May 02 02:32:14 PM PDT 24
Peak memory 200416 kb
Host smart-dd6c92f2-e11b-42fe-baf1-db2a6e0f381e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946606291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.2946606291
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.263085594
Short name T955
Test name
Test status
Simulation time 136620378123 ps
CPU time 911.25 seconds
Started May 02 02:29:09 PM PDT 24
Finished May 02 02:44:23 PM PDT 24
Peak memory 225296 kb
Host smart-7d12d007-98be-41ed-9d17-50b91ee15e40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263085594 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.263085594
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.2006083915
Short name T637
Test name
Test status
Simulation time 785484634 ps
CPU time 1.52 seconds
Started May 02 02:29:13 PM PDT 24
Finished May 02 02:29:17 PM PDT 24
Peak memory 198656 kb
Host smart-3f9a643f-0146-4d46-8bce-c00273700424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006083915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.2006083915
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.2803637353
Short name T291
Test name
Test status
Simulation time 236093607129 ps
CPU time 28.18 seconds
Started May 02 02:29:02 PM PDT 24
Finished May 02 02:29:32 PM PDT 24
Peak memory 200424 kb
Host smart-3bf735d0-09da-44ea-b37c-da7fc6192d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803637353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.2803637353
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.2655165692
Short name T895
Test name
Test status
Simulation time 163916035 ps
CPU time 0.56 seconds
Started May 02 02:24:48 PM PDT 24
Finished May 02 02:24:53 PM PDT 24
Peak memory 195184 kb
Host smart-4b091576-cfd5-4d9b-9cd0-c1d8e60c9e94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655165692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.2655165692
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.4273375466
Short name T1070
Test name
Test status
Simulation time 125237375136 ps
CPU time 44.53 seconds
Started May 02 02:24:45 PM PDT 24
Finished May 02 02:25:33 PM PDT 24
Peak memory 200444 kb
Host smart-f8a9c64f-11fd-4c87-98a2-d74659df5fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273375466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.4273375466
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.95353670
Short name T531
Test name
Test status
Simulation time 34635692430 ps
CPU time 14.66 seconds
Started May 02 02:24:47 PM PDT 24
Finished May 02 02:25:05 PM PDT 24
Peak memory 200344 kb
Host smart-3f2ffc43-b551-4fee-ba3b-3429e70b549c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95353670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.95353670
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.974209306
Short name T1170
Test name
Test status
Simulation time 12929663681 ps
CPU time 20.96 seconds
Started May 02 02:25:03 PM PDT 24
Finished May 02 02:25:27 PM PDT 24
Peak memory 200344 kb
Host smart-f9aabfbe-08b6-42c8-a54a-ba9d6c548366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974209306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.974209306
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.1868822062
Short name T653
Test name
Test status
Simulation time 16529193225 ps
CPU time 30.05 seconds
Started May 02 02:24:47 PM PDT 24
Finished May 02 02:25:21 PM PDT 24
Peak memory 200200 kb
Host smart-6ffc1859-b1fe-4701-abff-8ef33e290111
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868822062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.1868822062
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.2125971414
Short name T397
Test name
Test status
Simulation time 92543380224 ps
CPU time 540.52 seconds
Started May 02 02:24:46 PM PDT 24
Finished May 02 02:33:51 PM PDT 24
Peak memory 200432 kb
Host smart-5bbf2c6e-0839-41b2-8901-73fc534fa32d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2125971414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.2125971414
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.1403518509
Short name T1130
Test name
Test status
Simulation time 3853562518 ps
CPU time 2.37 seconds
Started May 02 02:24:48 PM PDT 24
Finished May 02 02:24:54 PM PDT 24
Peak memory 197896 kb
Host smart-5967dc15-1235-436d-995c-0bea2ef36551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403518509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.1403518509
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.2273672702
Short name T1094
Test name
Test status
Simulation time 127904772203 ps
CPU time 79.44 seconds
Started May 02 02:24:46 PM PDT 24
Finished May 02 02:26:10 PM PDT 24
Peak memory 208788 kb
Host smart-b7fd5d92-bae0-4cba-b20e-b9cdd9db7ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273672702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.2273672702
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.974150460
Short name T1138
Test name
Test status
Simulation time 19588547118 ps
CPU time 263.23 seconds
Started May 02 02:24:47 PM PDT 24
Finished May 02 02:29:14 PM PDT 24
Peak memory 200420 kb
Host smart-6c89a483-f7d3-4e85-bd2c-2e75aeaaa20b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=974150460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.974150460
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.315035253
Short name T496
Test name
Test status
Simulation time 4323596509 ps
CPU time 20.02 seconds
Started May 02 02:24:51 PM PDT 24
Finished May 02 02:25:14 PM PDT 24
Peak memory 199248 kb
Host smart-372a618c-f911-4d6d-a153-394f2ac34fab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=315035253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.315035253
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.2096277443
Short name T382
Test name
Test status
Simulation time 29034153632 ps
CPU time 15.15 seconds
Started May 02 02:24:46 PM PDT 24
Finished May 02 02:25:06 PM PDT 24
Peak memory 200352 kb
Host smart-08d01b43-8fa9-4e04-b785-a8cc07f7441f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096277443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2096277443
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.433927553
Short name T362
Test name
Test status
Simulation time 1338212845 ps
CPU time 2.66 seconds
Started May 02 02:24:46 PM PDT 24
Finished May 02 02:24:53 PM PDT 24
Peak memory 196100 kb
Host smart-a068dafb-af0d-4f40-8c00-109b1a0d0c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433927553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.433927553
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.2840631031
Short name T22
Test name
Test status
Simulation time 106877143 ps
CPU time 0.83 seconds
Started May 02 02:24:47 PM PDT 24
Finished May 02 02:24:52 PM PDT 24
Peak memory 218416 kb
Host smart-16a8103a-2a99-4fad-b472-480a9dd03cb6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840631031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.2840631031
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.4032921441
Short name T483
Test name
Test status
Simulation time 481376101 ps
CPU time 2.06 seconds
Started May 02 02:24:46 PM PDT 24
Finished May 02 02:24:52 PM PDT 24
Peak memory 199116 kb
Host smart-c053d0b9-cf27-4ffc-960e-b2f59087c6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032921441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.4032921441
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.800080660
Short name T647
Test name
Test status
Simulation time 164076490234 ps
CPU time 37.79 seconds
Started May 02 02:24:48 PM PDT 24
Finished May 02 02:25:30 PM PDT 24
Peak memory 200408 kb
Host smart-faebc76b-bdb5-45a7-a34c-2b6519dec937
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800080660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.800080660
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.2305328844
Short name T744
Test name
Test status
Simulation time 6631444319 ps
CPU time 28.39 seconds
Started May 02 02:24:46 PM PDT 24
Finished May 02 02:25:18 PM PDT 24
Peak memory 200344 kb
Host smart-2cf32dc2-1efc-428b-b007-9a5045553b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305328844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.2305328844
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.1505623099
Short name T693
Test name
Test status
Simulation time 45259925484 ps
CPU time 41.09 seconds
Started May 02 02:24:47 PM PDT 24
Finished May 02 02:25:32 PM PDT 24
Peak memory 200424 kb
Host smart-f952eaae-88bf-4022-a6fc-12ba719eb34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505623099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.1505623099
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.4132707891
Short name T583
Test name
Test status
Simulation time 22858027 ps
CPU time 0.54 seconds
Started May 02 02:29:20 PM PDT 24
Finished May 02 02:29:22 PM PDT 24
Peak memory 194776 kb
Host smart-eb2467b5-8656-4128-8fee-20c2824bba0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132707891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.4132707891
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.3290376733
Short name T530
Test name
Test status
Simulation time 17199697706 ps
CPU time 29.24 seconds
Started May 02 02:29:11 PM PDT 24
Finished May 02 02:29:42 PM PDT 24
Peak memory 200404 kb
Host smart-dcff181c-7d6e-4b9d-b853-8da4de3bd47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290376733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.3290376733
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.2759424709
Short name T609
Test name
Test status
Simulation time 40035045647 ps
CPU time 72.95 seconds
Started May 02 02:29:08 PM PDT 24
Finished May 02 02:30:23 PM PDT 24
Peak memory 200444 kb
Host smart-95a35c6e-438c-48d4-be4e-4834a45abd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759424709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.2759424709
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.865343913
Short name T1163
Test name
Test status
Simulation time 15252023253 ps
CPU time 27.96 seconds
Started May 02 02:29:08 PM PDT 24
Finished May 02 02:29:38 PM PDT 24
Peak memory 200444 kb
Host smart-57c6163b-11bb-413d-a0ae-ffbe62b49977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865343913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.865343913
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.1708694515
Short name T104
Test name
Test status
Simulation time 14004459652 ps
CPU time 12.51 seconds
Started May 02 02:29:09 PM PDT 24
Finished May 02 02:29:24 PM PDT 24
Peak memory 200428 kb
Host smart-da71a79e-09e5-4bca-a19c-41b469498033
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708694515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.1708694515
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.2668406541
Short name T552
Test name
Test status
Simulation time 109407475150 ps
CPU time 425.04 seconds
Started May 02 02:29:18 PM PDT 24
Finished May 02 02:36:25 PM PDT 24
Peak memory 200392 kb
Host smart-28634804-051a-47a0-8471-9848e1048b31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2668406541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2668406541
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.3833495919
Short name T326
Test name
Test status
Simulation time 4106197115 ps
CPU time 2.3 seconds
Started May 02 02:29:18 PM PDT 24
Finished May 02 02:29:22 PM PDT 24
Peak memory 200196 kb
Host smart-06f6498c-eff3-4eba-b981-f5bc7d6675b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833495919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.3833495919
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.1246271036
Short name T875
Test name
Test status
Simulation time 129840052309 ps
CPU time 57.87 seconds
Started May 02 02:29:08 PM PDT 24
Finished May 02 02:30:07 PM PDT 24
Peak memory 198800 kb
Host smart-494f92d4-fe38-4224-b66a-d58fd925bcc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246271036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.1246271036
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.3374713132
Short name T1058
Test name
Test status
Simulation time 10334404836 ps
CPU time 332.38 seconds
Started May 02 02:29:18 PM PDT 24
Finished May 02 02:34:51 PM PDT 24
Peak memory 200444 kb
Host smart-f3972631-3d08-427f-9969-1f76062c5474
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3374713132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.3374713132
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.1202613637
Short name T988
Test name
Test status
Simulation time 3798660746 ps
CPU time 28.97 seconds
Started May 02 02:29:10 PM PDT 24
Finished May 02 02:29:41 PM PDT 24
Peak memory 198792 kb
Host smart-119053d3-9c91-4333-bd77-264403ab4b8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1202613637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.1202613637
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.2063437914
Short name T261
Test name
Test status
Simulation time 64849482285 ps
CPU time 168.96 seconds
Started May 02 02:29:18 PM PDT 24
Finished May 02 02:32:08 PM PDT 24
Peak memory 200364 kb
Host smart-3539543a-a4d5-4b1e-973b-be0acc8627e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063437914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.2063437914
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.2873714594
Short name T1005
Test name
Test status
Simulation time 2881250456 ps
CPU time 3.21 seconds
Started May 02 02:29:11 PM PDT 24
Finished May 02 02:29:17 PM PDT 24
Peak memory 196124 kb
Host smart-c038cdd1-5f98-4b06-9b6d-8d78413aacf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873714594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.2873714594
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.4225570445
Short name T886
Test name
Test status
Simulation time 5498558907 ps
CPU time 7.99 seconds
Started May 02 02:29:08 PM PDT 24
Finished May 02 02:29:17 PM PDT 24
Peak memory 200028 kb
Host smart-9c5eeb58-0830-432b-89c5-61e1faefb320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225570445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.4225570445
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.1405785507
Short name T854
Test name
Test status
Simulation time 172840197608 ps
CPU time 371.91 seconds
Started May 02 02:29:18 PM PDT 24
Finished May 02 02:35:31 PM PDT 24
Peak memory 200344 kb
Host smart-0a850d26-26b3-4e77-a37c-7d4ccfd9ce15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405785507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.1405785507
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.1895415617
Short name T328
Test name
Test status
Simulation time 2266387632 ps
CPU time 1.78 seconds
Started May 02 02:29:16 PM PDT 24
Finished May 02 02:29:20 PM PDT 24
Peak memory 199212 kb
Host smart-526c3df0-79df-4c60-b179-4301ff4c5200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895415617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.1895415617
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.4104658941
Short name T924
Test name
Test status
Simulation time 68151980767 ps
CPU time 54.5 seconds
Started May 02 02:29:11 PM PDT 24
Finished May 02 02:30:07 PM PDT 24
Peak memory 200360 kb
Host smart-044a0163-c5fc-416f-8187-5bbbba5fce41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104658941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.4104658941
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.1401943183
Short name T451
Test name
Test status
Simulation time 19853263 ps
CPU time 0.54 seconds
Started May 02 02:29:41 PM PDT 24
Finished May 02 02:29:43 PM PDT 24
Peak memory 194736 kb
Host smart-0a216d3d-45d9-445a-baeb-67f7f6cb84f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401943183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.1401943183
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.4235693902
Short name T1046
Test name
Test status
Simulation time 213404380251 ps
CPU time 45.29 seconds
Started May 02 02:29:30 PM PDT 24
Finished May 02 02:30:17 PM PDT 24
Peak memory 200380 kb
Host smart-ca270699-e8bb-4fbc-80bc-888a17657883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235693902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.4235693902
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.877581802
Short name T287
Test name
Test status
Simulation time 18025874662 ps
CPU time 28.26 seconds
Started May 02 02:29:28 PM PDT 24
Finished May 02 02:29:57 PM PDT 24
Peak memory 200188 kb
Host smart-98c37c5a-7103-405f-a0bd-a20b770bb756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877581802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.877581802
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.4258144902
Short name T216
Test name
Test status
Simulation time 220862398950 ps
CPU time 89.17 seconds
Started May 02 02:29:26 PM PDT 24
Finished May 02 02:30:56 PM PDT 24
Peak memory 200348 kb
Host smart-eebc59b0-ded0-4f5f-820d-527b7cb0329e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258144902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.4258144902
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.2768364956
Short name T107
Test name
Test status
Simulation time 55290160320 ps
CPU time 26.84 seconds
Started May 02 02:29:28 PM PDT 24
Finished May 02 02:29:56 PM PDT 24
Peak memory 200376 kb
Host smart-fdb30f34-f16a-461c-b1c9-c862c9b54c23
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768364956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.2768364956
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.2643835438
Short name T557
Test name
Test status
Simulation time 124399406030 ps
CPU time 192.23 seconds
Started May 02 02:29:27 PM PDT 24
Finished May 02 02:32:40 PM PDT 24
Peak memory 200416 kb
Host smart-ff93fe66-748c-4a17-b75b-7f7bd2cc2eb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2643835438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.2643835438
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.3751847712
Short name T1116
Test name
Test status
Simulation time 7236633000 ps
CPU time 12.27 seconds
Started May 02 02:29:27 PM PDT 24
Finished May 02 02:29:40 PM PDT 24
Peak memory 200440 kb
Host smart-59a52abf-d4ed-45b7-9dfc-fb04c83c6a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751847712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.3751847712
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.1409578230
Short name T31
Test name
Test status
Simulation time 129518295368 ps
CPU time 325.83 seconds
Started May 02 02:29:27 PM PDT 24
Finished May 02 02:34:54 PM PDT 24
Peak memory 199988 kb
Host smart-558dd162-d3d4-4ead-a0d8-84de8bea2b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409578230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.1409578230
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.886269317
Short name T392
Test name
Test status
Simulation time 17343645017 ps
CPU time 301.31 seconds
Started May 02 02:29:26 PM PDT 24
Finished May 02 02:34:28 PM PDT 24
Peak memory 200372 kb
Host smart-cbc14d1a-2d71-4549-af52-ed83d5c912d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=886269317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.886269317
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.512696770
Short name T1101
Test name
Test status
Simulation time 2903878136 ps
CPU time 8.61 seconds
Started May 02 02:29:28 PM PDT 24
Finished May 02 02:29:37 PM PDT 24
Peak memory 198860 kb
Host smart-bf62134b-0935-42a9-acc4-658284fd505f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=512696770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.512696770
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.4049983561
Short name T426
Test name
Test status
Simulation time 41832402370 ps
CPU time 19.23 seconds
Started May 02 02:29:28 PM PDT 24
Finished May 02 02:29:48 PM PDT 24
Peak memory 200324 kb
Host smart-b9814bf4-05d5-46d6-a1b3-84238ae637c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049983561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.4049983561
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.2484846081
Short name T342
Test name
Test status
Simulation time 4723864232 ps
CPU time 1.17 seconds
Started May 02 02:29:26 PM PDT 24
Finished May 02 02:29:29 PM PDT 24
Peak memory 196712 kb
Host smart-903971e9-0ab4-4a6f-98de-73445eabe31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484846081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.2484846081
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.201504485
Short name T386
Test name
Test status
Simulation time 5887845538 ps
CPU time 21.91 seconds
Started May 02 02:29:17 PM PDT 24
Finished May 02 02:29:40 PM PDT 24
Peak memory 200284 kb
Host smart-cad2a573-be5c-4c1d-b6d7-841fd654ad12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201504485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.201504485
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.3475654509
Short name T1015
Test name
Test status
Simulation time 477343404439 ps
CPU time 213.42 seconds
Started May 02 02:29:26 PM PDT 24
Finished May 02 02:33:01 PM PDT 24
Peak memory 208716 kb
Host smart-89212c0f-ef98-4c98-8be4-10707e14429c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475654509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.3475654509
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.2813409905
Short name T187
Test name
Test status
Simulation time 49589571247 ps
CPU time 457.56 seconds
Started May 02 02:29:26 PM PDT 24
Finished May 02 02:37:05 PM PDT 24
Peak memory 216896 kb
Host smart-c2ffe1cc-b26a-44c7-8194-796dd1594958
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813409905 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.2813409905
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.912469953
Short name T972
Test name
Test status
Simulation time 6590198132 ps
CPU time 15.89 seconds
Started May 02 02:29:26 PM PDT 24
Finished May 02 02:29:43 PM PDT 24
Peak memory 200220 kb
Host smart-68a315c6-e0eb-4b05-bb8a-3ee0ef59cfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912469953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.912469953
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.2313004676
Short name T661
Test name
Test status
Simulation time 25489183471 ps
CPU time 43.99 seconds
Started May 02 02:29:28 PM PDT 24
Finished May 02 02:30:12 PM PDT 24
Peak memory 199416 kb
Host smart-4545006b-c4b7-40da-9a44-c1a80a131c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313004676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.2313004676
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.3374102367
Short name T19
Test name
Test status
Simulation time 42171757 ps
CPU time 0.54 seconds
Started May 02 02:29:35 PM PDT 24
Finished May 02 02:29:36 PM PDT 24
Peak memory 195212 kb
Host smart-a412ba85-ef57-4cd8-b4df-ad810fa89a5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374102367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.3374102367
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.2528334851
Short name T1062
Test name
Test status
Simulation time 33429975887 ps
CPU time 72.33 seconds
Started May 02 02:29:28 PM PDT 24
Finished May 02 02:30:42 PM PDT 24
Peak memory 200344 kb
Host smart-d8be18e7-0dd6-49b7-b471-0e896bd50fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528334851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.2528334851
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.884446510
Short name T764
Test name
Test status
Simulation time 33053462966 ps
CPU time 27.2 seconds
Started May 02 02:29:26 PM PDT 24
Finished May 02 02:29:55 PM PDT 24
Peak memory 200384 kb
Host smart-f96f0170-9e8d-4fe4-ad6a-86cb80a4e3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884446510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.884446510
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.1377072241
Short name T846
Test name
Test status
Simulation time 125211850907 ps
CPU time 192.68 seconds
Started May 02 02:29:35 PM PDT 24
Finished May 02 02:32:49 PM PDT 24
Peak memory 200124 kb
Host smart-996bc286-7610-42d6-8e22-b0f2b285ffb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377072241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.1377072241
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.2826231002
Short name T4
Test name
Test status
Simulation time 628790520427 ps
CPU time 471.59 seconds
Started May 02 02:29:37 PM PDT 24
Finished May 02 02:37:30 PM PDT 24
Peak memory 200416 kb
Host smart-c0a8082f-3fe8-4d82-9953-588ed9228627
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826231002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.2826231002
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.961144627
Short name T859
Test name
Test status
Simulation time 50356025246 ps
CPU time 128.54 seconds
Started May 02 02:29:39 PM PDT 24
Finished May 02 02:31:50 PM PDT 24
Peak memory 200372 kb
Host smart-69486944-499c-4ca4-ae1d-b3ac627f4680
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=961144627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.961144627
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.1956041449
Short name T1165
Test name
Test status
Simulation time 1035725546 ps
CPU time 2.53 seconds
Started May 02 02:29:38 PM PDT 24
Finished May 02 02:29:42 PM PDT 24
Peak memory 200024 kb
Host smart-ffe3afcf-e234-4040-a5d5-c546011504f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956041449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.1956041449
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.3689546470
Short name T636
Test name
Test status
Simulation time 113519866162 ps
CPU time 125.25 seconds
Started May 02 02:29:36 PM PDT 24
Finished May 02 02:31:42 PM PDT 24
Peak memory 200584 kb
Host smart-c6380e75-0e61-475f-aa5f-4389c47442d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689546470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.3689546470
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.859237869
Short name T476
Test name
Test status
Simulation time 5082970627 ps
CPU time 291.72 seconds
Started May 02 02:29:37 PM PDT 24
Finished May 02 02:34:30 PM PDT 24
Peak memory 200380 kb
Host smart-deae47f2-eff4-4855-82ff-04bf9e8a759f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=859237869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.859237869
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.228218970
Short name T1141
Test name
Test status
Simulation time 7559052745 ps
CPU time 60.1 seconds
Started May 02 02:29:34 PM PDT 24
Finished May 02 02:30:35 PM PDT 24
Peak memory 199876 kb
Host smart-ba77e9c4-e8ca-4631-97ba-456c00b1c8b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=228218970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.228218970
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.536830560
Short name T129
Test name
Test status
Simulation time 160619457715 ps
CPU time 104.17 seconds
Started May 02 02:29:35 PM PDT 24
Finished May 02 02:31:21 PM PDT 24
Peak memory 200352 kb
Host smart-25d433d4-4340-4536-aaef-270a350d3249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536830560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.536830560
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.3727007481
Short name T720
Test name
Test status
Simulation time 4528569024 ps
CPU time 4.08 seconds
Started May 02 02:29:40 PM PDT 24
Finished May 02 02:29:46 PM PDT 24
Peak memory 196688 kb
Host smart-0cb806b1-1d48-49cd-9541-a40c7aab4278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727007481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.3727007481
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.1763572788
Short name T396
Test name
Test status
Simulation time 5747425142 ps
CPU time 8.32 seconds
Started May 02 02:29:28 PM PDT 24
Finished May 02 02:29:37 PM PDT 24
Peak memory 200356 kb
Host smart-39850bd1-69b4-43f1-8353-c61b3c4ec0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763572788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.1763572788
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.4252874422
Short name T903
Test name
Test status
Simulation time 157112674070 ps
CPU time 437.81 seconds
Started May 02 02:29:36 PM PDT 24
Finished May 02 02:36:55 PM PDT 24
Peak memory 200368 kb
Host smart-e7f9817b-5870-4e9f-a9ab-6d10ff6c2566
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252874422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.4252874422
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.4133029380
Short name T626
Test name
Test status
Simulation time 163803420993 ps
CPU time 781.5 seconds
Started May 02 02:29:34 PM PDT 24
Finished May 02 02:42:37 PM PDT 24
Peak memory 225272 kb
Host smart-905ab8fe-d5d2-4d29-a441-bf6842c5ea0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133029380 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.4133029380
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.871838269
Short name T393
Test name
Test status
Simulation time 2579324010 ps
CPU time 2.47 seconds
Started May 02 02:29:35 PM PDT 24
Finished May 02 02:29:38 PM PDT 24
Peak memory 199972 kb
Host smart-a5a7848d-3eee-4570-b084-facd1302bd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871838269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.871838269
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.3294120154
Short name T890
Test name
Test status
Simulation time 142417245686 ps
CPU time 72.04 seconds
Started May 02 02:29:26 PM PDT 24
Finished May 02 02:30:40 PM PDT 24
Peak memory 200436 kb
Host smart-c252dcfa-afba-4ad3-831f-3fbb30d1062e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294120154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.3294120154
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.3980491353
Short name T871
Test name
Test status
Simulation time 22010158 ps
CPU time 0.52 seconds
Started May 02 02:29:44 PM PDT 24
Finished May 02 02:29:46 PM PDT 24
Peak memory 194792 kb
Host smart-1eff1b71-6664-4452-b8e4-d79d029798aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980491353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.3980491353
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.521215227
Short name T404
Test name
Test status
Simulation time 23846856797 ps
CPU time 15.58 seconds
Started May 02 02:29:35 PM PDT 24
Finished May 02 02:29:52 PM PDT 24
Peak memory 199592 kb
Host smart-2a23f580-ddf9-457e-a86e-29743d747375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521215227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.521215227
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.2688753791
Short name T478
Test name
Test status
Simulation time 78432768414 ps
CPU time 38.17 seconds
Started May 02 02:29:37 PM PDT 24
Finished May 02 02:30:16 PM PDT 24
Peak memory 200376 kb
Host smart-c3a4a4ce-f3fa-4183-9766-018cde0d8a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688753791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.2688753791
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.3441987649
Short name T758
Test name
Test status
Simulation time 44027394809 ps
CPU time 28.47 seconds
Started May 02 02:29:37 PM PDT 24
Finished May 02 02:30:07 PM PDT 24
Peak memory 200456 kb
Host smart-a419e1b2-34ca-4e79-9ed5-b6b844434519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441987649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.3441987649
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.2312590064
Short name T444
Test name
Test status
Simulation time 56919716669 ps
CPU time 94.76 seconds
Started May 02 02:29:36 PM PDT 24
Finished May 02 02:31:12 PM PDT 24
Peak memory 200468 kb
Host smart-d05b1933-e7ef-4c86-b08c-d27e605ff8b9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312590064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.2312590064
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.1233833099
Short name T468
Test name
Test status
Simulation time 48605604920 ps
CPU time 452.05 seconds
Started May 02 02:29:42 PM PDT 24
Finished May 02 02:37:16 PM PDT 24
Peak memory 200424 kb
Host smart-489341cf-4e2a-41de-b493-dfea273d9091
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1233833099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.1233833099
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.194431425
Short name T343
Test name
Test status
Simulation time 3659554280 ps
CPU time 3.58 seconds
Started May 02 02:29:42 PM PDT 24
Finished May 02 02:29:47 PM PDT 24
Peak memory 199964 kb
Host smart-a8bdcec4-73f2-4b5f-9deb-891265bfa6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194431425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.194431425
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.3884788951
Short name T912
Test name
Test status
Simulation time 60228995785 ps
CPU time 25.94 seconds
Started May 02 02:29:42 PM PDT 24
Finished May 02 02:30:09 PM PDT 24
Peak memory 199248 kb
Host smart-a3aaccb1-d60b-4365-89ae-c4ce40196fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884788951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.3884788951
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.2158609730
Short name T463
Test name
Test status
Simulation time 19761796668 ps
CPU time 56.22 seconds
Started May 02 02:29:46 PM PDT 24
Finished May 02 02:30:43 PM PDT 24
Peak memory 200452 kb
Host smart-18d6c714-ad84-41c9-9a24-28bd05f8a625
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2158609730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.2158609730
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.106996571
Short name T1095
Test name
Test status
Simulation time 7004643995 ps
CPU time 15.49 seconds
Started May 02 02:29:36 PM PDT 24
Finished May 02 02:29:53 PM PDT 24
Peak memory 199572 kb
Host smart-5b3c2a2a-6879-4d29-9765-0ed527d4e1c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=106996571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.106996571
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.2197452539
Short name T469
Test name
Test status
Simulation time 91806615913 ps
CPU time 234.96 seconds
Started May 02 02:29:41 PM PDT 24
Finished May 02 02:33:37 PM PDT 24
Peak memory 200356 kb
Host smart-f720e4ee-0caa-48b0-b8e8-929cf199d9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197452539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.2197452539
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.3061423251
Short name T819
Test name
Test status
Simulation time 2168347192 ps
CPU time 1.72 seconds
Started May 02 02:29:42 PM PDT 24
Finished May 02 02:29:45 PM PDT 24
Peak memory 195856 kb
Host smart-a3db1081-f0ca-488e-af27-75429e3d9f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061423251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.3061423251
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.3892941190
Short name T1029
Test name
Test status
Simulation time 114341731 ps
CPU time 0.89 seconds
Started May 02 02:29:34 PM PDT 24
Finished May 02 02:29:36 PM PDT 24
Peak memory 197668 kb
Host smart-b73597bc-ce34-4c31-9f59-ffd9afa4594a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892941190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.3892941190
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.2458466132
Short name T89
Test name
Test status
Simulation time 99199564233 ps
CPU time 75.09 seconds
Started May 02 02:29:42 PM PDT 24
Finished May 02 02:30:59 PM PDT 24
Peak memory 216068 kb
Host smart-84986c29-d086-4338-b90e-7051adebbba5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458466132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2458466132
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.1360368255
Short name T714
Test name
Test status
Simulation time 27828300292 ps
CPU time 221.34 seconds
Started May 02 02:29:46 PM PDT 24
Finished May 02 02:33:28 PM PDT 24
Peak memory 216832 kb
Host smart-d5c5fd0b-0318-4c18-a446-e5c77f4ed26e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360368255 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.1360368255
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.2046090476
Short name T688
Test name
Test status
Simulation time 872161347 ps
CPU time 3.3 seconds
Started May 02 02:29:44 PM PDT 24
Finished May 02 02:29:48 PM PDT 24
Peak memory 199316 kb
Host smart-5e3dcf5d-b932-4bb7-9830-e3697f617bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046090476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.2046090476
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.1445344828
Short name T1011
Test name
Test status
Simulation time 23402504781 ps
CPU time 10.86 seconds
Started May 02 02:29:35 PM PDT 24
Finished May 02 02:29:47 PM PDT 24
Peak memory 198176 kb
Host smart-028a118c-67a2-4fc8-90f6-e95187fd4922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445344828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1445344828
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.2321045218
Short name T837
Test name
Test status
Simulation time 26332870 ps
CPU time 0.58 seconds
Started May 02 02:29:56 PM PDT 24
Finished May 02 02:29:58 PM PDT 24
Peak memory 195792 kb
Host smart-7b01409e-870f-4c9c-89a2-df9fc1e76631
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321045218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.2321045218
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.4079251311
Short name T870
Test name
Test status
Simulation time 40656999071 ps
CPU time 30.35 seconds
Started May 02 02:29:51 PM PDT 24
Finished May 02 02:30:22 PM PDT 24
Peak memory 200244 kb
Host smart-2ee04302-b2c5-4f93-a687-06ad679c160a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079251311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.4079251311
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.2475774726
Short name T395
Test name
Test status
Simulation time 65713870355 ps
CPU time 27.07 seconds
Started May 02 02:29:48 PM PDT 24
Finished May 02 02:30:16 PM PDT 24
Peak memory 200248 kb
Host smart-11681144-f3d1-4c6c-9f14-7836943e1f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475774726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.2475774726
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.598028064
Short name T830
Test name
Test status
Simulation time 112010821942 ps
CPU time 86.14 seconds
Started May 02 02:29:50 PM PDT 24
Finished May 02 02:31:18 PM PDT 24
Peak memory 200416 kb
Host smart-3de50fcd-698e-48e9-83a2-cca0746e610b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598028064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.598028064
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.1050433016
Short name T635
Test name
Test status
Simulation time 44654509287 ps
CPU time 38.6 seconds
Started May 02 02:29:48 PM PDT 24
Finished May 02 02:30:28 PM PDT 24
Peak memory 200408 kb
Host smart-38075699-76be-4fa0-bc18-a6380cbbde15
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050433016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.1050433016
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.4179273789
Short name T699
Test name
Test status
Simulation time 111406215353 ps
CPU time 701.27 seconds
Started May 02 02:29:57 PM PDT 24
Finished May 02 02:41:40 PM PDT 24
Peak memory 200416 kb
Host smart-2ad9ce00-8aad-4c09-ab08-71d148777193
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4179273789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.4179273789
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.234608022
Short name T363
Test name
Test status
Simulation time 2201220228 ps
CPU time 11.81 seconds
Started May 02 02:29:56 PM PDT 24
Finished May 02 02:30:09 PM PDT 24
Peak memory 199060 kb
Host smart-b7e60e03-244c-459b-a799-371c30b119e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234608022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.234608022
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.1890907337
Short name T310
Test name
Test status
Simulation time 1403847785 ps
CPU time 0.82 seconds
Started May 02 02:29:50 PM PDT 24
Finished May 02 02:29:52 PM PDT 24
Peak memory 194976 kb
Host smart-25446a00-bd37-4dc2-aebc-5210ba3b9d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890907337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.1890907337
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.714428544
Short name T593
Test name
Test status
Simulation time 19318381141 ps
CPU time 224.64 seconds
Started May 02 02:29:57 PM PDT 24
Finished May 02 02:33:43 PM PDT 24
Peak memory 200404 kb
Host smart-f4b008a6-1153-41c5-a8e0-6163cbf0bd0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=714428544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.714428544
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.2285240195
Short name T464
Test name
Test status
Simulation time 1611623532 ps
CPU time 2.01 seconds
Started May 02 02:29:49 PM PDT 24
Finished May 02 02:29:52 PM PDT 24
Peak memory 197228 kb
Host smart-d1a5c09d-f09c-4982-896a-640fcfdaf22e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2285240195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.2285240195
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.2105971099
Short name T42
Test name
Test status
Simulation time 75786552918 ps
CPU time 118.57 seconds
Started May 02 02:29:50 PM PDT 24
Finished May 02 02:31:49 PM PDT 24
Peak memory 200392 kb
Host smart-c17b8f05-0090-49b6-b977-9e76f3904538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105971099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.2105971099
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.4077309984
Short name T282
Test name
Test status
Simulation time 552929660 ps
CPU time 1.39 seconds
Started May 02 02:29:49 PM PDT 24
Finished May 02 02:29:51 PM PDT 24
Peak memory 195812 kb
Host smart-1b28329e-8dde-47e8-9f52-8a1828d5ff63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077309984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.4077309984
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.2557667641
Short name T390
Test name
Test status
Simulation time 6215201337 ps
CPU time 24.93 seconds
Started May 02 02:29:46 PM PDT 24
Finished May 02 02:30:12 PM PDT 24
Peak memory 200184 kb
Host smart-4d71f835-e730-4206-a78a-69f00ef65916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557667641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.2557667641
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.3520490669
Short name T1028
Test name
Test status
Simulation time 154862226044 ps
CPU time 377.78 seconds
Started May 02 02:29:57 PM PDT 24
Finished May 02 02:36:17 PM PDT 24
Peak memory 200412 kb
Host smart-de5a5771-c536-4ade-aa0e-9527a262bfa1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520490669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.3520490669
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.2420369114
Short name T85
Test name
Test status
Simulation time 6888343599 ps
CPU time 24.02 seconds
Started May 02 02:29:56 PM PDT 24
Finished May 02 02:30:21 PM PDT 24
Peak memory 200220 kb
Host smart-d7971da7-0cbf-4de3-95ed-bbecffc762d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420369114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.2420369114
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.2899416277
Short name T1117
Test name
Test status
Simulation time 73101500326 ps
CPU time 40.13 seconds
Started May 02 02:29:44 PM PDT 24
Finished May 02 02:30:26 PM PDT 24
Peak memory 200464 kb
Host smart-ed440fdc-43af-47db-84e6-6d636c5766fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899416277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.2899416277
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.946224165
Short name T610
Test name
Test status
Simulation time 38469198 ps
CPU time 0.51 seconds
Started May 02 02:30:04 PM PDT 24
Finished May 02 02:30:05 PM PDT 24
Peak memory 195104 kb
Host smart-9d2deee6-cd82-4216-82cb-7ca05c5794a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946224165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.946224165
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.643524695
Short name T1123
Test name
Test status
Simulation time 126190090799 ps
CPU time 186.1 seconds
Started May 02 02:29:58 PM PDT 24
Finished May 02 02:33:05 PM PDT 24
Peak memory 200388 kb
Host smart-4c1dccdc-343a-4d04-b913-6f827bc7db62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643524695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.643524695
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.2107608151
Short name T293
Test name
Test status
Simulation time 160771162545 ps
CPU time 128.7 seconds
Started May 02 02:29:57 PM PDT 24
Finished May 02 02:32:07 PM PDT 24
Peak memory 200360 kb
Host smart-8c5bb3c1-32f5-44be-8451-8e7c485e9f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107608151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.2107608151
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.3905501620
Short name T781
Test name
Test status
Simulation time 75431142435 ps
CPU time 63.63 seconds
Started May 02 02:29:57 PM PDT 24
Finished May 02 02:31:02 PM PDT 24
Peak memory 200376 kb
Host smart-159179a0-f3a6-424b-8c41-8cb9d5dcfd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905501620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.3905501620
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.3964520263
Short name T506
Test name
Test status
Simulation time 19238598745 ps
CPU time 9.35 seconds
Started May 02 02:29:59 PM PDT 24
Finished May 02 02:30:10 PM PDT 24
Peak memory 197960 kb
Host smart-a50a5ece-5386-4c81-84bd-fc7814ffa2a8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964520263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.3964520263
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.2722406901
Short name T294
Test name
Test status
Simulation time 43651779285 ps
CPU time 258.9 seconds
Started May 02 02:30:06 PM PDT 24
Finished May 02 02:34:27 PM PDT 24
Peak memory 200456 kb
Host smart-c8b30896-feee-4f6c-a72c-a22a7c38036a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2722406901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.2722406901
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.1038798147
Short name T371
Test name
Test status
Simulation time 1219026855 ps
CPU time 2.89 seconds
Started May 02 02:30:02 PM PDT 24
Finished May 02 02:30:06 PM PDT 24
Peak memory 198828 kb
Host smart-ec055776-84d6-40ca-9610-c3b429ca5620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038798147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.1038798147
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.907716392
Short name T816
Test name
Test status
Simulation time 129557845931 ps
CPU time 265.57 seconds
Started May 02 02:30:01 PM PDT 24
Finished May 02 02:34:28 PM PDT 24
Peak memory 215988 kb
Host smart-fdf19433-8004-460f-9ee6-d68bba72092c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907716392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.907716392
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.3277852428
Short name T1041
Test name
Test status
Simulation time 18059969342 ps
CPU time 149.1 seconds
Started May 02 02:30:05 PM PDT 24
Finished May 02 02:32:35 PM PDT 24
Peak memory 200324 kb
Host smart-fde8b760-f1af-4865-8bd2-be1e028f443c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3277852428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.3277852428
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.25695528
Short name T88
Test name
Test status
Simulation time 7417142020 ps
CPU time 17.83 seconds
Started May 02 02:29:55 PM PDT 24
Finished May 02 02:30:14 PM PDT 24
Peak memory 198384 kb
Host smart-e338d409-623f-479a-9a74-c73cbfc70bbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=25695528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.25695528
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.2188209117
Short name T773
Test name
Test status
Simulation time 23845909402 ps
CPU time 37.68 seconds
Started May 02 02:30:03 PM PDT 24
Finished May 02 02:30:41 PM PDT 24
Peak memory 200188 kb
Host smart-bd7fa56a-f80e-4429-984b-a83a51946be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188209117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.2188209117
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.762703242
Short name T842
Test name
Test status
Simulation time 3940671827 ps
CPU time 3.92 seconds
Started May 02 02:30:04 PM PDT 24
Finished May 02 02:30:08 PM PDT 24
Peak memory 196432 kb
Host smart-238ab6ec-c523-4d3f-9876-476f6f73ba20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762703242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.762703242
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.3038593364
Short name T1086
Test name
Test status
Simulation time 681326783 ps
CPU time 2.44 seconds
Started May 02 02:29:58 PM PDT 24
Finished May 02 02:30:02 PM PDT 24
Peak memory 198636 kb
Host smart-a13849ef-f02b-4879-bf2c-62c9266e1da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038593364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.3038593364
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.1759784250
Short name T101
Test name
Test status
Simulation time 300402066675 ps
CPU time 205.06 seconds
Started May 02 02:30:05 PM PDT 24
Finished May 02 02:33:31 PM PDT 24
Peak memory 200380 kb
Host smart-c3985f4e-b048-4a33-b4b4-e30fbac998ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759784250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.1759784250
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.658490315
Short name T954
Test name
Test status
Simulation time 98803945793 ps
CPU time 594.68 seconds
Started May 02 02:30:03 PM PDT 24
Finished May 02 02:39:59 PM PDT 24
Peak memory 216888 kb
Host smart-407ce0a8-6d87-41f8-a4f9-0446dca412b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658490315 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.658490315
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.10756174
Short name T689
Test name
Test status
Simulation time 12619527107 ps
CPU time 26.44 seconds
Started May 02 02:30:03 PM PDT 24
Finished May 02 02:30:30 PM PDT 24
Peak memory 200360 kb
Host smart-85727cb7-b511-41ca-a9ad-1a2439b7b7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10756174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.10756174
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.2677104521
Short name T969
Test name
Test status
Simulation time 17428812416 ps
CPU time 29.34 seconds
Started May 02 02:29:57 PM PDT 24
Finished May 02 02:30:27 PM PDT 24
Peak memory 200460 kb
Host smart-80216d10-50c7-4b75-820f-9467798143e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677104521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.2677104521
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.517040906
Short name T650
Test name
Test status
Simulation time 20278208 ps
CPU time 0.57 seconds
Started May 02 02:30:20 PM PDT 24
Finished May 02 02:30:22 PM PDT 24
Peak memory 195820 kb
Host smart-39eaeb53-dda6-4cd7-82ed-61d797952e2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517040906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.517040906
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.3278523854
Short name T122
Test name
Test status
Simulation time 35793308869 ps
CPU time 20.49 seconds
Started May 02 02:30:11 PM PDT 24
Finished May 02 02:30:33 PM PDT 24
Peak memory 200428 kb
Host smart-095b607a-354e-4d97-b739-ca616f0e2f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278523854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.3278523854
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.1377206772
Short name T423
Test name
Test status
Simulation time 78670331424 ps
CPU time 35.72 seconds
Started May 02 02:30:11 PM PDT 24
Finished May 02 02:30:48 PM PDT 24
Peak memory 200140 kb
Host smart-b4758aab-4a1d-4c06-9b4f-863244d04f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377206772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.1377206772
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.5402118
Short name T761
Test name
Test status
Simulation time 81756371480 ps
CPU time 39.92 seconds
Started May 02 02:30:11 PM PDT 24
Finished May 02 02:30:52 PM PDT 24
Peak memory 200308 kb
Host smart-ea2b9f75-de52-4cd9-a9b3-83ffd2fe6021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5402118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.5402118
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.2576765626
Short name T727
Test name
Test status
Simulation time 85846525317 ps
CPU time 151.89 seconds
Started May 02 02:30:14 PM PDT 24
Finished May 02 02:32:47 PM PDT 24
Peak memory 200428 kb
Host smart-29ed3582-1932-415d-9e5d-76f47a1d653d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576765626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.2576765626
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.3487813005
Short name T991
Test name
Test status
Simulation time 285021244566 ps
CPU time 557.43 seconds
Started May 02 02:30:19 PM PDT 24
Finished May 02 02:39:37 PM PDT 24
Peak memory 200456 kb
Host smart-573baf14-9bcb-4dae-80a0-c0694fe479d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3487813005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3487813005
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.3736866800
Short name T1016
Test name
Test status
Simulation time 926204938 ps
CPU time 1.96 seconds
Started May 02 02:30:11 PM PDT 24
Finished May 02 02:30:15 PM PDT 24
Peak memory 195872 kb
Host smart-dd0d85a2-a115-48a0-8b5e-6e018bfc875f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736866800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.3736866800
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.2048971562
Short name T1146
Test name
Test status
Simulation time 16759024044 ps
CPU time 7.33 seconds
Started May 02 02:30:11 PM PDT 24
Finished May 02 02:30:20 PM PDT 24
Peak memory 200380 kb
Host smart-5d7d9498-82ba-4103-830b-44de431ff74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048971562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.2048971562
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.2370078780
Short name T763
Test name
Test status
Simulation time 9504372245 ps
CPU time 153.05 seconds
Started May 02 02:30:08 PM PDT 24
Finished May 02 02:32:42 PM PDT 24
Peak memory 200436 kb
Host smart-3de6440a-83b4-4dd1-a033-f83a2fb790e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2370078780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.2370078780
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.1982222594
Short name T1136
Test name
Test status
Simulation time 3665181672 ps
CPU time 31.53 seconds
Started May 02 02:30:13 PM PDT 24
Finished May 02 02:30:46 PM PDT 24
Peak memory 198524 kb
Host smart-595fc740-18de-4f85-8147-7bb0503b7528
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1982222594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.1982222594
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.2497334806
Short name T358
Test name
Test status
Simulation time 40056017868 ps
CPU time 21.29 seconds
Started May 02 02:30:11 PM PDT 24
Finished May 02 02:30:34 PM PDT 24
Peak memory 200168 kb
Host smart-471a0852-9fb9-41f3-8742-967a9cc41302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497334806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.2497334806
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.1997178986
Short name T771
Test name
Test status
Simulation time 33055115654 ps
CPU time 12.77 seconds
Started May 02 02:30:12 PM PDT 24
Finished May 02 02:30:26 PM PDT 24
Peak memory 196228 kb
Host smart-5b593608-be35-4605-911a-c0dee963671f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997178986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.1997178986
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.219690771
Short name T548
Test name
Test status
Simulation time 302186854 ps
CPU time 1.33 seconds
Started May 02 02:30:05 PM PDT 24
Finished May 02 02:30:07 PM PDT 24
Peak memory 199172 kb
Host smart-39f0d136-a915-41d8-82b4-22ae88099360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219690771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.219690771
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.1474355916
Short name T664
Test name
Test status
Simulation time 120223008724 ps
CPU time 178.57 seconds
Started May 02 02:30:22 PM PDT 24
Finished May 02 02:33:23 PM PDT 24
Peak memory 200380 kb
Host smart-d0e40092-9cd8-43e9-b4ce-25da0ffb1186
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474355916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.1474355916
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.1484258209
Short name T627
Test name
Test status
Simulation time 47459881666 ps
CPU time 178.63 seconds
Started May 02 02:30:19 PM PDT 24
Finished May 02 02:33:19 PM PDT 24
Peak memory 217100 kb
Host smart-85409169-363b-4783-a119-91f811cf083a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484258209 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.1484258209
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.602440779
Short name T943
Test name
Test status
Simulation time 762657489 ps
CPU time 2.11 seconds
Started May 02 02:30:10 PM PDT 24
Finished May 02 02:30:14 PM PDT 24
Peak memory 199360 kb
Host smart-23f7dfd0-d5c1-4a92-8247-bc12cdf35e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602440779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.602440779
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.3091301668
Short name T1074
Test name
Test status
Simulation time 39213460466 ps
CPU time 62.49 seconds
Started May 02 02:30:12 PM PDT 24
Finished May 02 02:31:16 PM PDT 24
Peak memory 200364 kb
Host smart-231f1a21-1a41-48da-886d-531b4db80a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091301668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.3091301668
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.969523118
Short name T948
Test name
Test status
Simulation time 12818701 ps
CPU time 0.56 seconds
Started May 02 02:30:32 PM PDT 24
Finished May 02 02:30:35 PM PDT 24
Peak memory 195144 kb
Host smart-fc3bbed8-392e-4ba8-ae93-6d715bdb1b57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969523118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.969523118
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.518803346
Short name T981
Test name
Test status
Simulation time 127900872764 ps
CPU time 49.55 seconds
Started May 02 02:30:21 PM PDT 24
Finished May 02 02:31:12 PM PDT 24
Peak memory 200340 kb
Host smart-4153a518-3a84-4944-8974-45b72d8ba7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518803346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.518803346
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.2211053359
Short name T686
Test name
Test status
Simulation time 19006943862 ps
CPU time 38.51 seconds
Started May 02 02:30:20 PM PDT 24
Finished May 02 02:30:59 PM PDT 24
Peak memory 200324 kb
Host smart-952ac3b8-c652-4215-8f0c-8e412b7fff10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211053359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.2211053359
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.612134982
Short name T581
Test name
Test status
Simulation time 69694699573 ps
CPU time 65.03 seconds
Started May 02 02:30:21 PM PDT 24
Finished May 02 02:31:28 PM PDT 24
Peak memory 200320 kb
Host smart-4fa21dc4-4533-4c92-b0cd-aff6ed8dc0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612134982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.612134982
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.3914118251
Short name T896
Test name
Test status
Simulation time 20783745336 ps
CPU time 11.17 seconds
Started May 02 02:30:21 PM PDT 24
Finished May 02 02:30:34 PM PDT 24
Peak memory 197496 kb
Host smart-1ed0d352-81cd-451f-816c-c3a9aed801f2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914118251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.3914118251
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.939302035
Short name T677
Test name
Test status
Simulation time 51919426797 ps
CPU time 252.25 seconds
Started May 02 02:30:28 PM PDT 24
Finished May 02 02:34:41 PM PDT 24
Peak memory 200432 kb
Host smart-0ab4c42e-554a-4033-bc43-d1e813f16b94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=939302035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.939302035
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.306609417
Short name T772
Test name
Test status
Simulation time 5668640610 ps
CPU time 3.09 seconds
Started May 02 02:30:21 PM PDT 24
Finished May 02 02:30:25 PM PDT 24
Peak memory 197916 kb
Host smart-5b169739-f731-4fc7-8e9a-a7753f288b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306609417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.306609417
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.2068520294
Short name T1127
Test name
Test status
Simulation time 32713526078 ps
CPU time 48.69 seconds
Started May 02 02:30:21 PM PDT 24
Finished May 02 02:31:11 PM PDT 24
Peak memory 198104 kb
Host smart-457d671d-3e41-4626-9e05-1c1d75508077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068520294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.2068520294
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.3941859606
Short name T1118
Test name
Test status
Simulation time 17695213565 ps
CPU time 247.42 seconds
Started May 02 02:30:24 PM PDT 24
Finished May 02 02:34:33 PM PDT 24
Peak memory 200340 kb
Host smart-d1cbad57-3b99-45c7-a0f4-076e5603d2fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3941859606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.3941859606
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.3761585827
Short name T303
Test name
Test status
Simulation time 5669471048 ps
CPU time 11.51 seconds
Started May 02 02:30:22 PM PDT 24
Finished May 02 02:30:35 PM PDT 24
Peak memory 198464 kb
Host smart-f4e8802e-8494-449f-971f-ea08b3a24647
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3761585827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.3761585827
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.3315548676
Short name T571
Test name
Test status
Simulation time 27781814204 ps
CPU time 48.59 seconds
Started May 02 02:30:21 PM PDT 24
Finished May 02 02:31:11 PM PDT 24
Peak memory 200332 kb
Host smart-27842bd3-a7c6-4644-a8c9-f9ad9e12f2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315548676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3315548676
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.3674215204
Short name T3
Test name
Test status
Simulation time 3285780575 ps
CPU time 3.12 seconds
Started May 02 02:30:20 PM PDT 24
Finished May 02 02:30:25 PM PDT 24
Peak memory 196196 kb
Host smart-914a35b9-db36-4dc7-9d89-0d5bc4fb3619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674215204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.3674215204
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.468142187
Short name T616
Test name
Test status
Simulation time 6212045269 ps
CPU time 8.91 seconds
Started May 02 02:30:20 PM PDT 24
Finished May 02 02:30:30 PM PDT 24
Peak memory 200180 kb
Host smart-5f485b76-983b-4b5b-8d00-9f10c16f6cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468142187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.468142187
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.4008625548
Short name T793
Test name
Test status
Simulation time 245200175768 ps
CPU time 276.54 seconds
Started May 02 02:30:28 PM PDT 24
Finished May 02 02:35:05 PM PDT 24
Peak memory 208764 kb
Host smart-71c3e30f-9849-451e-9235-dfddaa4fd69e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008625548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.4008625548
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.3795605336
Short name T281
Test name
Test status
Simulation time 31717786775 ps
CPU time 307.64 seconds
Started May 02 02:30:28 PM PDT 24
Finished May 02 02:35:37 PM PDT 24
Peak memory 208040 kb
Host smart-980f38ec-b547-4a94-bfed-ff159e7a70f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795605336 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.3795605336
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.4062557961
Short name T1097
Test name
Test status
Simulation time 865734334 ps
CPU time 2.71 seconds
Started May 02 02:30:21 PM PDT 24
Finished May 02 02:30:25 PM PDT 24
Peak memory 199092 kb
Host smart-bf570b40-c1ee-4d87-ba5b-7e8b0a2bb937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062557961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.4062557961
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.1882762609
Short name T682
Test name
Test status
Simulation time 30795566981 ps
CPU time 60.48 seconds
Started May 02 02:30:20 PM PDT 24
Finished May 02 02:31:22 PM PDT 24
Peak memory 200376 kb
Host smart-decd2b44-d0ed-4230-9605-2f8d0ca99475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882762609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.1882762609
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.132053168
Short name T477
Test name
Test status
Simulation time 19983625 ps
CPU time 0.57 seconds
Started May 02 02:30:36 PM PDT 24
Finished May 02 02:30:39 PM PDT 24
Peak memory 195752 kb
Host smart-5acfa61f-34df-40be-aed2-032565372c40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132053168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.132053168
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.1490009170
Short name T840
Test name
Test status
Simulation time 41418667558 ps
CPU time 18.4 seconds
Started May 02 02:30:30 PM PDT 24
Finished May 02 02:30:50 PM PDT 24
Peak memory 200372 kb
Host smart-2085f713-f453-45bd-ac70-35befc5e6b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490009170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.1490009170
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.1926212277
Short name T623
Test name
Test status
Simulation time 64208704668 ps
CPU time 24.62 seconds
Started May 02 02:30:29 PM PDT 24
Finished May 02 02:30:56 PM PDT 24
Peak memory 200464 kb
Host smart-145438d4-9d95-48ef-a2d4-cf8000a6677b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926212277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.1926212277
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.2618725450
Short name T106
Test name
Test status
Simulation time 38211456495 ps
CPU time 25.05 seconds
Started May 02 02:30:27 PM PDT 24
Finished May 02 02:30:54 PM PDT 24
Peak memory 200424 kb
Host smart-38177ad6-d563-49ad-8311-100214b92f4f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618725450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.2618725450
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.2991744003
Short name T498
Test name
Test status
Simulation time 38669916435 ps
CPU time 200.09 seconds
Started May 02 02:30:30 PM PDT 24
Finished May 02 02:33:53 PM PDT 24
Peak memory 200452 kb
Host smart-a2127cb9-e88d-46af-9b7d-dd0ca9ae4d80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2991744003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.2991744003
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.2908861313
Short name T1017
Test name
Test status
Simulation time 3893670864 ps
CPU time 13.1 seconds
Started May 02 02:30:30 PM PDT 24
Finished May 02 02:30:45 PM PDT 24
Peak memory 200072 kb
Host smart-59458b52-a2c9-4de5-9c5e-46b0991d415a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908861313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.2908861313
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.2772503673
Short name T380
Test name
Test status
Simulation time 23899053725 ps
CPU time 43.87 seconds
Started May 02 02:30:29 PM PDT 24
Finished May 02 02:31:15 PM PDT 24
Peak memory 200576 kb
Host smart-21670777-fbec-498e-a520-4778e5acb605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772503673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.2772503673
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.3010426862
Short name T1125
Test name
Test status
Simulation time 11803964307 ps
CPU time 610.42 seconds
Started May 02 02:30:32 PM PDT 24
Finished May 02 02:40:44 PM PDT 24
Peak memory 200468 kb
Host smart-c818ec8d-2857-46bd-9777-2439056eba51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3010426862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.3010426862
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.1313902020
Short name T711
Test name
Test status
Simulation time 3894200904 ps
CPU time 22.93 seconds
Started May 02 02:30:27 PM PDT 24
Finished May 02 02:30:51 PM PDT 24
Peak memory 199052 kb
Host smart-3308e094-66cc-4ddc-89b1-e8fdd2b03484
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1313902020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.1313902020
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.3669069850
Short name T144
Test name
Test status
Simulation time 22459829882 ps
CPU time 36.7 seconds
Started May 02 02:30:30 PM PDT 24
Finished May 02 02:31:09 PM PDT 24
Peak memory 200388 kb
Host smart-d2962737-3cd6-497f-b2cf-db84341968d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669069850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.3669069850
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.1995474760
Short name T959
Test name
Test status
Simulation time 2103802878 ps
CPU time 1.61 seconds
Started May 02 02:30:29 PM PDT 24
Finished May 02 02:30:33 PM PDT 24
Peak memory 195792 kb
Host smart-35b6b80d-08e5-4497-9ca9-d4746ea4e070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995474760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1995474760
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.4077130949
Short name T1168
Test name
Test status
Simulation time 450911955 ps
CPU time 2.42 seconds
Started May 02 02:30:29 PM PDT 24
Finished May 02 02:30:34 PM PDT 24
Peak memory 198004 kb
Host smart-85fc0048-5097-4c1d-b4ba-887a1f8bd47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077130949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.4077130949
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.3574840969
Short name T665
Test name
Test status
Simulation time 375348993579 ps
CPU time 107.8 seconds
Started May 02 02:30:35 PM PDT 24
Finished May 02 02:32:24 PM PDT 24
Peak memory 208756 kb
Host smart-19dda8b6-8a38-4d7c-8758-51a7041eea5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574840969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.3574840969
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.3944810868
Short name T999
Test name
Test status
Simulation time 133003633102 ps
CPU time 593.47 seconds
Started May 02 02:30:36 PM PDT 24
Finished May 02 02:40:32 PM PDT 24
Peak memory 211900 kb
Host smart-c7404b68-d1a3-4264-892d-bfa39c6072fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944810868 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.3944810868
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.1142286006
Short name T1083
Test name
Test status
Simulation time 1621646910 ps
CPU time 2.03 seconds
Started May 02 02:30:30 PM PDT 24
Finished May 02 02:30:34 PM PDT 24
Peak memory 199468 kb
Host smart-52afe86a-819d-4756-8d07-d5cd23d04403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142286006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.1142286006
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.3935379973
Short name T1161
Test name
Test status
Simulation time 45441258064 ps
CPU time 78.43 seconds
Started May 02 02:30:30 PM PDT 24
Finished May 02 02:31:50 PM PDT 24
Peak memory 200364 kb
Host smart-fb47e25d-c9f2-4d5c-ab00-790c136fbcd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935379973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.3935379973
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.2999411936
Short name T698
Test name
Test status
Simulation time 25528249 ps
CPU time 0.61 seconds
Started May 02 02:30:42 PM PDT 24
Finished May 02 02:30:45 PM PDT 24
Peak memory 195800 kb
Host smart-2d34e89e-b318-4cb6-9335-4ef7ead5b157
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999411936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.2999411936
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.4154261826
Short name T555
Test name
Test status
Simulation time 124384162077 ps
CPU time 114.75 seconds
Started May 02 02:31:01 PM PDT 24
Finished May 02 02:32:57 PM PDT 24
Peak memory 200420 kb
Host smart-9abaffd6-a365-44b6-b517-2760a199dec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154261826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.4154261826
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.2400731208
Short name T91
Test name
Test status
Simulation time 14084417023 ps
CPU time 24.18 seconds
Started May 02 02:30:36 PM PDT 24
Finished May 02 02:31:03 PM PDT 24
Peak memory 200368 kb
Host smart-bd1ac814-aaa4-467d-b388-986c66728a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400731208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.2400731208
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.781790150
Short name T1096
Test name
Test status
Simulation time 83018979229 ps
CPU time 116.6 seconds
Started May 02 02:30:42 PM PDT 24
Finished May 02 02:32:41 PM PDT 24
Peak memory 200428 kb
Host smart-6be9988c-2610-4663-95a2-388dd2d182fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781790150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.781790150
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.4192859832
Short name T255
Test name
Test status
Simulation time 4796343149 ps
CPU time 9.96 seconds
Started May 02 02:30:41 PM PDT 24
Finished May 02 02:30:53 PM PDT 24
Peak memory 200224 kb
Host smart-648f70a8-6fe2-4b4c-a363-d41152f4f1b2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192859832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.4192859832
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.4031881873
Short name T272
Test name
Test status
Simulation time 75327239739 ps
CPU time 683.76 seconds
Started May 02 02:30:44 PM PDT 24
Finished May 02 02:42:09 PM PDT 24
Peak memory 200464 kb
Host smart-98a90cbf-c28d-4566-97a0-5a9867a7cf67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4031881873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.4031881873
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.3492377745
Short name T742
Test name
Test status
Simulation time 3570682751 ps
CPU time 7.09 seconds
Started May 02 02:30:45 PM PDT 24
Finished May 02 02:30:54 PM PDT 24
Peak memory 199312 kb
Host smart-782c9bed-ce9e-4743-a8c0-b51cdec2178a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492377745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.3492377745
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.955019560
Short name T267
Test name
Test status
Simulation time 91221625752 ps
CPU time 52.14 seconds
Started May 02 02:30:45 PM PDT 24
Finished May 02 02:31:38 PM PDT 24
Peak memory 215988 kb
Host smart-37514917-612c-4813-a256-6198219b1b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955019560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.955019560
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.1377257256
Short name T335
Test name
Test status
Simulation time 4389729958 ps
CPU time 241.53 seconds
Started May 02 02:30:41 PM PDT 24
Finished May 02 02:34:45 PM PDT 24
Peak memory 200456 kb
Host smart-7c95a66c-7d0e-467b-8b8e-d53662f0d921
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1377257256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.1377257256
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.1489757701
Short name T432
Test name
Test status
Simulation time 6787188785 ps
CPU time 67.47 seconds
Started May 02 02:30:43 PM PDT 24
Finished May 02 02:31:52 PM PDT 24
Peak memory 198532 kb
Host smart-d0c908f3-717e-4191-940a-e3e4612d12a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1489757701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.1489757701
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.4271340029
Short name T1167
Test name
Test status
Simulation time 121084840211 ps
CPU time 220.12 seconds
Started May 02 02:30:44 PM PDT 24
Finished May 02 02:34:25 PM PDT 24
Peak memory 200408 kb
Host smart-8da9ff9d-0154-435e-9902-95eec864d187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271340029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.4271340029
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.2571059174
Short name T412
Test name
Test status
Simulation time 5875467647 ps
CPU time 2.7 seconds
Started May 02 02:30:43 PM PDT 24
Finished May 02 02:30:48 PM PDT 24
Peak memory 196416 kb
Host smart-78df8bed-f130-4f51-9589-19a753b0a5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571059174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.2571059174
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.132308060
Short name T1093
Test name
Test status
Simulation time 692872962 ps
CPU time 3.17 seconds
Started May 02 02:30:35 PM PDT 24
Finished May 02 02:30:40 PM PDT 24
Peak memory 199948 kb
Host smart-3bfd504b-2a1e-4c24-add1-d546fb6e0b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132308060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.132308060
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.4038406253
Short name T526
Test name
Test status
Simulation time 93207613408 ps
CPU time 97.19 seconds
Started May 02 02:30:44 PM PDT 24
Finished May 02 02:32:23 PM PDT 24
Peak memory 200412 kb
Host smart-fa9f7357-b34e-4a52-886b-d069af6ca7f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038406253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.4038406253
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.75479465
Short name T905
Test name
Test status
Simulation time 154201279763 ps
CPU time 366.99 seconds
Started May 02 02:31:04 PM PDT 24
Finished May 02 02:37:13 PM PDT 24
Peak memory 217300 kb
Host smart-ab12bf7a-6d2f-4f5f-b7fc-a78f5e4af989
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75479465 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.75479465
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.4198540867
Short name T1177
Test name
Test status
Simulation time 692742129 ps
CPU time 2 seconds
Started May 02 02:30:43 PM PDT 24
Finished May 02 02:30:47 PM PDT 24
Peak memory 199288 kb
Host smart-24500b9f-70a9-4da2-8838-f424907312f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198540867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.4198540867
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.2034371064
Short name T906
Test name
Test status
Simulation time 102534458802 ps
CPU time 18.35 seconds
Started May 02 02:30:38 PM PDT 24
Finished May 02 02:30:59 PM PDT 24
Peak memory 200424 kb
Host smart-e10c0852-6592-4e06-a3ef-12464a84b06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034371064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.2034371064
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.3685356750
Short name T1115
Test name
Test status
Simulation time 165258753 ps
CPU time 0.58 seconds
Started May 02 02:24:54 PM PDT 24
Finished May 02 02:24:57 PM PDT 24
Peak memory 195752 kb
Host smart-06251cc6-a046-4f37-ba9b-c8a111f630a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685356750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.3685356750
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1209125816
Short name T710
Test name
Test status
Simulation time 136538714583 ps
CPU time 204.91 seconds
Started May 02 02:24:52 PM PDT 24
Finished May 02 02:28:20 PM PDT 24
Peak memory 200392 kb
Host smart-7687e78f-d5b6-43eb-bb28-909a96941b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209125816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1209125816
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.971673420
Short name T604
Test name
Test status
Simulation time 303458702677 ps
CPU time 153.53 seconds
Started May 02 02:24:55 PM PDT 24
Finished May 02 02:27:31 PM PDT 24
Peak memory 200460 kb
Host smart-45734b66-a046-4715-8a05-7cc1e83aa3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971673420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.971673420
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.4136434795
Short name T510
Test name
Test status
Simulation time 37505207701 ps
CPU time 19.94 seconds
Started May 02 02:24:55 PM PDT 24
Finished May 02 02:25:17 PM PDT 24
Peak memory 200368 kb
Host smart-e4ef18bf-dc4a-416a-8d63-dc1582cc6baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136434795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.4136434795
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.2972077611
Short name T704
Test name
Test status
Simulation time 20686513419 ps
CPU time 10.52 seconds
Started May 02 02:24:58 PM PDT 24
Finished May 02 02:25:10 PM PDT 24
Peak memory 200152 kb
Host smart-62d1d1ee-ce39-411a-a74e-683bd9fd6995
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972077611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.2972077611
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.1016444272
Short name T431
Test name
Test status
Simulation time 86704065022 ps
CPU time 760.93 seconds
Started May 02 02:24:55 PM PDT 24
Finished May 02 02:37:38 PM PDT 24
Peak memory 200436 kb
Host smart-0bcdaf42-16a9-4ee2-9e3a-dd04d673edde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1016444272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.1016444272
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.327164635
Short name T995
Test name
Test status
Simulation time 4779067299 ps
CPU time 14.72 seconds
Started May 02 02:24:54 PM PDT 24
Finished May 02 02:25:11 PM PDT 24
Peak memory 199348 kb
Host smart-cbbdfcdd-5640-4256-8f5f-93d2961f2e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327164635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.327164635
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.3029164366
Short name T1
Test name
Test status
Simulation time 45439220274 ps
CPU time 19.07 seconds
Started May 02 02:24:53 PM PDT 24
Finished May 02 02:25:14 PM PDT 24
Peak memory 197924 kb
Host smart-cfa42f27-b88e-40cb-808b-6ce36c9ef607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029164366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.3029164366
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.2554898812
Short name T266
Test name
Test status
Simulation time 3523265632 ps
CPU time 98.99 seconds
Started May 02 02:24:53 PM PDT 24
Finished May 02 02:26:34 PM PDT 24
Peak memory 200388 kb
Host smart-49713b96-0ea5-4051-9e91-bef07a1bbff7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2554898812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2554898812
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.1574365742
Short name T820
Test name
Test status
Simulation time 3592225485 ps
CPU time 6.79 seconds
Started May 02 02:24:57 PM PDT 24
Finished May 02 02:25:05 PM PDT 24
Peak memory 198544 kb
Host smart-cfecac76-32a8-4001-8a52-a2b5f8ebfc94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1574365742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.1574365742
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.3561712811
Short name T14
Test name
Test status
Simulation time 193175676408 ps
CPU time 27.7 seconds
Started May 02 02:24:58 PM PDT 24
Finished May 02 02:25:27 PM PDT 24
Peak memory 200128 kb
Host smart-6e88e5bb-7fb5-4844-acdb-f1ff9b761e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561712811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.3561712811
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.1575830544
Short name T2
Test name
Test status
Simulation time 48719668400 ps
CPU time 51.91 seconds
Started May 02 02:24:54 PM PDT 24
Finished May 02 02:25:48 PM PDT 24
Peak memory 196404 kb
Host smart-14879334-8514-42a9-9721-62eced1774f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575830544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1575830544
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.1982809401
Short name T597
Test name
Test status
Simulation time 82631345 ps
CPU time 0.83 seconds
Started May 02 02:24:46 PM PDT 24
Finished May 02 02:24:51 PM PDT 24
Peak memory 197404 kb
Host smart-8f01f952-b746-4597-a7f8-9afa9c19ba5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982809401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1982809401
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.37337188
Short name T910
Test name
Test status
Simulation time 251786461120 ps
CPU time 1166.74 seconds
Started May 02 02:24:57 PM PDT 24
Finished May 02 02:44:26 PM PDT 24
Peak memory 200356 kb
Host smart-ba0b21ea-7cf2-4cea-8dd1-ca79f8066abc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37337188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.37337188
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.1384385464
Short name T743
Test name
Test status
Simulation time 53280101837 ps
CPU time 538.58 seconds
Started May 02 02:24:56 PM PDT 24
Finished May 02 02:33:56 PM PDT 24
Peak memory 216080 kb
Host smart-801826be-c45b-483f-847c-275bed9a0c5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384385464 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.1384385464
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.160106360
Short name T1051
Test name
Test status
Simulation time 7512830440 ps
CPU time 10.58 seconds
Started May 02 02:24:56 PM PDT 24
Finished May 02 02:25:08 PM PDT 24
Peak memory 199944 kb
Host smart-8462e60a-67ae-44a8-843a-da60df4349be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160106360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.160106360
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.2839437378
Short name T90
Test name
Test status
Simulation time 30901825157 ps
CPU time 48.5 seconds
Started May 02 02:24:49 PM PDT 24
Finished May 02 02:25:41 PM PDT 24
Peak memory 200416 kb
Host smart-68655f9c-d76a-4c13-87ad-b11ee31c0d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839437378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.2839437378
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.3065599507
Short name T1156
Test name
Test status
Simulation time 93917187112 ps
CPU time 661.42 seconds
Started May 02 02:30:50 PM PDT 24
Finished May 02 02:41:52 PM PDT 24
Peak memory 216896 kb
Host smart-62b9dc5d-7a21-403e-bd0c-db85b1a41edd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065599507 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.3065599507
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.3378018465
Short name T703
Test name
Test status
Simulation time 101872870885 ps
CPU time 169.7 seconds
Started May 02 02:30:51 PM PDT 24
Finished May 02 02:33:42 PM PDT 24
Peak memory 200232 kb
Host smart-6ac5892e-5f8a-4e20-aef4-d93e0bdc52cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378018465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.3378018465
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.3588326078
Short name T96
Test name
Test status
Simulation time 99055685069 ps
CPU time 463.04 seconds
Started May 02 02:30:54 PM PDT 24
Finished May 02 02:38:38 PM PDT 24
Peak memory 225216 kb
Host smart-5b7faa06-4499-4f0a-9c65-061e3732010f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588326078 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.3588326078
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.2032711776
Short name T1178
Test name
Test status
Simulation time 9179820133 ps
CPU time 109.06 seconds
Started May 02 02:30:51 PM PDT 24
Finished May 02 02:32:41 PM PDT 24
Peak memory 216960 kb
Host smart-a8080833-682b-48b0-b720-ae5aa53b4a5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032711776 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.2032711776
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.364274592
Short name T857
Test name
Test status
Simulation time 8794272535 ps
CPU time 15.67 seconds
Started May 02 02:30:50 PM PDT 24
Finished May 02 02:31:07 PM PDT 24
Peak memory 200436 kb
Host smart-71614da1-311e-4f8a-85ea-dc9261a53bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364274592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.364274592
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.2974780813
Short name T17
Test name
Test status
Simulation time 47827412122 ps
CPU time 951 seconds
Started May 02 02:30:52 PM PDT 24
Finished May 02 02:46:44 PM PDT 24
Peak memory 212044 kb
Host smart-a4123750-03c9-4d57-bc8f-2ec59aa54467
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974780813 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.2974780813
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.1310702415
Short name T1060
Test name
Test status
Simulation time 239583412242 ps
CPU time 326.03 seconds
Started May 02 02:30:50 PM PDT 24
Finished May 02 02:36:17 PM PDT 24
Peak memory 200436 kb
Host smart-26027b78-42d4-4ff9-b07f-d2a521da2644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310702415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.1310702415
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.90812171
Short name T50
Test name
Test status
Simulation time 70239341749 ps
CPU time 368.92 seconds
Started May 02 02:30:50 PM PDT 24
Finished May 02 02:36:59 PM PDT 24
Peak memory 209720 kb
Host smart-2810360e-6826-4629-baf7-ec51b7cc700c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90812171 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.90812171
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.1332695930
Short name T1069
Test name
Test status
Simulation time 11820017292 ps
CPU time 20.36 seconds
Started May 02 02:30:51 PM PDT 24
Finished May 02 02:31:12 PM PDT 24
Peak memory 200348 kb
Host smart-0c0890dc-6d4b-4c93-9f6a-ef0ba9bfc65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332695930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1332695930
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.845035746
Short name T826
Test name
Test status
Simulation time 14551861911 ps
CPU time 135.76 seconds
Started May 02 02:30:50 PM PDT 24
Finished May 02 02:33:06 PM PDT 24
Peak memory 216864 kb
Host smart-6f8def3f-4b47-454f-abf6-d7dda83430ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845035746 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.845035746
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.900403383
Short name T590
Test name
Test status
Simulation time 92388726733 ps
CPU time 84.5 seconds
Started May 02 02:30:58 PM PDT 24
Finished May 02 02:32:24 PM PDT 24
Peak memory 200360 kb
Host smart-cf4e4497-db82-49c8-bfca-0eb952187e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900403383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.900403383
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.2886576452
Short name T1079
Test name
Test status
Simulation time 10761992885 ps
CPU time 410.37 seconds
Started May 02 02:30:57 PM PDT 24
Finished May 02 02:37:49 PM PDT 24
Peak memory 215988 kb
Host smart-546e35c4-2357-4c3b-baed-098e6b82ae7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886576452 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.2886576452
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.996207764
Short name T484
Test name
Test status
Simulation time 15124181680 ps
CPU time 27.88 seconds
Started May 02 02:30:57 PM PDT 24
Finished May 02 02:31:27 PM PDT 24
Peak memory 200428 kb
Host smart-73003440-04d4-4ea5-ae51-e0f63ebed142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996207764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.996207764
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.1458173213
Short name T802
Test name
Test status
Simulation time 70670723774 ps
CPU time 888.4 seconds
Started May 02 02:30:57 PM PDT 24
Finished May 02 02:45:47 PM PDT 24
Peak memory 225252 kb
Host smart-49a91348-3f13-4217-81a7-dc80f9b0f4ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458173213 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.1458173213
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.1039884486
Short name T416
Test name
Test status
Simulation time 34216310797 ps
CPU time 22.33 seconds
Started May 02 02:30:56 PM PDT 24
Finished May 02 02:31:20 PM PDT 24
Peak memory 200388 kb
Host smart-06deba4e-b48b-4bed-9790-900c07f79672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039884486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1039884486
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.3966427545
Short name T767
Test name
Test status
Simulation time 32188119462 ps
CPU time 373.36 seconds
Started May 02 02:31:02 PM PDT 24
Finished May 02 02:37:17 PM PDT 24
Peak memory 216696 kb
Host smart-b5871d21-4ecc-4298-9661-3c2fdaa3eb78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966427545 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.3966427545
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.1613339309
Short name T737
Test name
Test status
Simulation time 62989115 ps
CPU time 0.57 seconds
Started May 02 02:25:03 PM PDT 24
Finished May 02 02:25:08 PM PDT 24
Peak memory 195832 kb
Host smart-34fb5f92-7e8a-4a65-9bec-4631e04dd0fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613339309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.1613339309
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.1812066827
Short name T337
Test name
Test status
Simulation time 16861170271 ps
CPU time 26.64 seconds
Started May 02 02:24:52 PM PDT 24
Finished May 02 02:25:21 PM PDT 24
Peak memory 200380 kb
Host smart-99e7859e-9dd0-453d-94f0-d2a535a85cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812066827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.1812066827
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.1138014943
Short name T643
Test name
Test status
Simulation time 73381916169 ps
CPU time 39.27 seconds
Started May 02 02:24:56 PM PDT 24
Finished May 02 02:25:37 PM PDT 24
Peak memory 200356 kb
Host smart-58efe78c-89b7-4afe-9018-2f3bae3cdc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138014943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.1138014943
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.543033114
Short name T180
Test name
Test status
Simulation time 42325765787 ps
CPU time 24.48 seconds
Started May 02 02:24:53 PM PDT 24
Finished May 02 02:25:20 PM PDT 24
Peak memory 200368 kb
Host smart-41c5be66-d97a-4959-982b-118133cf3540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543033114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.543033114
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.1012197449
Short name T1150
Test name
Test status
Simulation time 28391087810 ps
CPU time 16.43 seconds
Started May 02 02:24:53 PM PDT 24
Finished May 02 02:25:12 PM PDT 24
Peak memory 200348 kb
Host smart-80abc32b-f2b7-42bd-9f79-43d84e3013a5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012197449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1012197449
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.1951802518
Short name T528
Test name
Test status
Simulation time 131736180195 ps
CPU time 1037.14 seconds
Started May 02 02:25:02 PM PDT 24
Finished May 02 02:42:23 PM PDT 24
Peak memory 200384 kb
Host smart-5f3d4c14-c17c-4da2-8598-5221251d763a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1951802518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.1951802518
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.1673001186
Short name T512
Test name
Test status
Simulation time 4174920010 ps
CPU time 2.41 seconds
Started May 02 02:25:02 PM PDT 24
Finished May 02 02:25:08 PM PDT 24
Peak memory 197544 kb
Host smart-1fa74104-a7bf-44db-90f1-b3a9c46b9367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673001186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.1673001186
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.539653940
Short name T465
Test name
Test status
Simulation time 35671358616 ps
CPU time 56.22 seconds
Started May 02 02:25:01 PM PDT 24
Finished May 02 02:26:00 PM PDT 24
Peak memory 200576 kb
Host smart-29f68c89-b557-4eea-9dbf-febfb2e7e01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539653940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.539653940
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.875188078
Short name T523
Test name
Test status
Simulation time 2615240909 ps
CPU time 79.18 seconds
Started May 02 02:25:02 PM PDT 24
Finished May 02 02:26:25 PM PDT 24
Peak memory 200432 kb
Host smart-cbcbfadc-556e-4f11-8597-b3911ae2b97f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=875188078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.875188078
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.552538449
Short name T524
Test name
Test status
Simulation time 1788069883 ps
CPU time 12.16 seconds
Started May 02 02:25:00 PM PDT 24
Finished May 02 02:25:15 PM PDT 24
Peak memory 199212 kb
Host smart-aeabfa15-cf14-426b-aa1a-23a133389262
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=552538449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.552538449
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.2047938677
Short name T307
Test name
Test status
Simulation time 62260743964 ps
CPU time 104.71 seconds
Started May 02 02:25:18 PM PDT 24
Finished May 02 02:27:04 PM PDT 24
Peak memory 200348 kb
Host smart-e728013d-9b21-4150-b1af-57f62b166cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047938677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.2047938677
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.3353832983
Short name T409
Test name
Test status
Simulation time 2601631317 ps
CPU time 2.61 seconds
Started May 02 02:25:02 PM PDT 24
Finished May 02 02:25:08 PM PDT 24
Peak memory 196448 kb
Host smart-ef167ac5-fcb4-484e-b25e-d00856eda358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353832983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.3353832983
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.2728096716
Short name T37
Test name
Test status
Simulation time 6085447687 ps
CPU time 7.26 seconds
Started May 02 02:24:55 PM PDT 24
Finished May 02 02:25:05 PM PDT 24
Peak memory 200036 kb
Host smart-16809650-e553-4cd3-8d7c-da620a4df4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728096716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.2728096716
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.4254849916
Short name T1099
Test name
Test status
Simulation time 25724229860 ps
CPU time 105.94 seconds
Started May 02 02:25:06 PM PDT 24
Finished May 02 02:26:56 PM PDT 24
Peak memory 200616 kb
Host smart-f65be060-4371-4630-9b0f-99218d98e0b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254849916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.4254849916
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.2820446883
Short name T1090
Test name
Test status
Simulation time 6868756575 ps
CPU time 11.42 seconds
Started May 02 02:25:01 PM PDT 24
Finished May 02 02:25:17 PM PDT 24
Peak memory 199980 kb
Host smart-56d7f29a-f2d1-4d47-9fbc-832ae286157f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820446883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.2820446883
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.1296704472
Short name T262
Test name
Test status
Simulation time 152652799838 ps
CPU time 85.62 seconds
Started May 02 02:24:54 PM PDT 24
Finished May 02 02:26:22 PM PDT 24
Peak memory 200396 kb
Host smart-9d246ef9-f0fc-4056-a447-96b8cc364cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296704472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.1296704472
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.1252728389
Short name T169
Test name
Test status
Simulation time 29936649326 ps
CPU time 13.13 seconds
Started May 02 02:30:55 PM PDT 24
Finished May 02 02:31:10 PM PDT 24
Peak memory 200404 kb
Host smart-b26a71da-fd12-4f8b-9acc-daa27f0e3fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252728389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1252728389
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.1946565337
Short name T290
Test name
Test status
Simulation time 59854531314 ps
CPU time 131.61 seconds
Started May 02 02:30:57 PM PDT 24
Finished May 02 02:33:10 PM PDT 24
Peak memory 216816 kb
Host smart-9009e84f-d263-47d3-8f95-615d459c79ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946565337 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.1946565337
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.1706605876
Short name T740
Test name
Test status
Simulation time 205733019369 ps
CPU time 318.26 seconds
Started May 02 02:30:56 PM PDT 24
Finished May 02 02:36:16 PM PDT 24
Peak memory 200348 kb
Host smart-9c1de62a-5521-45d2-8fe4-ddc89a1b64df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706605876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.1706605876
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.1228741971
Short name T770
Test name
Test status
Simulation time 47554503555 ps
CPU time 482.56 seconds
Started May 02 02:30:56 PM PDT 24
Finished May 02 02:39:00 PM PDT 24
Peak memory 217040 kb
Host smart-6fb3d165-677a-412a-972c-9a6b35e57c86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228741971 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.1228741971
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.2576485511
Short name T459
Test name
Test status
Simulation time 90489361122 ps
CPU time 397.98 seconds
Started May 02 02:30:55 PM PDT 24
Finished May 02 02:37:35 PM PDT 24
Peak memory 217048 kb
Host smart-cee37492-b964-4f51-92d7-ea22f19d39c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576485511 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.2576485511
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.871413745
Short name T256
Test name
Test status
Simulation time 136856236344 ps
CPU time 51.13 seconds
Started May 02 02:30:58 PM PDT 24
Finished May 02 02:31:50 PM PDT 24
Peak memory 200364 kb
Host smart-bf476d7f-bf27-425c-8df4-e18ea9c7ca80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871413745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.871413745
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.2897290517
Short name T204
Test name
Test status
Simulation time 29336375193 ps
CPU time 336.33 seconds
Started May 02 02:30:59 PM PDT 24
Finished May 02 02:36:37 PM PDT 24
Peak memory 208732 kb
Host smart-799e2a9c-16d8-43ec-9aea-f48e6aca0759
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897290517 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.2897290517
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.3317073004
Short name T851
Test name
Test status
Simulation time 130037678071 ps
CPU time 73.24 seconds
Started May 02 02:30:57 PM PDT 24
Finished May 02 02:32:12 PM PDT 24
Peak memory 200460 kb
Host smart-f58601ea-509f-4ff4-9f58-5082aa64b4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317073004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.3317073004
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.3437607923
Short name T923
Test name
Test status
Simulation time 194283457805 ps
CPU time 1783.44 seconds
Started May 02 02:31:05 PM PDT 24
Finished May 02 03:00:51 PM PDT 24
Peak memory 232708 kb
Host smart-0eb7cffe-a2e6-4454-b768-63eae2717396
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437607923 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.3437607923
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.1554896505
Short name T738
Test name
Test status
Simulation time 21677305114 ps
CPU time 38.61 seconds
Started May 02 02:31:04 PM PDT 24
Finished May 02 02:31:44 PM PDT 24
Peak memory 200400 kb
Host smart-a6da7442-0711-475b-9f04-f9643ca36c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554896505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.1554896505
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.3373700597
Short name T1053
Test name
Test status
Simulation time 226259935689 ps
CPU time 558.54 seconds
Started May 02 02:31:04 PM PDT 24
Finished May 02 02:40:25 PM PDT 24
Peak memory 216848 kb
Host smart-b0abe3dd-a4f3-423d-8ec3-72322132e0f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373700597 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.3373700597
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.2745826846
Short name T12
Test name
Test status
Simulation time 28271149211 ps
CPU time 52.86 seconds
Started May 02 02:31:04 PM PDT 24
Finished May 02 02:31:59 PM PDT 24
Peak memory 200428 kb
Host smart-8aaf47fc-9ea4-4160-b058-1172147e6d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745826846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.2745826846
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.47732918
Short name T867
Test name
Test status
Simulation time 58252574662 ps
CPU time 359.31 seconds
Started May 02 02:31:16 PM PDT 24
Finished May 02 02:37:16 PM PDT 24
Peak memory 216828 kb
Host smart-5909998d-896b-4cd6-b4d9-92b5847e77c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47732918 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.47732918
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.391386382
Short name T32
Test name
Test status
Simulation time 8999731287 ps
CPU time 16.24 seconds
Started May 02 02:31:05 PM PDT 24
Finished May 02 02:31:24 PM PDT 24
Peak memory 200448 kb
Host smart-9dac21cd-a949-4381-b004-9d63d8c97fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391386382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.391386382
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.239796921
Short name T702
Test name
Test status
Simulation time 156920466037 ps
CPU time 381.45 seconds
Started May 02 02:31:03 PM PDT 24
Finished May 02 02:37:26 PM PDT 24
Peak memory 217184 kb
Host smart-483f2f1f-4aed-46f7-a849-6f3541199eaf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239796921 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.239796921
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.3558020155
Short name T757
Test name
Test status
Simulation time 142934747291 ps
CPU time 51.25 seconds
Started May 02 02:31:05 PM PDT 24
Finished May 02 02:31:58 PM PDT 24
Peak memory 200372 kb
Host smart-8440a3d5-496b-45ea-8fa1-f82f93892d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558020155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.3558020155
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.3778223994
Short name T93
Test name
Test status
Simulation time 539511435954 ps
CPU time 492 seconds
Started May 02 02:31:18 PM PDT 24
Finished May 02 02:39:32 PM PDT 24
Peak memory 216596 kb
Host smart-29e7d651-1e0c-45e3-88af-599afd788dd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778223994 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.3778223994
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.3917660142
Short name T284
Test name
Test status
Simulation time 36022666654 ps
CPU time 36.56 seconds
Started May 02 02:31:13 PM PDT 24
Finished May 02 02:31:51 PM PDT 24
Peak memory 200412 kb
Host smart-88dd9241-fe6c-486f-8232-605dc6c54970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917660142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.3917660142
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.3362878507
Short name T140
Test name
Test status
Simulation time 71771943719 ps
CPU time 562.58 seconds
Started May 02 02:31:11 PM PDT 24
Finished May 02 02:40:35 PM PDT 24
Peak memory 217008 kb
Host smart-e18fa01e-5edb-44fc-bb6c-2c182180a344
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362878507 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.3362878507
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.3310303606
Short name T1133
Test name
Test status
Simulation time 13533867 ps
CPU time 0.56 seconds
Started May 02 02:25:12 PM PDT 24
Finished May 02 02:25:16 PM PDT 24
Peak memory 195800 kb
Host smart-80146b46-7ed3-4d79-ad36-d811d2bc85ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310303606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.3310303606
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.1677080230
Short name T280
Test name
Test status
Simulation time 115473797867 ps
CPU time 205.15 seconds
Started May 02 02:25:03 PM PDT 24
Finished May 02 02:28:31 PM PDT 24
Peak memory 200364 kb
Host smart-61f92205-939a-4780-afe5-496d09c7f72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677080230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.1677080230
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.1166334630
Short name T960
Test name
Test status
Simulation time 39737803797 ps
CPU time 23.47 seconds
Started May 02 02:25:01 PM PDT 24
Finished May 02 02:25:28 PM PDT 24
Peak memory 200308 kb
Host smart-6316f496-1f90-4d0a-9a46-e3401321f1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166334630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.1166334630
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.2259439816
Short name T822
Test name
Test status
Simulation time 99933514800 ps
CPU time 159.16 seconds
Started May 02 02:25:03 PM PDT 24
Finished May 02 02:27:46 PM PDT 24
Peak memory 200368 kb
Host smart-deaf23a8-a9e2-4737-b56d-d6f31c145c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259439816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2259439816
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.4268916799
Short name T372
Test name
Test status
Simulation time 58745303363 ps
CPU time 52.21 seconds
Started May 02 02:25:01 PM PDT 24
Finished May 02 02:25:57 PM PDT 24
Peak memory 200384 kb
Host smart-4b543e21-c355-4638-a2f4-26146c3a2212
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268916799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.4268916799
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.2223312012
Short name T40
Test name
Test status
Simulation time 92207825915 ps
CPU time 279.06 seconds
Started May 02 02:25:14 PM PDT 24
Finished May 02 02:29:55 PM PDT 24
Peak memory 200400 kb
Host smart-5b7842a8-cf3a-473a-b074-adf2257fadc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2223312012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.2223312012
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.2648006919
Short name T866
Test name
Test status
Simulation time 9087624941 ps
CPU time 8.15 seconds
Started May 02 02:25:12 PM PDT 24
Finished May 02 02:25:23 PM PDT 24
Peak memory 198688 kb
Host smart-bfdf0ba3-0331-4f0b-b97c-5c997dfbc678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648006919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.2648006919
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.907051421
Short name T368
Test name
Test status
Simulation time 48399327828 ps
CPU time 43.21 seconds
Started May 02 02:25:01 PM PDT 24
Finished May 02 02:25:48 PM PDT 24
Peak memory 200600 kb
Host smart-beb996f5-2027-48b5-bff0-773d0da41ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907051421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.907051421
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.1123949600
Short name T1105
Test name
Test status
Simulation time 3091991123 ps
CPU time 150.67 seconds
Started May 02 02:25:12 PM PDT 24
Finished May 02 02:27:45 PM PDT 24
Peak memory 200408 kb
Host smart-58b7a2f8-bf9f-4c10-8d51-c821d07179bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1123949600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.1123949600
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.2245866197
Short name T422
Test name
Test status
Simulation time 4374118279 ps
CPU time 13.06 seconds
Started May 02 02:25:01 PM PDT 24
Finished May 02 02:25:17 PM PDT 24
Peak memory 199452 kb
Host smart-406b256f-62ed-4895-83c5-6c1aede3ccbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2245866197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.2245866197
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.4111677453
Short name T145
Test name
Test status
Simulation time 27288061558 ps
CPU time 46.27 seconds
Started May 02 02:25:01 PM PDT 24
Finished May 02 02:25:50 PM PDT 24
Peak memory 200372 kb
Host smart-6c4dda9f-2778-4840-88ed-8ea6cc09ad15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111677453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.4111677453
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.19342665
Short name T649
Test name
Test status
Simulation time 7462681661 ps
CPU time 2.51 seconds
Started May 02 02:25:06 PM PDT 24
Finished May 02 02:25:12 PM PDT 24
Peak memory 196432 kb
Host smart-5cd7e12c-d9c5-4acb-bb58-6eb1abef48fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19342665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.19342665
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.2159774897
Short name T985
Test name
Test status
Simulation time 861609389 ps
CPU time 2.79 seconds
Started May 02 02:25:01 PM PDT 24
Finished May 02 02:25:08 PM PDT 24
Peak memory 198748 kb
Host smart-6c25c2b3-695d-406e-a80c-03d8c29782f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159774897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2159774897
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.581069522
Short name T559
Test name
Test status
Simulation time 521306036407 ps
CPU time 209.47 seconds
Started May 02 02:25:16 PM PDT 24
Finished May 02 02:28:48 PM PDT 24
Peak memory 216712 kb
Host smart-78552e62-b9a4-4fc1-9953-3d28bf40d796
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581069522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.581069522
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.1182964502
Short name T54
Test name
Test status
Simulation time 69904907442 ps
CPU time 652.59 seconds
Started May 02 02:25:12 PM PDT 24
Finished May 02 02:36:08 PM PDT 24
Peak memory 216888 kb
Host smart-9ea57297-0289-4b70-b7b8-83f0d3507cd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182964502 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.1182964502
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.2930810490
Short name T427
Test name
Test status
Simulation time 1063125949 ps
CPU time 1.44 seconds
Started May 02 02:25:13 PM PDT 24
Finished May 02 02:25:17 PM PDT 24
Peak memory 198644 kb
Host smart-2d8a7dbd-f9c1-4857-8568-a2ff42d2370e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930810490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.2930810490
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.2318044228
Short name T259
Test name
Test status
Simulation time 69795837357 ps
CPU time 60.2 seconds
Started May 02 02:25:00 PM PDT 24
Finished May 02 02:26:03 PM PDT 24
Peak memory 200288 kb
Host smart-cbf20c3e-1d18-4af3-a6ae-918d8577258f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318044228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2318044228
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.3533353051
Short name T629
Test name
Test status
Simulation time 40997044504 ps
CPU time 41.12 seconds
Started May 02 02:31:10 PM PDT 24
Finished May 02 02:31:53 PM PDT 24
Peak memory 199736 kb
Host smart-3bbfb997-9a21-47ca-94b3-1637242afba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533353051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.3533353051
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.117203781
Short name T888
Test name
Test status
Simulation time 26891393200 ps
CPU time 239.95 seconds
Started May 02 02:31:17 PM PDT 24
Finished May 02 02:35:18 PM PDT 24
Peak memory 208676 kb
Host smart-de3b8dd4-18ab-4f19-8b30-c02e9612bf6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117203781 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.117203781
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.2686793616
Short name T562
Test name
Test status
Simulation time 84499131919 ps
CPU time 126.29 seconds
Started May 02 02:31:12 PM PDT 24
Finished May 02 02:33:20 PM PDT 24
Peak memory 200420 kb
Host smart-9073a09a-19a5-483f-998b-10a625a01c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686793616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.2686793616
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.1099722217
Short name T448
Test name
Test status
Simulation time 50569220810 ps
CPU time 995.78 seconds
Started May 02 02:31:11 PM PDT 24
Finished May 02 02:47:48 PM PDT 24
Peak memory 216988 kb
Host smart-13a6645f-0b98-4c70-a96e-edfdd4df1e68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099722217 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.1099722217
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.3878814134
Short name T670
Test name
Test status
Simulation time 19475105879 ps
CPU time 30.59 seconds
Started May 02 02:31:18 PM PDT 24
Finished May 02 02:31:50 PM PDT 24
Peak memory 200148 kb
Host smart-c0f29bac-c548-42a0-a752-b0454c75bdde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878814134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3878814134
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.757818646
Short name T490
Test name
Test status
Simulation time 19480851106 ps
CPU time 678.1 seconds
Started May 02 02:31:18 PM PDT 24
Finished May 02 02:42:38 PM PDT 24
Peak memory 215832 kb
Host smart-96a18fd9-a56e-43d7-af05-ad4c653508cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757818646 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.757818646
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.3283836435
Short name T519
Test name
Test status
Simulation time 127419985293 ps
CPU time 45.99 seconds
Started May 02 02:31:11 PM PDT 24
Finished May 02 02:31:59 PM PDT 24
Peak memory 200428 kb
Host smart-7bb9ea63-5684-4d0e-aa94-fbf8725a0019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283836435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.3283836435
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.936838636
Short name T794
Test name
Test status
Simulation time 16840367850 ps
CPU time 398.09 seconds
Started May 02 02:31:11 PM PDT 24
Finished May 02 02:37:50 PM PDT 24
Peak memory 216844 kb
Host smart-20c6f68a-830a-40fc-8b02-6207d177ee6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936838636 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.936838636
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.1591560214
Short name T173
Test name
Test status
Simulation time 16082820591 ps
CPU time 25.3 seconds
Started May 02 02:31:12 PM PDT 24
Finished May 02 02:31:39 PM PDT 24
Peak memory 200348 kb
Host smart-1c49ad8d-88d0-46f0-a9c7-a49d7de6104e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591560214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.1591560214
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.2087310802
Short name T936
Test name
Test status
Simulation time 20091600318 ps
CPU time 14.85 seconds
Started May 02 02:31:14 PM PDT 24
Finished May 02 02:31:31 PM PDT 24
Peak memory 199292 kb
Host smart-d3e9e003-6acb-4f2d-82ae-b640a7e577f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087310802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.2087310802
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.3460660287
Short name T51
Test name
Test status
Simulation time 53487377322 ps
CPU time 517.05 seconds
Started May 02 02:31:18 PM PDT 24
Finished May 02 02:39:56 PM PDT 24
Peak memory 216748 kb
Host smart-9f87eea0-a13d-4800-92d5-a7becfd8dc7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460660287 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.3460660287
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.2225133981
Short name T709
Test name
Test status
Simulation time 27607860534 ps
CPU time 25.66 seconds
Started May 02 02:31:18 PM PDT 24
Finished May 02 02:31:45 PM PDT 24
Peak memory 200408 kb
Host smart-3be7a4db-737c-44c0-96f9-ce0ae6aa76cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225133981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.2225133981
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.4081156555
Short name T49
Test name
Test status
Simulation time 49376546897 ps
CPU time 755.08 seconds
Started May 02 02:31:16 PM PDT 24
Finished May 02 02:43:53 PM PDT 24
Peak memory 216984 kb
Host smart-2d4cc503-83b5-4b53-88ea-c4359194bf4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081156555 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.4081156555
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.1719778449
Short name T254
Test name
Test status
Simulation time 191212818396 ps
CPU time 97.56 seconds
Started May 02 02:31:16 PM PDT 24
Finished May 02 02:32:56 PM PDT 24
Peak memory 200412 kb
Host smart-ded2f421-2a75-4770-bc41-84f416fd21af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719778449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.1719778449
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.1469040229
Short name T1160
Test name
Test status
Simulation time 24249733614 ps
CPU time 323.64 seconds
Started May 02 02:31:17 PM PDT 24
Finished May 02 02:36:42 PM PDT 24
Peak memory 216860 kb
Host smart-daddf198-988d-41f7-8b22-09cbb3f863db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469040229 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.1469040229
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.2194912732
Short name T133
Test name
Test status
Simulation time 96744091908 ps
CPU time 118.6 seconds
Started May 02 02:31:16 PM PDT 24
Finished May 02 02:33:16 PM PDT 24
Peak memory 200344 kb
Host smart-6b1f86dd-2636-40a4-be58-b8e5ae14c2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194912732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.2194912732
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.2015021047
Short name T56
Test name
Test status
Simulation time 52318622374 ps
CPU time 485.89 seconds
Started May 02 02:31:24 PM PDT 24
Finished May 02 02:39:30 PM PDT 24
Peak memory 212740 kb
Host smart-acd105f2-3b08-4bb0-b893-b08163100550
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015021047 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.2015021047
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.3578777967
Short name T864
Test name
Test status
Simulation time 26413839168 ps
CPU time 21.87 seconds
Started May 02 02:31:21 PM PDT 24
Finished May 02 02:31:44 PM PDT 24
Peak memory 200204 kb
Host smart-82cca0b3-a103-4fea-a295-aec7197b317a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578777967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.3578777967
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.2673332707
Short name T577
Test name
Test status
Simulation time 37435925 ps
CPU time 0.55 seconds
Started May 02 02:25:21 PM PDT 24
Finished May 02 02:25:24 PM PDT 24
Peak memory 195796 kb
Host smart-bd6418c8-5135-4caa-b12b-9119708be8fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673332707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.2673332707
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.443288987
Short name T765
Test name
Test status
Simulation time 93624197246 ps
CPU time 106.1 seconds
Started May 02 02:25:12 PM PDT 24
Finished May 02 02:27:01 PM PDT 24
Peak memory 200392 kb
Host smart-0c2329e9-2de8-41f6-b489-c4952f3a0524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443288987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.443288987
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.3998493443
Short name T598
Test name
Test status
Simulation time 118922161256 ps
CPU time 174.44 seconds
Started May 02 02:25:12 PM PDT 24
Finished May 02 02:28:09 PM PDT 24
Peak memory 200296 kb
Host smart-930f1617-2091-4897-b9ff-97882d786e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998493443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.3998493443
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.2078770656
Short name T845
Test name
Test status
Simulation time 22647160436 ps
CPU time 31.82 seconds
Started May 02 02:25:12 PM PDT 24
Finished May 02 02:25:47 PM PDT 24
Peak memory 200296 kb
Host smart-9cbe8846-e0a9-4151-ba43-220b48faa094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078770656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.2078770656
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.3307600544
Short name T971
Test name
Test status
Simulation time 31435650247 ps
CPU time 27.36 seconds
Started May 02 02:25:13 PM PDT 24
Finished May 02 02:25:43 PM PDT 24
Peak memory 200364 kb
Host smart-a772af5d-544a-4d9e-8e1b-c6de215aabf2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307600544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.3307600544
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.3987891433
Short name T1120
Test name
Test status
Simulation time 165591680713 ps
CPU time 401.79 seconds
Started May 02 02:25:12 PM PDT 24
Finished May 02 02:31:57 PM PDT 24
Peak memory 200432 kb
Host smart-bcf5c233-f8d0-470e-9955-03ed8df5866c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3987891433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.3987891433
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.1984390323
Short name T433
Test name
Test status
Simulation time 4427764823 ps
CPU time 1.98 seconds
Started May 02 02:25:17 PM PDT 24
Finished May 02 02:25:21 PM PDT 24
Peak memory 197140 kb
Host smart-b6a61e58-0ae9-4a72-97f8-0b03b2762267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984390323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1984390323
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.3341158946
Short name T305
Test name
Test status
Simulation time 4723487278 ps
CPU time 7.48 seconds
Started May 02 02:25:14 PM PDT 24
Finished May 02 02:25:24 PM PDT 24
Peak memory 195020 kb
Host smart-5c229016-caa6-42ba-b58e-9d8dbc9f4d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341158946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.3341158946
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.3300693536
Short name T753
Test name
Test status
Simulation time 24968242381 ps
CPU time 634.36 seconds
Started May 02 02:25:12 PM PDT 24
Finished May 02 02:35:49 PM PDT 24
Peak memory 200448 kb
Host smart-f754efd3-1da7-4dc7-8a04-a53c516dc6d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3300693536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3300693536
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.1312586130
Short name T1179
Test name
Test status
Simulation time 5563560201 ps
CPU time 4.17 seconds
Started May 02 02:25:11 PM PDT 24
Finished May 02 02:25:18 PM PDT 24
Peak memory 199188 kb
Host smart-efcdd2b7-ed4d-4fb1-855c-78cbfa70389e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1312586130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.1312586130
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.94882101
Short name T580
Test name
Test status
Simulation time 79021220265 ps
CPU time 38.74 seconds
Started May 02 02:25:12 PM PDT 24
Finished May 02 02:25:53 PM PDT 24
Peak memory 200348 kb
Host smart-7263b479-4a88-4eb0-bef6-b68a6a998988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94882101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.94882101
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.3393522121
Short name T669
Test name
Test status
Simulation time 32290675947 ps
CPU time 9.11 seconds
Started May 02 02:25:12 PM PDT 24
Finished May 02 02:25:24 PM PDT 24
Peak memory 196384 kb
Host smart-f23f5920-54b9-40c3-9644-ae0adc5c1342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393522121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.3393522121
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.1391571044
Short name T1044
Test name
Test status
Simulation time 710763332 ps
CPU time 1.77 seconds
Started May 02 02:25:14 PM PDT 24
Finished May 02 02:25:18 PM PDT 24
Peak memory 199164 kb
Host smart-bef0278e-8f37-4de9-a370-3f95723e7fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391571044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.1391571044
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.1145008634
Short name T882
Test name
Test status
Simulation time 27627845017 ps
CPU time 16.32 seconds
Started May 02 02:25:13 PM PDT 24
Finished May 02 02:25:32 PM PDT 24
Peak memory 200388 kb
Host smart-5d2b4c32-be9c-4f12-9fd8-83da31cc15ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145008634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.1145008634
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.2679999540
Short name T276
Test name
Test status
Simulation time 27259148438 ps
CPU time 410.31 seconds
Started May 02 02:25:12 PM PDT 24
Finished May 02 02:32:06 PM PDT 24
Peak memory 216692 kb
Host smart-d7715f62-9ed9-4ed8-a206-074eee1ac912
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679999540 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.2679999540
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.778624709
Short name T540
Test name
Test status
Simulation time 903204615 ps
CPU time 1.78 seconds
Started May 02 02:25:14 PM PDT 24
Finished May 02 02:25:18 PM PDT 24
Peak memory 199372 kb
Host smart-aa022062-80a7-4184-ae2b-4d09415c6b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778624709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.778624709
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.1616725586
Short name T1007
Test name
Test status
Simulation time 37296316779 ps
CPU time 14.38 seconds
Started May 02 02:25:11 PM PDT 24
Finished May 02 02:25:28 PM PDT 24
Peak memory 199876 kb
Host smart-2e88edaf-9b77-4d72-ac81-8ef8d61d36be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616725586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.1616725586
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.1713605153
Short name T53
Test name
Test status
Simulation time 101309789482 ps
CPU time 1006.01 seconds
Started May 02 02:31:17 PM PDT 24
Finished May 02 02:48:05 PM PDT 24
Peak memory 225304 kb
Host smart-161944c6-2f28-4dfe-a9d1-936f98492ea2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713605153 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.1713605153
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.792711021
Short name T329
Test name
Test status
Simulation time 48188651212 ps
CPU time 89.3 seconds
Started May 02 02:31:25 PM PDT 24
Finished May 02 02:32:56 PM PDT 24
Peak memory 200368 kb
Host smart-dac9c9f4-9ef9-401a-8620-5d3e5421bd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792711021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.792711021
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.3536095096
Short name T1121
Test name
Test status
Simulation time 414479575420 ps
CPU time 431.13 seconds
Started May 02 02:31:24 PM PDT 24
Finished May 02 02:38:37 PM PDT 24
Peak memory 227832 kb
Host smart-9164e407-79b0-4dbf-ae7a-f8ee8776949d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536095096 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.3536095096
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.1878797490
Short name T1034
Test name
Test status
Simulation time 35102224709 ps
CPU time 9.9 seconds
Started May 02 02:31:25 PM PDT 24
Finished May 02 02:31:36 PM PDT 24
Peak memory 200288 kb
Host smart-55327a00-72ae-4de2-97e1-02590a58f1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878797490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.1878797490
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.1630047980
Short name T434
Test name
Test status
Simulation time 85393407658 ps
CPU time 64.28 seconds
Started May 02 02:31:25 PM PDT 24
Finished May 02 02:32:31 PM PDT 24
Peak memory 200416 kb
Host smart-a44b6554-0ed3-4b4a-a48a-11398c1405b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630047980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.1630047980
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.1341403233
Short name T97
Test name
Test status
Simulation time 111703044904 ps
CPU time 650.71 seconds
Started May 02 02:31:25 PM PDT 24
Finished May 02 02:42:17 PM PDT 24
Peak memory 217064 kb
Host smart-7529d7f5-5473-4bd9-9bd2-0765ce667cf0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341403233 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.1341403233
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.4043608238
Short name T221
Test name
Test status
Simulation time 57267454621 ps
CPU time 30.33 seconds
Started May 02 02:31:26 PM PDT 24
Finished May 02 02:31:57 PM PDT 24
Peak memory 200420 kb
Host smart-63fad2e3-8c35-458d-82de-5d6df2a00d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043608238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.4043608238
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.1313354140
Short name T873
Test name
Test status
Simulation time 77000544574 ps
CPU time 1005.95 seconds
Started May 02 02:31:27 PM PDT 24
Finished May 02 02:48:14 PM PDT 24
Peak memory 225080 kb
Host smart-3b125aa6-f26c-4440-b78b-a369e06a8857
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313354140 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.1313354140
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.488373863
Short name T499
Test name
Test status
Simulation time 32500203222 ps
CPU time 31.02 seconds
Started May 02 02:31:25 PM PDT 24
Finished May 02 02:31:57 PM PDT 24
Peak memory 200292 kb
Host smart-9fb144f0-553b-49ba-bf21-b3ca062013a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488373863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.488373863
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.3378315083
Short name T1143
Test name
Test status
Simulation time 214325298452 ps
CPU time 401.15 seconds
Started May 02 02:31:25 PM PDT 24
Finished May 02 02:38:07 PM PDT 24
Peak memory 216752 kb
Host smart-2f51ea59-6fe0-4b46-bf0b-658949766384
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378315083 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.3378315083
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.2599085282
Short name T545
Test name
Test status
Simulation time 32807442898 ps
CPU time 51.23 seconds
Started May 02 02:31:25 PM PDT 24
Finished May 02 02:32:18 PM PDT 24
Peak memory 200408 kb
Host smart-7df622fa-7112-4a3b-b6f0-c9b0b5d6e6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599085282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.2599085282
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.327489145
Short name T114
Test name
Test status
Simulation time 35814587774 ps
CPU time 641.29 seconds
Started May 02 02:31:26 PM PDT 24
Finished May 02 02:42:09 PM PDT 24
Peak memory 216096 kb
Host smart-5ebbc83b-44ec-4967-a08d-99d65716f1aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327489145 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.327489145
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.2400160335
Short name T206
Test name
Test status
Simulation time 10463273532 ps
CPU time 23.9 seconds
Started May 02 02:31:33 PM PDT 24
Finished May 02 02:31:59 PM PDT 24
Peak memory 200364 kb
Host smart-0f2b017f-d152-4adc-be1a-4ae907cc3e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400160335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.2400160335
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.2653731754
Short name T1145
Test name
Test status
Simulation time 21230045570 ps
CPU time 333.2 seconds
Started May 02 02:31:35 PM PDT 24
Finished May 02 02:37:11 PM PDT 24
Peak memory 208704 kb
Host smart-6f459458-9ff0-4ffa-8a43-58fea5c218ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653731754 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.2653731754
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.931661341
Short name T98
Test name
Test status
Simulation time 35826273576 ps
CPU time 144.88 seconds
Started May 02 02:31:34 PM PDT 24
Finished May 02 02:34:02 PM PDT 24
Peak memory 216804 kb
Host smart-30940ae0-d39b-4805-8fd9-fa5ca69ce279
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931661341 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.931661341
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.3084881952
Short name T179
Test name
Test status
Simulation time 105289815966 ps
CPU time 229.02 seconds
Started May 02 02:31:36 PM PDT 24
Finished May 02 02:35:27 PM PDT 24
Peak memory 200144 kb
Host smart-3b8a28a9-5bf5-42dd-942d-602f9e0e7823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084881952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.3084881952
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.3508152963
Short name T302
Test name
Test status
Simulation time 244512881075 ps
CPU time 663.86 seconds
Started May 02 02:31:37 PM PDT 24
Finished May 02 02:42:45 PM PDT 24
Peak memory 225308 kb
Host smart-003bfd97-00ab-40fd-8b9b-da79e619f17e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508152963 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.3508152963
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.2219489217
Short name T520
Test name
Test status
Simulation time 33309835 ps
CPU time 0.55 seconds
Started May 02 02:25:20 PM PDT 24
Finished May 02 02:25:22 PM PDT 24
Peak memory 195772 kb
Host smart-c9ccf992-09d3-4ee7-8677-62451d8fb49a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219489217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.2219489217
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.608652502
Short name T646
Test name
Test status
Simulation time 102325913095 ps
CPU time 79.89 seconds
Started May 02 02:25:20 PM PDT 24
Finished May 02 02:26:42 PM PDT 24
Peak memory 200444 kb
Host smart-364ca349-f43f-43db-83c2-859406ce6deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608652502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.608652502
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.4107524095
Short name T868
Test name
Test status
Simulation time 72192334579 ps
CPU time 34.15 seconds
Started May 02 02:25:23 PM PDT 24
Finished May 02 02:25:59 PM PDT 24
Peak memory 200428 kb
Host smart-688bea12-d3d8-4a49-88ff-2759af7513db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107524095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.4107524095
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.3744018249
Short name T584
Test name
Test status
Simulation time 56368969530 ps
CPU time 29.98 seconds
Started May 02 02:25:21 PM PDT 24
Finished May 02 02:25:52 PM PDT 24
Peak memory 200424 kb
Host smart-8b29e01c-8160-411f-bf71-ce4beac601b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744018249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.3744018249
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.2691111865
Short name T756
Test name
Test status
Simulation time 57313666032 ps
CPU time 43.61 seconds
Started May 02 02:25:21 PM PDT 24
Finished May 02 02:26:06 PM PDT 24
Peak memory 196480 kb
Host smart-7afa123a-2453-4daa-a905-9f22a35d84b9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691111865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.2691111865
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.1022237187
Short name T1137
Test name
Test status
Simulation time 91998192198 ps
CPU time 597.93 seconds
Started May 02 02:25:27 PM PDT 24
Finished May 02 02:35:27 PM PDT 24
Peak memory 200452 kb
Host smart-f939e8a3-ccfc-4e37-b6fc-904e8662eec7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1022237187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.1022237187
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.3258634122
Short name T1023
Test name
Test status
Simulation time 3143607024 ps
CPU time 2.25 seconds
Started May 02 02:25:20 PM PDT 24
Finished May 02 02:25:24 PM PDT 24
Peak memory 199340 kb
Host smart-db35c883-17b1-4181-94d0-f1f3f60915eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258634122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.3258634122
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.665859843
Short name T1154
Test name
Test status
Simulation time 31216359728 ps
CPU time 22.65 seconds
Started May 02 02:25:26 PM PDT 24
Finished May 02 02:25:51 PM PDT 24
Peak memory 200600 kb
Host smart-077a0500-3ea9-40d7-96e1-89e5836a4872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665859843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.665859843
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.32777335
Short name T269
Test name
Test status
Simulation time 15111014580 ps
CPU time 192.14 seconds
Started May 02 02:25:22 PM PDT 24
Finished May 02 02:28:36 PM PDT 24
Peak memory 200360 kb
Host smart-3f5e79c6-0b4b-4a07-bcf6-a0df395430fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=32777335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.32777335
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.4139912285
Short name T977
Test name
Test status
Simulation time 3722541964 ps
CPU time 34.73 seconds
Started May 02 02:25:21 PM PDT 24
Finished May 02 02:25:58 PM PDT 24
Peak memory 199012 kb
Host smart-ca18666f-3fc6-4c34-ae3e-7295785a504d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4139912285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.4139912285
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.632409665
Short name T785
Test name
Test status
Simulation time 201320134439 ps
CPU time 39.19 seconds
Started May 02 02:25:22 PM PDT 24
Finished May 02 02:26:03 PM PDT 24
Peak memory 200152 kb
Host smart-969855cd-d043-47c8-9655-1812deec54c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632409665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.632409665
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.674083549
Short name T719
Test name
Test status
Simulation time 5567376989 ps
CPU time 2.17 seconds
Started May 02 02:25:22 PM PDT 24
Finished May 02 02:25:26 PM PDT 24
Peak memory 196736 kb
Host smart-2043680f-0242-4d01-aff6-88e244a1d783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674083549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.674083549
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.1001486467
Short name T485
Test name
Test status
Simulation time 89287792 ps
CPU time 0.88 seconds
Started May 02 02:25:20 PM PDT 24
Finished May 02 02:25:22 PM PDT 24
Peak memory 197484 kb
Host smart-1605776f-2898-4047-9d96-839ed356b0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001486467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.1001486467
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.1630842532
Short name T306
Test name
Test status
Simulation time 28654794018 ps
CPU time 104.65 seconds
Started May 02 02:25:22 PM PDT 24
Finished May 02 02:27:09 PM PDT 24
Peak memory 200396 kb
Host smart-e9d9204c-eea7-4972-84c7-4b8e9ee0d172
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630842532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.1630842532
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.1510554546
Short name T495
Test name
Test status
Simulation time 282106463409 ps
CPU time 914.75 seconds
Started May 02 02:25:23 PM PDT 24
Finished May 02 02:40:40 PM PDT 24
Peak memory 225248 kb
Host smart-35d6cb97-0b9a-4573-a755-f42eefc3a413
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510554546 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.1510554546
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.3723464675
Short name T639
Test name
Test status
Simulation time 1720244014 ps
CPU time 2.16 seconds
Started May 02 02:25:22 PM PDT 24
Finished May 02 02:25:26 PM PDT 24
Peak memory 199144 kb
Host smart-0d8daf45-e47b-413d-a615-ba46301fd8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723464675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.3723464675
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.2838958398
Short name T547
Test name
Test status
Simulation time 13932487384 ps
CPU time 22.43 seconds
Started May 02 02:25:21 PM PDT 24
Finished May 02 02:25:45 PM PDT 24
Peak memory 200360 kb
Host smart-ffafbcfc-71c8-41ac-ab62-939d349f4dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838958398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.2838958398
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.2522132118
Short name T160
Test name
Test status
Simulation time 73608438347 ps
CPU time 26.22 seconds
Started May 02 02:31:33 PM PDT 24
Finished May 02 02:32:02 PM PDT 24
Peak memory 200444 kb
Host smart-23291d2a-b9a7-49da-ae78-d42886b8c449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522132118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.2522132118
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.3367350859
Short name T823
Test name
Test status
Simulation time 200046017373 ps
CPU time 445.17 seconds
Started May 02 02:31:35 PM PDT 24
Finished May 02 02:39:03 PM PDT 24
Peak memory 216788 kb
Host smart-c53f38a1-6c67-4424-9ad9-05539398c152
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367350859 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.3367350859
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.951972485
Short name T234
Test name
Test status
Simulation time 67091290605 ps
CPU time 31.82 seconds
Started May 02 02:31:34 PM PDT 24
Finished May 02 02:32:09 PM PDT 24
Peak memory 200408 kb
Host smart-3fca12e7-6088-4ab7-accc-5140776de38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951972485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.951972485
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.130117500
Short name T521
Test name
Test status
Simulation time 11486626351 ps
CPU time 552.68 seconds
Started May 02 02:31:34 PM PDT 24
Finished May 02 02:40:49 PM PDT 24
Peak memory 215916 kb
Host smart-405b4e76-e4ea-4972-bc81-140f39038f00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130117500 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.130117500
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.4066643322
Short name T1027
Test name
Test status
Simulation time 95336341906 ps
CPU time 25.2 seconds
Started May 02 02:31:35 PM PDT 24
Finished May 02 02:32:02 PM PDT 24
Peak memory 200416 kb
Host smart-70044666-24a3-4d12-85ca-f2148e702ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066643322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.4066643322
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.1331723496
Short name T166
Test name
Test status
Simulation time 935387266430 ps
CPU time 587.8 seconds
Started May 02 02:31:41 PM PDT 24
Finished May 02 02:41:31 PM PDT 24
Peak memory 225268 kb
Host smart-54e2e9ae-5b06-4ff0-bb8a-ffd4fdfc0d05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331723496 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.1331723496
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.1498002124
Short name T491
Test name
Test status
Simulation time 8284075343 ps
CPU time 16.85 seconds
Started May 02 02:31:42 PM PDT 24
Finished May 02 02:32:01 PM PDT 24
Peak memory 200364 kb
Host smart-ea90ba3a-f12c-46de-a3ee-44df4e1c3c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498002124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.1498002124
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.2987780224
Short name T210
Test name
Test status
Simulation time 8763374672 ps
CPU time 13.53 seconds
Started May 02 02:31:42 PM PDT 24
Finished May 02 02:31:58 PM PDT 24
Peak memory 199980 kb
Host smart-b35122bb-5b54-4888-ab58-aa418b384ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987780224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.2987780224
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.2978948456
Short name T94
Test name
Test status
Simulation time 30103398435 ps
CPU time 267.87 seconds
Started May 02 02:31:42 PM PDT 24
Finished May 02 02:36:12 PM PDT 24
Peak memory 216360 kb
Host smart-b42e12d2-39d1-4468-b75b-11860d436745
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978948456 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.2978948456
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.1357370873
Short name T984
Test name
Test status
Simulation time 93698397444 ps
CPU time 150.19 seconds
Started May 02 02:31:41 PM PDT 24
Finished May 02 02:34:14 PM PDT 24
Peak memory 200388 kb
Host smart-5f2fd614-3535-4d2e-b6f7-93a20d151529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357370873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.1357370873
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.2243859803
Short name T1035
Test name
Test status
Simulation time 150278615897 ps
CPU time 1843.83 seconds
Started May 02 02:31:41 PM PDT 24
Finished May 02 03:02:28 PM PDT 24
Peak memory 225544 kb
Host smart-0d4c71be-75e0-4d00-9435-3df515d62f2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243859803 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.2243859803
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.2485442412
Short name T181
Test name
Test status
Simulation time 185749292193 ps
CPU time 113.37 seconds
Started May 02 02:31:42 PM PDT 24
Finished May 02 02:33:38 PM PDT 24
Peak memory 200424 kb
Host smart-a9b772c4-b4d9-4230-8ce2-7f15d5729bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485442412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.2485442412
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.3482968298
Short name T26
Test name
Test status
Simulation time 11334547285 ps
CPU time 127.36 seconds
Started May 02 02:31:42 PM PDT 24
Finished May 02 02:33:52 PM PDT 24
Peak memory 208868 kb
Host smart-ff3f6e88-7659-4e17-b5ee-a38e15afdafa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482968298 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.3482968298
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.3526082057
Short name T975
Test name
Test status
Simulation time 32427304163 ps
CPU time 21.8 seconds
Started May 02 02:31:41 PM PDT 24
Finished May 02 02:32:06 PM PDT 24
Peak memory 200452 kb
Host smart-c65c14ff-87fa-4742-b89d-70f1fefc4f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526082057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.3526082057
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.3466914050
Short name T52
Test name
Test status
Simulation time 278362341111 ps
CPU time 258.92 seconds
Started May 02 02:31:51 PM PDT 24
Finished May 02 02:36:11 PM PDT 24
Peak memory 217056 kb
Host smart-afdb1dcd-2ca3-4c95-ba3a-88c2ae5b768b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466914050 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.3466914050
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.906681404
Short name T916
Test name
Test status
Simulation time 70475905893 ps
CPU time 31.27 seconds
Started May 02 02:31:48 PM PDT 24
Finished May 02 02:32:20 PM PDT 24
Peak memory 200400 kb
Host smart-4c776322-3705-4dc0-a7eb-304227e763a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906681404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.906681404
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.645097527
Short name T121
Test name
Test status
Simulation time 21395550908 ps
CPU time 248.37 seconds
Started May 02 02:31:49 PM PDT 24
Finished May 02 02:35:59 PM PDT 24
Peak memory 217100 kb
Host smart-8734b0be-b749-43d3-bc1e-cba4dc0cf664
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645097527 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.645097527
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.363426180
Short name T1100
Test name
Test status
Simulation time 7652858044 ps
CPU time 9.85 seconds
Started May 02 02:31:51 PM PDT 24
Finished May 02 02:32:02 PM PDT 24
Peak memory 200272 kb
Host smart-a2eba6c0-325e-4b20-9a0e-465f8ed87a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363426180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.363426180
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.2767546276
Short name T908
Test name
Test status
Simulation time 17272883138 ps
CPU time 487.75 seconds
Started May 02 02:31:48 PM PDT 24
Finished May 02 02:39:57 PM PDT 24
Peak memory 216076 kb
Host smart-6d905be2-ce8b-4a5f-8b76-abe64475620e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767546276 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.2767546276
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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