Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}
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Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 12 0 12 100.00
Crosses 32 0 32 100.00


Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_intr 8 0 8 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_cg_cc 32 0 32 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_intr

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
all_values[0] 99981 1 T1 37 T2 1 T3 4
all_values[1] 99981 1 T1 37 T2 1 T3 4
all_values[2] 99981 1 T1 37 T2 1 T3 4
all_values[3] 99981 1 T1 37 T2 1 T3 4
all_values[4] 99981 1 T1 37 T2 1 T3 4
all_values[5] 99981 1 T1 37 T2 1 T3 4
all_values[6] 99981 1 T1 37 T2 1 T3 4
all_values[7] 99981 1 T1 37 T2 1 T3 4



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 407210 1 T1 113 T2 5 T3 18
auto[1] 392638 1 T1 183 T2 3 T3 14



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 745770 1 T1 253 T2 7 T3 28
auto[1] 54078 1 T1 43 T2 1 T3 4



Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for intr_cg_cc

Bins
cp_intr   cp_intr_en   cp_intr_state   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
all_values[0] auto[0] auto[0] 30140 1 T1 1 T3 1 T4 10
all_values[0] auto[0] auto[1] 21004 1 T1 25 T3 1 T4 8
all_values[0] auto[1] auto[0] 28309 1 T1 11 T3 1 T6 196
all_values[0] auto[1] auto[1] 20528 1 T2 1 T3 1 T6 392
all_values[1] auto[0] auto[0] 47606 1 T1 4 T2 1 T3 4
all_values[1] auto[0] auto[1] 1959 1 T1 10 T9 1 T12 2
all_values[1] auto[1] auto[0] 48558 1 T1 23 T4 8 T6 596
all_values[1] auto[1] auto[1] 1858 1 T8 6 T9 14 T13 19
all_values[2] auto[0] auto[0] 46765 1 T2 1 T4 4 T5 1
all_values[2] auto[0] auto[1] 2732 1 T4 4 T5 1 T6 1
all_values[2] auto[1] auto[0] 47873 1 T1 29 T3 2 T4 9
all_values[2] auto[1] auto[1] 2611 1 T1 8 T3 2 T4 1
all_values[3] auto[0] auto[0] 49816 1 T1 14 T3 3 T4 2
all_values[3] auto[0] auto[1] 330 1 T9 2 T12 1 T13 2
all_values[3] auto[1] auto[0] 49446 1 T1 23 T2 1 T3 1
all_values[3] auto[1] auto[1] 389 1 T9 3 T13 13 T24 3
all_values[4] auto[0] auto[0] 51659 1 T1 14 T4 16 T5 2
all_values[4] auto[0] auto[1] 490 1 T9 2 T13 11 T14 2
all_values[4] auto[1] auto[0] 47299 1 T1 23 T2 1 T3 4
all_values[4] auto[1] auto[1] 533 1 T9 7 T13 10 T16 8
all_values[5] auto[0] auto[0] 51708 1 T1 11 T2 1 T3 3
all_values[5] auto[0] auto[1] 194 1 T9 2 T13 6 T14 1
all_values[5] auto[1] auto[0] 47843 1 T1 26 T3 1 T4 3
all_values[5] auto[1] auto[1] 236 1 T13 5 T14 2 T84 3
all_values[6] auto[0] auto[0] 50979 1 T1 23 T2 1 T3 3
all_values[6] auto[0] auto[1] 206 1 T13 6 T14 3 T84 2
all_values[6] auto[1] auto[0] 48586 1 T1 14 T3 1 T4 11
all_values[6] auto[1] auto[1] 210 1 T9 3 T13 6 T84 2
all_values[7] auto[0] auto[0] 51220 1 T1 11 T2 1 T3 3
all_values[7] auto[0] auto[1] 402 1 T9 1 T12 2 T13 5
all_values[7] auto[1] auto[0] 47963 1 T1 26 T3 1 T4 8
all_values[7] auto[1] auto[1] 396 1 T9 1 T12 1 T13 6