Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2364	1			T1	1		T2	19		T3	1
auto[BaudRate115200]	1922	1			T3	1		T4	1		T7	2
auto[BaudRate230400]	2000	1			T1	1		T3	3		T6	3
auto[BaudRate128Kbps]	2088	1			T4	1		T5	1		T6	3
auto[BaudRate256Kbps]	2101	1			T5	1		T6	5		T7	1
auto[BaudRate1Mbps]	1874	1			T1	2		T3	2		T4	1
auto[BaudRate1p5Mbps]	1345	1			T1	1		T6	4		T7	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1043	1			T31	8		T32	10		T112	10
freqs[25]	1391	1			T1	5		T258	10		T34	10
freqs[48]	668	1			T8	9		T11	11		T280	2
freqs[50]	457	1			T12	7		T124	7		T215	5
freqs[100]	1264	1			T83	12		T33	9		T270	9

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	232	1			T31	1		T32	4		T112	2
auto[BaudRate9600]	freqs[25]	226	1			T1	1		T258	3		T34	2
auto[BaudRate9600]	freqs[48]	85	1			T11	1		T180	2		T316	11
auto[BaudRate9600]	freqs[50]	73	1			T12	1		T124	2		T215	1
auto[BaudRate9600]	freqs[100]	176	1			T83	3		T270	2		T264	5
auto[BaudRate115200]	freqs[24]	160	1			T32	2		T112	1		T262	1
auto[BaudRate115200]	freqs[25]	201	1			T258	1		T34	2		T123	2
auto[BaudRate115200]	freqs[48]	81	1			T11	3		T253	1		T97	1
auto[BaudRate115200]	freqs[50]	66	1			T12	2		T124	3		T215	1
auto[BaudRate115200]	freqs[100]	180	1			T83	5		T33	2		T270	2
auto[BaudRate230400]	freqs[24]	142	1			T31	2		T32	1		T112	3
auto[BaudRate230400]	freqs[25]	216	1			T1	1		T258	2		T34	1
auto[BaudRate230400]	freqs[48]	76	1			T11	1		T280	1		T303	1
auto[BaudRate230400]	freqs[50]	74	1			T12	1		T124	2		T302	1
auto[BaudRate230400]	freqs[100]	197	1			T83	1		T133	1		T42	4
auto[BaudRate128Kbps]	freqs[24]	130	1			T31	2		T32	1		T112	1
auto[BaudRate128Kbps]	freqs[25]	204	1			T34	3		T289	1		T123	3
auto[BaudRate128Kbps]	freqs[48]	86	1			T11	3		T303	1		T253	2
auto[BaudRate128Kbps]	freqs[50]	59	1			T215	1		T302	1		T44	1
auto[BaudRate128Kbps]	freqs[100]	190	1			T83	1		T264	2		T42	5
auto[BaudRate256Kbps]	freqs[24]	146	1			T112	3		T262	3		T276	1
auto[BaudRate256Kbps]	freqs[25]	207	1			T34	1		T123	2		T132	3
auto[BaudRate256Kbps]	freqs[48]	98	1			T8	5		T11	1		T256	3
auto[BaudRate256Kbps]	freqs[50]	74	1			T12	1		T302	3		T44	3
auto[BaudRate256Kbps]	freqs[100]	165	1			T83	1		T33	1		T270	3
auto[BaudRate1Mbps]	freqs[24]	157	1			T31	3		T262	1		T126	1
auto[BaudRate1Mbps]	freqs[25]	231	1			T1	2		T258	4		T34	1
auto[BaudRate1Mbps]	freqs[48]	129	1			T8	1		T11	2		T256	1
auto[BaudRate1Mbps]	freqs[50]	48	1			T12	1		T215	1		T302	1
auto[BaudRate1Mbps]	freqs[100]	171	1			T83	1		T33	3		T270	1
auto[BaudRate1p5Mbps]	freqs[25]	106	1			T1	1		T123	3		T132	1
auto[BaudRate1p5Mbps]	freqs[48]	113	1			T8	3		T280	1		T256	5
auto[BaudRate1p5Mbps]	freqs[50]	63	1			T12	1		T215	1		T302	1
auto[BaudRate1p5Mbps]	freqs[100]	185	1			T33	3		T270	1		T133	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded