Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.92	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	10	120	92.31

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	10	120	92.31	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	25153780	1			T1	15		T2	1		T3	27
all_levels[1]	182537	1			T3	5		T4	18		T6	148
all_levels[2]	2409	1			T3	2		T4	2		T6	4
all_levels[3]	1071	1			T3	2		T6	1		T11	4
all_levels[4]	767	1			T6	2		T9	1		T11	6
all_levels[5]	574	1			T9	1		T11	2		T13	1
all_levels[6]	410	1			T3	1		T7	1		T31	3
all_levels[7]	339	1			T7	1		T12	1		T14	1
all_levels[8]	272	1			T7	2		T31	1		T16	1
all_levels[9]	264	1			T12	3		T112	2		T122	2
all_levels[10]	215	1			T12	2		T14	2		T112	1
all_levels[11]	200	1			T7	3		T12	2		T14	2
all_levels[12]	153	1			T12	1		T32	1		T14	1
all_levels[13]	161	1			T112	1		T115	2		T123	1
all_levels[14]	131	1			T12	1		T124	1		T112	1
all_levels[15]	138	1			T12	1		T36	2		T125	1
all_levels[16]	131	1			T12	1		T31	1		T16	1
all_levels[17]	107	1			T7	1		T9	2		T124	1
all_levels[18]	93	1			T7	1		T31	1		T16	1
all_levels[19]	89	1			T124	4		T35	2		T25	1
all_levels[20]	89	1			T12	1		T126	2		T127	1
all_levels[21]	70	1			T13	1		T128	1		T125	1
all_levels[22]	86	1			T9	1		T13	1		T16	1
all_levels[23]	76	1			T113	1		T129	3		T130	1
all_levels[24]	77	1			T131	1		T127	1		T132	1
all_levels[25]	60	1			T31	2		T36	1		T25	1
all_levels[26]	56	1			T36	2		T126	1		T25	1
all_levels[27]	60	1			T12	1		T24	2		T115	1
all_levels[28]	48	1			T128	1		T125	1		T133	1
all_levels[29]	36	1			T112	1		T56	2		T114	1
all_levels[30]	37	1			T1	1		T125	1		T25	1
all_levels[31]	50	1			T112	2		T128	1		T127	2
all_levels[32]	34	1			T1	1		T12	1		T124	1
all_levels[33]	33	1			T112	1		T128	1		T134	1
all_levels[34]	30	1			T25	1		T130	1		T135	1
all_levels[35]	31	1			T36	1		T126	1		T136	1
all_levels[36]	18	1			T36	1		T137	1		T138	1
all_levels[37]	13	1			T115	1		T139	1		T140	1
all_levels[38]	31	1			T141	1		T61	1		T142	4
all_levels[39]	16	1			T12	1		T127	1		T40	1
all_levels[40]	25	1			T143	1		T25	1		T113	1
all_levels[41]	28	1			T16	2		T34	1		T113	1
all_levels[42]	35	1			T131	2		T137	1		T144	1
all_levels[43]	23	1			T13	1		T25	1		T145	1
all_levels[44]	21	1			T16	1		T62	1		T146	1
all_levels[45]	10	1			T16	1		T125	1		T114	1
all_levels[46]	6	1			T13	1		T137	1		T147	1
all_levels[47]	9	1			T115	1		T148	1		T149	1
all_levels[48]	15	1			T40	1		T150	1		T151	1
all_levels[49]	10	1			T131	1		T152	2		T153	1
all_levels[50]	14	1			T36	1		T129	1		T151	1
all_levels[51]	15	1			T45	1		T146	2		T154	2
all_levels[52]	20	1			T25	1		T56	1		T155	2
all_levels[53]	16	1			T156	1		T151	1		T157	2
all_levels[54]	6	1			T158	1		T49	1		T159	1
all_levels[55]	12	1			T31	1		T160	3		T161	1
all_levels[56]	5	1			T151	1		T162	1		T163	1
all_levels[57]	4	1			T31	1		T25	1		T164	1
all_levels[58]	8	1			T165	1		T166	1		T167	1
all_levels[59]	8	1			T156	1		T168	1		T159	1
all_levels[60]	6	1			T36	2		T169	1		T170	1
all_levels[61]	13	1			T31	1		T114	2		T171	1
all_levels[62]	10	1			T1	1		T172	1		T107	1
all_levels[63]	5	1			T173	1		T51	1		T174	1
all_levels[64]	111	1			T9	1		T12	1		T34	2

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25340373

1

T1

17

T3

37

T4

256

auto[1]

4854

1

T1

1

T2

1

T7

4

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	10	120	92.31	10

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[18]]	[auto[1]]	0	1	1
[all_levels[39]]	[auto[1]]	0	1	1
[all_levels[46]]	[auto[1]]	0	1	1
[all_levels[53] , all_levels[54]]	[auto[1]]	--	--	2
[all_levels[56] , all_levels[57] , all_levels[58]]	[auto[1]]	--	--	3
[all_levels[60]]	[auto[1]]	0	1	1
[all_levels[62]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	25149401	1			T1	14		T3	27		T4	236
all_levels[0]	auto[1]	4379	1			T1	1		T2	1		T7	3
all_levels[1]	auto[0]	182443	1			T3	5		T4	18		T6	148
all_levels[1]	auto[1]	94	1			T31	2		T34	2		T175	3
all_levels[2]	auto[0]	2384	1			T3	2		T4	2		T6	4
all_levels[2]	auto[1]	25	1			T131	1		T136	2		T176	3
all_levels[3]	auto[0]	1052	1			T3	2		T6	1		T11	4
all_levels[3]	auto[1]	19	1			T130	1		T177	1		T60	1
all_levels[4]	auto[0]	742	1			T6	2		T9	1		T11	6
all_levels[4]	auto[1]	25	1			T133	2		T148	1		T138	1
all_levels[5]	auto[0]	555	1			T9	1		T11	2		T13	1
all_levels[5]	auto[1]	19	1			T35	3		T178	1		T179	1
all_levels[6]	auto[0]	392	1			T3	1		T7	1		T31	3
all_levels[6]	auto[1]	18	1			T143	1		T180	1		T44	2
all_levels[7]	auto[0]	318	1			T7	1		T12	1		T14	1
all_levels[7]	auto[1]	21	1			T130	3		T62	1		T181	1
all_levels[8]	auto[0]	265	1			T7	2		T31	1		T16	1
all_levels[8]	auto[1]	7	1			T182	1		T183	1		T184	1
all_levels[9]	auto[0]	252	1			T12	3		T112	2		T122	2
all_levels[9]	auto[1]	12	1			T185	2		T186	5		T187	1
all_levels[10]	auto[0]	206	1			T12	2		T14	2		T112	1
all_levels[10]	auto[1]	9	1			T134	2		T188	1		T189	3
all_levels[11]	auto[0]	186	1			T7	2		T12	2		T14	2
all_levels[11]	auto[1]	14	1			T7	1		T190	3		T191	2
all_levels[12]	auto[0]	146	1			T12	1		T32	1		T14	1
all_levels[12]	auto[1]	7	1			T192	1		T154	1		T193	3
all_levels[13]	auto[0]	141	1			T112	1		T115	2		T123	1
all_levels[13]	auto[1]	20	1			T194	2		T195	3		T146	2
all_levels[14]	auto[0]	125	1			T12	1		T124	1		T112	1
all_levels[14]	auto[1]	6	1			T196	2		T197	1		T198	1
all_levels[15]	auto[0]	126	1			T12	1		T36	2		T125	1
all_levels[15]	auto[1]	12	1			T156	1		T199	1		T200	1
all_levels[16]	auto[0]	121	1			T12	1		T31	1		T16	1
all_levels[16]	auto[1]	10	1			T201	1		T99	2		T202	1
all_levels[17]	auto[0]	97	1			T7	1		T9	2		T124	1
all_levels[17]	auto[1]	10	1			T203	1		T204	2		T205	2
all_levels[18]	auto[0]	93	1			T7	1		T31	1		T16	1
all_levels[19]	auto[0]	76	1			T124	3		T35	1		T25	1
all_levels[19]	auto[1]	13	1			T124	1		T35	1		T206	3
all_levels[20]	auto[0]	84	1			T12	1		T126	2		T127	1
all_levels[20]	auto[1]	5	1			T207	2		T206	1		T208	1
all_levels[21]	auto[0]	68	1			T13	1		T128	1		T125	1
all_levels[21]	auto[1]	2	1			T209	1		T210	1		-	-
all_levels[22]	auto[0]	78	1			T9	1		T13	1		T16	1
all_levels[22]	auto[1]	8	1			T211	2		T212	1		T213	1
all_levels[23]	auto[0]	69	1			T113	1		T129	2		T130	1
all_levels[23]	auto[1]	7	1			T129	1		T62	2		T214	1
all_levels[24]	auto[0]	71	1			T131	1		T127	1		T132	1
all_levels[24]	auto[1]	6	1			T215	3		T129	1		T216	1
all_levels[25]	auto[0]	54	1			T31	1		T36	1		T25	1
all_levels[25]	auto[1]	6	1			T31	1		T209	1		T217	1
all_levels[26]	auto[0]	55	1			T36	2		T126	1		T25	1
all_levels[26]	auto[1]	1	1			T192	1		-	-		-	-
all_levels[27]	auto[0]	53	1			T12	1		T24	1		T115	1
all_levels[27]	auto[1]	7	1			T24	1		T133	1		T218	1
all_levels[28]	auto[0]	43	1			T128	1		T125	1		T133	1
all_levels[28]	auto[1]	5	1			T190	1		T219	1		T220	1
all_levels[29]	auto[0]	35	1			T112	1		T56	1		T114	1
all_levels[29]	auto[1]	1	1			T56	1		-	-		-	-
all_levels[30]	auto[0]	34	1			T1	1		T125	1		T25	1
all_levels[30]	auto[1]	3	1			T214	1		T221	1		T222	1
all_levels[31]	auto[0]	46	1			T112	2		T128	1		T127	2
all_levels[31]	auto[1]	4	1			T45	1		T155	1		T193	1
all_levels[32]	auto[0]	32	1			T1	1		T12	1		T124	1
all_levels[32]	auto[1]	2	1			T223	1		T224	1		-	-
all_levels[33]	auto[0]	27	1			T112	1		T128	1		T134	1
all_levels[33]	auto[1]	6	1			T182	3		T225	1		T226	2
all_levels[34]	auto[0]	28	1			T25	1		T130	1		T135	1
all_levels[34]	auto[1]	2	1			T209	2		-	-		-	-
all_levels[35]	auto[0]	28	1			T36	1		T126	1		T136	1
all_levels[35]	auto[1]	3	1			T227	2		T228	1		-	-
all_levels[36]	auto[0]	17	1			T36	1		T137	1		T138	1
all_levels[36]	auto[1]	1	1			T229	1		-	-		-	-
all_levels[37]	auto[0]	11	1			T115	1		T139	1		T140	1
all_levels[37]	auto[1]	2	1			T99	1		T230	1		-	-
all_levels[38]	auto[0]	26	1			T141	1		T61	1		T142	1
all_levels[38]	auto[1]	5	1			T142	3		T231	2		-	-
all_levels[39]	auto[0]	16	1			T12	1		T127	1		T40	1
all_levels[40]	auto[0]	23	1			T143	1		T25	1		T113	1
all_levels[40]	auto[1]	2	1			T232	1		T159	1		-	-
all_levels[41]	auto[0]	27	1			T16	2		T34	1		T113	1
all_levels[41]	auto[1]	1	1			T233	1		-	-		-	-
all_levels[42]	auto[0]	25	1			T131	1		T137	1		T144	1
all_levels[42]	auto[1]	10	1			T131	1		T196	1		T234	1
all_levels[43]	auto[0]	21	1			T13	1		T25	1		T145	1
all_levels[43]	auto[1]	2	1			T159	1		T235	1		-	-
all_levels[44]	auto[0]	18	1			T16	1		T62	1		T146	1
all_levels[44]	auto[1]	3	1			T236	1		T237	1		T238	1
all_levels[45]	auto[0]	8	1			T16	1		T125	1		T114	1
all_levels[45]	auto[1]	2	1			T239	1		T240	1		-	-
all_levels[46]	auto[0]	6	1			T13	1		T137	1		T147	1
all_levels[47]	auto[0]	7	1			T115	1		T148	1		T149	1
all_levels[47]	auto[1]	2	1			T241	2		-	-		-	-
all_levels[48]	auto[0]	13	1			T40	1		T150	1		T151	1
all_levels[48]	auto[1]	2	1			T242	1		T243	1		-	-
all_levels[49]	auto[0]	9	1			T131	1		T152	1		T153	1
all_levels[49]	auto[1]	1	1			T152	1		-	-		-	-
all_levels[50]	auto[0]	12	1			T36	1		T129	1		T151	1
all_levels[50]	auto[1]	2	1			T244	2		-	-		-	-
all_levels[51]	auto[0]	12	1			T45	1		T146	1		T154	1
all_levels[51]	auto[1]	3	1			T146	1		T154	1		T245	1
all_levels[52]	auto[0]	17	1			T25	1		T56	1		T155	1
all_levels[52]	auto[1]	3	1			T155	1		T246	1		T247	1
all_levels[53]	auto[0]	16	1			T156	1		T151	1		T157	2
all_levels[54]	auto[0]	6	1			T158	1		T49	1		T159	1
all_levels[55]	auto[0]	10	1			T31	1		T160	1		T161	1
all_levels[55]	auto[1]	2	1			T160	2		-	-		-	-
all_levels[56]	auto[0]	5	1			T151	1		T162	1		T163	1
all_levels[57]	auto[0]	4	1			T31	1		T25	1		T164	1
all_levels[58]	auto[0]	8	1			T165	1		T166	1		T167	1
all_levels[59]	auto[0]	5	1			T156	1		T168	1		T159	1
all_levels[59]	auto[1]	3	1			T248	3		-	-		-	-
all_levels[60]	auto[0]	6	1			T36	2		T169	1		T170	1
all_levels[61]	auto[0]	10	1			T31	1		T114	1		T171	1
all_levels[61]	auto[1]	3	1			T114	1		T192	1		T249	1
all_levels[62]	auto[0]	10	1			T1	1		T172	1		T107	1
all_levels[63]	auto[0]	4	1			T173	1		T51	1		T174	1
all_levels[63]	auto[1]	1	1			T200	1		-	-		-	-
all_levels[64]	auto[0]	95	1			T9	1		T12	1		T34	2
all_levels[64]	auto[1]	16	1			T250	1		T97	1		T251	2