Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99981	1			T1	37		T2	1		T3	4
all_pins[1]	99981	1			T1	37		T2	1		T3	4
all_pins[2]	99981	1			T1	37		T2	1		T3	4
all_pins[3]	99981	1			T1	37		T2	1		T3	4
all_pins[4]	99981	1			T1	37		T2	1		T3	4
all_pins[5]	99981	1			T1	37		T2	1		T3	4
all_pins[6]	99981	1			T1	37		T2	1		T3	4
all_pins[7]	99981	1			T1	37		T2	1		T3	4

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	772166	1			T1	288		T2	7		T3	29
values[0x1]	27682	1			T1	8		T2	1		T3	3
transitions[0x0=>0x1]	26487	1			T1	8		T2	1		T3	3
transitions[0x1=>0x0]	26061	1			T1	8		T3	3		T4	9

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	79395	1			T1	37		T3	3		T4	18
all_pins[0]	values[0x1]	20586	1			T2	1		T3	1		T6	392
all_pins[0]	transitions[0x0=>0x1]	20058	1			T2	1		T3	1		T6	392
all_pins[0]	transitions[0x1=>0x0]	1328	1			T8	6		T9	11		T13	16
all_pins[1]	values[0x0]	98125	1			T1	37		T2	1		T3	4
all_pins[1]	values[0x1]	1856	1			T8	6		T9	14		T13	19
all_pins[1]	transitions[0x0=>0x1]	1730	1			T8	6		T9	14		T13	17
all_pins[1]	transitions[0x1=>0x0]	2533	1			T1	8		T3	2		T4	1
all_pins[2]	values[0x0]	97322	1			T1	29		T2	1		T3	2
all_pins[2]	values[0x1]	2659	1			T1	8		T3	2		T4	1
all_pins[2]	transitions[0x0=>0x1]	2579	1			T1	8		T3	2		T4	1
all_pins[2]	transitions[0x1=>0x0]	308	1			T9	3		T13	12		T24	3
all_pins[3]	values[0x0]	99593	1			T1	37		T2	1		T3	4
all_pins[3]	values[0x1]	388	1			T9	3		T13	13		T24	3
all_pins[3]	transitions[0x0=>0x1]	324	1			T9	1		T13	9		T24	3
all_pins[3]	transitions[0x1=>0x0]	469	1			T9	5		T13	6		T16	8
all_pins[4]	values[0x0]	99448	1			T1	37		T2	1		T3	4
all_pins[4]	values[0x1]	533	1			T9	7		T13	10		T16	8
all_pins[4]	transitions[0x0=>0x1]	441	1			T9	7		T13	6		T16	8
all_pins[4]	transitions[0x1=>0x0]	195	1			T13	1		T14	2		T16	1
all_pins[5]	values[0x0]	99694	1			T1	37		T2	1		T3	4
all_pins[5]	values[0x1]	287	1			T13	5		T14	2		T16	1
all_pins[5]	transitions[0x0=>0x1]	221	1			T13	3		T14	2		T16	1
all_pins[5]	transitions[0x1=>0x0]	911	1			T4	8		T7	1		T9	3
all_pins[6]	values[0x0]	99004	1			T1	37		T2	1		T3	4
all_pins[6]	values[0x1]	977	1			T4	8		T7	1		T9	3
all_pins[6]	transitions[0x0=>0x1]	896	1			T4	8		T7	1		T9	3
all_pins[6]	transitions[0x1=>0x0]	315	1			T9	1		T12	1		T13	3
all_pins[7]	values[0x0]	99585	1			T1	37		T2	1		T3	4
all_pins[7]	values[0x1]	396	1			T9	1		T12	1		T13	6
all_pins[7]	transitions[0x0=>0x1]	238	1			T12	1		T13	5		T84	1
all_pins[7]	transitions[0x1=>0x0]	20002	1			T3	1		T6	392		T9	17